CA1039393A - Matrix module and switching network - Google Patents
Matrix module and switching networkInfo
- Publication number
- CA1039393A CA1039393A CA230,207A CA230207A CA1039393A CA 1039393 A CA1039393 A CA 1039393A CA 230207 A CA230207 A CA 230207A CA 1039393 A CA1039393 A CA 1039393A
- Authority
- CA
- Canada
- Prior art keywords
- control
- matrix module
- signal input
- matrix
- conductors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/52—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker using static devices in switching stages, e.g. electronic switching arrangements
- H04Q3/521—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker using static devices in switching stages, e.g. electronic switching arrangements using semiconductors in the switching stages
Abstract
ABSTRACT
A matrix module for integrated construction which is provided with electronic crosspoints, the control gates of which are connected to gate control circuits which are connected to the vertical conductors.
A description is given of an embodiment having a minimum number of terminals and comprising one selection signal input, one sense signal output and one marking signal input. These terminals can be reduced to one terminal by utilizing different voltage and/or current levels for the various signals.
Test signal generators, connected to the horizontal conductors, and a test control circuit controlled by the selection signal and controlling the test signal generators, enable test procedures to be performed, free paths to be searched and selected and paths to be established.
A matrix module for integrated construction which is provided with electronic crosspoints, the control gates of which are connected to gate control circuits which are connected to the vertical conductors.
A description is given of an embodiment having a minimum number of terminals and comprising one selection signal input, one sense signal output and one marking signal input. These terminals can be reduced to one terminal by utilizing different voltage and/or current levels for the various signals.
Test signal generators, connected to the horizontal conductors, and a test control circuit controlled by the selection signal and controlling the test signal generators, enable test procedures to be performed, free paths to be searched and selected and paths to be established.
Description
PHN. 7599~
1~9393 Matrix module and switching netw~rk".
Background of the inv~ntion.
(1) Field of the invention.
m e invention relates to a matrix module, comprising electronic crosspoint elements which are arranged at crosspoints of two groups of oonductors, separately denoted as horizontal and vertical conductors, and which are each pr~vided with a first main electrode connected to the horizontal conductor and a second main electrode connected to the vertical conductor and also with a control gate, the control gates of the crosspoint elements connected to the same vertical conductor being connected to a gate oontrol circuit which is connected to the vertical conductor.
m e invention furthermore relates to a multi- -stage switching network, comprising a nu~ber of switching stages which are interconnected by link conductors and which each oomprise a plurality of matrix modules, each matrix module comprising electronic crosspoint elements which are arranged at crosspoints of two groups of conduc- -tors which are separately denoted as horizontal and vertical conductors, each of the said crosspoint elements being provided with a first main electr~de oonnected to the horizontal conductor and a second main electrode connected to the vertical oonductor and also with a control gate, the control gates of the crosspoints elements which ar~
connecied to the sam~ vertical conductor being connected
1~9393 Matrix module and switching netw~rk".
Background of the inv~ntion.
(1) Field of the invention.
m e invention relates to a matrix module, comprising electronic crosspoint elements which are arranged at crosspoints of two groups of oonductors, separately denoted as horizontal and vertical conductors, and which are each pr~vided with a first main electrode connected to the horizontal conductor and a second main electrode connected to the vertical conductor and also with a control gate, the control gates of the crosspoint elements connected to the same vertical conductor being connected to a gate oontrol circuit which is connected to the vertical conductor.
m e invention furthermore relates to a multi- -stage switching network, comprising a nu~ber of switching stages which are interconnected by link conductors and which each oomprise a plurality of matrix modules, each matrix module comprising electronic crosspoint elements which are arranged at crosspoints of two groups of conduc- -tors which are separately denoted as horizontal and vertical conductors, each of the said crosspoint elements being provided with a first main electr~de oonnected to the horizontal conductor and a second main electrode connected to the vertical oonductor and also with a control gate, the control gates of the crosspoints elements which ar~
connecied to the sam~ vertical conductor being connected
- 2 - ~ `
PHN. 7599.
1039~93 to a gate control circuit which is connected to the vertical conductor.
Switching netwDrks for telecommunication exchanges may comprise electronic crosspoints such as four-layer diodes or four-layer transistors. Attempts are made to construct the electronic crosspoints and the ;
required control circuits in integrated form in ~ne semiconductor body. It is notably attempbed to accommodate one matrix switch together with the required control circuits, together referred to as matrix module, in one integrated unit (chip).
m e invention relates to the filed of the cir- ~-cuits for matrix modules which are suitable for realization in one integrated unit. A problem in this respect is to ~
minimize the number of terminals of the integratsd unit. --(2) Description of the state of the art. ~ ~
A crosspoint sub-system for integrated con- ~-struction is kncwn from Digest of Technical Papers, 1974, ~ International Solid-State Circuits Conference, pages 120, 121, 238. This sub-system comprises the crosspoints of one vertical of a matrix switch. me crosspoints are formed by four-layer transistors. me subsystem comprises one control input for the crosspoints, one test output, as many signal inputs as there are crosspoints, and one ~ -signal output. If a plurality of sub,systems are combined to form one matrix switch, there will be as many contr~l inputs and test outputs per matrix switch as there are sub-systems in a ~atrix switch. me number of terminals PHN. 7599.
of a matrix switch can then already become too large for matrix switches of small dimensions (limited number of verticals) so as to be realized in an integrated unit.
A matrix switch for integrated construction is known from IEF~ Transactions on Oommunications, Vol.
COM~22, No. 3, March 1974, pages 279-287. m e crosspoints are formed therein by four-layer transistors. The control gates of the crosspoints of a vertical are oonnected to a common gate control circuit, which is also connected to the vertical conductor. m e number of terminals of such a matrix switch is limited.
However, in a switching netw~rk incorporating such matrix switches it is difficult to realize the test procedures required in practice (before, during and after the establishment of the connection) and possibly also the searching and selection of free paths.
Summary of the invention The matrix module according to the invention is ch æacterized in that the matrix module comprises a selection signal input, accessible to a central control unit, and first means for deriving control signals frnm the selection signal input so as to control the gate control circuits therewith.
It is a further characteristic that the select-ion signal input has connected thereto a test control circuit for controlling, in reaction to a selection signal, test signal generators which are connected to the horizontal conductors.
PHN. 7599.
tO39~93 It is a further characteristic yet that the matrix module comprises a sense signal output, acoessible to the oe ntral control unit, and second means which are connected to the selection signal input and to the vertical conductos for controlling the sense signal output in the presence of a selection signal on the selection signal input and a free signal on at least one of the vertical conductors.
It is another characteristic that the matrix module ccmprises a marking signal input, accessible to the oe ntral control unit, and fourth means for deriving -- -control signals from the marking signal input in order to control the gate control circuits therewith, each gate control circuit comprising fifth means for forming the logic AND~function of the control signals originating from the first and fourth means and a test signal originating from the vertical conductor.
According to the first characteristic, each matrix mDdule ccmpriæs an input by means of which the matrix module can be selected; the gate control circuits will be activated only in a selected matrix module.
-, According to the second characteristic, the selection signal activates test signal generators which pass a test signal on to the horizontal conductors. In a multistage switch network this means that the selection of a matrix module causes test signals to be applied to the matrix nodules of the preceding switching stage vla the link condhctors.
PHN. 7599.
~039;~93 According to the third characteristic, the selection signal activates a sense signal output by means ;
of which it can be determined per matrix module whether a test signal appears on one of the vertical conductors.
According to the fourth eharacteristic, a marking signal is re~uired to activate the gate control circuits, with the result that test procedures can be performed independent of the establishment of connections.
It is to be noted that the selection signal input, the marking signal input, and the sense signal output may be different physical connections, but that the use of different voltage and/or current levels for -the various signals also enables the connection with the central contr~l unit to be established via one conductor.
A second aspect of the invention is formed by a multi-stage switching netw~rk. For this aspect of the invention, reference is made to the Claims.
Brief d~ cript;on of the Figures Figure 1 is a diagram of a mLlti-stage switching network.
Fig. 2 is a diagram of a matrix module accord-ing to the invention, shown between tw~ terminal circuits.
Fig. 3a shows the synbol of a crosspoint and Fig. 3b shows the diagram of an e~bodiment of the cross-point.
Fig. 4 shows a voltage diagram.
Fig. 5a shows the symbol of a crosspoint, and Fig. 5b shows the diagram of an e~bodi~ent of the cn~sspoint.
PHN. 759g.
1039;~93 ~ -Fig. 6 shows the diagram of a matrix module according to the invention, comprising crosspoints as shown in Fig. 5.
Fig. 7a shows the same as the lower part of Fig. 6, and Fig. 7b is a simplified representation of the same part.
Fig. 8a shows the test control circuit of Fig. 7b, and Fig. 8b shows the diagram of the electronic embodiment thereof.
Fig. 9a shows the gate control circuit and the sense output circuit of Fig. 7b, and Fig. 9b shows the diagram of the electronic embc~ ment of these circuits.
escriE ion: of the embodiments.
Fig. 1 shows a switching network camprising three stages A, B and C, each of which cc~prises a plurality of matrix switches, 100, 101 and 102 in stage A, 103, 104 and 105 in stage B, and 106, 107 and 108 in stage C. me stages ~--A, B and C are interconnected by link oDnductors, 109, 110 etc. be~ween the stages A and B, and 111, 112 etc. between ;~
the stages B and C. ~ -m e inputs of the matrix switches of stage A -have connected thereto terminal circuits 113, 114 etc., and the outputs of the matrix switches of stage C have connected --thereto termLnal circuits 115, 116 etc. The terms "input"
and "output" have no other significance then to make a distinction between the tw~ groups of connections of a matrix switch; they do not relate to the direction of the signal transmission or to the direction in which connections - -:-..
~ ' . ' : , , ' . ~ ,' :. ' , ' :'''` ' . ' ' .. . . . .
PHN. 7599.
1039;~93 are established. The terminal circuits 113, 114 etc. are referred to as left-hand terminal circuits for obvious reasons, and the terminal circuits 115, 116 are referred to as right-hand terminal circuits.
m e central part of Fig. 2 shows a matrix switch with the associated control circuits. The left-hand part of Fig. 2 shcws the essential parts of a left-hand terminal circuit, and the right-hand part of Fig. 2 shows the essential parts of a right-hand terminal circuit.
m e matrix switch shown in Fig. 2 comprises the inputs 200 and 201 and the outputs 202 and 203. Provided at the crosspoints between the inputs and the outputs are the crosspoint circuits 204, 205, 206 and 207. Each cross-point circuit is provided with an anode a, a cathcde k and a control gate s as shown in Fig. 2 for crosspoint circuit 204. The anodes of the crosspoint circuits are connected to the inputs of the matrix switch, and the cathodes are connected to the outputs of the matrix switch.
m e conLI~l gates of the crosspoint circuits 204 and 205 are connected to a gate oontrol circuit 208, and the oDntrol gates of the crosspoint circuits 206 and 207 are corn~cted to a gate control circuit 209. It is to be noted that the gate control circuit 208 is connected to the crosspoint circuits which are oonnected to output 202, and that the gate control circuit 209 is oonnected to the cross-point circuits which æe connected to output 203.
m e input 200 has connected thereto a source of constant current 210, whilst a source of const~nt current PHN. 7599.
1039~93 211 is oonnected to the input 201. Also connected to the in~ut 200 is a diode 212, whilst input 201 has connected thereto a diode 213. me diodes 212 and 213 are connected to test control circuit 214.
m e matrix switch furthermDre comprises a sense output circuit 215 which is connected to the gate control circuits 208 and 209, a sense signal output 216, a selection signal input 217 and a marking signal input 218.
m e right-hand terminal circuit 219 comprises a pnp transistor 220, the emitter of which is connected to an output of a matrix switch of stage C (oompare Fig. 1), its collector being connected to the signal output 221 and its base being connected to earth. me collector is -~
fur~hermDre connected, via a resistor 222, to a supply point 231 (-). me emitter has connected thereto a source of constant current 232 and a diode 233. m e diode is further-mare connected to a test control circuit 234 which is provided with a selection signal input 235. ;
The left-hand terminal circuit 223 comprises a ~
transistor 224, the collector of which is connected to an -input of a matrix switch of stage A (compare Fig. 1), its emitter being connected to a circuit which leads to a supply point 225 (+), its base being connected to a supply point -226 (+). me emitter circuit comprises a resistor 227, an (electronic) switch 228 which is controlled by a flipflop 229, and a signal generator 230. This signal generator represents the source of the signals which are to be trans-mitted, via a path through the switching network, to a _ g _ - . ; ~ , .
, .
' ' , , :,,,: , . : , PHN. 75g9, ~39~93 signal output of a right-hand terminal circuit.
me broken line between the output 202 of the matrix switch and the right-hand terminal circuit 219 may be considered as a symbolic representation of the presence of none, one or tWD stages of the switching netw~rk, depending on whether the matrix switch is situated in stage C, stage B or stage A. m e same applies to the broken line shcwn between left-hand terminal circuit 223 and the input 200 of the matrix switch.
It will be obvious that the description given with referenoe to the matrix switch shcwn is actually applicable to all matrix switches, no matter in what stage they are situated.
Fig. 3 adjacently shows the symbol of a cross point circuit and a feasible embodiment thereof. m is embod1ment is descrlbed in detail in U.S. Patent Specific~
ation 3,688,051, and will be descriked herein only in as far as is necessary for proper understanding of the present invention. me crosspoint circuit oomprises a pnpn transis-tor 300, a control transistor 301, and a current source 302. The collector of transistor 301 is oonnected to the n-region of the pnpn transistor which is situated on the anode side and which acts as a gate for triggering the pnpn transistor.
In the oondition in which the crosspoint circuit is not conductive and is not marked, the control gate s receives from the relevant gate control circuit (compare in Fig. 2 the gate control circuits 208 and 209) PHN. 7599.
1039~93 -a positive voltage which is denoted by GIP (gate idle p~tenr tial). m is GIP is more positive than any voltage liable to oocur in the switching netw~rk, and under these circumr stances the pnpn transistor is cut off. The control transis-tor 301 is then saturated and presents a low impedance to pnpn transistor 300. The collector current of control tran-sistor 301 equals the gate leakage current of pnpn transistor 300.
In order to trigger a crosspoint, a p~sitive voltage, denoted by L~P (link marking potential) and being slightly less positive than the ~1~, is applied to the anode a. A positive voltage, denoted by GMP and slightly less positive than the IMP, is applied to the control gate s. As a result, the voltage between the anode a and the con, -trol gate s of the marked crosspoint which was initially negative, reverses its sign and now beoomes positive. Cbn sequently, the gate current of the pnpn transistor reverses its ~irection and assumes a value such that the hold current -is reduced to zerD, with the result that the pnpn transistor constitutes substantially a short-circuit between the anode and the cathode. If it is ensured that in this condition a current of sufficient strength can flow between the anode and the cathode, the pnpn transistor remains conductive, also when the voltage of the oont;~l gate s is reduced to ~1~ and the transmission path (exteQdiDg via the crosspoint circuit) is kept at a positive voltage which is denoted by LCP (link connecting potential) and which is slightly less positive than the GMP.
., PHN. 7599 ~Q39~93 The mutual relationships between the above voltages and the regions in which these voltages are situated is illustrated in Fig. 4. This Figure also shows two negative voltages, iOe. a voltage denoted by LIP (link idle potential) and a voltage denoted by LTP (link test potential).
These voltages will be discussed hereinafter. In Fig. 4 the relationship of the value of the positive voltages is denoted by a number of +signs, i.e. the nu~ber of +signs is larger as the voltage is higher. The same applies to the negative voltages.
As is shown in Fig. 2, each matrix switch comprises a selection signal input 217. The matrix switch can be selected by means of the selection signal input. The selection signal inputs are generally indicated in Fig. 1.
Let it be assumed first that the route followed by a tranæmission path through the switching network is known, so that it is kncwn via which matrix switches the transmission path extends. Let us consider, by way of example, a transmission path extending between the terminal circuits 113 and 115 via the matrix switches 100, 104 and 106.
The establishment of the transmission path will be described in detail hereinafter with reference to Fig. 2, in which the terminal circuit 223 will be taken as a representa-tive of the terminal circuit 113, the terminal circuit 219 as a repre æntative of the terminal circuit 115, and the matrix switch successively as the representative of the matrix switches 100, 104 and 106.
The switch 228 in the terminal circuit 223 PHN. 7599.
~039;~93 is closed by suitable control of flipflop 229, with the result that transistor 224 is saturated and the collector assu~es the voltage of the supply point 226. m e input 200 of matrix switch 100, consequently, re oe ives the p~tential S LMP. me continuity of the collector current of transistor 224 is ensured by the current source 210. m e diode 212 is blocked in these circumstances.
me selection signal input 217 of ~he matrix switches 100, 104 and 106 and the selection signal input 235 of terminal circuit 115 receive a selection signal which activates various circuits in the matrix switches and the terminal circuit. First of all, the test control circuits 214, 234 are made to reduce the clamp potential LIP +Vj (Vj is the junction vDltage) applied to the diode to LTP +Vj (compare Fig. 4). Secondly, the gate control circuits 208 and 209 which are oonnect~d to the test control circuit 214 ,~.
are set to the state in which they are sensitive to the potential L~P on the relevant output of the matrix switch.
me operation of the current sources 210, 211 -and the diodes 212, 213 and the test control circuit 214 will be described hereinafter.
m e current source 210 and the diode 212 together constitute a test signal generator 210-212; a test signal generator 211-213 is similarly formed by the current source 211 and the diode 213.
When the test circuit 214 applies the potential - -LIP +Vj to the conductors 212 and 213, the inputs 200 and 201 cannot have a potential which is lower than LIP. An .
PHN. 7599.
1039;~93 input which does not form part of a completely or partly established transmission path, and hence is free, will assume the potential LIP.
A link oonductor which is busy has the potential TrP or L~P.
When test circuit 214 applieQ the potential LTP + Vj to the diodes 212 and 213, the inputs 200 and 201 will assume the potential LTP only if they are free. mis potential, indicating that an input is free, constitutes a so~termed "free signal" which is one of the possible output signals of the said test signal generators 210-212, 211-213.
For example, if the input 200 is busy and test control cir-cuit 214 applies the potential LTP +Vj to diode 212, the diode 212 will remain blocked (at the given polarity) because the potential of input 200 is ICP or LMP and because this potential is more positive than LTP. m e switching over of the potential by the test control circuit, oonsequently has no effect whatsoever on busy inputs.
It is to be noted that, when input 200 is busy, the current source 210 makes!a contribution to the current in the transmission path incorporating input 200. This contribution, hcwever, is constant and is not influenced by the test contr~l circuit 214, so that it has no disturbing effect whatsoever.
m e gate control circuits of the selected matrix switch in the preceding stage are in the state in which they were sensitive to the potential LTP. Because the link conductor oonnecting matrix switch 106 to matrix switch PHN. 7599 ~039~
104 and the link oonductor oonnecting matrix switch 104 to matrix switch 100 are assumed to be free, these link conductors will assume the potential LTP. Furtherm~re, the output of matrix switch 106 connected to terminal circuit 115 receives the potential LTP from this terminal circuit.
In the switching network the potential LTP is thus adjusted on the link conductors and on the output of the desired transmission path, and the potential LMP is adjusted on the input of the transmission path. In each of -the selected matrix switches 100, 104 and 106 the gate oon-trol circuits 208 and 209 have been made sensitive to the potential LTP, and one of these gate control circuits actually detects the potential LTP on an output of the matrix switch.
It will be assumed that this is the output 202 of the matrix ~ -switch shcwn in Fig. 2.
The potential LTP on the output 202 of matrix switch 100, the operation of which will be oonsidered first, is detected by the gate oontrol circuit 208. A marking signal is subsequently applied to the marking signal input 218 which is connected to the gate control circuits 208 and 209. ~-In reacti~n to the presence of the potential LTP on the output 202, the selection signal on input 217 and the narking signal on input 218, the gate circuit 208 decreases the potential of the control gates s of the cross-point circuits 204 and 205 from the potential GIP to GMP.
The input 200 has the potential LMP, with the result that the crosspoint circuit 204 is triggered and changes over to the oonductive state. As a result, the potential of output 202 PHN. 759g.
~039;~93 is increased from LTP to LMP. The gate control d rcuit 208 reacts thereto by adjusting the potential of the control gates of the crosspoint circuits 204 and 205 to GIP.
The continuity of the current through the cross-point circuit 204 is ensured by the current sour oe 210, 211 of the selected matrix switch of the next stage, in this case the matrix switch 104. mis current has a value such that the crosspoint circuit 204 remains conductive after the potential of the oontrol gate s has returned to GIP.
From output 202 of matrix switch 100 the poten-tial LMP is transferred to an input of the matrix switch 104 of the next stage, via the link oonductor 110. In this matrix switch the operation as described above for matrix switch 100 is repeated after application of a marking signal to the marking signal input 218 of matrix switch 104. Sub, sequently, this pro oedure is reFeated in matrix switch 106, after a marking signal has been applied to the marking signal input 21a thereof.
When the crossp~int circuit of a matrix switch of stage C beoomes conductive, it is to be noted that the potential of the transmission path decreases from L~P to LCP
due to the fact that the transistor 220 in the right-hand terminal circuit 219 beccmes conductive. Due to the decrease of the potential of the transmission path to LCP, no branch-ing can occur from this transmission path to other link con-ductors. Add-on on a busy link conductor is also precluded because such a o~nductor cannot assume the potential LTP.
The marking signal inputs 218 of the matrix PHN. 7599.
1039393 -:
switches of a given stage can be parallel oDnnected. This can be done because a gate control circuit can be activated only if also a selection signal is applied to the matrix switch.
The presence of the marking signal input enables a step-wise establishment of a transmission path, i.e. first in stage A, subsequently at a controlled instant in stage B, and subse-quently in stage C. However, the function of the marking signal can be combined with that of the selection signal. In that case, after the application of the selection signals to the selected matrix switches and the right-hand terminal cir-cuit and the closing of the switch 228 in the left-hand terminal circuit, the transmission path is switched through substantially simLltaneously in all stages.
me use of a separate marking signal input (which may be ccmmDn to all matrix switches per stage), -however, offers advantages if supervision of the establish-ment of a transmission path is desired, and if the switching netw~rk must also perform functions related to the searching -of free connection paths. --The matrix switch shcwn in Fig. 2 comprises a facility for testing link conductors as regards their being -free or busy, the said facility being usable, in conjunction with a central control unit, for searching free transmission paths, for testing the establishment of the oonnection and for traffic supervision.
When a matrix switch has been selected, the gate control circuits 208 and 209, detecting the potential LTP on the relevant output of the matrix switch, apply, via ,, ~ . . "., PHN. 7599-1039~93 the sense output circuit 215, a sense signal to the sense signal output 216. The sense signal outputs of the matrix switches of a given stage can be parallel aonnected. This may be done because a matrix switch can supply a sense sig-nal only if it has been selected. A sense signal appearing on the common sense signal output can then be directly related to the selected matrix switch.
The testing of the link a~nductors connected to the outputs of a matrix switch can be effected as follows.
The relevant matrix switch is selected and the matrix switches of the next stage are subsequently selected one after the other. As a result, the outputs of the first matrix switch which are connected to free link aonductors successively assume the potentials LTP. When it is noted at which selective matrix switch of the next stage the sense signal output of the relevant stage supplies a sense signal, the free outputs of the selected matrix switch of this stage can be determined.
The testing of the link conductors connected to the inputs of a matrix switch can be effected as follcws.
The matrix switch is selected, and subsequently the matrix switches of the preceding stage are selected one after the other. When it is noted at which selected matrix switches of this stage the sense signal output of this stage supplies a sense signal, the free inputs of the selected matrix switch of the relevant stage can be determLned.
The operation described above can be readily verified on the basis of Fig. 2 and Fig. 1, and will not be further elaborated herein.
, , ' , , ' P~IN. 7599.
A simple procedure for searching a free transmission path will be briefly described hereinafter.
m e right-hand terminal circuit of the transmission path is selected and subsequently the matrix switches of stage C are successively selected. It is noted which matrix switches supply a sense signal, and subsequently these matrix switches are simultaneously selected. (A
right-hand terminal circuit can be connected to a plurality of matrix switches of stage C). m e same is effected in stage B, and subsequently in stage A. me potential LTP
which is applied to the switching netw~rk by the right-hand terminal circuit, thus branches out through the switching netwDrk to the left-hand terminal circuits, where it can be detected. It can then be determined if the potential LTP
occurs in a given left-hand termunal circuit, or a left-hand terminal circuit can be determined in which the potential -LTP occurs.
After it has been determined that a free trans-mission path is available, a free transmission path must be selected from the various possibilities. Tb this end, the selection signals are rem~ved in a given stage, for example, starting with stage A, after which they are restored one after the other until the potential LTP is again detected in the left-hand terminal circuit. m e same process is re-peated in stage B and subsequently in stage C. The number of selected matrix switches in each stage is thus reduced to one, and the transmission path can be established in the manner described above.
, . ,, , " .:
PHN. 759g.
1039;~93 Fig. 5 adjaoently shows the symbol of an alternative version of a crosspoint circuit and the con-struction of this crosspoint circuit. m e symbol of Fig. 5a differs frcm that of Fig. 3a by the presen oe of a reference voltage input r. m e crosspoint circuit shown in Fig. 5 ccmprises, in addition to the pnpn transistor 500, tw~
cascade-connected transistors 501 and 502. The emitter of transistor 502 is connected, v a resistor 503, to a supply point 504 (+). m e control gate s is connected to the base of transistor 501, and the reference voltage input r is connected to the base of transistor 502. The latter acts as a source of constant current for transistor 501.
Fig. 6 shows the construction of a matrix switch comprising the crosspoint circuits of Fig. 5, parts corresponding to Fig. 2 being denoted by the same references.
In this embodiment the reference voltage inputs r of the crosspoint circuits 204 and 205 are connected to gate control circuit 208, and those of the crosspoint circuits 206 and 207 are connected to the gate control circuit 209.
It is to be noted that the functional behaviour of the crosspoint circuit of Fig. 5 does not differ from that of Fig. 3. The emtodlment of Fig. 5 offers advantages in view of the realization in integrated circuits and as regards the transmission properties.
Fig. 6 shows a second connection between the test oDntrol circuit 214 and the gate control circuits 208 and 209. m is additional connection is present in the practical circuit realization for the supply of a given ", , . . . .
PHN. 75g9.
1039~93 reference voltage to the gate control circuits.
Fig. 7 adjacently shows the circuits and their interconnections as shown in the lower part of Fig. 6, and a representation in which the gate control circuit 209 has been omitted. me connections to the gate control circuit 209 and any further gate oontrol circuits are represented in Fig. 7 by multiple signs.
Fig. 8 adjacently shows the sy~bol of the gate control circuit 214 (compare Fig. 7b) and an embodiment thereof. r me selection signal which is received on input (4) is applied, via the emitter follower Tl, to the difference voltage amplifier T2-T3. ~ -m e collector voltages of the transistors T2 and T3 are limited to +Vj (= junction voltage) by transistor T6 or to -2Vj by the transistors T7 and T8. m e level of the signals of the outputs (1) and (2) is OV ("1") or -3Vj ("O").
me output (2) is "1" in the presence of a selection signal on input (4); the output (1) is then "O". me potential applie to the diodes 210 and 211 (Fig. 6) by input (1) thus am~unts to CV or -3Vj, so that LIP = -Vj and LTP = -4Vj.
me transistors Tll, T13 and T14 in Fig. 8 serve as sources of oonstant current, and the transistor T12 serves as a voltage reference for these current sources.
Transistor T4 serves as a current source having the transis-tor T5 as a reference. m e transistors T9 and T10 serve as output stages. A reference v~ltage of 1.6 V is derived from PHN. 7599.
1039;~93 a voltage divider and is applied to output (3).
Fig. 9 adjacently shows the symbols of the gate control circuit 208 and the sense output circuit 215 (compare Fig. 7b) and an e~bodiment thereof.
The sense output circuit 215 is formed by the resistor RD and the transistor TO. The reference voltage of 1.6 V is applied to the input (4).
Different situations will yet be considered to explain the operation of the circuit of Fig. 9b.
1) when input (1) is "O" (-3Vj) or if input (1) is "1" (O V) and input (6) does not have the potential LTP (-4Vj) (Fig. 4), transistor Tl is not conductive and no sense signal appears on output (2). The point C is clamped to 12V - Vj by transistor T9, and the output (7) has the potential GIP = 12V-2Vj via transistor T7.
2) when input (1) is "1" (aV) and input (3) is "0" (oV) and input (6) has the potential LTP, a current flows via transistor Tl, resistor RD and transistor TO to the sense signal output (2).
A current also flows via transistor Tl, resis-tor Rl, transistor T2 and transistor T3, with the result that the output (7) remQins at the potential GIP.
PHN. 7599.
1039~93 to a gate control circuit which is connected to the vertical conductor.
Switching netwDrks for telecommunication exchanges may comprise electronic crosspoints such as four-layer diodes or four-layer transistors. Attempts are made to construct the electronic crosspoints and the ;
required control circuits in integrated form in ~ne semiconductor body. It is notably attempbed to accommodate one matrix switch together with the required control circuits, together referred to as matrix module, in one integrated unit (chip).
m e invention relates to the filed of the cir- ~-cuits for matrix modules which are suitable for realization in one integrated unit. A problem in this respect is to ~
minimize the number of terminals of the integratsd unit. --(2) Description of the state of the art. ~ ~
A crosspoint sub-system for integrated con- ~-struction is kncwn from Digest of Technical Papers, 1974, ~ International Solid-State Circuits Conference, pages 120, 121, 238. This sub-system comprises the crosspoints of one vertical of a matrix switch. me crosspoints are formed by four-layer transistors. me subsystem comprises one control input for the crosspoints, one test output, as many signal inputs as there are crosspoints, and one ~ -signal output. If a plurality of sub,systems are combined to form one matrix switch, there will be as many contr~l inputs and test outputs per matrix switch as there are sub-systems in a ~atrix switch. me number of terminals PHN. 7599.
of a matrix switch can then already become too large for matrix switches of small dimensions (limited number of verticals) so as to be realized in an integrated unit.
A matrix switch for integrated construction is known from IEF~ Transactions on Oommunications, Vol.
COM~22, No. 3, March 1974, pages 279-287. m e crosspoints are formed therein by four-layer transistors. The control gates of the crosspoints of a vertical are oonnected to a common gate control circuit, which is also connected to the vertical conductor. m e number of terminals of such a matrix switch is limited.
However, in a switching netw~rk incorporating such matrix switches it is difficult to realize the test procedures required in practice (before, during and after the establishment of the connection) and possibly also the searching and selection of free paths.
Summary of the invention The matrix module according to the invention is ch æacterized in that the matrix module comprises a selection signal input, accessible to a central control unit, and first means for deriving control signals frnm the selection signal input so as to control the gate control circuits therewith.
It is a further characteristic that the select-ion signal input has connected thereto a test control circuit for controlling, in reaction to a selection signal, test signal generators which are connected to the horizontal conductors.
PHN. 7599.
tO39~93 It is a further characteristic yet that the matrix module comprises a sense signal output, acoessible to the oe ntral control unit, and second means which are connected to the selection signal input and to the vertical conductos for controlling the sense signal output in the presence of a selection signal on the selection signal input and a free signal on at least one of the vertical conductors.
It is another characteristic that the matrix module ccmprises a marking signal input, accessible to the oe ntral control unit, and fourth means for deriving -- -control signals from the marking signal input in order to control the gate control circuits therewith, each gate control circuit comprising fifth means for forming the logic AND~function of the control signals originating from the first and fourth means and a test signal originating from the vertical conductor.
According to the first characteristic, each matrix mDdule ccmpriæs an input by means of which the matrix module can be selected; the gate control circuits will be activated only in a selected matrix module.
-, According to the second characteristic, the selection signal activates test signal generators which pass a test signal on to the horizontal conductors. In a multistage switch network this means that the selection of a matrix module causes test signals to be applied to the matrix nodules of the preceding switching stage vla the link condhctors.
PHN. 7599.
~039;~93 According to the third characteristic, the selection signal activates a sense signal output by means ;
of which it can be determined per matrix module whether a test signal appears on one of the vertical conductors.
According to the fourth eharacteristic, a marking signal is re~uired to activate the gate control circuits, with the result that test procedures can be performed independent of the establishment of connections.
It is to be noted that the selection signal input, the marking signal input, and the sense signal output may be different physical connections, but that the use of different voltage and/or current levels for -the various signals also enables the connection with the central contr~l unit to be established via one conductor.
A second aspect of the invention is formed by a multi-stage switching netw~rk. For this aspect of the invention, reference is made to the Claims.
Brief d~ cript;on of the Figures Figure 1 is a diagram of a mLlti-stage switching network.
Fig. 2 is a diagram of a matrix module accord-ing to the invention, shown between tw~ terminal circuits.
Fig. 3a shows the synbol of a crosspoint and Fig. 3b shows the diagram of an e~bodiment of the cross-point.
Fig. 4 shows a voltage diagram.
Fig. 5a shows the symbol of a crosspoint, and Fig. 5b shows the diagram of an e~bodi~ent of the cn~sspoint.
PHN. 759g.
1039;~93 ~ -Fig. 6 shows the diagram of a matrix module according to the invention, comprising crosspoints as shown in Fig. 5.
Fig. 7a shows the same as the lower part of Fig. 6, and Fig. 7b is a simplified representation of the same part.
Fig. 8a shows the test control circuit of Fig. 7b, and Fig. 8b shows the diagram of the electronic embodiment thereof.
Fig. 9a shows the gate control circuit and the sense output circuit of Fig. 7b, and Fig. 9b shows the diagram of the electronic embc~ ment of these circuits.
escriE ion: of the embodiments.
Fig. 1 shows a switching network camprising three stages A, B and C, each of which cc~prises a plurality of matrix switches, 100, 101 and 102 in stage A, 103, 104 and 105 in stage B, and 106, 107 and 108 in stage C. me stages ~--A, B and C are interconnected by link oDnductors, 109, 110 etc. be~ween the stages A and B, and 111, 112 etc. between ;~
the stages B and C. ~ -m e inputs of the matrix switches of stage A -have connected thereto terminal circuits 113, 114 etc., and the outputs of the matrix switches of stage C have connected --thereto termLnal circuits 115, 116 etc. The terms "input"
and "output" have no other significance then to make a distinction between the tw~ groups of connections of a matrix switch; they do not relate to the direction of the signal transmission or to the direction in which connections - -:-..
~ ' . ' : , , ' . ~ ,' :. ' , ' :'''` ' . ' ' .. . . . .
PHN. 7599.
1039;~93 are established. The terminal circuits 113, 114 etc. are referred to as left-hand terminal circuits for obvious reasons, and the terminal circuits 115, 116 are referred to as right-hand terminal circuits.
m e central part of Fig. 2 shows a matrix switch with the associated control circuits. The left-hand part of Fig. 2 shcws the essential parts of a left-hand terminal circuit, and the right-hand part of Fig. 2 shows the essential parts of a right-hand terminal circuit.
m e matrix switch shown in Fig. 2 comprises the inputs 200 and 201 and the outputs 202 and 203. Provided at the crosspoints between the inputs and the outputs are the crosspoint circuits 204, 205, 206 and 207. Each cross-point circuit is provided with an anode a, a cathcde k and a control gate s as shown in Fig. 2 for crosspoint circuit 204. The anodes of the crosspoint circuits are connected to the inputs of the matrix switch, and the cathodes are connected to the outputs of the matrix switch.
m e conLI~l gates of the crosspoint circuits 204 and 205 are connected to a gate oontrol circuit 208, and the oDntrol gates of the crosspoint circuits 206 and 207 are corn~cted to a gate control circuit 209. It is to be noted that the gate control circuit 208 is connected to the crosspoint circuits which are oonnected to output 202, and that the gate control circuit 209 is oonnected to the cross-point circuits which æe connected to output 203.
m e input 200 has connected thereto a source of constant current 210, whilst a source of const~nt current PHN. 7599.
1039~93 211 is oonnected to the input 201. Also connected to the in~ut 200 is a diode 212, whilst input 201 has connected thereto a diode 213. me diodes 212 and 213 are connected to test control circuit 214.
m e matrix switch furthermDre comprises a sense output circuit 215 which is connected to the gate control circuits 208 and 209, a sense signal output 216, a selection signal input 217 and a marking signal input 218.
m e right-hand terminal circuit 219 comprises a pnp transistor 220, the emitter of which is connected to an output of a matrix switch of stage C (oompare Fig. 1), its collector being connected to the signal output 221 and its base being connected to earth. me collector is -~
fur~hermDre connected, via a resistor 222, to a supply point 231 (-). me emitter has connected thereto a source of constant current 232 and a diode 233. m e diode is further-mare connected to a test control circuit 234 which is provided with a selection signal input 235. ;
The left-hand terminal circuit 223 comprises a ~
transistor 224, the collector of which is connected to an -input of a matrix switch of stage A (compare Fig. 1), its emitter being connected to a circuit which leads to a supply point 225 (+), its base being connected to a supply point -226 (+). me emitter circuit comprises a resistor 227, an (electronic) switch 228 which is controlled by a flipflop 229, and a signal generator 230. This signal generator represents the source of the signals which are to be trans-mitted, via a path through the switching network, to a _ g _ - . ; ~ , .
, .
' ' , , :,,,: , . : , PHN. 75g9, ~39~93 signal output of a right-hand terminal circuit.
me broken line between the output 202 of the matrix switch and the right-hand terminal circuit 219 may be considered as a symbolic representation of the presence of none, one or tWD stages of the switching netw~rk, depending on whether the matrix switch is situated in stage C, stage B or stage A. m e same applies to the broken line shcwn between left-hand terminal circuit 223 and the input 200 of the matrix switch.
It will be obvious that the description given with referenoe to the matrix switch shcwn is actually applicable to all matrix switches, no matter in what stage they are situated.
Fig. 3 adjacently shows the symbol of a cross point circuit and a feasible embodiment thereof. m is embod1ment is descrlbed in detail in U.S. Patent Specific~
ation 3,688,051, and will be descriked herein only in as far as is necessary for proper understanding of the present invention. me crosspoint circuit oomprises a pnpn transis-tor 300, a control transistor 301, and a current source 302. The collector of transistor 301 is oonnected to the n-region of the pnpn transistor which is situated on the anode side and which acts as a gate for triggering the pnpn transistor.
In the oondition in which the crosspoint circuit is not conductive and is not marked, the control gate s receives from the relevant gate control circuit (compare in Fig. 2 the gate control circuits 208 and 209) PHN. 7599.
1039~93 -a positive voltage which is denoted by GIP (gate idle p~tenr tial). m is GIP is more positive than any voltage liable to oocur in the switching netw~rk, and under these circumr stances the pnpn transistor is cut off. The control transis-tor 301 is then saturated and presents a low impedance to pnpn transistor 300. The collector current of control tran-sistor 301 equals the gate leakage current of pnpn transistor 300.
In order to trigger a crosspoint, a p~sitive voltage, denoted by L~P (link marking potential) and being slightly less positive than the ~1~, is applied to the anode a. A positive voltage, denoted by GMP and slightly less positive than the IMP, is applied to the control gate s. As a result, the voltage between the anode a and the con, -trol gate s of the marked crosspoint which was initially negative, reverses its sign and now beoomes positive. Cbn sequently, the gate current of the pnpn transistor reverses its ~irection and assumes a value such that the hold current -is reduced to zerD, with the result that the pnpn transistor constitutes substantially a short-circuit between the anode and the cathode. If it is ensured that in this condition a current of sufficient strength can flow between the anode and the cathode, the pnpn transistor remains conductive, also when the voltage of the oont;~l gate s is reduced to ~1~ and the transmission path (exteQdiDg via the crosspoint circuit) is kept at a positive voltage which is denoted by LCP (link connecting potential) and which is slightly less positive than the GMP.
., PHN. 7599 ~Q39~93 The mutual relationships between the above voltages and the regions in which these voltages are situated is illustrated in Fig. 4. This Figure also shows two negative voltages, iOe. a voltage denoted by LIP (link idle potential) and a voltage denoted by LTP (link test potential).
These voltages will be discussed hereinafter. In Fig. 4 the relationship of the value of the positive voltages is denoted by a number of +signs, i.e. the nu~ber of +signs is larger as the voltage is higher. The same applies to the negative voltages.
As is shown in Fig. 2, each matrix switch comprises a selection signal input 217. The matrix switch can be selected by means of the selection signal input. The selection signal inputs are generally indicated in Fig. 1.
Let it be assumed first that the route followed by a tranæmission path through the switching network is known, so that it is kncwn via which matrix switches the transmission path extends. Let us consider, by way of example, a transmission path extending between the terminal circuits 113 and 115 via the matrix switches 100, 104 and 106.
The establishment of the transmission path will be described in detail hereinafter with reference to Fig. 2, in which the terminal circuit 223 will be taken as a representa-tive of the terminal circuit 113, the terminal circuit 219 as a repre æntative of the terminal circuit 115, and the matrix switch successively as the representative of the matrix switches 100, 104 and 106.
The switch 228 in the terminal circuit 223 PHN. 7599.
~039;~93 is closed by suitable control of flipflop 229, with the result that transistor 224 is saturated and the collector assu~es the voltage of the supply point 226. m e input 200 of matrix switch 100, consequently, re oe ives the p~tential S LMP. me continuity of the collector current of transistor 224 is ensured by the current source 210. m e diode 212 is blocked in these circumstances.
me selection signal input 217 of ~he matrix switches 100, 104 and 106 and the selection signal input 235 of terminal circuit 115 receive a selection signal which activates various circuits in the matrix switches and the terminal circuit. First of all, the test control circuits 214, 234 are made to reduce the clamp potential LIP +Vj (Vj is the junction vDltage) applied to the diode to LTP +Vj (compare Fig. 4). Secondly, the gate control circuits 208 and 209 which are oonnect~d to the test control circuit 214 ,~.
are set to the state in which they are sensitive to the potential L~P on the relevant output of the matrix switch.
me operation of the current sources 210, 211 -and the diodes 212, 213 and the test control circuit 214 will be described hereinafter.
m e current source 210 and the diode 212 together constitute a test signal generator 210-212; a test signal generator 211-213 is similarly formed by the current source 211 and the diode 213.
When the test circuit 214 applies the potential - -LIP +Vj to the conductors 212 and 213, the inputs 200 and 201 cannot have a potential which is lower than LIP. An .
PHN. 7599.
1039;~93 input which does not form part of a completely or partly established transmission path, and hence is free, will assume the potential LIP.
A link oonductor which is busy has the potential TrP or L~P.
When test circuit 214 applieQ the potential LTP + Vj to the diodes 212 and 213, the inputs 200 and 201 will assume the potential LTP only if they are free. mis potential, indicating that an input is free, constitutes a so~termed "free signal" which is one of the possible output signals of the said test signal generators 210-212, 211-213.
For example, if the input 200 is busy and test control cir-cuit 214 applies the potential LTP +Vj to diode 212, the diode 212 will remain blocked (at the given polarity) because the potential of input 200 is ICP or LMP and because this potential is more positive than LTP. m e switching over of the potential by the test control circuit, oonsequently has no effect whatsoever on busy inputs.
It is to be noted that, when input 200 is busy, the current source 210 makes!a contribution to the current in the transmission path incorporating input 200. This contribution, hcwever, is constant and is not influenced by the test contr~l circuit 214, so that it has no disturbing effect whatsoever.
m e gate control circuits of the selected matrix switch in the preceding stage are in the state in which they were sensitive to the potential LTP. Because the link conductor oonnecting matrix switch 106 to matrix switch PHN. 7599 ~039~
104 and the link oonductor oonnecting matrix switch 104 to matrix switch 100 are assumed to be free, these link conductors will assume the potential LTP. Furtherm~re, the output of matrix switch 106 connected to terminal circuit 115 receives the potential LTP from this terminal circuit.
In the switching network the potential LTP is thus adjusted on the link conductors and on the output of the desired transmission path, and the potential LMP is adjusted on the input of the transmission path. In each of -the selected matrix switches 100, 104 and 106 the gate oon-trol circuits 208 and 209 have been made sensitive to the potential LTP, and one of these gate control circuits actually detects the potential LTP on an output of the matrix switch.
It will be assumed that this is the output 202 of the matrix ~ -switch shcwn in Fig. 2.
The potential LTP on the output 202 of matrix switch 100, the operation of which will be oonsidered first, is detected by the gate oontrol circuit 208. A marking signal is subsequently applied to the marking signal input 218 which is connected to the gate control circuits 208 and 209. ~-In reacti~n to the presence of the potential LTP on the output 202, the selection signal on input 217 and the narking signal on input 218, the gate circuit 208 decreases the potential of the control gates s of the cross-point circuits 204 and 205 from the potential GIP to GMP.
The input 200 has the potential LMP, with the result that the crosspoint circuit 204 is triggered and changes over to the oonductive state. As a result, the potential of output 202 PHN. 759g.
~039;~93 is increased from LTP to LMP. The gate control d rcuit 208 reacts thereto by adjusting the potential of the control gates of the crosspoint circuits 204 and 205 to GIP.
The continuity of the current through the cross-point circuit 204 is ensured by the current sour oe 210, 211 of the selected matrix switch of the next stage, in this case the matrix switch 104. mis current has a value such that the crosspoint circuit 204 remains conductive after the potential of the oontrol gate s has returned to GIP.
From output 202 of matrix switch 100 the poten-tial LMP is transferred to an input of the matrix switch 104 of the next stage, via the link oonductor 110. In this matrix switch the operation as described above for matrix switch 100 is repeated after application of a marking signal to the marking signal input 218 of matrix switch 104. Sub, sequently, this pro oedure is reFeated in matrix switch 106, after a marking signal has been applied to the marking signal input 21a thereof.
When the crossp~int circuit of a matrix switch of stage C beoomes conductive, it is to be noted that the potential of the transmission path decreases from L~P to LCP
due to the fact that the transistor 220 in the right-hand terminal circuit 219 beccmes conductive. Due to the decrease of the potential of the transmission path to LCP, no branch-ing can occur from this transmission path to other link con-ductors. Add-on on a busy link conductor is also precluded because such a o~nductor cannot assume the potential LTP.
The marking signal inputs 218 of the matrix PHN. 7599.
1039393 -:
switches of a given stage can be parallel oDnnected. This can be done because a gate control circuit can be activated only if also a selection signal is applied to the matrix switch.
The presence of the marking signal input enables a step-wise establishment of a transmission path, i.e. first in stage A, subsequently at a controlled instant in stage B, and subse-quently in stage C. However, the function of the marking signal can be combined with that of the selection signal. In that case, after the application of the selection signals to the selected matrix switches and the right-hand terminal cir-cuit and the closing of the switch 228 in the left-hand terminal circuit, the transmission path is switched through substantially simLltaneously in all stages.
me use of a separate marking signal input (which may be ccmmDn to all matrix switches per stage), -however, offers advantages if supervision of the establish-ment of a transmission path is desired, and if the switching netw~rk must also perform functions related to the searching -of free connection paths. --The matrix switch shcwn in Fig. 2 comprises a facility for testing link conductors as regards their being -free or busy, the said facility being usable, in conjunction with a central control unit, for searching free transmission paths, for testing the establishment of the oonnection and for traffic supervision.
When a matrix switch has been selected, the gate control circuits 208 and 209, detecting the potential LTP on the relevant output of the matrix switch, apply, via ,, ~ . . "., PHN. 7599-1039~93 the sense output circuit 215, a sense signal to the sense signal output 216. The sense signal outputs of the matrix switches of a given stage can be parallel aonnected. This may be done because a matrix switch can supply a sense sig-nal only if it has been selected. A sense signal appearing on the common sense signal output can then be directly related to the selected matrix switch.
The testing of the link a~nductors connected to the outputs of a matrix switch can be effected as follows.
The relevant matrix switch is selected and the matrix switches of the next stage are subsequently selected one after the other. As a result, the outputs of the first matrix switch which are connected to free link aonductors successively assume the potentials LTP. When it is noted at which selective matrix switch of the next stage the sense signal output of the relevant stage supplies a sense signal, the free outputs of the selected matrix switch of this stage can be determined.
The testing of the link conductors connected to the inputs of a matrix switch can be effected as follcws.
The matrix switch is selected, and subsequently the matrix switches of the preceding stage are selected one after the other. When it is noted at which selected matrix switches of this stage the sense signal output of this stage supplies a sense signal, the free inputs of the selected matrix switch of the relevant stage can be determLned.
The operation described above can be readily verified on the basis of Fig. 2 and Fig. 1, and will not be further elaborated herein.
, , ' , , ' P~IN. 7599.
A simple procedure for searching a free transmission path will be briefly described hereinafter.
m e right-hand terminal circuit of the transmission path is selected and subsequently the matrix switches of stage C are successively selected. It is noted which matrix switches supply a sense signal, and subsequently these matrix switches are simultaneously selected. (A
right-hand terminal circuit can be connected to a plurality of matrix switches of stage C). m e same is effected in stage B, and subsequently in stage A. me potential LTP
which is applied to the switching netw~rk by the right-hand terminal circuit, thus branches out through the switching netwDrk to the left-hand terminal circuits, where it can be detected. It can then be determined if the potential LTP
occurs in a given left-hand termunal circuit, or a left-hand terminal circuit can be determined in which the potential -LTP occurs.
After it has been determined that a free trans-mission path is available, a free transmission path must be selected from the various possibilities. Tb this end, the selection signals are rem~ved in a given stage, for example, starting with stage A, after which they are restored one after the other until the potential LTP is again detected in the left-hand terminal circuit. m e same process is re-peated in stage B and subsequently in stage C. The number of selected matrix switches in each stage is thus reduced to one, and the transmission path can be established in the manner described above.
, . ,, , " .:
PHN. 759g.
1039;~93 Fig. 5 adjaoently shows the symbol of an alternative version of a crosspoint circuit and the con-struction of this crosspoint circuit. m e symbol of Fig. 5a differs frcm that of Fig. 3a by the presen oe of a reference voltage input r. m e crosspoint circuit shown in Fig. 5 ccmprises, in addition to the pnpn transistor 500, tw~
cascade-connected transistors 501 and 502. The emitter of transistor 502 is connected, v a resistor 503, to a supply point 504 (+). m e control gate s is connected to the base of transistor 501, and the reference voltage input r is connected to the base of transistor 502. The latter acts as a source of constant current for transistor 501.
Fig. 6 shows the construction of a matrix switch comprising the crosspoint circuits of Fig. 5, parts corresponding to Fig. 2 being denoted by the same references.
In this embodiment the reference voltage inputs r of the crosspoint circuits 204 and 205 are connected to gate control circuit 208, and those of the crosspoint circuits 206 and 207 are connected to the gate control circuit 209.
It is to be noted that the functional behaviour of the crosspoint circuit of Fig. 5 does not differ from that of Fig. 3. The emtodlment of Fig. 5 offers advantages in view of the realization in integrated circuits and as regards the transmission properties.
Fig. 6 shows a second connection between the test oDntrol circuit 214 and the gate control circuits 208 and 209. m is additional connection is present in the practical circuit realization for the supply of a given ", , . . . .
PHN. 75g9.
1039~93 reference voltage to the gate control circuits.
Fig. 7 adjacently shows the circuits and their interconnections as shown in the lower part of Fig. 6, and a representation in which the gate control circuit 209 has been omitted. me connections to the gate control circuit 209 and any further gate oontrol circuits are represented in Fig. 7 by multiple signs.
Fig. 8 adjacently shows the sy~bol of the gate control circuit 214 (compare Fig. 7b) and an embodiment thereof. r me selection signal which is received on input (4) is applied, via the emitter follower Tl, to the difference voltage amplifier T2-T3. ~ -m e collector voltages of the transistors T2 and T3 are limited to +Vj (= junction voltage) by transistor T6 or to -2Vj by the transistors T7 and T8. m e level of the signals of the outputs (1) and (2) is OV ("1") or -3Vj ("O").
me output (2) is "1" in the presence of a selection signal on input (4); the output (1) is then "O". me potential applie to the diodes 210 and 211 (Fig. 6) by input (1) thus am~unts to CV or -3Vj, so that LIP = -Vj and LTP = -4Vj.
me transistors Tll, T13 and T14 in Fig. 8 serve as sources of oonstant current, and the transistor T12 serves as a voltage reference for these current sources.
Transistor T4 serves as a current source having the transis-tor T5 as a reference. m e transistors T9 and T10 serve as output stages. A reference v~ltage of 1.6 V is derived from PHN. 7599.
1039;~93 a voltage divider and is applied to output (3).
Fig. 9 adjacently shows the symbols of the gate control circuit 208 and the sense output circuit 215 (compare Fig. 7b) and an e~bodiment thereof.
The sense output circuit 215 is formed by the resistor RD and the transistor TO. The reference voltage of 1.6 V is applied to the input (4).
Different situations will yet be considered to explain the operation of the circuit of Fig. 9b.
1) when input (1) is "O" (-3Vj) or if input (1) is "1" (O V) and input (6) does not have the potential LTP (-4Vj) (Fig. 4), transistor Tl is not conductive and no sense signal appears on output (2). The point C is clamped to 12V - Vj by transistor T9, and the output (7) has the potential GIP = 12V-2Vj via transistor T7.
2) when input (1) is "1" (aV) and input (3) is "0" (oV) and input (6) has the potential LTP, a current flows via transistor Tl, resistor RD and transistor TO to the sense signal output (2).
A current also flows via transistor Tl, resis-tor Rl, transistor T2 and transistor T3, with the result that the output (7) remQins at the potential GIP.
3) when input (1) is "1" (aV) and input (3) is "1" ( 7 3.1V), and input (6) has the potential LTP
(-4Vj), a curr~.L flows via transistor Tl, resistor RD and transistor TO to the sense signal output (2).
A current also flows via transistor Tl, resistor Rl, transistor T2 and transistor T4. This current dominates PHN. 7599.
1039~93 the collector current of the transistor T10 which acts as a current source, with the result that the potential of Fint C is clamFed to 5V +Vj, determined by the transistors T8 and T6. There are ncw two possibilities for the output (7).
a) none of the crosspoints connected to output (7) receives the potential LMP on its anode. m e output (7) is then at the potential GMP = 5V+Vj, determined by the transistors T8 and T6.
b) the potential LMP is present on the anode of one of the crosspoint circuits connected to the output (7). me crosspoint circuit is then triggered and a current flows via the output (7). m e current flowing via output (7) is limited by transistor T5, and the output (7) receives ;-the potential LMP -2Vj via the crosspoint circuit. m e crosspoint circuit beoo~es conductive and the input (6) receives the potential LMP, with the result that transistor Tl interrupts the current flcwing via sense signal output (2). me transistors T2 and T4 also become currentless, with the result that output (7) returns to the potential GIP.
The output (8) has a potential of 12V-Vj via transistor Tll, which serves as a referenoe voltage for the crosspoint circuits and for the transistor T10 which acts as a current souroe.
(-4Vj), a curr~.L flows via transistor Tl, resistor RD and transistor TO to the sense signal output (2).
A current also flows via transistor Tl, resistor Rl, transistor T2 and transistor T4. This current dominates PHN. 7599.
1039~93 the collector current of the transistor T10 which acts as a current source, with the result that the potential of Fint C is clamFed to 5V +Vj, determined by the transistors T8 and T6. There are ncw two possibilities for the output (7).
a) none of the crosspoints connected to output (7) receives the potential LMP on its anode. m e output (7) is then at the potential GMP = 5V+Vj, determined by the transistors T8 and T6.
b) the potential LMP is present on the anode of one of the crosspoint circuits connected to the output (7). me crosspoint circuit is then triggered and a current flows via the output (7). m e current flowing via output (7) is limited by transistor T5, and the output (7) receives ;-the potential LMP -2Vj via the crosspoint circuit. m e crosspoint circuit beoo~es conductive and the input (6) receives the potential LMP, with the result that transistor Tl interrupts the current flcwing via sense signal output (2). me transistors T2 and T4 also become currentless, with the result that output (7) returns to the potential GIP.
The output (8) has a potential of 12V-Vj via transistor Tll, which serves as a referenoe voltage for the crosspoint circuits and for the transistor T10 which acts as a current souroe.
Claims (11)
1. A matrix module, comprising electronic cross-point elements which are arranged at crosspoints of two groups of conductors, separately denoted as horizontal and vertical conductors, and which are each provided with a first main electrode connected to the horizontal conductor and a second main electrode connected to the vertical con-ductor and also with a control gate, the control gates of the crosspoint elements connected to the same vertical con-ductor being connected to a gate control circuit which is connected to the vertical conductor, characterized in that the matrix module comprises a selection signal input, accessible to a central control unit, and first means for deriving control signals from the selection signal input so as to control the gate control circuits therewith.
2. A matrix module as claimed in Claim 1, charac-terized in that the selection signal input has connected thereto a test control circuit for controlling, in reaction to a selection signal, test signal generators which are con-nected to the horizontal conductors.
3. A matrix module as claimed in Claim 1, charac-terized in that the matrix module comprises a sense signal output, accessible to the central control unit, and second means which are connected to the selection signal input and to the vertical conductors for controlling the sense signal output in the presence of a selection signal on the selection signal input and a free signal on at least one of the vertical conductors.
4. A matrix module as claimed in Claim 3, charac-terized in that the said second means camprise test signal discriminators in the gate control circuits and third means for deriving control signals from the selection sig-nal input in order to control therewith a common sense output circuit which is connected to the said test signal discriminators.
5. A matrix module as claimed in Claim 2, charac-terized in that each of the test signal generators comprises a source of constant current which is connected to the hori-zontal conductor and a clamp circuit with controllable clamp voltage which is also connected to the horizontal conductor.
6. A matrix module as claimed in Claim 1, charac-terized in that the matrix module comprises a marking signal input, accessible to the central control unit, and fourth means for deriving control signals from the marking signal input in order to control the gate control circuits therewith, each gate control circuit comprising fifth means for forming the logic AND-function of the control signals originating from the first and fourth means and a free signal originating from the vertical conductor.
7. A matrix module as claimed in Claim 6, charac-terized in that each gate control circuit comprises sixth means for deriving control signals from the fifth means in order to control the control gates therewith.
8. A multi-stage switching network comprising a number of switching stages which are interconnected by link conductors, each switching stage comprising a plurality of matrix modules, each matrix module comprising electronic crosspoint elements which are arranged at crosspoints of two groups of conductors which are separately denoted as horizontal and vertical conductors, each of the said crosspoint elements being provided with a first main elec-trode which is connected to the horizontal conductor and a second main electrode which is connected to the vertical conductor, and with a control gate, the control gates of the crosspoint elements which are connected to the same vertical conductor being connected to a gate control cir-cuit which is connected to the vertical conductor, charac-terized in that each matrix module comprises an individual selection signal input, selectively accessible for a central control unit, and first means for deriving control signals from the selection signal input in order to control the gate control circuits therewith.
9. A multi-stage switching network as claimed in Claim 8, characterized in that each matrix module comprises a sense signal output which is accessible to the central control unit, each matrix module also comprising second means which are connected to the control signal input and the verti-cal conductors in order to control the sense signal output in the presence of a selection signal on the selection signal input and a free signal on at least one of the vertical con-ductors.
10. A multi-stage switching network as claimed in Claim 8, characterized in that each matrix module comprises a marking signal input which is accessible to the central control unit, each matrix module comprising fourth means for deriving control signals from the marking signal input in order to control the gate control circuits therewith, each gate control circuit comprising fifth means for forming the logic AND-function of the control signals originating from the first and fourth means and a free signal originating from the vertical conductor.
11. A multi-stage switching network as claimed in Claim 8, characterized in that the horizontal conductors of the matrix modules of each of the switching stages and the vertical conductors of the matrix modules of the last switch-ing stage have connected thereto controllable test signal generators.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL7408823A NL7408823A (en) | 1974-07-01 | 1974-07-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1039393A true CA1039393A (en) | 1978-09-26 |
Family
ID=19821661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA230,207A Expired CA1039393A (en) | 1974-07-01 | 1975-06-26 | Matrix module and switching network |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US3928730A (en) |
| JP (1) | JPS5810037B2 (en) |
| CA (1) | CA1039393A (en) |
| DE (1) | DE2528741C2 (en) |
| FR (1) | FR2277485A1 (en) |
| GB (1) | GB1503540A (en) |
| NL (1) | NL7408823A (en) |
| SE (1) | SE413969B (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5169908A (en) * | 1974-12-16 | 1976-06-17 | Hitachi Ltd | Tsuwaromono seigyohoshiki |
| US4110566A (en) * | 1977-10-27 | 1978-08-29 | Bell Telephone Laboratories, Incorporated | Switching network control arrangement |
| JPS56104537A (en) * | 1980-01-23 | 1981-08-20 | Nec Corp | Switch matrix device |
| US4417245A (en) * | 1981-09-02 | 1983-11-22 | International Business Machines Corp. | Digital space division exchange |
| JPS5958364U (en) * | 1982-10-12 | 1984-04-16 | 日新製鋼株式会社 | Molten metal probe |
| US4803720A (en) * | 1986-09-22 | 1989-02-07 | International Business Machines Corporation | Dual plane cross point switch architecture for a micro-PBX |
| US5329470A (en) * | 1988-12-02 | 1994-07-12 | Quickturn Systems, Inc. | Reconfigurable hardware emulation system |
| US5109353A (en) * | 1988-12-02 | 1992-04-28 | Quickturn Systems, Incorporated | Apparatus for emulation of electronic hardware system |
| US5175539A (en) * | 1989-01-24 | 1992-12-29 | Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V. | Interconnecting network |
| US5369593A (en) * | 1989-05-31 | 1994-11-29 | Synopsys Inc. | System for and method of connecting a hardware modeling element to a hardware modeling system |
| US5353243A (en) * | 1989-05-31 | 1994-10-04 | Synopsys Inc. | Hardware modeling system and method of use |
| US5680583A (en) * | 1994-02-16 | 1997-10-21 | Arkos Design, Inc. | Method and apparatus for a trace buffer in an emulation system |
| US5784003A (en) * | 1996-03-25 | 1998-07-21 | I-Cube, Inc. | Network switch with broadcast support |
| US5841967A (en) * | 1996-10-17 | 1998-11-24 | Quickturn Design Systems, Inc. | Method and apparatus for design verification using emulation and simulation |
| US5960191A (en) | 1997-05-30 | 1999-09-28 | Quickturn Design Systems, Inc. | Emulation system with time-multiplexed interconnect |
| US5970240A (en) * | 1997-06-25 | 1999-10-19 | Quickturn Design Systems, Inc. | Method and apparatus for configurable memory emulation |
| US7590503B2 (en) * | 2003-08-15 | 2009-09-15 | Broadcom Corporation | Method and system for rerouteable cyclic redundancy check sum (CRC) for different sources |
| KR101492764B1 (en) | 2005-09-26 | 2015-02-12 | 맥스위치 테크놀로지 월드와이드 피티와이 리미티드 | Magnet arrays |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2071181A6 (en) * | 1969-12-19 | 1971-09-17 | Labo Cent Telecommunicat | |
| US3828314A (en) * | 1971-02-03 | 1974-08-06 | Wescom | End mark controlled switching system and matrix |
-
1974
- 1974-07-01 NL NL7408823A patent/NL7408823A/xx not_active Application Discontinuation
- 1974-10-10 US US513547A patent/US3928730A/en not_active Expired - Lifetime
-
1975
- 1975-06-20 GB GB26310/75A patent/GB1503540A/en not_active Expired
- 1975-06-26 CA CA230,207A patent/CA1039393A/en not_active Expired
- 1975-06-27 DE DE2528741A patent/DE2528741C2/en not_active Expired
- 1975-06-27 SE SE7507375A patent/SE413969B/en unknown
- 1975-06-28 JP JP50079748A patent/JPS5810037B2/en not_active Expired
- 1975-07-01 FR FR7520614A patent/FR2277485A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2277485B1 (en) | 1982-01-22 |
| JPS5810037B2 (en) | 1983-02-23 |
| JPS5119426A (en) | 1976-02-16 |
| US3928730A (en) | 1975-12-23 |
| SE7507375L (en) | 1976-01-02 |
| DE2528741A1 (en) | 1976-01-22 |
| DE2528741C2 (en) | 1982-12-16 |
| NL7408823A (en) | 1974-09-25 |
| GB1503540A (en) | 1978-03-15 |
| FR2277485A1 (en) | 1976-01-30 |
| SE413969B (en) | 1980-06-30 |
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