CA1063673A - Four-layer semiconductor switch - Google Patents
Four-layer semiconductor switchInfo
- Publication number
- CA1063673A CA1063673A CA262,388A CA262388A CA1063673A CA 1063673 A CA1063673 A CA 1063673A CA 262388 A CA262388 A CA 262388A CA 1063673 A CA1063673 A CA 1063673A
- Authority
- CA
- Canada
- Prior art keywords
- transistor
- emitter
- switch
- cathode
- pnpn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/72—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
- H03K17/73—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region for dc voltages or currents
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/08124—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in thyristor switches
Abstract
ABSTRACT OF THE DISCLOSURE
A stable semiconductor switch comprising a PNPN switch, a transistor, a driving device, and diodes.
The PNPN switch is composed of four-layered PNPN structure and has three PN-junctions, an anode, an anode gate, a cathode gate, and a cathode. The collector and the emitter of the transistor are connected to the cathode gate and the cathode of the PNPN switch, respectively. The driving device has its one end connected to the anode gate of the PNPN switch and its other end connected to the base of the transistor so as to drive the transistor in transient state.
The diodes are connected between the driving device and the emitter of the transistor in a manner so that, when the PNPN switch is controlled to fire and a back current tends to flow through the PNPN switch temporarily, the back current does not flow through the transistor so as to prevent the transistor from causing any abnormal actions such as oscillation.
A stable semiconductor switch comprising a PNPN switch, a transistor, a driving device, and diodes.
The PNPN switch is composed of four-layered PNPN structure and has three PN-junctions, an anode, an anode gate, a cathode gate, and a cathode. The collector and the emitter of the transistor are connected to the cathode gate and the cathode of the PNPN switch, respectively. The driving device has its one end connected to the anode gate of the PNPN switch and its other end connected to the base of the transistor so as to drive the transistor in transient state.
The diodes are connected between the driving device and the emitter of the transistor in a manner so that, when the PNPN switch is controlled to fire and a back current tends to flow through the PNPN switch temporarily, the back current does not flow through the transistor so as to prevent the transistor from causing any abnormal actions such as oscillation.
Description
1~63673 1 The present invention relates to a semiconductor switch of a PNPN eour-layered equivalent structure with three PN-junctions used as a switching element for a control apparatus and the like.
~ig. 1 is a circuit diagram of a semiconductor switch including a PNPN switch which is provided with well-known countermeasures against dv/dt, effect.
Fig. 2 is a circuit diagram of a semiconductor switch which has already been proposed by the present inventors and is most analogous to that according to the present invention.
Figs. 3 and 4 respectively show an equivalent . circuit diagram representing the case where the semi-`, conductor switch shown in Fig. 2 is applied for a telephone exchange, and waveforms representing voltage and current variations wlth time.
, ~ig. 5 is a circuit diagram showing a first ,. , embodiment of the semiconductor switch according to ~, the present invention.
~, 20 Figs. 6 to 13 are circuit diagrams respectively showing second to ninth embodiments of the semiconductor switch according to the present invention.
Generally, a PNPN switch o-f a PNPN four~layered , t, équivalen-t structure including three PN junctions i. .
(hereinafter referred to merely as the "PNPN switch") called an ~R or thyristor has a disadvantage that it ,~
is erroneously fired in response to a forward voltage ~ abrupt]y applied between the anode and cathode thereo:
3, even during the cut-off state. This is called a rate ~0 effect and a countermeasure against it is re-ferred to , - 1 ~ ' .~ .
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~i3~3 1 as dt-immunity. A method generally employed to prevent this erroneous firlng is to shunt the gate G and the cathode K of the PNP~ switch 1 by means of a resistor 2 as shown in Fig. 1. In case of improving the dVt i~unity by the method shown in ~ig. 1, it will be necessary to set the resistor 2 at a low resistance value. This naturally reduces the gate sensitivity, thus making the method of Fig. 1 quite useless for some applications.
In order to obviate this shortcoming, the applicants earlier suggested a semiconductor switch of ~ig. 2 in which both the dv/dt-immunity and the gate-sensitivity are remarkably improved. In the semiconductor switch of ~ig. 2, another P-type region P3 is formed in the second layer nl of the P~PN switch 11, thus forming a couple of collectors P2 and P3. The base of transistor 13 between the gate G and the cathode K is connected to the P region through a level shift diode 14. A
- resistor 12 is inserted between the gate G and the cathode K, whlle a diode 15 is connected between -the base and emitter of the transistor 13. When a voltage .. : , .
is abruptly applied between the anode A and the cathode K of the PNPN switch 11, the current for charging the .,~
PN-junction formed by the nl layer and the P~ region is utilized to drive the transistor 13, so that the ~ 25 gate G and the cathode K of the P~P~ switch 11 are ; short-circuited in the transient s-tate so as to prevent -the erroneous firing of the P~PN switch 11. The resistor 12, which is inserted as an auxiliary element for prevention of erroneous firing of the PNPN switch, which otherwise might occur due to the leakage current
~ig. 1 is a circuit diagram of a semiconductor switch including a PNPN switch which is provided with well-known countermeasures against dv/dt, effect.
Fig. 2 is a circuit diagram of a semiconductor switch which has already been proposed by the present inventors and is most analogous to that according to the present invention.
Figs. 3 and 4 respectively show an equivalent . circuit diagram representing the case where the semi-`, conductor switch shown in Fig. 2 is applied for a telephone exchange, and waveforms representing voltage and current variations wlth time.
, ~ig. 5 is a circuit diagram showing a first ,. , embodiment of the semiconductor switch according to ~, the present invention.
~, 20 Figs. 6 to 13 are circuit diagrams respectively showing second to ninth embodiments of the semiconductor switch according to the present invention.
Generally, a PNPN switch o-f a PNPN four~layered , t, équivalen-t structure including three PN junctions i. .
(hereinafter referred to merely as the "PNPN switch") called an ~R or thyristor has a disadvantage that it ,~
is erroneously fired in response to a forward voltage ~ abrupt]y applied between the anode and cathode thereo:
3, even during the cut-off state. This is called a rate ~0 effect and a countermeasure against it is re-ferred to , - 1 ~ ' .~ .
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~i3~3 1 as dt-immunity. A method generally employed to prevent this erroneous firlng is to shunt the gate G and the cathode K of the PNP~ switch 1 by means of a resistor 2 as shown in Fig. 1. In case of improving the dVt i~unity by the method shown in ~ig. 1, it will be necessary to set the resistor 2 at a low resistance value. This naturally reduces the gate sensitivity, thus making the method of Fig. 1 quite useless for some applications.
In order to obviate this shortcoming, the applicants earlier suggested a semiconductor switch of ~ig. 2 in which both the dv/dt-immunity and the gate-sensitivity are remarkably improved. In the semiconductor switch of ~ig. 2, another P-type region P3 is formed in the second layer nl of the P~PN switch 11, thus forming a couple of collectors P2 and P3. The base of transistor 13 between the gate G and the cathode K is connected to the P region through a level shift diode 14. A
- resistor 12 is inserted between the gate G and the cathode K, whlle a diode 15 is connected between -the base and emitter of the transistor 13. When a voltage .. : , .
is abruptly applied between the anode A and the cathode K of the PNPN switch 11, the current for charging the .,~
PN-junction formed by the nl layer and the P~ region is utilized to drive the transistor 13, so that the ~ 25 gate G and the cathode K of the P~P~ switch 11 are ; short-circuited in the transient s-tate so as to prevent -the erroneous firing of the P~PN switch 11. The resistor 12, which is inserted as an auxiliary element for prevention of erroneous firing of the PNPN switch, which otherwise might occur due to the leakage current
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~6i3673 1 at a high temperature, may have a resistance value much higher than the resistor 2 in Fig. 1, thus making possible the high dv/dt-immunity as well as the hig~h gate-sensitivity of the PNPN switch. The level shift diode 14 is provided for preventing an abnormal increase in the holding current whlch o:therwise mlght be caused by the energization of the transistor 13 since the P3 region acts as the collector of the PNP transistor comprising the Pl, nl and P3 regions when the PNPN switch 11 is driven to fire. The diode 15 is inserted for the purpose of preventing the base of the transistor 13 from being subjected to a large negative potential in response to the dlscharge of charges stored in the -PN-junctlon made up of the nl layer and the P3 region.
This construction has an effect similar to that obtained by shunting the base and the emitter of the transistor ` 13 with a resistor and is suitable for the circuit integration. The semiconductor switch shown in Fig. 2 has a shortcoming that it may cause oscillation in special applications such as a telephone exchange.
- In Fig. 3 is shown a typical exchange process in the telephone exchange system to which the sernl-conductor switch of Fig. 2 is applied. The anode A
of the PNPN switch 11 is connected with a constant-current circuit 16 and a capacitor 17, while the cathode K
thereof is connected with a series circuit of a coil 18, a resistor 19 and a battery 20. Whcn the gate G
~, is driven continuously by another constant-curren-t circuit 21, an oscillation as shown in Fig. ~ occurs, resulting in an intermittent conduction of the PNPN
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~6i3673 1 at a high temperature, may have a resistance value much higher than the resistor 2 in Fig. 1, thus making possible the high dv/dt-immunity as well as the hig~h gate-sensitivity of the PNPN switch. The level shift diode 14 is provided for preventing an abnormal increase in the holding current whlch o:therwise mlght be caused by the energization of the transistor 13 since the P3 region acts as the collector of the PNP transistor comprising the Pl, nl and P3 regions when the PNPN switch 11 is driven to fire. The diode 15 is inserted for the purpose of preventing the base of the transistor 13 from being subjected to a large negative potential in response to the dlscharge of charges stored in the -PN-junctlon made up of the nl layer and the P3 region.
This construction has an effect similar to that obtained by shunting the base and the emitter of the transistor ` 13 with a resistor and is suitable for the circuit integration. The semiconductor switch shown in Fig. 2 has a shortcoming that it may cause oscillation in special applications such as a telephone exchange.
- In Fig. 3 is shown a typical exchange process in the telephone exchange system to which the sernl-conductor switch of Fig. 2 is applied. The anode A
of the PNPN switch 11 is connected with a constant-current circuit 16 and a capacitor 17, while the cathode K
thereof is connected with a series circuit of a coil 18, a resistor 19 and a battery 20. Whcn the gate G
~, is driven continuously by another constant-curren-t circuit 21, an oscillation as shown in Fig. ~ occurs, resulting in an intermittent conduction of the PNPN
- 3 -.
.. . . .
. . . :
1~636'73 1 switch.
In Figo 4, the upper waveform represents variations in the anode potential VA of the PNPN switch 11 with time, and the lower waveform variations in the anode current IA with time. Ihe transistor 13 is tem-porarily driven by the oscillation curren-t due to the capacitor 17 and the coil 18, so that the PNPN switch 11 is cut off as the gate and the cathode thereof is short-circuited. In the subsequent stage where the capacitor 17 is charged by the constant-current circuit 16 and rises in potential, the dv/dt protective function surpases the gate current, and therefore the PNPN switch cannot be driven to fire until the voltage becomes constant after completion of charging operation. In other words, when the PNPN switch 11 is driven to fire, the charges in the capacitor 17 are released through the coil 18 and the resistor 19, while the current oscillates due to the coil 18 and the capacitor 17 `: and temporarily flows backward through the PNPN switch ;20 11. ~his back current flows from the cathode K to -the Pl layer through the diode 15, the base of transistor 13, the collector of the transistor 13, the P2 layer, and nl layer during the storage time when the PNPN
switch 11 is not cut off as yet. In the process, the ~ , :
transistor 13 acts as an inverse NPN transistor which :, has the collector and the emitter thereof interchanged with each other. In the subsequent stage where the current begins to flow in forward direction, the transistor 13 continues to operate temporarily due to the s-torage effect. As a result, the gate G and the cathode K o ,~
, .. . .. .
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~L~6;3~73 1 the PNPN switch 11 are short-circuited by the transistor 13, so that the PNPN switch 11 is cut off. Since the potential of the anode A rises steadily, the transistor 13 is driven by the ; charge current of the nlP3 junction. Accordingly, the circuit of Fig. 3 has a shortcoming that it continues oscillation and therefore cannot stabilize the PNPN switch 11 in the turned-on state.
An object of the present invention is to provide a : semiconductor switch of PNPN four-layered structure with high gate-sensitivity and high dv/dt-immunity~ which can be stably controlled without oscillation even when it is used in a circuit including a capacitor and a coil.
Another object of the invention is to provide a semiconductor switch of PNPN four-layered structure which can be easily formed into semiconductor integrated circuits.
-~ According to the present invention, there is pro-vided a semiconductor switch comprising a PNPN switch with at ,~ .
least three PN-junctions, a transistor, drive means coupled to the PNPN switch for driving the transistor in the transient 20 state, a diode, and a bypass circuit for preventing a back current between an anode and a cathode of the PNPN switch from passing through the base and collector of the transistor. The collector and the emitter of the transistor are so connected - as to short-circuit one of the PN-junctions at one end of the 25 PNPN switch. The diode is inserted between the emitter and - the base of the transistor. The bypass circuit is provided between the emitter of the transistor and a selected one of :.
an anode gate and a cathode gate of the PNPN switch. The ~ invention will be further understood from the following -; 30 detailed description of the preferred embodiments thereof .. . .
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~3673 1 illustrated in Figs. 5 to 13 of the accom~anying drawings.
A circuit diagram of a first em~odiment of the semi-conductor switch according to the present invention is shown in Fig. 5. Another P-type region P3 is formed on the second layer nl of the PNPN switch 11, so that a couple of collectors are formed by the P-type regions P2 and P3. The collector and the emitter of a transistor are connected to the gate and the cathode of the PNPN switch 11 respectively, while the base of the transistor 13 is connected in series with a level shift diode 14. Through this diode 14, the base of the transistor ; 13 is further connected to the P3 region formed on the second j layer nl of the PNPN switch 11, which makes up the driving device for driving the transistor 13 in the transient state. A
discharging diode 15 is inserted between the emitter of the transistor 13 and the driving device. The gate and the cathode of the PNPN switch are connected by the resistor 12. By the `~ way, like component elements are denoted by like reference numerals in Fig. 2 as in the drawing under consideration. In the semiconductor switch of Fig. 5 with this construction, assume that an instantaneous back current tends to flow in the . PNPN switch 11 as shown in Fig~ 3, namely, that even when the potential of the cathode K of the PNPN switch instantaneously ~ ~
becomes higher than that o the anode A in the conducting ;
;l~ state, the back current flows from the diode 15 to :1 .
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', ', ''' ,'"', ,, ', ' ' '' , ' ' .,"'"'' ' ~', ,"' '' ', ''. ','.'',.'. ' ' ~063673 1 the anode A through the P3 region, nl layer, and P1 layer when the PNPN switch 11 is still within a storage time and maintained in semi-energized state. Since the vo]tage drop is increased by that equivalent to two diodes more than in the previously-shown path, substantially no current flows through the level shift diode 14 and the base-collector side of the transistor 13. If the semiconductor switch as shown in Fig. 5 is used in the circuit of Fig~ 3, the PNPN switch can be ~; 10 transferred into the stable conduction state without any oscillation even though a small oscillatory current ; is observed at the instant when the PNPN switch 11 is driven to fire.
~he circuit con-~iguration of a second embodiment of the semiconductor switch according to the present ., 'f~ invention is shown in Fig. 6. In the semiconductor switch of Fig. 5, the nl layer of the PNP~ switch 11 and the capacitance o~ the nlP3 junction between the n layer and the P3 region are used as the driving device for turning on the transistor 13 only in the transient state to prevent the rate effect o~ the PNPN switch 11.
In the semiconductor switch shown in Fig. 6, on the other hand, the voltage applied between the anode A and cathode K is di~erentiated by a diode 22 having comparatively large junction capacitance so as to drive . .
the transistor 13. ~he circuit con-~iguration o~ Fig. 6 ~ . .
is substantially the same a,s that of Fig. 5 except that the diode 22 partially acts as a capacitor. In other words, the level shi-ft dlode 1~ is connected to the base oL the -tra~sistor 13 7 whi1e the discharging _ 7 _ ' - . ~
,: . .
1~i3673 1 diode 15 is connected directly to the diode 22 providlng the driving device. The function and the effec-t of this configuration are the same as those of the circuit of Fig. 5-. The circuit configuration of a third embodimentof the semiconductor switch according to the present invention is shown in ~ig. 7. In the semiconductor switch shown in Fig. 7, the collector of a transistor ; 23 is connected to the nl layer of the PNP~ switch 11, and the emitter thereof to the base of the transistor 13, with a discharging diode 15 connected to the base of the transistor 23. According to the circuit configura-` tion shown in ~ig. 7, the voltage applied between anode A and cathode K is fed to the collector-base junction 15 of the transistor 23, so that the charge current of -thls junction is amplified by the transistor 23 itself so as to drive the transistor 13 in the transient state, thus preventing the rate effect of the PNPN swi-tch 11.
It will be understood that this construction is similar to that of the circuit of Fig. 6 with the diode 22 ; integrated with the diode 14 excep-t for -the amplifying .
function of the transistor 23. In other words, the base-emitter junction of the transistor 23 performs the same :, .
~ function as the level shift diode 14 shown in ~ig. 6.
.. . . . . .. .
~y the use of the transistor 23, the transient current . . .
is amplified and therefore higher dv/dt-immuni-ty is obtained. ~t the same time, against the back current ..~
due to the oscilIatory current, the transistor 23 ` functions as a inverse transistor with the emittex and collector theroof opera-tively interchanged with each other, ~ ' ............................................
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1 thus reducing the base voltage of the transistor 13.
In other words9 the transistor 13 is biased into the turned-off state.
The circuit configura-tion of a fourth embodiment ; 5 of the semiconductor switch according to the present invention is shown in Fig. 8. This semiconductor switch -~
is such that the driving device for the transistor 13 are configured as a Darlington circuit including - -transistors 24 and 25. Since the current for charging ; 10 the base-collector capacitance of the transistor 24 is arnplified to a larger extent, this circuit offers a configuration advantageous in obtaining higher dv/dt-,A immunity or the same dv/dt--immunity in spite of a miniature transistor. In the circuit configuration of Fig. 8, the level shift diode 1~ of Fig. 6 is considered to be equivalent to the series-connected base-emitter junctions of the transistors 24 and 25, thus offering a sufficient counteraction against a back current.
~he diagram of Fig. 9 shows the circuit configuration of a fifth embodiment of the semiconductor switch according to the present invention. ~his circuit is equivalent to the circuit of Fig. 7 with a resistor ~ 26 inserted between the emitter and the base of the ; transistor 23 making up the driving device for the transistor 13, the other configuration being identical to that of Fig. 7. In the semiconductor switch thus :; . . .
-~ constructed, the breakdown voltage between the ernitter ~ and collector of the transistor 23 making up the driving `` device for the transistor 13 is much more improved as cornpared with the circuit shown in Fig. 7~ so that ;~ .
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~636~3 1 a semiconductor switch more advantageous to a high voltage circuit can be provided.
A sixth embodiment o~ the semiconductor switch according to the present invention is shown in the circuit configuration of Fig. 10. ~ike the circuit shown in Fig. 9, the semiconductor switch under con-sideration is identical to the circuit of Fig. 8 except with resistors 27 and 28 inserted between the emitter ` and base of the transistors 24 and 25 in Darlington configuration respectively making up the driving device i for the transistor 13. Therefore, the effect and functions of this embodiment will not be described.
The circuit diagram of a seventh embodiment of the semiconductor switch according to the present ~
15 invention is shown in Fig. 11. Another P-type region ~-P3 is formed on the second layer nl of the PNPN switch 11, so that the P-type regions P2 and P3 make up a couple of collectors. A transistor 13 has the collector and the emitter thereof connected to the gate and the - 20 cathode of the PNPN switch 11, respectively. ~he base of the translstor 13 is connected to the P3 -region through the level shift diode 1~. A resistor 1~ is inserted between the gate G and the cathode K. A diode 29 is inserted between the emi-tter of the transistor ~ 25 13 and the gate ~ of the PNPN switch 11 in such a manner `` as to pass the back current of the PNPN switch llo A diode 15 is connected between the base and the emitter of the transistor 13. Component elements similar to those included in the circuit of Fig. 2 are denoted by like reicrcnce nurnerals.
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~Cl163673 1 In the semiconductor switch with this construc-tion, the diode 29 -fails to operate in response to the forward current of the PNP~ switch 11 from the anode A
to the cathode K, thus displaying the high gate-sensitivity as well as the high dv/dt-immunity. When this semi-conductor switch is used in the circuit shown in Fig. 3, the oscillatory current flowing backward through the PNP~ switch 11 is bypassed through the diode 29, so -tha-t the oscillated condition which otherwise might be caused by the back current flowing through the transistor 13 is prevented completely. In other words, when a back current flows temporarily through the PNP~ switch 11 `which has already been fired, the transistor section composed of the Pl, nl and P2 layers of the P~PN switch 15 11 with a comparatively long storage time is kept in -conduction, with the result that a current flows from the cathode K to the anode A through the diode 29, the P2 layer, the nl layer, and the Pl layer. In that ~ ~ .
process, substantially no current flows in the diode 15 sinoe the voltage drop of the path including the diode 15, the base of the transistor 13, and -the collector thereof is approximately twice as much as that of the path including the diode 29. That does not result in any oscillation as explained with reference to Fig. 3, thus making possible a stable switchingr operation.
The clrcuit configuration O:e an eighth embodi-ment of the semiconductor switch according to the presen-t invention is shown in Fig. 12. In the semiconductor switch shown in Fig. 11, the capacitance of the nlP3 ~0 junction ~ormed by the nl layer, namely~ between .
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~al63673 1 the second layer nl and -the P3 layer of thc P~TPN switch 11 is used. In the semiconductor switch shown in Fig. 12, like in the circuit of Fig. 6, the vol-ta~e applied between the anode A and the cathode K is differentiated by the diode 22 with a comparatively large junction capacitance -thereby to drive -the transistor 13. ~he circuit shown in Fig. 12, like the circuit of Fig. 6, utilizes the diode 22 partially as a capacitor.
The other construction, the functions, and the effects thereof are identlcal to those of the circuit shown in ~ig. 11.
A ninth embodiment of the semiconductor switch ~ -according to the present invention is shown in the circuit configuration of Fig. 13. In the semiconductor switch of Fig. 13, a transistor 23 has the collector thereof connected to the second layer nl of the PNPN
switch 11 and the emitter thereof connected to the base of the transistor 13. A resistor 26 is inserted ~ -- between the base and the emitter of the transistor 23.
` 20 ~urther, the diode 29 is inserted between the emitter ... .
of the transistor 13 and -the second layer nl of the PNPN
.~ switch 11. According to the circuit configuration - shown in Fig. 13, the voltage applied between the anode ;1 A and the cathode K is applied to the collector-base junction of the transistor 23, while the charge current in that junc-tion is amplified by the transistor 23 itself thereby to drive the transistor 13 in a transient :~ .... ..
way, thus preventin~ the rate effect of the PNPN switch 11. ~he resistor 26, like -the resistors 26, 27 and 28 shown in Figs. 9 and 10, is for improvin~ the breakdown ' '' ' :
~ . . : ..
~L~63~ii73 1 voltage between the emitter and the collector of the transistor 23.
It will thus be seen that according to the present invention, a semiconductor switch is realized~
which, in spite of its'high gate-sensitivity and high dv/dt-immunity, performs a stable switching operation without causing any abnormal actions such as oscillation. '~
Although the foregoing descriptions of the embodiments relate to the short-circuiting of the P2n junction counted as the third junction from the anode of the P~PN switch by means of a transistor for prevent-, ing the rate effect, the Plnl junction counted as the first junction from the anode A may alternatively be ' - short-circuited by the P~P transistor or otherwise a .. . .
``~ 15 circuit quite complementary with the above~mentioned , ~
. . - . .
- construction may be employed with equal effect. Further- ' ,- more 9 a couple of semiconductor switches according to ', the present invention may be, connected in inverse-`~ ~ paralle] to form a bidirectional switch with equal , ''; 20 effect.
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1~636'73 1 switch.
In Figo 4, the upper waveform represents variations in the anode potential VA of the PNPN switch 11 with time, and the lower waveform variations in the anode current IA with time. Ihe transistor 13 is tem-porarily driven by the oscillation curren-t due to the capacitor 17 and the coil 18, so that the PNPN switch 11 is cut off as the gate and the cathode thereof is short-circuited. In the subsequent stage where the capacitor 17 is charged by the constant-current circuit 16 and rises in potential, the dv/dt protective function surpases the gate current, and therefore the PNPN switch cannot be driven to fire until the voltage becomes constant after completion of charging operation. In other words, when the PNPN switch 11 is driven to fire, the charges in the capacitor 17 are released through the coil 18 and the resistor 19, while the current oscillates due to the coil 18 and the capacitor 17 `: and temporarily flows backward through the PNPN switch ;20 11. ~his back current flows from the cathode K to -the Pl layer through the diode 15, the base of transistor 13, the collector of the transistor 13, the P2 layer, and nl layer during the storage time when the PNPN
switch 11 is not cut off as yet. In the process, the ~ , :
transistor 13 acts as an inverse NPN transistor which :, has the collector and the emitter thereof interchanged with each other. In the subsequent stage where the current begins to flow in forward direction, the transistor 13 continues to operate temporarily due to the s-torage effect. As a result, the gate G and the cathode K o ,~
, .. . .. .
:. - : ~ ~ . . . : . .
~L~6;3~73 1 the PNPN switch 11 are short-circuited by the transistor 13, so that the PNPN switch 11 is cut off. Since the potential of the anode A rises steadily, the transistor 13 is driven by the ; charge current of the nlP3 junction. Accordingly, the circuit of Fig. 3 has a shortcoming that it continues oscillation and therefore cannot stabilize the PNPN switch 11 in the turned-on state.
An object of the present invention is to provide a : semiconductor switch of PNPN four-layered structure with high gate-sensitivity and high dv/dt-immunity~ which can be stably controlled without oscillation even when it is used in a circuit including a capacitor and a coil.
Another object of the invention is to provide a semiconductor switch of PNPN four-layered structure which can be easily formed into semiconductor integrated circuits.
-~ According to the present invention, there is pro-vided a semiconductor switch comprising a PNPN switch with at ,~ .
least three PN-junctions, a transistor, drive means coupled to the PNPN switch for driving the transistor in the transient 20 state, a diode, and a bypass circuit for preventing a back current between an anode and a cathode of the PNPN switch from passing through the base and collector of the transistor. The collector and the emitter of the transistor are so connected - as to short-circuit one of the PN-junctions at one end of the 25 PNPN switch. The diode is inserted between the emitter and - the base of the transistor. The bypass circuit is provided between the emitter of the transistor and a selected one of :.
an anode gate and a cathode gate of the PNPN switch. The ~ invention will be further understood from the following -; 30 detailed description of the preferred embodiments thereof .. . .
_ 5 .,~ .
~: G ~
.
~3673 1 illustrated in Figs. 5 to 13 of the accom~anying drawings.
A circuit diagram of a first em~odiment of the semi-conductor switch according to the present invention is shown in Fig. 5. Another P-type region P3 is formed on the second layer nl of the PNPN switch 11, so that a couple of collectors are formed by the P-type regions P2 and P3. The collector and the emitter of a transistor are connected to the gate and the cathode of the PNPN switch 11 respectively, while the base of the transistor 13 is connected in series with a level shift diode 14. Through this diode 14, the base of the transistor ; 13 is further connected to the P3 region formed on the second j layer nl of the PNPN switch 11, which makes up the driving device for driving the transistor 13 in the transient state. A
discharging diode 15 is inserted between the emitter of the transistor 13 and the driving device. The gate and the cathode of the PNPN switch are connected by the resistor 12. By the `~ way, like component elements are denoted by like reference numerals in Fig. 2 as in the drawing under consideration. In the semiconductor switch of Fig. 5 with this construction, assume that an instantaneous back current tends to flow in the . PNPN switch 11 as shown in Fig~ 3, namely, that even when the potential of the cathode K of the PNPN switch instantaneously ~ ~
becomes higher than that o the anode A in the conducting ;
;l~ state, the back current flows from the diode 15 to :1 .
:i. ~ .:
j ;., :`~ .'' ~ . . .
`-7,~ ..
.' ~ :
', ', ''' ,'"', ,, ', ' ' '' , ' ' .,"'"'' ' ~', ,"' '' ', ''. ','.'',.'. ' ' ~063673 1 the anode A through the P3 region, nl layer, and P1 layer when the PNPN switch 11 is still within a storage time and maintained in semi-energized state. Since the vo]tage drop is increased by that equivalent to two diodes more than in the previously-shown path, substantially no current flows through the level shift diode 14 and the base-collector side of the transistor 13. If the semiconductor switch as shown in Fig. 5 is used in the circuit of Fig~ 3, the PNPN switch can be ~; 10 transferred into the stable conduction state without any oscillation even though a small oscillatory current ; is observed at the instant when the PNPN switch 11 is driven to fire.
~he circuit con-~iguration of a second embodiment of the semiconductor switch according to the present ., 'f~ invention is shown in Fig. 6. In the semiconductor switch of Fig. 5, the nl layer of the PNP~ switch 11 and the capacitance o~ the nlP3 junction between the n layer and the P3 region are used as the driving device for turning on the transistor 13 only in the transient state to prevent the rate effect o~ the PNPN switch 11.
In the semiconductor switch shown in Fig. 6, on the other hand, the voltage applied between the anode A and cathode K is di~erentiated by a diode 22 having comparatively large junction capacitance so as to drive . .
the transistor 13. ~he circuit con-~iguration o~ Fig. 6 ~ . .
is substantially the same a,s that of Fig. 5 except that the diode 22 partially acts as a capacitor. In other words, the level shi-ft dlode 1~ is connected to the base oL the -tra~sistor 13 7 whi1e the discharging _ 7 _ ' - . ~
,: . .
1~i3673 1 diode 15 is connected directly to the diode 22 providlng the driving device. The function and the effec-t of this configuration are the same as those of the circuit of Fig. 5-. The circuit configuration of a third embodimentof the semiconductor switch according to the present invention is shown in ~ig. 7. In the semiconductor switch shown in Fig. 7, the collector of a transistor ; 23 is connected to the nl layer of the PNP~ switch 11, and the emitter thereof to the base of the transistor 13, with a discharging diode 15 connected to the base of the transistor 23. According to the circuit configura-` tion shown in ~ig. 7, the voltage applied between anode A and cathode K is fed to the collector-base junction 15 of the transistor 23, so that the charge current of -thls junction is amplified by the transistor 23 itself so as to drive the transistor 13 in the transient state, thus preventing the rate effect of the PNPN swi-tch 11.
It will be understood that this construction is similar to that of the circuit of Fig. 6 with the diode 22 ; integrated with the diode 14 excep-t for -the amplifying .
function of the transistor 23. In other words, the base-emitter junction of the transistor 23 performs the same :, .
~ function as the level shift diode 14 shown in ~ig. 6.
.. . . . . .. .
~y the use of the transistor 23, the transient current . . .
is amplified and therefore higher dv/dt-immuni-ty is obtained. ~t the same time, against the back current ..~
due to the oscilIatory current, the transistor 23 ` functions as a inverse transistor with the emittex and collector theroof opera-tively interchanged with each other, ~ ' ............................................
",.
.,; . . .. .... . , , .. . . . . . .. . .,, .. , " .: :., .,:,: . . . , . . :
: ,. .,, .. :, . . : .. , . .: . , . , . . .. . . . .. ,: : : " " : ,. ., .. , : : .: . , . : . .: ,. ..
1 thus reducing the base voltage of the transistor 13.
In other words9 the transistor 13 is biased into the turned-off state.
The circuit configura-tion of a fourth embodiment ; 5 of the semiconductor switch according to the present invention is shown in Fig. 8. This semiconductor switch -~
is such that the driving device for the transistor 13 are configured as a Darlington circuit including - -transistors 24 and 25. Since the current for charging ; 10 the base-collector capacitance of the transistor 24 is arnplified to a larger extent, this circuit offers a configuration advantageous in obtaining higher dv/dt-,A immunity or the same dv/dt--immunity in spite of a miniature transistor. In the circuit configuration of Fig. 8, the level shift diode 1~ of Fig. 6 is considered to be equivalent to the series-connected base-emitter junctions of the transistors 24 and 25, thus offering a sufficient counteraction against a back current.
~he diagram of Fig. 9 shows the circuit configuration of a fifth embodiment of the semiconductor switch according to the present invention. ~his circuit is equivalent to the circuit of Fig. 7 with a resistor ~ 26 inserted between the emitter and the base of the ; transistor 23 making up the driving device for the transistor 13, the other configuration being identical to that of Fig. 7. In the semiconductor switch thus :; . . .
-~ constructed, the breakdown voltage between the ernitter ~ and collector of the transistor 23 making up the driving `` device for the transistor 13 is much more improved as cornpared with the circuit shown in Fig. 7~ so that ;~ .
' 9 .. , ' ~ . .
. .
:: . , ~ . , . : . .: :
" .. :.......... . .
:. :.
~636~3 1 a semiconductor switch more advantageous to a high voltage circuit can be provided.
A sixth embodiment o~ the semiconductor switch according to the present invention is shown in the circuit configuration of Fig. 10. ~ike the circuit shown in Fig. 9, the semiconductor switch under con-sideration is identical to the circuit of Fig. 8 except with resistors 27 and 28 inserted between the emitter ` and base of the transistors 24 and 25 in Darlington configuration respectively making up the driving device i for the transistor 13. Therefore, the effect and functions of this embodiment will not be described.
The circuit diagram of a seventh embodiment of the semiconductor switch according to the present ~
15 invention is shown in Fig. 11. Another P-type region ~-P3 is formed on the second layer nl of the PNPN switch 11, so that the P-type regions P2 and P3 make up a couple of collectors. A transistor 13 has the collector and the emitter thereof connected to the gate and the - 20 cathode of the PNPN switch 11, respectively. ~he base of the translstor 13 is connected to the P3 -region through the level shift diode 1~. A resistor 1~ is inserted between the gate G and the cathode K. A diode 29 is inserted between the emi-tter of the transistor ~ 25 13 and the gate ~ of the PNPN switch 11 in such a manner `` as to pass the back current of the PNPN switch llo A diode 15 is connected between the base and the emitter of the transistor 13. Component elements similar to those included in the circuit of Fig. 2 are denoted by like reicrcnce nurnerals.
: ' ' . ' - ,., ,, - 10 -. .
, . - . . .
.
:, . . .
~Cl163673 1 In the semiconductor switch with this construc-tion, the diode 29 -fails to operate in response to the forward current of the PNP~ switch 11 from the anode A
to the cathode K, thus displaying the high gate-sensitivity as well as the high dv/dt-immunity. When this semi-conductor switch is used in the circuit shown in Fig. 3, the oscillatory current flowing backward through the PNP~ switch 11 is bypassed through the diode 29, so -tha-t the oscillated condition which otherwise might be caused by the back current flowing through the transistor 13 is prevented completely. In other words, when a back current flows temporarily through the PNP~ switch 11 `which has already been fired, the transistor section composed of the Pl, nl and P2 layers of the P~PN switch 15 11 with a comparatively long storage time is kept in -conduction, with the result that a current flows from the cathode K to the anode A through the diode 29, the P2 layer, the nl layer, and the Pl layer. In that ~ ~ .
process, substantially no current flows in the diode 15 sinoe the voltage drop of the path including the diode 15, the base of the transistor 13, and -the collector thereof is approximately twice as much as that of the path including the diode 29. That does not result in any oscillation as explained with reference to Fig. 3, thus making possible a stable switchingr operation.
The clrcuit configuration O:e an eighth embodi-ment of the semiconductor switch according to the presen-t invention is shown in Fig. 12. In the semiconductor switch shown in Fig. 11, the capacitance of the nlP3 ~0 junction ~ormed by the nl layer, namely~ between .
- 11. _ . -: ~ - . ,..................... . : :
i, ' ''~
~al63673 1 the second layer nl and -the P3 layer of thc P~TPN switch 11 is used. In the semiconductor switch shown in Fig. 12, like in the circuit of Fig. 6, the vol-ta~e applied between the anode A and the cathode K is differentiated by the diode 22 with a comparatively large junction capacitance -thereby to drive -the transistor 13. ~he circuit shown in Fig. 12, like the circuit of Fig. 6, utilizes the diode 22 partially as a capacitor.
The other construction, the functions, and the effects thereof are identlcal to those of the circuit shown in ~ig. 11.
A ninth embodiment of the semiconductor switch ~ -according to the present invention is shown in the circuit configuration of Fig. 13. In the semiconductor switch of Fig. 13, a transistor 23 has the collector thereof connected to the second layer nl of the PNPN
switch 11 and the emitter thereof connected to the base of the transistor 13. A resistor 26 is inserted ~ -- between the base and the emitter of the transistor 23.
` 20 ~urther, the diode 29 is inserted between the emitter ... .
of the transistor 13 and -the second layer nl of the PNPN
.~ switch 11. According to the circuit configuration - shown in Fig. 13, the voltage applied between the anode ;1 A and the cathode K is applied to the collector-base junction of the transistor 23, while the charge current in that junc-tion is amplified by the transistor 23 itself thereby to drive the transistor 13 in a transient :~ .... ..
way, thus preventin~ the rate effect of the PNPN switch 11. ~he resistor 26, like -the resistors 26, 27 and 28 shown in Figs. 9 and 10, is for improvin~ the breakdown ' '' ' :
~ . . : ..
~L~63~ii73 1 voltage between the emitter and the collector of the transistor 23.
It will thus be seen that according to the present invention, a semiconductor switch is realized~
which, in spite of its'high gate-sensitivity and high dv/dt-immunity, performs a stable switching operation without causing any abnormal actions such as oscillation. '~
Although the foregoing descriptions of the embodiments relate to the short-circuiting of the P2n junction counted as the third junction from the anode of the P~PN switch by means of a transistor for prevent-, ing the rate effect, the Plnl junction counted as the first junction from the anode A may alternatively be ' - short-circuited by the P~P transistor or otherwise a .. . .
``~ 15 circuit quite complementary with the above~mentioned , ~
. . - . .
- construction may be employed with equal effect. Further- ' ,- more 9 a couple of semiconductor switches according to ', the present invention may be, connected in inverse-`~ ~ paralle] to form a bidirectional switch with equal , ''; 20 effect.
i: . .
.... .. .
. ~ .
:~
: ~' . . .
..
.' ' .
.
.
,' . '.
~ 13 _ , .~ .
,. : . : -. , ,: . : , .. ~ :
. , . ; . , . . - . .. . . .. . . . .
- . . . . . , ~
Claims (11)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A semiconductor switch comprising:
a PNPN switch including at least three PN-junctions;
a first transistor connected so as to short circuit in transient state one of the PN-junctions at one end of said PNPN switch; drive means coupled to said PNPN switch for driving said first transistor in transient state; and a first . .
diode connected between the emitter and the base of said first transistor, wherein said semiconductor switch further compris-es a bypass circuit for preventing a back current between an anode and a cathode of said PNPN switch from passing through the base and the collector of said first transistor, said by-pass circuit being provided between the emitter of said first transistor and a selected one of an anode gate and a cathode gate of said PNPN switch.
a PNPN switch including at least three PN-junctions;
a first transistor connected so as to short circuit in transient state one of the PN-junctions at one end of said PNPN switch; drive means coupled to said PNPN switch for driving said first transistor in transient state; and a first . .
diode connected between the emitter and the base of said first transistor, wherein said semiconductor switch further compris-es a bypass circuit for preventing a back current between an anode and a cathode of said PNPN switch from passing through the base and the collector of said first transistor, said by-pass circuit being provided between the emitter of said first transistor and a selected one of an anode gate and a cathode gate of said PNPN switch.
2. A semiconductor switch according to Claim 1, further comprising an element having at least a PN-junction, and a second diode, the base of said first transistor being connected to said drive means through said element having the PN-junction, said second diode being inserted between the emitter of said transistor and said drive means.
3. A semiconductor switch comprising:
a PNPN switch having four PN-junctions, an anode gate, cathode gate and a cathode;
a transistor;
a couple of diodes, and a resistor;
said PNPN switch including an additional P-type collector region on a region of said anode gate thereof, said resistor being inserted between the collector and the emitter of said transistor, said collector and said emitter of said transistor being connected to the cathode gate and the cathode of said PNPN switch, respectively, the base of said transistor being connected through one of said diodes to said P-type collector region formed on said anode gate region of said PNPN
switch, the other diode being inserted between said emitter of said transistor and said P-type collector region formed on said anode gate region of said PNPN switch.
a PNPN switch having four PN-junctions, an anode gate, cathode gate and a cathode;
a transistor;
a couple of diodes, and a resistor;
said PNPN switch including an additional P-type collector region on a region of said anode gate thereof, said resistor being inserted between the collector and the emitter of said transistor, said collector and said emitter of said transistor being connected to the cathode gate and the cathode of said PNPN switch, respectively, the base of said transistor being connected through one of said diodes to said P-type collector region formed on said anode gate region of said PNPN
switch, the other diode being inserted between said emitter of said transistor and said P-type collector region formed on said anode gate region of said PNPN switch.
4. A semiconductor switch according to Claim 1, further comprising a resistor inserted between the collector and the emitter of said transistor, said drive means including a second diode having one end thereof connected to the anode gate of said PNPN switch in a direction opposite to an anode gate current, said bypass circuit including a third diode connected between the other end of said second diode and the base of said transistor in the same direction as the current flowing into said base, and said first diode being connected between the other end of said second diode and the cathode of said PNPN
switch.
switch.
5. A semiconductor switch according to Claim 1, further comprising a resistor connected between the collector and the emitter of said first transistor, said drive means including a second transistor, the emitter of said second transistor being connected to the base of said first transistor, the collector of said second transistor being connected to the anode gate of said PNPN switch, the base of said second transistor being connected to the cathode of said PNPN switch through said first diode.
6. A semiconductor switch according to Claim 1 further comprising a resistor connected between the collector and the emitter of said first transistor, said drive means including a second and a third transistor, said second and third transistors being connected in Darlington configuration, the collectors of said second and third transistors being connected in common to the anode gate of said PNPN switch, the emitter of said third transistor being connected to the base of said first transistor, the base of said second transistor being connected through said first diode to the cathode of said PNPN switch.
7. A semiconductor switch according to Claim 1, further comprising a couple of resistors, one of said resistors being connected between the collector and the emitter of said first transistor, said drive means including a second transistor, the collector of said second transistor being connected to the anode gate of said PNPN switch, the emitter of said second transistor being connected to the base of said first transistor the base of said second transistor being connected to the cathode of said PNPN switch through said first diode, the other resistor being connected between the base and the emitter of said second transistor.
8. A semiconductor switch comprising: a PNPN switch having three PN-junctions, an anode gate, a cathode gate and a cathode; a first transistor; a second transistor; a third transistor; three resistors; and a diode, wherein a first one of said resistors is inserted between the collector and the emitter of said first transistor, said collector and said emitter of said first transistor being connected to the cathode gate and the cathode of said PNPN switch, respectively, said second transistor and said third transistor being connected in Darlington configuration, the collectors of said second and said third transistors being connected in common to the anode gate of said PNPN switch, the emitter of said third transistor in said Darlington configuration being connected to the base of said first transistor, the base of said second transistor being connected through said diode to the cathode of said PNPN switch, a second one of said resistors and a third one of said resist-ors being inserted between the base and the emitter of said second transistor and between the base and the emitter of said third transistor, respectively.
9. A semiconductor switch comprising: a PNPN switch having four PN-junctions, an anode gate, a cathode gate, and a cathode; a transistor; three diodes; and a resistor, said PNPN
switch further including an additional P-type collector region on a region of said anode gate thereof, wherein said resistor is inserted between the collector and the emitter of said transistor, said collector and said emitter of said transistor being connected to the cathode gate and the cathode of said PNPN switch, respectively, a first one of said diodes being connected between the emitter and the base of said transistor, said base of said transistor being connected through a second one of said diodes to said P-type collector region added to said anode gate region of said PNPN switch, a third one of said diodes being inserted between said emitter of said transistor and a selected one of said anode gate and said cathode gate of said PNPN switch in the direction opposite to the forward current of said PNPN switch.
switch further including an additional P-type collector region on a region of said anode gate thereof, wherein said resistor is inserted between the collector and the emitter of said transistor, said collector and said emitter of said transistor being connected to the cathode gate and the cathode of said PNPN switch, respectively, a first one of said diodes being connected between the emitter and the base of said transistor, said base of said transistor being connected through a second one of said diodes to said P-type collector region added to said anode gate region of said PNPN switch, a third one of said diodes being inserted between said emitter of said transistor and a selected one of said anode gate and said cathode gate of said PNPN switch in the direction opposite to the forward current of said PNPN switch.
10. A semiconductor switch according to Claim 1, further comprising a resistor, said resistor being inserted between the collector and the emitter of said first transistor, said drive means including a second diode having one end thereof connected to the anode gate of said PNPN switch in a direction opposite to an anode gate current, said bypass circuit including a third diode connected between the emitter of said first transistor and selected one of said anode gate and said cathode gate of said PNPN switch in a direction opposite to a forward current of said PNPN switch.
11. A semiconductor switch according to Claim 1, further comprising a couple of resistors, one of said resistors being inserted between the collector and the emitter of said first transistor, said drive means including a second transistor, the collector of said second transistor being connected to the anode gate of said PNPN switch, the emitter of said second transistor being connected to the base of said first transistor, the other resistor being inserted between the base and the emitter of said second transistor, said bypass circuit including a third diode connected between the emitter of said first transistor and selected one of the anode gate and the cathode gate of said PNPN switch in a direction opposite to a forward current of said PNPN switch.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11772475A JPS5814777B2 (en) | 1975-10-01 | 1975-10-01 | Hand tie switch |
| JP11772375A JPS5242242A (en) | 1975-10-01 | 1975-10-01 | Semiconductor switch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1063673A true CA1063673A (en) | 1979-10-02 |
Family
ID=26455790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA262,388A Expired CA1063673A (en) | 1975-10-01 | 1976-09-30 | Four-layer semiconductor switch |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4084110A (en) |
| CA (1) | CA1063673A (en) |
| DE (1) | DE2643935C2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS605142B2 (en) * | 1977-05-11 | 1985-02-08 | 株式会社日立製作所 | semiconductor switching equipment |
| US4323793A (en) * | 1978-09-27 | 1982-04-06 | Eaton Corporation | Thyristor having widened region of temperature sensitivity with respect to breakover voltage |
| US4213067A (en) * | 1978-12-22 | 1980-07-15 | Eaton Corporation | Integrated gate turn-off device with non-regenerative power portion and lateral regenerative portion having split emission path |
| EP0060912B1 (en) * | 1981-03-24 | 1986-10-22 | Siemens Aktiengesellschaft | Thyristor having a disconnectible emitter short |
| US4458408A (en) * | 1981-07-31 | 1984-07-10 | Motorola, Inc. | Method for making a light-activated line-operable zero-crossing switch |
| US4553041A (en) * | 1983-08-22 | 1985-11-12 | Motorola, Inc. | Monolithic zero crossing triac driver |
| JP3222330B2 (en) * | 1994-09-20 | 2001-10-29 | 株式会社日立製作所 | Semiconductor circuit and semiconductor integrated circuit |
| US5686857A (en) * | 1996-02-06 | 1997-11-11 | Motorola, Inc. | Zero-crossing triac and method |
| JP5540801B2 (en) * | 2010-03-19 | 2014-07-02 | 富士通セミコンダクター株式会社 | ESD protection circuit and semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3434022A (en) * | 1967-01-27 | 1969-03-18 | Motorola Inc | Semiconductor controlled rectifier device |
| US3488522A (en) * | 1967-03-22 | 1970-01-06 | Bell Telephone Labor Inc | Thyristor switch circuit |
-
1976
- 1976-09-28 US US05/727,453 patent/US4084110A/en not_active Expired - Lifetime
- 1976-09-29 DE DE2643935A patent/DE2643935C2/en not_active Expired
- 1976-09-30 CA CA262,388A patent/CA1063673A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4084110A (en) | 1978-04-11 |
| DE2643935A1 (en) | 1977-04-14 |
| DE2643935C2 (en) | 1981-09-17 |
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