CA1106977A - Microprogrammed unit for a data set incorporating a modem for use at a data transmission terminal and an associated exchange of a data network - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
The invention provides data sets for connecting a data terminal to an exchange of data network using ordinary telephone lines and links, the sets being used at either end of the line or link and comprising interface and modem functions implemented by a unit comprising a processing unit, which processes, organises, modulates and demodulates incoming and outgoing signals under the control of a control unit providing instructions from a stored program in response to timing signals provided by a timing unit.
At the exchange end of the line the timing unit is slaved to the exchange clock, and at the data terminal the timing unit is phase and frequency locked to synchronizing signals received from the exchange.

Description

The present invention relates to data transmission and more particularly it refers to a microprogrammed unit designed for a data set incorporating a modulation-demodulation device (modem) and useful at a data transmission terminal and an associated exchangeO
At present, data transmission mainly employs the existing telephone network, and is implemented both by utilizing lines switch-ed by conventional telephone exchanges and privileged lines ex-clusively assigned from point-to-pointO
As telephone networks are not originally intended for data traffic, their hybrid utilization does not allow an optimal data service either from the point of view of the q~antity or from the point of view of maintainance costsO
More particularly, the following disadvantages are en-countered:
considerable limitations of data transmission speed;
long delays in establishing connections;
large error ratiosO
To overcome these disadvantages a New Data Network, generally referred to as NRD, has been internationally recommended by CCITT
(International Telegraph and Telephone Consulatative Committee).
whose main features are as follows:
(1) high transmission speed;

(2) short times for establishing connection;

(3) very low error rate assured;

(4) completely digital networks,utilizing for transmission as as well as for signaling, formats generally consistinq, as in Italy, of 8 bits: six bits represent data and are ori-ginated by the subscriber, 2 bits are for control purposes and are synchronously added to the data stream of information generated by the subscriberO An on-line rate of transmission (gross bit rate) results equal to 4/3 of the standard sub-scriber's speed (net bit rate);

(5) base band connection between the data set or network terminat-ing equipment (DCE) at the subscriber's location, and the exchangeO
The base band connection is economically viable as it is known that a base band modem is less complicated and expensive than a speech band modem which is able to transmit only on a tra-ditionaI speech channel (300 - 3O400 Hz)o It has to be emphasized however that a base band connection is not possible when the subscriber is at a considerable distance, for instance more than 10 km, from the nearest exchange, because, for such big distances, the line attenuation of data signals can-not be accommodated. Even if the inconvenience of line attenuation s overcome by the insertion of intermediate amplifiers, it would give rise to very costly installationsO
Moreover, a distribution network designed for data, operat-ing at base-band, and able to serve all subscribers, does not presently existO This means that at present only subscribers very near the exchange could use the service suggested by CCITT for the New Data Network (NRD).
The connection of remote subscribers by means of tradi-tional speech-band channels, requires the use of costly speech band modemsO Besides, if the net subscriber's rate is, for in-stance, 2.400 bits per second, such speech-band modems must operate on line, according to CCITT recommenda-tions, at a gross rate equal to 4/3 of the net rate, that is 30200 bit /s; band modems designed to operate at such a rate are not presently commercially p~a~

available.
The microprogrammed unit of the present invention solves these problems, providing a data set allowing connection, even of remote subscribers, to NRD by means of traditional telephone channels.
Such a unit allows the NRD service to be offered to all telephone subscribers, wherever they may live.
Another characteristic of the present microprogrammed unit is that, due to its realization by means of a fast micro-processor, it is able to operate as a data signal modem and alsoas a data network terminating equipment (DCE), according to the CCITT International Recommendations Xo21 and Xo21 biso According to the present invention a microprogrammed unit, for use as in a data set at a data terminal and at an exchange,o~sists of three functional blocks, the first functional block comprising:
the arithmetic logic unit of a microprocessor;
a multiplyer unit to carry out fast multiplications between parallel bit configurations;
a memory comprising a read-only memory portion and a random-access memory portion acting as a data memory in conjunction with said arithmetic logic unit and with said multiplyer unit;
a multiplexer to select a bit configuration to be sent to said arithmetic logic unit; and a programmable scaler able to carry out binary multiplication and/or division with a variable modulus which is a power of two, on bit configurations selected by said multiplexer;
the second functional block comprising:
a read-only-memory acting as program memory and containing to this end a predetermined set of microinstructions;

7t7 a sequencer to supervise the operative sequence of said micro-instructions and to supply to said program memory the address of microinstructions for immediate execution; and a register to store temporarily microinstructions received from said program memory;
the third operating block comprising:
a digital oscillator to generate a fundamental frequency;
a first frequency divider dividing by three said fundamental frequency to generate a main clock signal;
a programmable frequency divider to divide said fundamental frequency by a pre-determined coefficient incremented or de-creased by a correcting value computed for each successive symbol by said computing unit so as to originate a programmed frequency; :
a second frequency divider able to divide the programmed fre-quency origi~ ted by said programmable divider by constants

6, 20, 120 so as to obtain respectively three timing signals controlling the operation of the unitO
These a~ other characteristics of the present invention will become clearer from the following description of an exemplary em-bodiment with reference to the accompanying drawings in which:
FigO 1 is a schematic diagram showing the insertion of a data set (AU) at a data terminal and a data set AC at the exchange of a data network;
FigO 2 is a block diagram showing the data set denoted by AU in Fig. l;
FigO 3 is a detailed block diagram of the block denoted by UM in FigO 2;
FigO 4 is a flow-chart illustrating the operation of the

7~
UM of FigO 30 With reference to FigO ], NRD denotes a "new data network", comprising all the necessary switching and multiplexing devices, which have not been represented, with the sole exception of OC
representing a conventional unit for data multiplexing, able to multiplex or demulciplex into or from a single frame the data streams coming from several subscribers.
Reference W denotes a subscriber geographically situated near OC; inside UV reference TDl denotes a conventional synchro-nous data terminal and DCEl a conventional data setO
TDl is the effective subscriber's data source and may con-sist of any "intelligent" terminal, i.e. an electronic processor9 data set DCEl acts as an interface between TDl and OC (to which it is connected by means of a base-band connection denoted by 1) as it adapts network signalling to the signalling of terminal TDl and ; vice versa.
Reference UL denotes a subscriber geographically situated far from OC; inside UL reference TD2 denotes a synchronous data terminal analogous to TDl; reference AU denotes a data set (subscriber's equipment)bidirectionally connected to TD2 by means of a connection 2; AU forms part of the apparatus of the present invention and will be described in detail hereinafter in connection with FigsO 2 and 30 The functions of AU are those of an interface, analogous to those carried out by DCEl for subscriber W, and moreover those of a modem which are necessary for a speech-band transmission over, for instance, a subscriber's telephone pair, denoted by 3, by one of more sections of FDM (frequency-division multiplex) tranmsission denoted generally by CF, and by an exchange pair denoted by 4O

)7~7 Reference AC denotes a data set (exchange equipment) whose structure is similar to that of AU; AC is also constructed in accordance with the present invention and will be described in de-tail with reference to FigsO 2 and 3O
The functions of AC are those of a modem, analogous and complementary to those carried out by AU, and also those of an interface between the already examined speech band link (3, CF, 4) and the multiplexing unit OC to which AC is connected by means of connection 55; it is worth noting that such interfacing operations do not imply, as for AU, any signal processing, but only the necessary electrical signal matchingO
More particularly, a bidirectional data stream and a timing signal from OC towards AC pass through the connection 550 Devices denoted by TDl, TD2, DCEl, OC are known to the skilled in the art and, as they form no part of the present invention, they will not be further describedO
In FigO 2 reference IN denotes a conventional bidirectional interface circuit able electrically to match, on the basis of the characteristics forseen by Recommendations Xo26, Xo27 of CCITT, the signals present on line 2 generated or received by TD2 (FigOl), in such a way as to make them compatible with the electric character-stics required by signals which are to be processed by other blocks of the subscriber's equipment AUo References RI and RU (FigO 2) denote two conventional input and output registers, performing as buffers and synchronizers of signals which pass therethroughO RI and RU are both clocked by signals T3, T4 which will be examined hereinafterO
Moreover RI and RU carry out the functions of parallel-serial conversion as well as of serial-parallel conversion of the 7~7 data they process.
References D/A and A/D denote two conventional data converters carrying out respectively digital-to-analog conversion and vice versaO Reference SH denotes a conventional means for sampling and holding the analog signal coming from the lineO D/A, A/D and SH
are clocked by a signal T2 which will be examined hereinafterO
References FI, FU denote two analog circuits acting as inter-faces for the telephone line 3, and performing as input and output channel filters respectivelyO

Reference UM denotes a complex microprogrammed logic unit forming the core of the apparatus of the invention; UM, which will be described in connection with FigO 3, is connected to registers RU, RI by means of connections 15, 5, 6 respectively, and to con-verters D/A, A/D through connections 15, 7 and 8 respectivelyO
The block denoted by AC in FigO 1 has the same structure as the block AU just described, the only difference being that inter-face IN (FigO 2) of AU interchanges data with TD2 (Fig. 1) and so it operates at a net rate which is the standard subscriber's rate, while the corresponding interface in AC interchanges data with OC
and so operates at the gross rate of the data stream in NRDo Additionally, while AC is clocked directly from the exchange (NRD) and so it is directly slaved to the exchange clock, AU ex-tracts synchronization from the data stream coming from the line (4, CF, 3) and in turn synchronizes TD2 so as to conform it to the exchange clock.
Thus, whilst AU needs a phase - locked loop PLL which will be examined hereinafter in connection with FigO3, AC is directly slaved to the exchange clock and so needs no phase-locked loopO
Release from this task makes its construction simplerO

~ 6~7 7 In FigO 3 the references UC, UE, UT, denote three blocks forming a control unit, a processing unit and a timing unit, respectivelyO
Control unit UC consists of a read-only-memory MM storing the ordered set of microinstructions necessary to the operation of the whole equipment AU (FigO 2), as well as of a sequencer SQ
(FigO 3) controlling the operative microinstruction sequence by supplying MM, through connection 9, with the address of the micro-instruction to be next executed; this address is determined by SQ
depending on:
the address present at that moment on connection 9;
a portion of the present instruction containing the address code, that SQ receives from MM through connection 14;
information relative to external events (control bits) coming : from IN (FigO 2) through RI and connections 6, 12 (FigO3);
the results of processing operations in progress in UE, and results received by SQ as status information, through con-nection 130 As clearly shown in FigO 3, connection 6 from RI is sub-divided into connection 12, carrying the control portion, and into connection 11 carrying the data portion of the bits present on connection 6.
The microinstruction that MM presents at its output, is sub-divided onto two connections 10 and 14; more particularly, the operating portion of the microinstruction is present on connection 10; this portion is responsible for the simultaneous parallel control of the remaining devices of unit UMo The portion of the microinstruction controlling the sequencing of the microinstruc-tions, which is utilized as already seen by SQ, is present on connection 140 7~7 To transfer instructions from MM to units UE and UT a re-gister P is utilized, which operates according to the "pipeline"
technique. P stores the instruction coming from MM for a time corresponding to the period of the operating cycle, timed by a signal Tl, so as to make up for the delay caused by SQ in supplying the address to MM on connection 9 and for the access time of MM, that is the propagation delay between inputs 9 and outputs 10 of MMo Register P has seven output connections carrying configura-tions of control bits, denoted by Cl, C2, C3, C4, C7, C8 and an out-put connection carrying a binary signal S, this being a constant which is contained in each microinstruction, and whose utilization will be examined hereafterO
Obviously the whole of the control bit configurations at the output of P exactly reproduces, except for the delay already discussed, the bit configuration present at the input on connection lOo Register P transfers to and maintains at its outputs the bit configuration present at its input on connection 10 at every leading edge of timing signal Tl which clocks the operative cycle of the equipmentO
Reference MX denotes a conventional multiplexer having five multiplex inputs and one mu~tiplex output of the same order as the inputs, and able to transfer to its output the bit configuration present at any one of its five inputs, upon a "select" order C3 it receives from P~ Of the five inputs the first is connected to con-nection 11, carrying the data portion of the bit configuration coming from RI on connection 6, the second is connected to connect-ion 8, coming from A/D, carrying the information coming from line _ g _ ~ 7 3, CF, 4 (FigO l); the third is connected to connection 16 (FigO
3) carrying information from memory MD, which will be discussed hereinafter; the fourth input is connected to a connection 17 coming from register RD, which will also be discussed hereinafter;
the last input is connected to connection 15 carrying the bit con-figuration present at the output of unit UEo The output of MX is connected, through connection 18, to a scaler SCO
According to an order C2 coming from register P9 SC effects on the bits received by connection 18 a leftwards or rightwards shift through a number of positions depending on the code contained in order C20 Thus in practice SC acts as a conventional program-mable divider or multiplier, acting with a modulus which is a power of twoO The function of SC will be further explained here-inafter, while describing its operation.
Reference AL denotes an arithmetic logic unit provided with a bank of addressable registers, of known type, able to carry out, on the basis of the timing of signal Tl, the neces-sary processing operations on the bit configurations received by SC through connection l9o AL receives also the following input signals:
control code Cl, coming from P, consisting of two portions:
the first specifies to AL the kind of operation to be carried out and the second detects the internal register of AL appro-priate to such an operation;
binary signal S, coming from PO
The outputs of AL consist of:
an output, connected to connection 15, which carries the data processed by UE;
an output, connected to connection 20, carrying the address 3 for data memory MD.

9~'7 an output, connected to connection 13, supplying sequencer SQ with the already examined status information for the correct operation of memory MM:
finally, an output connected to timing unit UT through wire 21, able to supply the correction signal to the portion of the phase locked loop (PLL) which is located near UTo In practice AL may consist of the arithmetic logic unit of a commercially available type of microprocessor, provided it is sufficiently fast and versatile as to the utilization of outputs and inputs; in technical language such microprocessors are re-ferred to as "bit-slice"O
Reference MD denotes a data memory partly realized by means of read-only-elements (ROM) (read-only memory) and partly by read-write elements (RAM) (random access memory)O
The read-only portion of the memory stores some constants to be utilized during the processing operation; the read- and-write portion is utilized to temporarily store the intermediate results of previous processing operations.
MD receives at its input through connection 20 the bit configuration necessary to the entire addressing of the memory, and through connection 15 the bits to be stored in the read-and-write portion; an order on line C7 enables MD to write data com-ing from connection 15 at the address contained in the bit con-figuration present on connection 200 At the output of MD, on connection 16, there is always present the bit configuration memorized in MD at the address pre-sent on connection 200 RG denotes a conventional register able temporarily to store, on receipt of an order C8 from P~ the configuration of bits present at its input connected to connection 16; this configuration is maintained available at the output, on connection 22, until re-ceipt of the next order C8.
Reference M denotes a convent:ional multiplier able to multi-ply the configuration of bits present at a first input connected to connection 16 by the configuration of bits present at the second input connected to connection 220 The result of such multiplication is presented, through con-nection 23, to a conventional register RD which memorizes it at the instance of an order C4 coming from P0 Such a result is always present at the output of RD~ con-nected to MX through connection 17, until a new order C4 arrivesO
Blocks RG~ M, RD form together a multiplying block BM, con-nected at its input to connection 16 and at its output to connection 17, to which reference will be made later to discuss generally all the operations just examined for RG~ M, RDo Unit UT consists essentially of a digital quartz oscillator OD~ which for the exemplary gross line speed of 3200 bits per second~selected for the purposesof description, oscillates at a basic frequency fO of 12288kHz, and feeds two cascades of frequency dividersO
A first cascade comprises a divide-by-three circuit DT~
which generates a signal Tl, having, in the chosen example, a fre-quency of 4096kHz; as already seen, Tl is uti.lized as the master clock for blocks SQ, P, ALo A second cascade comprises two frequency dividers DP, DFo DP is a conventional programmable frequency divider, in the sense that its division ratio may be modified from tilne to time upon receiving a suitable correction signal; in this case, said ~.` i 6~7 signal comes from AL through connection 21.
DP receives from OD the basic frequency fO and carries out the division of the same by a suitable coefficient N, which in our ex-example is 256,incremented or decreased by a corrective factor e which coindices with the correction signal present on connection 21; the modulus and sign of the factor ~ are automatically computed by AL
at each symbol interval.
At the output from DP a frequency f is obtained, which has the value:
fo fo fo fa -- ~
N + ~ N N
Frequency divider DF receives at its input the frequency f and generates at the output signals T2, T3, T40 Signal T2 has a frequency equal to f /6, which corresponds to [8 - (1/6)(fo/N)o~ kHz; T2 controls blocks SQ, A/D and D/A (FigO
2)o Signal T3 (FigO 3) has a frequency fa/20, which corres-ponds to (204 _ 1 0 fo e ) kHz T3 controls, in the blocks RI, RU (Fig.2), data synchronization to and from TD2 at subscriber's frequencyO
Signal T4 (Fig. 3) has a frequency f /120, which corre-sponds to ~0,4 - (1/120)o(fO/N)oeJkHz; T4 synchronizes, in the blocks RI, RU (FigO2), the signalling information from and towards TD2 at the format frequency, which is equal as known to 1/6 of the net subscriber's speedO
The term~(fo/N)oe]J just emphasized, represents a small frequency shift with respect to the frequencies considered (i.eO
relative to the basic frequencies of signals T2, T3, T4); it is able to change the sampling frequency of the signal coming from the line ?~ 7 and present on connection 3 (FigO 1), so as completely to slavethe locai clock to the network clock both in frequency and phaseO
This slaving is realized in practice through a phase-locked-loop (PLL) of digital type, consisting of unit UT, of a connection carrying the signal T2 to blocks SH and A/D (FigO 2), of the same blocks SH, A/D, of unit UE (FigO 3) and finally of a connection 21 which transfers the correction signal to unit UTo The resulting feedback branch of PLL is realized more specifically by means of the previously discussed programmable fre-quency divider DP and divider DF, which generate a variable sampl-ing frequency coincident with signal T2, such as to allow sampling of the signal coming from the line (3, CF, 4 of FigO 1) at the optimum instantO
As already explained, unit AC needs no phase-locked loop;
consequently the programmable divider DP (FigO3) may be replaced by a f ixed f requency divider, provided that the latter is duly synchronized to the signal coming from OC (FigO l)o FigO 4 shows, in time sequence, the operating phases of the logic unit UM represented in the scheme of Fig. 30 More particularly, the notations contained in the flow chart of Fig. 4 have the following meanings;
ACC - switch on of the equipment;
INIZ - initialization phase;
SYNC - waiting for synchronising signal, coincident with leading edges of signal T2;
PORT - carrier generation; in the chosen example it has a fre-quency of 1800 HZ;
TR - generation of the sample of modulated signal to be trans-mitted onto the line;

U7 ~ emission towards D/A (FigO2) of the sample generated in the previous step TR (Fig. 4);
18 - loading of the sample of the modulated signal, coming from the line through A/D (FigO 2);
RIC - reception and demodulation of the sample loaded in the previous phase 18 (FigO4);
DEC - check of the conditions essential to the recognition of the optimum decision instant; if said conditions are verified, path SI is followed, otherwise path N0 is followed, thus returning to phase SYNC;
DIBIT - decision and recognition of a received dibit (pair of bits)o As it will be seen later herein, the modulation system adopted is such that it groups the information relative to two bits into a single ~ymbol;
PLL - extraction of synchronism from the samples loaded during phase 18 and processed during phases RIC, DEC, DIBIT;
SGRR - processing at the receiving end of the signal network.
In this phase a received 8 bit envelope is loaded and pro-cessed;
0 ALL - check of the frame synchronism of the received format sequence;if such synchronism is verified, the path denoted by SI i9 followed, otherwise the path denoted by NO is followed and subsequent phase RALL is reached;
RALL - recovery of the frame synchronism condition;
I6 - loading of data and signaling instructions coming from RI
(FigO 2) and generated by the subscriber;
SGU - processing of subscriber's signals;
U5 ~ emission towards subscriber, through RU (FigO 2), of signal-ing instructions and data;

3~'7 SGRT - processing, during transmission,of network signalsO In this pase a 8 bit envelope for transfer to the network is built upO
The time interval necessary to follow any loop shown in FigO 4 is always equal to the period of signal T2, iOeO 125 microseconds.
There will now be described, with reference to the drawings, the whole operation of the apparatus and more particularly of the microprogrammed unit of the inventionO
Hereinafter it will be supposed, by way of example,that quaternary differential phase modulation system (DPSK) is used with a modulation speed of 1600 baud, and transmission of two bits of information per symbol (dibit transmission), thus giving, as already mentioned, a transmission speed of 3200 bits per secondO Thus, by the sampling of signal T2, carried out at a frequency of 8 kHz, five samples per symbol are obtained, resulting from the ratio bet-ween the values 1600 and 8000.
The carrier frequency is assumed to be 1800 Hz; a spectral contour is adopted so that at a relative attenuation of 50%, the modulated signal has a bandwidth extending between 600 Hz and 3000 HZo In the microprogrammed unit of the invention, all the operat-ions relative to carrier generation, modulation and demodulation of the DPSK signal, sync extraction from the received signal and locking thereto of the transmitted signal, are carried out wholly digitally, under microprogram control in unit UC (FigO 3)0 The subscriber's data set AU (FigO 1), as already described, carries out the double function of modulation and demodulation of the data signals and of processing the signals from the network and from the subscriber; the former takes place between the phase 7'7 PORT (Fig. 4) and the phase DIBIT, whilst the latter takes placebetween phase PLL and phase SGRT.
The exchange data set AC (FigO l) does not carry out, as al-ready mentioned, any signaling processing, and so it merely performs a modulation and demodulation operation, the steps of which are comprised between the phase PORT (FigO 4) and the phase DIBIT, and acts also as a pure interface between the line and exchange equip-ment OC (FigO 1) this taking place, for data only, in two phases analogous to those described as I6 and U5 (Fig. 4).

To examine in detail the operation of equipment AU (Fig.l) further reference will be made to the diagram of FigO 4O
The significance of the first two phases ACC and INIZ is ob-vious and common to all logic apparatus, and so will not be further described.
If there are no transmissionsin progress, AU (Fig. 1) emits and receives continuously a determined bit sequence with respect to the line (3, CF, 4) consisting, for instance in the transmission phase of an 8-bit envelope, having the following structure;
the first bit (F) is alternatively 0 and 1 and is used for frame synchronisation;
from the second to the 7th bit, binary 1 s are transmitted, to indicate that the subscriber's terminal equipment TD2 is available (free);
the 8th bit is at 0 to indicate that no data transmission is in progressO
The microprogrammed unit UM of UA first generates by itself the bits of the above envelope; then, during phases PORT and TR
(Fig. 4), AU (FigO 1) groups them into dibits and modulates them according to the DPSK system, so generating digital samples 7~

representing the amplitude of signal DPSKo The computation of each of said samples is effected as hereinafter described.
In the phase PORT (FigO 4), the address is calculated in AL of the locations in the ROM (read-only-memory) of MD containing two constants expressing the present values of the sine and cosine of the sinusoidal carrier. These values, through connections 16, 18, 19 and blocks MX and SC, are transferred to AL, which makes them available at the output on connection 15; then they are memoriz-ed, upon order C7, in the read-write portion RAM (random access memory) of the memory MD, at addresses previously supplied by AL
on the connection 200 In the subsequent phase TR (FigO 4) signal modulation is carried outO
In the read-only-memory portion (ROM) of MD (FigO 3), there are present among the constants recorded, there are present constants characterizing the entire output of a shaping filter for the transmission signal, for the purpose of limiting the band occupation of the signal and operating at a sampling frequency of

8 kHzo For technical design reasons, such shaping is carried out on the modulating signal instead of on the modulated signal, that is to say at base-bandO
To carry out the modulation it is r.ecessary to carry out a band shift; the shifted band, as is conventional in telephone channel modems, has a central frequency of 1800 HZo Such a band shift, as it will be better disclosed after-wards, is obtained by multiplying, at a rate of 8 kHz, two of said shaping filter constants by the relative in-phase ( cosine) and in-quadrature (sine) constants of the carrier at 1800 HZ, as calculated in the phase PORT and memorized in another portion of the RAM of MD.
For these operations, the addressing of MD is calculated in AL in the phase TR (Fig. 4), on the basis of the information supplied from P through Cl (FigO 3) and S, and sent to MD through connection 200 More particularly, still in phase TR (FigO 4), the first , filter constant which relates to the less significant bit of the dibits is first addressed and read, then the bits of said constant are offered at the output connection 16 (FigO 3), but they are memorized by RG only upon order C8.
Subsequently AL supplies the address of the sine constant of the sinusoidal carrier which is sent to MD through connection 20;
at the output from MD, on connection 16, there are the bits of the constant of the sine of the carrier, which are multiplied automatical-ly in M~ in combinatory way, by the bits of the filter constant previously memorized in RG and presented to M through connection 220 The bits of the resulting product are sent by M to RD
through connection 23 and memorized in RD upon order C40 Multiplexer MX, upon order C3, selects connection 17 coming from RD, connecting it with connection 18 at the output of MX, and the signal C2 predisposes SC to pass the signal directly (scaling it by 2) between the input connected to connection 18 and the output connected to connection l9o Upon order Cl, AL memorizes in one of its internal load registers the bits present at the input connected to connection l9o MD is then addressed by AL through connection 20, to read the second filter constant relating to the more significant of the '7 bits comprised by the dibits; the bits of the constant are offered at the output on connection 16 and mernorized by RG upon order C8, in a similar manner to that described previously.
The address of the constant corresponding to the cosine of the carrier is supplied by MD and sent to AL through connection 20; the bits of the constant are then sent to M, through connection 16, and there multiplied by the bits of the filter constant, pre-viously memorized in RG and presented to M through connection 22.
The product produced in M is transferred through connection 23 to RD and there memorized upon order C~0 As meanwhile orders C3 and C2 remain unchanged, MX and SC go on transferring the bits present on connection 17 directly to AL on connection l9o Upon receiving order Cl, the bits present at the input of AL on connection l9 are added to the contents of the loaded internal register previously considered, wherein the result of the sum is memorized.
This result is transferred from AL first to MX, through connection 15, and subsequently, upon receipt of order C3, from MX
to circuit SC, through connection 180 The result sotransferred undergoes in SC, upon receipt of order C2, an 8 bit scaling towards the least significant bit, that is it is divided by 28, so as to align its most significant bit the less significant portion of the configuration; this alignment operates to adjust the output to the capacity of converters D/A
which operates on configurations having a lesser number of bits than ALo Thus, a sample of DPSK signal to be transmitted to the line through connections 15 and 17 has been prepared in ALo In fact there is present in AL a bit configuration which represents the sumof the products of two constants representing the signal shaping filter and constants representing the corresponding samples of the sine and cosine of the carrierO
It should be noted that this DPSK sample is the first of five samples to be prepared in respect of the symbol comprising the first dibit of the envelope previously considered which represents the condition in which no transmissions are in progress through the data setO
The actual transmission of the prepared sample to D/A occurs during phase U7 (FigO 4) through connections 15 and 7 (FigO 3)O
As already mentioned, each sample is transmitted at a rate of 8 kHz, and is subsequently converted into analog form by D/A
(FigO 2), filtered by FU, and transmitted as an analog signal to line 30 The second sample to be generated by the procedure discussed above will be the second of five samples relative to the first dibit;
the third sample will be the third among said five samples and so on to the sixth sample, which will be the first among the five samples 20 of the second dibit, and so onO
The transmission of the envelope being processed will be over when twenty samples are transmitted, that is five samples for the four dibits of the envelope.
Within the period of signal T2, which is 125 microseconds, besides the transmission phase described above, AU may receive and process a DPSK signal from line 30 More particularly, the DPSK signal, which is transmitted along the line in analog form~ is filtered from noise in FI, is sampled and held at a rate of 8 kHz (timing signal T2) in SH; is con-30 verted into digital form by A/D and is then sent to MX (FigO 3) through connection 80 In phase I8 (FigO 4) there is present on connection 8(FigO
3) a parallel bit configuration which digitally represents the amplitude and the sign of one of the samples obtained from SHo Still in phase I8 (FigO 4) order C3 (FigO 3) MX to select theinput connected to connection 8, and order C2 maintains in SC
a direct connection between connection 18 and connection l9o Then order Cl gives to AL the instruction to transfer the bits of the received sample, present at theinput 19, to output 150 Subsequently AL, through connection 20, supplies to MD
the address in which the bits present on connect~n 15 are to be memorized; this memorizing operation in MD then occurs upon receipt order C70 It is then necessary to carry out, on the signal represent-ed by said bit configuration just memorized in MD, a transfer to base-band which is complementary to the opposited transfer carried out in the transmission phaseO
To this end, it is necesaary to m~ltiply the memorized bit configuration by constants representing samples of the sine and co-sine of the carrier, corresponding to those already considered inthe description of the transmission phase, as a demodulation of coherent type is carried out; it is then also essential to carry out a filtering operation to eliminate the component which is generated at a frequency double that of the carrier frequencyO
Such multiplications are carried out by AL in phase RIC
(FigO 4) by utilizing multiplying block BM (FigO 3) and blocks MD, MX and SC following a procedure analogous to that previously de-scribed in relation to the transmission phase TR (FigO 4)0 Still during phase RIC, the filtering operation is carried 3 out on both the in - phase (cosine) and quadrature (sine) branches ~ ~ ~T~6~7 7 of the product of the received signal memorized in MD (FigO 3), and the samples of cosine and sine of the carrier. This filtering operation is carried out by two transversal filters, identical for the two branches, each having a predetermined number L of inter-mediate tapsO Filter coefficients are stored in yet a further portion of the read-- only - memory (ROM) of MDo In a part, different from those previously mentioned, of the portion RAM of MD there are stored, in suitable cells, L + L sam-ples representing the product of the value of the received signal sampled in L subsequent instants distant 125~ sec from one another and multiplied by constants representing L samples of the sinusoidal carrier (phase and quadrature) at successive intervals of 125 ~sec, each in the manner already described.
The filtering operation is carried out in AL by summing up the products of the filter coefficients and the contents of the aforementioned portions of the RAM of MD; said cells are equivalent to the delay line of the filterO
The results of the filtering operation of the in-phase branch as well as of the quadrature branch are stored in the RAM
of MDo At this point, the RAM contains two samples of the signal received and reconverted to base band, one obtained fr~m the in-phase branch, the other one from the quadrature branchO These two samples remain in the RAM for one symbol duration, so that they may be compared with the samples which will be processed in five successive cycles of the signal T2 at 8 kHz.
This comparison, as is known in the art, is useful to ex-tract information relating to phase shift between successive symbols of DPSK signal received from the line, so as to recover the dibit represented by the received symbolO

7~7 This comparison is made in practice between the results of the filtering (in-phase and quadrature) of the sample under con-sideration and the filtering results loaded five samples beforeO
To carry out this comparison, blocks AL, BM and MD CO-operate, still in phase RIC (FigO 4) in a series of crossed multi-plications and subsequent sums,effecte~ according to the procedure already discussed, so as to implement the functions of a conventional comparison detectorO
At the end of the comparison detection procedure, two samples are present in two registers of AL; each sample represents the demodulated signal relative to one of the two bits of the dibit which is being received; this demodulate~d signal may be used to produce the eye diagram, as is well known to those skilled in the art.
Although the demodulation comprised by phase RIC of FigO 4 is complete, as yet no assessment has been effected on the receiv-ing dibit; this assessment is carried out during the subsequent pha~es DEC and DIBIT as it will be described belowO
In phase DEC, unit AL (FigO 3) calculates the derivative of each of the two demodulated signals obtained at the end of the pre-vious comparison operationO This derivative is in practice comput-ed as an incremental ratio between the sample of demodulated signal and the sample of the signal which was demodulated two periods of signal T2 (at 8 kHz) previously and is proportional to the derivative computed in respect of the intervening sampleO
The operations for the computation of the derivative are carried out by unit AL with the cooperation of memory MDo The derivative is correlated by AL and MD with the intervening sample by multiplying it by the sign of said sample so as to make the information of the derivative independent of the sign of demodulated 7~;~
signal.
The two correlated derivatives that are derived from the two demodulated signals, are added together by AL in order to obtain a single resulting derivative, proportional to the arith-metical mean of the two correlated derivatives, in respect of the two in - phase and quadrature branchesO
Obviously, as for demodulated signals, the resulting derivative also consists of a discrete sequence of digital values which follow one another at a rate T2, and are associated in fives with each received symbolO
Then the mean in time of each of the five digital values for each symbol is carried out, thus obtaining five new values (derivative samples), expressing the median trend of the derivative resulting within each symbolO In practice this mean~is calculated by AL and MD which cooperate to implement a first order recursive low-pass filter having an appropriate time constantO
The optimum decision instant, as known in the art, coincides with the point of maximum opening of the eye diagramO When con-sidering the derivative of the demodulated signal to which latter the diagram strictly speaking applies, the maximum opening con-dition of the eye corresponds to the zero condition for the deriva-tive, such a zero being present at points of the same negative slopeO
Thus, on the basis of the consideration discussed above, it will be sufficient to identify that derivative having a value nearest to zero among the derivatives of the five samples already discussed provided it is preceded by a positive derivative of a sample and followed by a negative derivative of a sampleO
To make this choice, during each period of signal T2, that is every 125 microseconds, AL compares the most recently computed ~ 25 -derivative with the two preceding derivatives stored in MD.
This comparison is made as follows: denoting by A thevalue of the derivative just computed, by B the immediately pre-ceding derivative, and by C the derivative preceding B, the occurrence of the following four conditions is checked, still in phase DEC;
(a) A < O
(b) C ~ O
(c) ¦BI~ ~Al (in modulus values) (d) ¦ B~ C¦ (in modulus values)O
As soon as AL (FigD 3) detects the non-occurrence of one of said conditions, DEC is exited (FigO 4) by the path denoted by NO and phase SYNC is reentered in order to process the subsequent DPSK samples both going out on and entering from the lineO
Otherwise, the path denoted by SI is followed, thus passing to phase DIBITo It will be understood that if one derivative out of five is to be chosen, path NO must be followed four times and path SI once in every symbol intervalO
In phase DIBITJ AL (FigO 3) makes a decision on the re-ceived dibit, and accepts as optimal instant for the decision it-self that corresponding to sample derivative B, the middle one of a group of three which satisfy the four conditions discussed aboveO
Then in phase PLL (FigO 4), AL (FigO 3), on the basis of the modulus and sign value of the derivative B, generates the correction factor ~, already previously described, which is sent to UT through connection 210 More particularly, AL compares the modulus value of B
with a predetermined thresholdO If the threshold is not exceeded, it means that in that symbol period, no correction is needed and AL allots to ~ the value zero; if, on the contrary, the threshold is exceeded, AL examines the sign of B and allots it to ~, which will take a pre-determined modulus valueO
The correction operation carried out by signal ~ on sampl-ing timing T2 of the signal coming from the line, minimizes as a consequence the valùe of the modulus of the above utilized deri-vative B, at the decision instant; this implies that the decision instant corresponds to the instant of maximum eye opening.
At this point in the cycle, the modulation/demodulation function of equipment is complete.
~ow phase SGRR (FigO 4) and the following phases are ac-complished, during which signals generated both by the subscriber and by the network a~e processedO
At this point, if the condition considered initially is maintained,in which no connections are in progress or are being formed, the already discussed envelope to be transmitted (FllllllO) is confirmed, and the dibit just recognized cooperates in the for-mation of the envelope which is being received, this also having the form (FllllllO)o O ~erwise, if a connection is in progress or is being formed or broken, the envelope, in the reception phase as well as in transmission phase, takes up a different configuration; more particularly:
the first bit (F) is always alternatively 0 and 1 and is utilized for frame synchronisation;
the 2nd to 7th bits present either configurations of 1 and 0 forming data transmitted or received, or pre-determined binary configurations forming control signals from NRD (FigO 1) to AU or vice versa;

7'7 the 8th bit is at 1 when data transmission is in progress, that is the 2nd to the 7th bits represent data; otherwise the 8th bit is 0 when the 2nd to the 7th bits represent a control signalO
The phases from SYNC (FigO 1~) to PLL, already described, are all followed even when a connection is in progress or is being made or broken, and the associated different types of envelopes are being dealt witho In phase SGGRR, AL (FigO 3) examines bit by bit the re-ceived dibit to decide its location within the incoming envelope.To establish this location AL counts, with modulus 8, the number of received bits: once the position of the received bit within the envelope is detected AL behaves subsequently in the manner to be described belowO
If, on the basis of the above described count, the re-ceived bit is assumed to be bit F, iOeO a frame synchronisation bit, then AL, in conjunction with MD, starts a checking procedure of the frame alignment of the received envelopeS~basically con-sisting in checking the alternation of 0 and 1 for the sequence of bits F; this procedure takes place during phase ALL (FigO 4).
To avoid losses of alignment due to possible demodulation errors, AL ( Fig. 3) extends this alternation check to an integral number of envelopes greater than two, and only after a predetermined number of transgressions of the alternation requirement does AL
decide that an out-of-alignment condition existsO
More particularly, when an out-of-alignment condition is revealed, phase ALL iS exited (FigO 4) by the route denoted N0 towards phase RALL which will be considered hereinafter; otherwise, under alignment conditions, phase ALL is exited, passing along the route denoted by SI towards phases I6, SGU, U5, SGRT, which in the case of bit F do not carry out any processing operation9 then phase SYNC is again reached for processing subsequent bitso In phase RALL, the recovery of frame alignment is ac-complished by shifting the modulo - 8 counter contained in AL
(FigO 3) through one position, so that the following bit may be processed as a bit Fo If, in successive envelopes, this bit on examination satisfies the condition of alternation of 0 and 1 for a predeter-mined number of cycles, its recognition as bit F is confirmed andalignment is considered to be recoveredO Obviously this examina-tion is effected on a number of received envelopes in excess of 2, implying a corresponding number of repetitions of the phases ALL, RALL of FigO 4.
If on the other hand the bit examined does not verify the alignment condition, the recovery procedure is continued by further shifts of the modulo - 8 register in AL, until a bit is found which is able to confirm the alignment conditionO
The 2nd to the 7th bits and the 8th bit of each received envelope are recognized on the basis of the counting operation carried out by AL (FigO 3) on bits received in phase SGRR (Fig.4), and are memorized in portion RAM of MD (FigO 3)0 In respect of the 2nd to the 7th bits phases ALL (FigO 4), RALL, 16, SGU, U5, SGRT are accomplished without carrying out any operation; for the 8th bit only phases ALL and RALL are accomplished without any operationO
The exchange of information coming from IN (Fig. 2) and transferred to UM through register RI is now examined.
In phase I6 (FigO 4) data bits present on connection ll are loaded by AL (FigO 3) through MX and SC, and control bits, present on connection 12, are transferred to SQo In phase SGU (FigO 4) the subscriber's signal is pro-cessed on the basis of the bits loaded during preceding phase I6, and on the basis of the envelope received from the line and loaded in phase SGRRo More particularly, the bits present on connection 12 (FigO
3) condition the addressing of MM by SQ, and thus the microinstruc-tion placed by MM on connections 10 and 14, and thence the whole subsequent progress of the microprogram, depend upon the control information coming from the subscriber, through RIo Furthermore, if the logic state of the 8th bit of the en-velope received from the line is at 0, this signals that control signals from the 2nd to 7th bits of said envelope are to be re-cognized; such recognition allows the received control signals to be decoded and suitable decisions to be takenO
In phase U5 (Fig. 4) the bits processed in previous phase SGU are sent to the subscriber, through RU and IN (FigO 2)o In phase SGRT (FigO 4), on the basis of the same inform-ation which conditions the processing taking place in phase SGU,either the network signal in course of transmission is processed, or the 8 bit envelope to be transferred onto the line is built up and memorized in MD (Fig. 3).
This envelope, divided into four dibits, will also be utilized in the four subsequent cycles in phase TRJ for applying the DPSK signal to the line, according to the above described procedureO

Claims (5)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A microprogrammed unit for use in a data set at a data terminal or at an associated exchange of a network said data set comprising, besides said unit, an interface, a pair of buffer registers, a complementary pair of analog/digital and digital/
analog converters, a pair of filters and a sampler, said micro-programmed unit consisting of three functional blocks;
the first functional block being a processing unit comprising:
an arithmetic logic unit of a microprocessor;
a multiplier unit to carry out fast multiplications be-tween parallel bit-configurations;
a memory comprising a read-only memory portion and a random-access memory portion acting as a data memory in conjunction with said arithmetic logic unit and said multiplier unit;
a multiplexer to select a bit configuration to be sent to said arithmetic logic unit; and a programmable scaler able to carry out multiplication and/
or division with a variable modulus which is a power of two, on the bit configuration selected by said multiplexer;
the second functional block being a control unit comprising:
a read-only memory acting as a program memory and con-taining a predetermined set of microinstructions;
a sequencer to supervise the operative sequence of micro-instructions and to supply to said program memory the address of microinstructions for immediate execution; and a register to convert the microinstructions received from said program memory into control bit configurations and able also to identify a binary signal forming a constant characteristic of each microinstruction; and the third functional block being a timing unit comprising:
a digital oscillator generating a fundamental frequency;
a first frequency divider dividing by three said funda-mental frequency to generate a master clock signal;
a programmable frequency divider dividing said fundamental frequency by a predetermined coefficient incremented or decreased by a corrective value computed at successive symbol intervals by said arithmetic logic unit, so as to originate a programmed frequency; and a second frequency divider dividing the programmed freq-quency generated by said programmable divider by constants 6, 20, 120 so as to obtain three timing signals used to control the operation of the unit.

2. A microprogrammed unit according to claim 1, characterized in that said multiplier unit comprises:
a first register, acting as a buffer memory, to receive in sequence the configurations of parallel bits obtained by reading said data memory;
a multiplier able to carry out parallel combinatory multi-plication between the bit configuration present at the output of said first register and a subsequent bit con-figuration as soon as it is presented at the input of said first register; and a second register, also acting as a buffer memory, to store temporarily the result present at the output of said multiplier.

3. A microprogrammed unit according to claim 1 or 2, when used in a data set at a data terminal of the network, wherein said first block and said second block operate in conjunction and are programmed so as to perform in real-time, both as a modem and to perform control operations characteristic of a network terminal.

4. A microprogrammed unit according to claim 1, when used in a data set out at a data terminal of the network, wherein said first block and said third block operate in conjunction and are programmed to lock, both in frequency and in phase, the timing of the unit to the network timing, said slaving being realized through a phase locked loop comprising of said programmable frequency divider said second frequency divider, of a connection carrying the first of said timing signals to the analog-to-digital con-verter of said pair of converters and to said sampler, of the same said analog-to-digital converter and sampler, of the arithmetic logic unit and of the connection carrying said corrective factor to said programmable frequency divider.

5. A microprogrammed unit according to claim 4, wherein the frequencies of said three timing signals generated by said second frequency divider are modifed in real time by a shifting factor which is proportional to said corrective factor, in order to obtain said frequency and phase lock.