CA1147072A - Electrical communications system - Google Patents
Electrical communications systemInfo
- Publication number
- CA1147072A CA1147072A CA000363041A CA363041A CA1147072A CA 1147072 A CA1147072 A CA 1147072A CA 000363041 A CA000363041 A CA 000363041A CA 363041 A CA363041 A CA 363041A CA 1147072 A CA1147072 A CA 1147072A
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- Prior art keywords
- memory
- communications system
- communications
- coupled
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- 230000006854 communication Effects 0.000 title claims abstract description 95
- 230000015654 memory Effects 0.000 claims abstract description 112
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
- H04B10/2575—Radio-over-fibre, e.g. radio frequency signal modulated onto an optical carrier
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
Abstract
ELECTRICAL COMMUNICATIONS SYSTEM
Abstract Disclosed is a system for communicating electri-cal signals, digital and/or analog, from one location to another first over an RF communications link and then secondly over an optical communications link. A first digital memory is included on the transmitter side of the RF communications link so that a plurality of fixed or portable signal sources can feed data thereto in a desired sequence for subsequent transmission upon demand first to at least one second or interim digital memory at the end of the RF communications link and then to at least one third digital memory at the end of the optical communications link. The third memory is located in a terminal unit, fixed or portable, which is adapted to feed the data transmitted thereto to one or more utiliza-tion devices.
Abstract Disclosed is a system for communicating electri-cal signals, digital and/or analog, from one location to another first over an RF communications link and then secondly over an optical communications link. A first digital memory is included on the transmitter side of the RF communications link so that a plurality of fixed or portable signal sources can feed data thereto in a desired sequence for subsequent transmission upon demand first to at least one second or interim digital memory at the end of the RF communications link and then to at least one third digital memory at the end of the optical communications link. The third memory is located in a terminal unit, fixed or portable, which is adapted to feed the data transmitted thereto to one or more utiliza-tion devices.
Description
~71:3~2 Back~ound of -the Invention . . ~
This invention rela-tes generally to cornmunica-tions apparatus and more particularly to a sys-tem whereby both digita] and analog s;gnals in any desired combination are transmitted on demand from one or more sign~l sources to a selected one or more utilization devices.
Communica-tions at radio frequencies over wired and wireless transrnission channels are well known. More recently the emergence of fiber optic conductors of ligh-t has found utility as a medium for transmitting a signal carrier in the light region of -the electromagnetic spec--trum. In the case of digital data, memories have also been included at either end for purposes of multiplexing and demultiplexing data from plural sources so tha-t a common channel can be utilized. I~hile these various and sundry systems are adapted to accomplish a wide range of tasks, it is the purpose o:~ the present invention to provide an improvement in such communica-tions systems, particularly for transmitting digi-tal data, originating at diverse signal sources, ~rom one loca-tion to another and stor;ng the data for a momentary or predetermined time for subsequent selec-ted utilization by one or more diverse utilization devices.
Summar~
The present invention is directed to a system wherein a plurality o~ data streams originating at separate input signal sources, fixed or portable, are fed to a first random access memory which when loaded is ou-tputted on demand, either automatically or manually, over a first energy type or RF communications link ~o a second random access memory. The second memory on demand, outputs the data coupled thereto from the ~irst memory over a second energy type, optical or when desir-able inductive, communications link to a terminal device including a third random access memory. On demand, -the third memory outputs its contents to one or more utiliza-tion devices. The means included in the first energy type ~7¢~'72 COmlllUniCat; OllS li~k ls also adapted to i.nclude means for simultaneously -transml-t-ting analog data along with the digital data. In one form, the first and second random access memories on ei-ther side of the first -type communications li.nk are adapted to remain rela-tively stationary, whereas the input signal sources and the terminal device including the third random access memory may be selectively a portable or fixed piece of appara-tus, depending upon the use intended.
Brief Description of the Drawings Figure 1 is a block diagram broadly illustra-tive of the subject invention;
Figure 2 is a detailed block diagram illustra-tive of the preferred embodiment of the RF transmission portion of the system shown in Figure l;
Figure 3 is a detailed block diagram illustra-tive of -the RF receiver and optical transmi-t-ter portion of the system shown in Figure l;
Figure 4 is a detailed block diagram illus-tra--tive of the optical receiver portion of the system shown in Figure l; and Figure 5 is a de-tailed block diagram illus-trative o~ a -typical memory control circuit for opera-ting the random access memories shown in Figures 2, 3 and 4.
Descrlption of -the Preferred Embodiment ~ eferring now to the drawings and more particu larly -to Figure 1, a plurality o~ signal sources 101, 12 and 103 are shown coupled to a digital memory 12, preferably a random access memory (P~AM) operated by means of a memory controller 14. The memory controller 14, a typical example of which is further disclosed in Figure 5, is adapted to load data into the RAM 12 and upon demand, either automatically or manually, ou-tput i-ts contents in sequence to an RF (first energy type) transmitter 16 where it is modulated onto an RF carrier. The carrier is then coupled to an RF communications link 18 in the 7~7~d form of a signal which is adapted for transmission via a radio/microwave antenna or a coaxial cable. Additionally, an analog signal source 20 which is adapted, for example, to generate an audio and/or video signal, is also applied to the RF transmitter 16 for simultaneous single or multi-plexed transmission over the RF communications link 18 with the digital da-ta outputted ~rom the memory 12.
A-t the far or receiving end of the RF communica-tions link 18 is located an RF receiver 22 which is adapted to demodula-te the communications signals on the carrier and accordingly couple the analog signal -transmitted to an analog signal utilization device 24 while the digi-tal data outputted from the RAM 12 is fed into a second random access memory 26 under the control of a respec-tive memory controller 28. The memory controller 28 ondemand subsequently ou-tputs the conten-ts of the RAM
26 to an optical (second energy type) transmitter 30 where the data is modula-ted onto a carrier of light energy. The light energy is transmitted over an optical communications link 32 -to an optical receiver located in a -terminal device, no-t sho~n. The light signal is de--modula-ted and the digital data is fed into a third random access memory 36 under the control o~ its own memory controller 38. Upon demand, the digital memory 36 ou-tputs the digital data fed thereto selectively to one or more utility devices 4l~ 402 and ~03.
What the broad sys-tem disclosure of Figure 1 is intended to show is the concept of first sending digital and/or analog signals originating at a plurality of input signal sources, some or all of which may be portable, over RF communication means utilizing various types of modula-tion techniques e.g. frequency modulation, phase modula-tion-, amplitude modulation, pulse code modulation, stored either on a real time or long term basis for later optical transmission to a device, either portable or fixed, which is adapted to store the selected s;gnals ~7 ~ 2 as necessary arld thereafter apply i-t -to prede-termined ut;li~ation device(s). Particularly, however, digi-tal data in the ~orm of a data stream is adapted to be intermedia-tely or momentarily stored, for selective -trans-5 ~er upon command to the next location. Thus the datafrom any of the digital signal sources 101, 12 and 103 is first relayed to the digital RAM 26 over -the RF link 18 a-t some appointed time. Thereafter when it is desir-able to do so, the data s-tream is then coupled over the optical communications link 32 to thedigital memory 3S.
This concept has particular utility, for example, where -the optical receiver 34, the digi-tal memory 36 and the memory controller 38 are all included in a portable terminal, not shown, which is adapted to be brought, from time to time, into proximity with the optical -transmitter 30, which is located in a fixed installation, also not shown. r~ore particularly, the fixed installation at the RF end an~ op-tical transmitter loca~tion may consis-t of a piece o~ hard~are secured to a wall of a building or inside a room with ~the optical transmitter 30 including at least one light emitting diode or other such device which is adapted to output an IR or pulse/in-tensity modula-ted signal. This signal is coupled to a pho-to pick up device contained in a rela-tively small por-table device which is brought into proximi~ty with and pointed at the light emitting source wherein the light is then directed to the photo pick up device, thus completing the optical link 32. The digital memory 26 in the fixed installation can then be ordered when desirable to -transfer its data to the digi-tal memory 36 in the portable device where i-t is then adapted to be displayed, coupled to a pr;nter, or activate some type of control device.
Re~erring now to Figure 2, -there is shown in greater detail -the input side of the system. Whereas the RAM 12 and the memory con-tro~ler 14 are as shown in ~7~172 Fi~ure 1, F;gllre 2 is intended to addi-tionally illus~
tra-te that a plurality o~ diverse input signal sources are adapted -to feed respective digital data s-treams -to the R~M 12 by means o~ a data bus 42, which includes, for example, a pluraLity o~ parallel data lines. The data bus 42 couples -the RAM 12 to the outputs of four input devices; a keyboard 44, a graphics generator 46, a television camera 48 and an auxiliary storage 50 which may be, for example, a read only memory (ROM~. The storage 50 may be comprised of disk, -tape, bubble, core, semiconductor -type of memory of known -type. When desir-able these input devices may be duplicated and some or all may be made selectively portable and coupling to the RAM 12 effected by way of respective optical input/
output ports.
The memory controller 14 is adapted to strobe load the memory addresses of the RAM 12 upon receiving clock signals from the respective signal sources unt;l the desired number of data bytes have been inpu-tted thereto. Upon command, as will be shown when Figure 5 is considered, the memory controller 14 resets the memory -~ddress o~ the RAM 12 an'd th-e data'by-tes stored therein are coupled ln sequence to a multi-line parallel output data bus 60. The data bus 60 feeds into an input gated parallel-to-serial converter 62, which is strobe loaded upon receipt of ~three control signals i.e. gate, strobe load, and clock signals from -the memory controller 14.
The parallel-to-serial converter 62 is a well known device t a typical example being a Fairchild F3843 USART
-(Universal Synchronous or Asynchronous Receiver and Trans~
mitter.) The output from the parallel-to-serial converter 62 is coupled to a frequency shift keying XR-2206 type voltage to ~requency converter 64. ~oupled to the vari-able frequency outpu-t of the converter 64 is a multi-3~ plexer type circuit 66 which is adapted for single ormultiplexed operation so that an analog signal from the source 68 can be applied simultaneously along with the ~SK
ou-tput ~rom the converter 64. The signal source 68 may be, for example, an audio signal source. ~hen desirable, it may be comprised of a video signal source.
The output from the multiplexer 66 is coupled to an RF modulator 70 of any selected design. The RF
modulator generates an R~ carrier signal modulated in accordance with the signals supplied *rom the circuits 64 and 68. The modulated carrier is then fed to a radia-ting antenna 72 or when desirable, to a co-axial cable 74. The RF transmission elements sho~n are not meant to be interpreted in a limiting sense since when desirable other means may also be employed such as, for example, microwave apparatus could also be utilized. Also as noted above, other types of modulation may be resor-ted to when desirable.
Referring now to Figure 3, the RF communications llnk 18 is terminated, as shown, either in a receiving an-tenna 76 or the far end of the co-axial cable 74~ The RF signals appearing thereat are coupled to the input of an RF demodulator and demultiplexer 78 which is oper- -able to remove the analog signal from the carrier and couple it to a transducer elemen~t 80l, which may be, for example, a loud-speaker in the case of an audio signal emanating from the analog signal source 68. The digital data format outputted from the RAM 12 as shown in Figure 2, is also removed from the carrier and is fed to at ]east one digital memory module 801 which includes the RA~ 26 and its associated memory controller 28 originally shown in Fi~ure 1. The memory module 801 may be duplicated when desirable to other identical modules 802 and 803.
In each ins-tance the respective module includes an active filter 82 which is adapted to be frequency selective so that a routing action can be obtained, when desirable, be-tween the multiple memory units. The active filter 82 is coupled to a frequerlcy to voltage ~R-2211 type ~re-quency to vol-tage converter 84 where the frequency shift keying operation is reversed. The variable voltage signal outputted from the converter 84 is next fed to a serial--to-parallel converter 86 which may also be comprised of a Fairchild ~3843 USART inasmuch as it is a duplex device whereby both parallel-to-serial and serial-to-parallel conversions can be implemented thereby. A parallel multi-line data bus 88 couples to the RAM 26 and the multi-bit data stream in the form of bytes are fed into the RAM under the control of -the memory controller 28 which is also adapted to receive a clock signal from the serial-to-parallel converter 86. When desirable the serial-to-parallel converter 86 may embody an address-able gate con-trolling data flow to RAM 26. Once the RAM
26 has been loaded with data from the RAM 12 shown in Figure 2, the memory controller 28 will cause the memory to become inactive until such time that a cycle out command is provided, ei-ther manually or by some des;red means, at which time the RA~ will output its contents which is then strobe loaded into an input gated parallel-to-serial conver~ter 92 over the data bus 94. The serial da-ta s-tream ou-tputted from ~the converter 92 is fed to an amplifier 96 which is adapted to intensity modulate -the light output from a respective light emitting source 98, a typical example being a light emitting diode.
Each of the other memory modules 802 and 803 also couple to individual ligh-t emitting sources 100 and 102 which are respectively modulated in accordance with signals outputted from the respective memories contained therein.
The intensity modulated light outputted from the light emitting source 98 and the light emitting sources 100 and 102 when utilized, are launched into the optical communi- - -cations link 32 which may comprise simply a gaseous medium such as air, or when desirable space or a vacuum, but may also consist of one or more optical fibers 104, which are adapted to couple any one light emitting source to a remo~te pho-to pickup device which may be, for example, a matching photo-diode.
~7~72 _ 9 ~
Turning a-t-ten-tion now -to I~igure 4, a photo pickup device 106 is coupled to the light emitting source 98 o~ Figure 3. Additionally/ photo pickups 108 and 110 are adap-ted to be coupled to light emitting sources 100 and 102 also shown in Figure 3. While -the use of light emitting diodes and the respective photo-diodes is pre-ferred, inductive coupling means can be utilized when desirable for the second energy type communications link.
Each of the photo pickup devices 106, 108 and 110 are adapted to form part of and be coupled to respective terminal units 1121, 1122 and 1123, each of which is adapted to include a RAM 36 and memory controller 38 such as shown in Figure 1.
Each terminal unit 112 includes an amplifier 114 coupled to the respective photo pickup device. The amplifier ou-tput is coupled to a serial-to-parallel con-verter 116 which converts the serial data stream into a parallel data stream which is fed into -the RAM 36 via the data bus 118. The memory controller 38 ~lso receives a clock signal from the converter 116 in order to inîtially reset the memory addresses, strobe tl~e data into the memory--- -and sequentially index the address f`ollowing completion of the storage of each data byte. When desirable, a display device 120 is included. Fol:lowing receipt of the data into the RAM 36, the memory con-troller 38 is then adapted on command such as by means of a cycle out switch, not shown, to output the data contained therein onto an output bus 120 where it is strobe loaded into an input gated parallel-to-serial converter 122, whereupon a serial data stream in the form required by one or more utilization devices, is provided. Utilization devices 4l. 402. 403 shown in Figure 1 are shown in Figure 4 com-prising cathode ray tube display 124, an output printer 126, a graphics display 128 or a switch mechanism 130 for 3~ con-trolling an ex~ternal device, not shown.
~7~7~
Thus the individual random access memories 12, 26 and 36 act in combina-tion with its respective peripheral hardware -to store and transfer digital data which ls coupled to and from the respective memories in ^the form of multiple bi-t data streams or bytes. In order that in-telligent management of the data stream flow be pro-vided an illustrative embodiment of the memory con-trollers 14, 28 and 30 is sho~m in Figure 5.
There a clock signal, generated in any one o~
the data sources 44, 46 .... 50 shown in ~igure 2 or by the serial-to-parallel converters 86 and 116 shown in Figures 3 and 4, is coupled toan input lead 132 which is applied to a one-shot circuit 134. This circuit is an electrical circuit ~or generating a trigger pulse in response to a signal being applied and thereafter auto-matically resetting itsel~ until the next signal is applied. The one shot circuit 134 accordingly responds to the clock signal applied to gene,rate a memory strobe load signal which is coupled to its associated memory for s-trobe loading -the parallel data presentation or byte into a particular memory address. Aclditionall-y, an initial- ~
rese-t swi^tch 136 is included which is adapted to be responsive, ~or example, to the leading edge of the first clock signal to provide a reset signal for recycling the respective memory to the initial or first address posi-tion. Additionally, the initial reset switch 136 is coupled to an address counter 138 and a memory counter 140 which are reset to the zero count position by the action of the initial reset switch. It should also be pointed out that when desirable the reset switch 136 may be comprised of a manually actuated switch device rather than one being shown as operated in accordance with a leading edge of the clock signal.
A second one-shot circuit 142 is coupled to -the one-shot circuit 134 and is adapted to be triggered when ~7~i7;~
circuit 134 resets. The ou-tput of the one-shot circuit 142 provides an ou-tput pulse which is qpplied directly to counter 140 and through buffer 141 to counter 138 to advance -the count each time a byte of data is entered into the respective memory. This process is repeated until all the desired data bytes are en-tered into the appropriate addresses.
~llhen the contents of the respective memory is desired to be outputted i.e. translated to its respective output data bus, a cycle out switch 144t included in each memory controller, is actuated on demand either manually or by remote control and operates to trigger a third one-shot circuit 146 which generates a pulse to reset the address counter 138 to a zero count and triggers on a latch 148 which in turn enables the converter's gated input as well as gate circuit 150 coupled to a local source of clock signals 152. The output of gate 150 provides a clock signal for the parallel--to-serial con-verters. Pulses gated from the local clock source 152 and also divided by a ~ N counter 155 and are fed to a one-shot circuit 154 which is adapted to strobe load the respective parallel-to-serial conver-ters 62, 92 and 122, respectively. The N count is equal to the number of data lines being inputted from serial-to-parallel converters 86 and 116 to their respective memories 26 and 36. Each time the one-shot circuit 154 restores it triggers one-shot circuit 156 which produces a trigger pulse which is coupled -to -the address counter 138 through the buffer amplifier 158, thereby causing the address counter 138 to advance the memory to the next address position. On the next clock pulse outputted from the clock 152 the readout process is repeated. This action continues until the count in the address counter 138 matches -the previously stored coun-t in the memory counter 140. A
comparator circuit 160, coupled to both counters 138 and 140, moni-tors the counters looking for a match, meaning ~7~72 that on readout the a~dr~?ss counter 138 has cycled the rnemory to the same number of coun~ts read into the ~emory counter 140 during the read-in phase. When bo-th counts are equal, the comparator circuit 160 triggers another one-sho-t circuit 1~2 which produces a trigger signal to trigger off the latch 148, which acts to disable the gate 150, thereby interrupting the output o~ clock pulses from the clock 152 to the one-shot circuit 154. This causes the readout cycle to stop, meaning that the read-ou-t process of the da-ta from the respective rnemory has been completed.
Thus what has been shown and described is a means for relaying electrical signals such as digital data first over an RF communications link, and then over an optical communications link, so that data can be conveyed from a local source of diverse signals to a remo-te data terminal having a memory which upon demand can thereafter output the data to one or more selec-ted dlverse types of utilization devices.
Having thus shown and desc:ribed what is at present considered -to be the preferred embodiment of the subjec-t invention, modifications and al-terations thereto will readily occur to -those skilled in -the ar-t. It is not desired, therefore, -that the invention be limited to the specific arrangements shown and described, but it is intended to cover all such modifications and alterations which fall within the true spirit and scope o~ the inven-tion as defined by the appended claims.
This invention rela-tes generally to cornmunica-tions apparatus and more particularly to a sys-tem whereby both digita] and analog s;gnals in any desired combination are transmitted on demand from one or more sign~l sources to a selected one or more utilization devices.
Communica-tions at radio frequencies over wired and wireless transrnission channels are well known. More recently the emergence of fiber optic conductors of ligh-t has found utility as a medium for transmitting a signal carrier in the light region of -the electromagnetic spec--trum. In the case of digital data, memories have also been included at either end for purposes of multiplexing and demultiplexing data from plural sources so tha-t a common channel can be utilized. I~hile these various and sundry systems are adapted to accomplish a wide range of tasks, it is the purpose o:~ the present invention to provide an improvement in such communica-tions systems, particularly for transmitting digi-tal data, originating at diverse signal sources, ~rom one loca-tion to another and stor;ng the data for a momentary or predetermined time for subsequent selec-ted utilization by one or more diverse utilization devices.
Summar~
The present invention is directed to a system wherein a plurality o~ data streams originating at separate input signal sources, fixed or portable, are fed to a first random access memory which when loaded is ou-tputted on demand, either automatically or manually, over a first energy type or RF communications link ~o a second random access memory. The second memory on demand, outputs the data coupled thereto from the ~irst memory over a second energy type, optical or when desir-able inductive, communications link to a terminal device including a third random access memory. On demand, -the third memory outputs its contents to one or more utiliza-tion devices. The means included in the first energy type ~7¢~'72 COmlllUniCat; OllS li~k ls also adapted to i.nclude means for simultaneously -transml-t-ting analog data along with the digital data. In one form, the first and second random access memories on ei-ther side of the first -type communications li.nk are adapted to remain rela-tively stationary, whereas the input signal sources and the terminal device including the third random access memory may be selectively a portable or fixed piece of appara-tus, depending upon the use intended.
Brief Description of the Drawings Figure 1 is a block diagram broadly illustra-tive of the subject invention;
Figure 2 is a detailed block diagram illustra-tive of the preferred embodiment of the RF transmission portion of the system shown in Figure l;
Figure 3 is a detailed block diagram illustra-tive of -the RF receiver and optical transmi-t-ter portion of the system shown in Figure l;
Figure 4 is a detailed block diagram illus-tra--tive of the optical receiver portion of the system shown in Figure l; and Figure 5 is a de-tailed block diagram illus-trative o~ a -typical memory control circuit for opera-ting the random access memories shown in Figures 2, 3 and 4.
Descrlption of -the Preferred Embodiment ~ eferring now to the drawings and more particu larly -to Figure 1, a plurality o~ signal sources 101, 12 and 103 are shown coupled to a digital memory 12, preferably a random access memory (P~AM) operated by means of a memory controller 14. The memory controller 14, a typical example of which is further disclosed in Figure 5, is adapted to load data into the RAM 12 and upon demand, either automatically or manually, ou-tput i-ts contents in sequence to an RF (first energy type) transmitter 16 where it is modulated onto an RF carrier. The carrier is then coupled to an RF communications link 18 in the 7~7~d form of a signal which is adapted for transmission via a radio/microwave antenna or a coaxial cable. Additionally, an analog signal source 20 which is adapted, for example, to generate an audio and/or video signal, is also applied to the RF transmitter 16 for simultaneous single or multi-plexed transmission over the RF communications link 18 with the digital da-ta outputted ~rom the memory 12.
A-t the far or receiving end of the RF communica-tions link 18 is located an RF receiver 22 which is adapted to demodula-te the communications signals on the carrier and accordingly couple the analog signal -transmitted to an analog signal utilization device 24 while the digi-tal data outputted from the RAM 12 is fed into a second random access memory 26 under the control of a respec-tive memory controller 28. The memory controller 28 ondemand subsequently ou-tputs the conten-ts of the RAM
26 to an optical (second energy type) transmitter 30 where the data is modula-ted onto a carrier of light energy. The light energy is transmitted over an optical communications link 32 -to an optical receiver located in a -terminal device, no-t sho~n. The light signal is de--modula-ted and the digital data is fed into a third random access memory 36 under the control o~ its own memory controller 38. Upon demand, the digital memory 36 ou-tputs the digital data fed thereto selectively to one or more utility devices 4l~ 402 and ~03.
What the broad sys-tem disclosure of Figure 1 is intended to show is the concept of first sending digital and/or analog signals originating at a plurality of input signal sources, some or all of which may be portable, over RF communication means utilizing various types of modula-tion techniques e.g. frequency modulation, phase modula-tion-, amplitude modulation, pulse code modulation, stored either on a real time or long term basis for later optical transmission to a device, either portable or fixed, which is adapted to store the selected s;gnals ~7 ~ 2 as necessary arld thereafter apply i-t -to prede-termined ut;li~ation device(s). Particularly, however, digi-tal data in the ~orm of a data stream is adapted to be intermedia-tely or momentarily stored, for selective -trans-5 ~er upon command to the next location. Thus the datafrom any of the digital signal sources 101, 12 and 103 is first relayed to the digital RAM 26 over -the RF link 18 a-t some appointed time. Thereafter when it is desir-able to do so, the data s-tream is then coupled over the optical communications link 32 to thedigital memory 3S.
This concept has particular utility, for example, where -the optical receiver 34, the digi-tal memory 36 and the memory controller 38 are all included in a portable terminal, not shown, which is adapted to be brought, from time to time, into proximity with the optical -transmitter 30, which is located in a fixed installation, also not shown. r~ore particularly, the fixed installation at the RF end an~ op-tical transmitter loca~tion may consis-t of a piece o~ hard~are secured to a wall of a building or inside a room with ~the optical transmitter 30 including at least one light emitting diode or other such device which is adapted to output an IR or pulse/in-tensity modula-ted signal. This signal is coupled to a pho-to pick up device contained in a rela-tively small por-table device which is brought into proximi~ty with and pointed at the light emitting source wherein the light is then directed to the photo pick up device, thus completing the optical link 32. The digital memory 26 in the fixed installation can then be ordered when desirable to -transfer its data to the digi-tal memory 36 in the portable device where i-t is then adapted to be displayed, coupled to a pr;nter, or activate some type of control device.
Re~erring now to Figure 2, -there is shown in greater detail -the input side of the system. Whereas the RAM 12 and the memory con-tro~ler 14 are as shown in ~7~172 Fi~ure 1, F;gllre 2 is intended to addi-tionally illus~
tra-te that a plurality o~ diverse input signal sources are adapted -to feed respective digital data s-treams -to the R~M 12 by means o~ a data bus 42, which includes, for example, a pluraLity o~ parallel data lines. The data bus 42 couples -the RAM 12 to the outputs of four input devices; a keyboard 44, a graphics generator 46, a television camera 48 and an auxiliary storage 50 which may be, for example, a read only memory (ROM~. The storage 50 may be comprised of disk, -tape, bubble, core, semiconductor -type of memory of known -type. When desir-able these input devices may be duplicated and some or all may be made selectively portable and coupling to the RAM 12 effected by way of respective optical input/
output ports.
The memory controller 14 is adapted to strobe load the memory addresses of the RAM 12 upon receiving clock signals from the respective signal sources unt;l the desired number of data bytes have been inpu-tted thereto. Upon command, as will be shown when Figure 5 is considered, the memory controller 14 resets the memory -~ddress o~ the RAM 12 an'd th-e data'by-tes stored therein are coupled ln sequence to a multi-line parallel output data bus 60. The data bus 60 feeds into an input gated parallel-to-serial converter 62, which is strobe loaded upon receipt of ~three control signals i.e. gate, strobe load, and clock signals from -the memory controller 14.
The parallel-to-serial converter 62 is a well known device t a typical example being a Fairchild F3843 USART
-(Universal Synchronous or Asynchronous Receiver and Trans~
mitter.) The output from the parallel-to-serial converter 62 is coupled to a frequency shift keying XR-2206 type voltage to ~requency converter 64. ~oupled to the vari-able frequency outpu-t of the converter 64 is a multi-3~ plexer type circuit 66 which is adapted for single ormultiplexed operation so that an analog signal from the source 68 can be applied simultaneously along with the ~SK
ou-tput ~rom the converter 64. The signal source 68 may be, for example, an audio signal source. ~hen desirable, it may be comprised of a video signal source.
The output from the multiplexer 66 is coupled to an RF modulator 70 of any selected design. The RF
modulator generates an R~ carrier signal modulated in accordance with the signals supplied *rom the circuits 64 and 68. The modulated carrier is then fed to a radia-ting antenna 72 or when desirable, to a co-axial cable 74. The RF transmission elements sho~n are not meant to be interpreted in a limiting sense since when desirable other means may also be employed such as, for example, microwave apparatus could also be utilized. Also as noted above, other types of modulation may be resor-ted to when desirable.
Referring now to Figure 3, the RF communications llnk 18 is terminated, as shown, either in a receiving an-tenna 76 or the far end of the co-axial cable 74~ The RF signals appearing thereat are coupled to the input of an RF demodulator and demultiplexer 78 which is oper- -able to remove the analog signal from the carrier and couple it to a transducer elemen~t 80l, which may be, for example, a loud-speaker in the case of an audio signal emanating from the analog signal source 68. The digital data format outputted from the RAM 12 as shown in Figure 2, is also removed from the carrier and is fed to at ]east one digital memory module 801 which includes the RA~ 26 and its associated memory controller 28 originally shown in Fi~ure 1. The memory module 801 may be duplicated when desirable to other identical modules 802 and 803.
In each ins-tance the respective module includes an active filter 82 which is adapted to be frequency selective so that a routing action can be obtained, when desirable, be-tween the multiple memory units. The active filter 82 is coupled to a frequerlcy to voltage ~R-2211 type ~re-quency to vol-tage converter 84 where the frequency shift keying operation is reversed. The variable voltage signal outputted from the converter 84 is next fed to a serial--to-parallel converter 86 which may also be comprised of a Fairchild ~3843 USART inasmuch as it is a duplex device whereby both parallel-to-serial and serial-to-parallel conversions can be implemented thereby. A parallel multi-line data bus 88 couples to the RAM 26 and the multi-bit data stream in the form of bytes are fed into the RAM under the control of -the memory controller 28 which is also adapted to receive a clock signal from the serial-to-parallel converter 86. When desirable the serial-to-parallel converter 86 may embody an address-able gate con-trolling data flow to RAM 26. Once the RAM
26 has been loaded with data from the RAM 12 shown in Figure 2, the memory controller 28 will cause the memory to become inactive until such time that a cycle out command is provided, ei-ther manually or by some des;red means, at which time the RA~ will output its contents which is then strobe loaded into an input gated parallel-to-serial conver~ter 92 over the data bus 94. The serial da-ta s-tream ou-tputted from ~the converter 92 is fed to an amplifier 96 which is adapted to intensity modulate -the light output from a respective light emitting source 98, a typical example being a light emitting diode.
Each of the other memory modules 802 and 803 also couple to individual ligh-t emitting sources 100 and 102 which are respectively modulated in accordance with signals outputted from the respective memories contained therein.
The intensity modulated light outputted from the light emitting source 98 and the light emitting sources 100 and 102 when utilized, are launched into the optical communi- - -cations link 32 which may comprise simply a gaseous medium such as air, or when desirable space or a vacuum, but may also consist of one or more optical fibers 104, which are adapted to couple any one light emitting source to a remo~te pho-to pickup device which may be, for example, a matching photo-diode.
~7~72 _ 9 ~
Turning a-t-ten-tion now -to I~igure 4, a photo pickup device 106 is coupled to the light emitting source 98 o~ Figure 3. Additionally/ photo pickups 108 and 110 are adap-ted to be coupled to light emitting sources 100 and 102 also shown in Figure 3. While -the use of light emitting diodes and the respective photo-diodes is pre-ferred, inductive coupling means can be utilized when desirable for the second energy type communications link.
Each of the photo pickup devices 106, 108 and 110 are adapted to form part of and be coupled to respective terminal units 1121, 1122 and 1123, each of which is adapted to include a RAM 36 and memory controller 38 such as shown in Figure 1.
Each terminal unit 112 includes an amplifier 114 coupled to the respective photo pickup device. The amplifier ou-tput is coupled to a serial-to-parallel con-verter 116 which converts the serial data stream into a parallel data stream which is fed into -the RAM 36 via the data bus 118. The memory controller 38 ~lso receives a clock signal from the converter 116 in order to inîtially reset the memory addresses, strobe tl~e data into the memory--- -and sequentially index the address f`ollowing completion of the storage of each data byte. When desirable, a display device 120 is included. Fol:lowing receipt of the data into the RAM 36, the memory con-troller 38 is then adapted on command such as by means of a cycle out switch, not shown, to output the data contained therein onto an output bus 120 where it is strobe loaded into an input gated parallel-to-serial converter 122, whereupon a serial data stream in the form required by one or more utilization devices, is provided. Utilization devices 4l. 402. 403 shown in Figure 1 are shown in Figure 4 com-prising cathode ray tube display 124, an output printer 126, a graphics display 128 or a switch mechanism 130 for 3~ con-trolling an ex~ternal device, not shown.
~7~7~
Thus the individual random access memories 12, 26 and 36 act in combina-tion with its respective peripheral hardware -to store and transfer digital data which ls coupled to and from the respective memories in ^the form of multiple bi-t data streams or bytes. In order that in-telligent management of the data stream flow be pro-vided an illustrative embodiment of the memory con-trollers 14, 28 and 30 is sho~m in Figure 5.
There a clock signal, generated in any one o~
the data sources 44, 46 .... 50 shown in ~igure 2 or by the serial-to-parallel converters 86 and 116 shown in Figures 3 and 4, is coupled toan input lead 132 which is applied to a one-shot circuit 134. This circuit is an electrical circuit ~or generating a trigger pulse in response to a signal being applied and thereafter auto-matically resetting itsel~ until the next signal is applied. The one shot circuit 134 accordingly responds to the clock signal applied to gene,rate a memory strobe load signal which is coupled to its associated memory for s-trobe loading -the parallel data presentation or byte into a particular memory address. Aclditionall-y, an initial- ~
rese-t swi^tch 136 is included which is adapted to be responsive, ~or example, to the leading edge of the first clock signal to provide a reset signal for recycling the respective memory to the initial or first address posi-tion. Additionally, the initial reset switch 136 is coupled to an address counter 138 and a memory counter 140 which are reset to the zero count position by the action of the initial reset switch. It should also be pointed out that when desirable the reset switch 136 may be comprised of a manually actuated switch device rather than one being shown as operated in accordance with a leading edge of the clock signal.
A second one-shot circuit 142 is coupled to -the one-shot circuit 134 and is adapted to be triggered when ~7~i7;~
circuit 134 resets. The ou-tput of the one-shot circuit 142 provides an ou-tput pulse which is qpplied directly to counter 140 and through buffer 141 to counter 138 to advance -the count each time a byte of data is entered into the respective memory. This process is repeated until all the desired data bytes are en-tered into the appropriate addresses.
~llhen the contents of the respective memory is desired to be outputted i.e. translated to its respective output data bus, a cycle out switch 144t included in each memory controller, is actuated on demand either manually or by remote control and operates to trigger a third one-shot circuit 146 which generates a pulse to reset the address counter 138 to a zero count and triggers on a latch 148 which in turn enables the converter's gated input as well as gate circuit 150 coupled to a local source of clock signals 152. The output of gate 150 provides a clock signal for the parallel--to-serial con-verters. Pulses gated from the local clock source 152 and also divided by a ~ N counter 155 and are fed to a one-shot circuit 154 which is adapted to strobe load the respective parallel-to-serial conver-ters 62, 92 and 122, respectively. The N count is equal to the number of data lines being inputted from serial-to-parallel converters 86 and 116 to their respective memories 26 and 36. Each time the one-shot circuit 154 restores it triggers one-shot circuit 156 which produces a trigger pulse which is coupled -to -the address counter 138 through the buffer amplifier 158, thereby causing the address counter 138 to advance the memory to the next address position. On the next clock pulse outputted from the clock 152 the readout process is repeated. This action continues until the count in the address counter 138 matches -the previously stored coun-t in the memory counter 140. A
comparator circuit 160, coupled to both counters 138 and 140, moni-tors the counters looking for a match, meaning ~7~72 that on readout the a~dr~?ss counter 138 has cycled the rnemory to the same number of coun~ts read into the ~emory counter 140 during the read-in phase. When bo-th counts are equal, the comparator circuit 160 triggers another one-sho-t circuit 1~2 which produces a trigger signal to trigger off the latch 148, which acts to disable the gate 150, thereby interrupting the output o~ clock pulses from the clock 152 to the one-shot circuit 154. This causes the readout cycle to stop, meaning that the read-ou-t process of the da-ta from the respective rnemory has been completed.
Thus what has been shown and described is a means for relaying electrical signals such as digital data first over an RF communications link, and then over an optical communications link, so that data can be conveyed from a local source of diverse signals to a remo-te data terminal having a memory which upon demand can thereafter output the data to one or more selec-ted dlverse types of utilization devices.
Having thus shown and desc:ribed what is at present considered -to be the preferred embodiment of the subjec-t invention, modifications and al-terations thereto will readily occur to -those skilled in -the ar-t. It is not desired, therefore, -that the invention be limited to the specific arrangements shown and described, but it is intended to cover all such modifications and alterations which fall within the true spirit and scope o~ the inven-tion as defined by the appended claims.
Claims (36)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A communications system for electrical signals, comprising in combination:
a plurality of input signal sources generating respective electrical communications signals;
first memory means coupled to at least one of said plurality of input signal sources and including con-trol means for controlling the inputting and storing of said electrical communications signals in said first memory means and, upon command, thereafter outputting said electri-cal communications signals therefrom;
first energy type transmitter means coupled to said first memory means and being responsive to the elec-trical communications signals outputted from said first memory means to generate a modulated carrier signal includ-ing said electrical communications signals and coupling said carrier signal to a first energy type communications link;
first energy type receiver means coupled to said first energy type communications link;
second memory means coupled to said first energy type receiver means and including control means for con-trolling the inputting and storing of said electrical communications signals in said second memory means and, upon another command, thereafter outputting the stored electri-cal communications signals from said second memory means;
second energy type transmitter means coupled to said second memory means and being responsive to said elec-trical signals outputted from said second memory means to generate a modulated carrier signal including said elec-trical communications signals and coupling said carrier signal to a second energy type communications link;
second energy type receiver means coupled to said second energy type communications link and being respon-sive to said last recited carrier signal to demodulate the carrier signal to reproduce said electrical communications signals;
third memory means coupled to said second energy type receiver means and including control means for controlling the inputting and storing of said communica-tions signals into said third memory means and upon yet another command thereafter outputting the data from said third memory means; and at least one utilization device coupled to said third memory means and being responsive to the elec-trical communications signals outputted therefrom to perform a desired task depending upon the nature of said electrical communications signals fed thereto.
a plurality of input signal sources generating respective electrical communications signals;
first memory means coupled to at least one of said plurality of input signal sources and including con-trol means for controlling the inputting and storing of said electrical communications signals in said first memory means and, upon command, thereafter outputting said electri-cal communications signals therefrom;
first energy type transmitter means coupled to said first memory means and being responsive to the elec-trical communications signals outputted from said first memory means to generate a modulated carrier signal includ-ing said electrical communications signals and coupling said carrier signal to a first energy type communications link;
first energy type receiver means coupled to said first energy type communications link;
second memory means coupled to said first energy type receiver means and including control means for con-trolling the inputting and storing of said electrical communications signals in said second memory means and, upon another command, thereafter outputting the stored electri-cal communications signals from said second memory means;
second energy type transmitter means coupled to said second memory means and being responsive to said elec-trical signals outputted from said second memory means to generate a modulated carrier signal including said elec-trical communications signals and coupling said carrier signal to a second energy type communications link;
second energy type receiver means coupled to said second energy type communications link and being respon-sive to said last recited carrier signal to demodulate the carrier signal to reproduce said electrical communications signals;
third memory means coupled to said second energy type receiver means and including control means for controlling the inputting and storing of said communica-tions signals into said third memory means and upon yet another command thereafter outputting the data from said third memory means; and at least one utilization device coupled to said third memory means and being responsive to the elec-trical communications signals outputted therefrom to perform a desired task depending upon the nature of said electrical communications signals fed thereto.
2. A communications system for electrical signals, comprising in combination:
a plurality of input signal sources generating respective electrical communications signals;
first memory means coupled to at least one of said plurality of input signal sources and including control means for controlling the inputting and storing of said electrical communications signals in said first memory means and upon command thereafter outputting said electrical communications signals therefrom;
RF transmitter means coupled to said first memory means and being responsive to the electrical communications signals outputted from said first memory means to generate a modulated signal including said elec-trical communications signals and coupling said carrier signal to an RF communications link;
RF receiver means coupled to the RF communica-tions link and being responsive to said carrier signal to demodulate the carrier signal to reproduce said elec-trical communications signals;
second memory means coupled to said RF receiver means and including control means for controlling the inputting and storing of said electrical communications signals in said second memory means and upon another command, thereafter outputting the stored electrical communications signals from said second memory means;
optical transmitter means coupled to said second memory means and being responsive to said electri-cal signals outputted from said second memory means to generate a modulated optical carrier signal including said electrical communications signals and coupling said carrier signal to an optical communications link;
optical receiver means coupled to the optical communications link and being responsive to said optical carrier signal to demodulate the carrier signal to reproduce said electrical communications signals;
third memory means coupled to said optical receiver means and including control means for controlling the inputting and storing of said communications signals into said third memory means and upon yet another command thereafter outputting the data from said third memory means; and at least one utilization device coupled to said third memory means and being responsive to the electri-cal communications signals outputted therefrom to perform a desired task depending upon the nature of said electrical communications signals fed thereto.
a plurality of input signal sources generating respective electrical communications signals;
first memory means coupled to at least one of said plurality of input signal sources and including control means for controlling the inputting and storing of said electrical communications signals in said first memory means and upon command thereafter outputting said electrical communications signals therefrom;
RF transmitter means coupled to said first memory means and being responsive to the electrical communications signals outputted from said first memory means to generate a modulated signal including said elec-trical communications signals and coupling said carrier signal to an RF communications link;
RF receiver means coupled to the RF communica-tions link and being responsive to said carrier signal to demodulate the carrier signal to reproduce said elec-trical communications signals;
second memory means coupled to said RF receiver means and including control means for controlling the inputting and storing of said electrical communications signals in said second memory means and upon another command, thereafter outputting the stored electrical communications signals from said second memory means;
optical transmitter means coupled to said second memory means and being responsive to said electri-cal signals outputted from said second memory means to generate a modulated optical carrier signal including said electrical communications signals and coupling said carrier signal to an optical communications link;
optical receiver means coupled to the optical communications link and being responsive to said optical carrier signal to demodulate the carrier signal to reproduce said electrical communications signals;
third memory means coupled to said optical receiver means and including control means for controlling the inputting and storing of said communications signals into said third memory means and upon yet another command thereafter outputting the data from said third memory means; and at least one utilization device coupled to said third memory means and being responsive to the electri-cal communications signals outputted therefrom to perform a desired task depending upon the nature of said electrical communications signals fed thereto.
3. The communications system as defined by claim 2 wherein said plurality of input signal sources comprises digital data signal sources generating respec-tive digital data signals and wherein said first, second and third memory means comprises digital memories.
4. The communications system as defined by claim 3 wherein said digital memories are comprised of random access memories.
5. The communications system as defined by claim 4 wherein said plurality of digital data sources are comprised of diverse types of digital data sources.
6. The communications system as defined by claim 2 wherein at least one utilization device comprises a plurality of diverse types of digital data utilization devices.
7. The communications system as defined by claim 3 wherein at least one of said control means of said first, second and third memory means includes selec-tively actuable cycle out switch means to cause the respective memory means to output the data stored therein.
8. The communications system as defined by claim 7 wherein at least one cycle out switch means com-prises a manually actuable switch.
9. The communications system as defined by claim 7 wherein said at least one cycle out switch means is included in the memory control means of said third memory means.
10. The communications system as defined by claim 7 wherein said at least one cycle out switch means is included in said control means of said second memory means.
11. The communications system as defined by claim 7 wherein said at least one cycle out switch means is included in said control means of said first memory means.
12. The communications system as defined by claim 3 and additionally including an analog signal source, generating an analog input signal, coupled to said RF transmitter means, said RF transmitter means also being responsive to said analog input signal to generate a modulated RF carrier signal also including said analog input signal;
said RF receiver means being responsive to said carrier signal including said analog input signal to demodulate the carrier signal to reproduce said analog input signal; and analog signal transducer means coupled to said RF receiver means and being responsive to said analog signal to reproduce said analog signal.
said RF receiver means being responsive to said carrier signal including said analog input signal to demodulate the carrier signal to reproduce said analog input signal; and analog signal transducer means coupled to said RF receiver means and being responsive to said analog signal to reproduce said analog signal.
13. The communications system as defined by claim 12 and additionally including signal conversion means coupled between said first memory means and said RF transmitter means, and wherein said RF transmitter means includes means for modulating said carrier signal with both said data signals and said analog signal.
14. The communications system as defined by claim 3 wherein said first, second and third digital memories comprises memories having plural parallel input and output data lines and additionally including an input parallel line data bus coupled to the input lines and an output parallel line data bus coupled to the output lines.
15. The communications system as defined by claim 14 and additionally including a parallel-to-serial digital data converter coupled to the output of said first memory via said output data bus for providing a serial data stream of digital data, and wherein the input data bus of said first memory is coupled to said at least one of said plurality of digital data sources.
16. The communications system as defined by claim 15 and additionally including signal converter means coupled to said parallel-to-serial digital data converter for providing a signal conversion of said serial data stream, and wherein said RF transmitter means includes modulation means for modulating said carrier signal with said converted signals.
17. The communications system as defined by claim 16 wherein said RF receiver means additionally includes demodulator means to demodulate the carrier signal to reproduce said converted signals;
signal reconversion means coupled to said con-verted signals to again provide said serial data stream;
a serial-to-parallel converter coupled to said reconversion means and being adapted to produce a parallel digital data stream of said digital data signals which in turn are coupled to said second memory via its respec-tive input data bus; and a parallel-to-serial signal converter coupled to said second memory via its respective output data bus to provide a serial digital data stream of said digital data signals to said optical transmitter means.
signal reconversion means coupled to said con-verted signals to again provide said serial data stream;
a serial-to-parallel converter coupled to said reconversion means and being adapted to produce a parallel digital data stream of said digital data signals which in turn are coupled to said second memory via its respec-tive input data bus; and a parallel-to-serial signal converter coupled to said second memory via its respective output data bus to provide a serial digital data stream of said digital data signals to said optical transmitter means.
18. The communications system as defined by claim 17 wherein said optical transmitter means includes a light emitting source.
19. The communications system as defined by claim 18 wherein said light emitting source comprises a light emitting semiconductor device.
20. The communications system as defined by claim 18 wherein said light emitting source comprises a light emitting diode.
21. The communications system as defined by claim 17 and additionally including means for providing a selective data transfer path to said second memory.
22. The communications system as defined by claim 21 wherein said last recited means comprises a filter circuit.
23. The communications system as defined by claim 21 wherein said last recited means comprises a filter circuit coupled between said demodulator means and said reconverter means.
24. The communications system as defined by claim 17 and additionally includes a serial-to-parallel signal converter coupled between said optical receiver means and the input data bus of said third memory for applying said digital data as a parallel data stream to said third memory; and a parallel-to-serial converter coupled to the output data bus of said third memory for providing a serial data stream of said digital data for coupling to said at least one utilization device.
25. The communications system as defined by claim 24 wherein said first, second and third memories are random access memories.
26. The communications system as defined by claim 24 wherein said optical receiver means includes a photo pick device.
27. The communications system as defined by claim 26 wherein said photo pickup device comprises a photosensitive semiconductor device.
28. The communications system as defined by claim 27 wherein said semiconductor device comprises a photodiode.
29. The communications system as defined by claim 3 wherein said optical communications link includes a gaseous transmission medium.
30. The communications system as defined by claim 3 wherein said optical communications link includes a vacuum or space transmission medium.
31. The communications system as defined by claim 2 wherein said optical communications link includes at least one optical fiber linking said optical trans-mitter means to said optical receiver means.
32. The communications system as defined by claim 1 wherein at least one of said input signal sources comprises a portable device.
33. The communications system as defined by claim 32 and additionally including optical coupling means coupling said at least one portable device to said first memory means.
34. The communications system as defined by claim 1 wherein said third memory means comprises a portable device.
35. The communications system as defined by claim 1 wherein said second energy type communications link includes inductive coupling means coupling said second energy type transmitter means to said energy type receiver means.
36. The system as defined in claim 17 wherein said serial-to-parallel-to-converter embodies an address-able gate to control data flow to said second memory.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/088,332 US4259746A (en) | 1979-10-26 | 1979-10-26 | Electrical communications system |
| US06/088,332 | 1979-10-26 |
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| Publication Number | Publication Date |
|---|---|
| CA1147072A true CA1147072A (en) | 1983-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000363041A Expired CA1147072A (en) | 1979-10-26 | 1980-10-23 | Electrical communications system |
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| US (1) | US4259746A (en) |
| JP (1) | JPS5683153A (en) |
| CA (1) | CA1147072A (en) |
| GB (1) | GB2062420B (en) |
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| US3480733A (en) * | 1964-08-04 | 1969-11-25 | Nippon Electric Co | Frequency allocation system for common amplification of multifrequency carriers |
| US3838412A (en) * | 1965-04-19 | 1974-09-24 | Gen Electric | Optical link for illuminated traveling message display sign system |
| US3462554A (en) * | 1966-01-14 | 1969-08-19 | Motorola Inc | Transmission system utilizing independent diversity reception on plural sideband components |
| US3699525A (en) * | 1970-11-27 | 1972-10-17 | Honeywell Inf Systems | Use of control words to change configuration and operating mode of a data communication system |
| US3885217A (en) * | 1973-07-11 | 1975-05-20 | Computer Specifics Corp | Data transmission system |
| FR2246211A5 (en) * | 1973-09-28 | 1975-04-25 | Ibm France | |
| US4054794A (en) * | 1975-03-12 | 1977-10-18 | Varo, Inc. | Optical communications link |
| US4001692A (en) * | 1975-07-07 | 1977-01-04 | Barry Research Corporation | Time diversity data transmission apparatus |
| US4061577A (en) * | 1976-08-18 | 1977-12-06 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Fiber optic multiplex optical transmission system |
| US4092599A (en) * | 1976-11-26 | 1978-05-30 | Werner Yee | Annunciator communication system |
| US4196450A (en) * | 1977-01-18 | 1980-04-01 | Datacopy Corporation | Selective copying apparatus |
| US4120003A (en) * | 1977-01-21 | 1978-10-10 | Idr, Inc. | Multiple channel CATV system utilizing row grabber interface as CATV input |
| US4201907A (en) * | 1977-08-29 | 1980-05-06 | International Totalizing Systems, Inc. | Totalizer system |
| US4160903A (en) * | 1977-10-07 | 1979-07-10 | The United States Of America As Represented By The Secretary Of The Navy | Electro-optical radio system |
-
1979
- 1979-10-26 US US06/088,332 patent/US4259746A/en not_active Expired - Lifetime
-
1980
- 1980-10-09 GB GB8032535A patent/GB2062420B/en not_active Expired
- 1980-10-23 CA CA000363041A patent/CA1147072A/en not_active Expired
- 1980-10-25 JP JP14889880A patent/JPS5683153A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5683153A (en) | 1981-07-07 |
| GB2062420B (en) | 1984-05-10 |
| GB2062420A (en) | 1981-05-20 |
| US4259746A (en) | 1981-03-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |