CA1158782A

CA1158782A - Programmable cell for use in programmable electronic arrays

Info

Publication number: CA1158782A
Application number: CA000366711A
Authority: CA
Inventors: Scott H. Holmberg; Richard A. Flasck
Original assignee: Energy Conversion Devices Inc
Current assignee: Energy Conversion Devices Inc
Priority date: 1979-12-13
Filing date: 1980-12-12
Publication date: 1983-12-13
Also published as: GB2065972A; DE3046721A1; AU526351B2; IL61678A0; DE3046721C2; FR2472246A1; US4599705A; IE802614L; MX148783A; IT1194002B; SE451514B; GB2065972B; BE886629A; IT8026644A0; NL8006769A; FR2472246B1; IL61678A; SE8008737L; AU6531480A; IE50698B1

Abstract

ABSTRACT
A programmable cell for use in programmable electronic arrays such as PROM devices, logic ar-rays, gate arrays and die interconnect arrays. The cells have a highly non-conductive state settable and substantially non-resettable into a highly conductive state. The cells have a resistance of 10,000 ohms or more in the non-conductive state which are settable into the conductive state by a threshold voltage of 20 volts or less, a current of 25 milliamps or less, for 1000 microseconds or less. The cells in the conductive state have a resistance of 500 ohms or less. The cells have a maximum permittable processing temperature of 200°
centigrade or more and a storage temperature of 175° centigrade or more. The cells can be formed from chalcogenide elements, such as germanium tel-lurium and selenium or combination thereof. The cells also can be formed from tetrahedral elements, such as silicon, germanium and carbon or combina-tions thereof.
Each cell in an array is a thin film deposited cell and includes an isolating device which can be a bipolar or MOS device or can be a thin film diode or transistor. The associated addressing circuitry also can be conventional bipolar or MOS devices or thin film deposited devices. The cells have a cell area of less than one square mil to provide a high cell packing density.

Description

Case 556.1 The present invention is related to a program-mable cell for use in programmable electronic ar-rays such as PROM devices, logic arrays, gate ar-rays and die interconnect arrays. In particular each cell has a memory region made of a phase change material which is settable and substantially non-resettable in a highly conductive state from a highly non-conductive state. This invention is related to the storing of information with phase change switch devices first invented by Stanford R.
Ovshinsky, as for example, disclosed in U.S. Patent No. 3,271,591.
Heretofore various memory systems have been proposed which are divided into several types. One type is the serial type where the information in the memory system is obtained serially and where the read time for reading a particular bit of in-formation in the memory is dependent upon where it is located in the memory. This results in long read times for obtaining the information from mem-ory. Such types of memory systems include memory devices including a magnetic tape or a magnetic disc including the so-called floppy disc and mag-netic "bubble memory" devices.

-Another type of memory system is the random access memory system (RAM) where the read time for each bit is substantially the same as for any other bit.
~hile the storage information in "bubble" type memory devices potentially reduces the size and cost of memory systems and provides high informa-tion packing densities, i.e., small center-to-center distance between adjacent memory regions ~Jhere the bits of information are stored, such "bubble" s~stems are limite~ to serial reading of information and do not provide for fast read, ran-dom access to the stored information.
Also, heretofore, short term data storage has been provided by R~ memory devices including tran~
sistors or capacitors at the cross over points ~f X
and Y axis conductors. Such a memory device can be set in one of two operational states. These memory devices provide a fairly high packing density, i.e~, a small center-to-center distance between memory locations. A major disadvantage is that such devices are volatile since they must be con-tinually supplied with a volta~e if they are to 71~Z

retain their stored data. Such short term data storage devices are often referred to as volatile fast read and write memory systems.
A fast read memory system is the read only memories (ROM) which use transistors and rectifiers formed in semiconductor substrates with permanently open contact points or permanently closed contact poin~s Eor storage o~ bits of information. Such a ROM system is programmed during the manufacture thereof and has a short read time and a relatively high packing density as well as being non-volatile.
However, the obvious disadvantage of such a ROM
system is that the data stored cannot be altered.
Accordingly, ROM devices are made-to-order for applications involving storing of the basic oper-ating program of a data processor or other non-altered information.
Another memory system used is a programmable read only memory (PROM) system which can be pro-grammed once by the user and remains in that state.Once it is programmed a PROM system will operate identically to a ROM system of the same config-uration.

The most commonly used PROM system incor-porates fuse links positioned at each cross over point of an X-Y matrix of conductors. The storage of information (loqic one or logic zero) is ob-tained by blowing the use links in a given pre-determined pattern. Such fuse links extend lat-erally on a substrate instead of vertically between cross over conductors and, as a result, such fuse links necessarily require a large area. The area of a typical memory cell or region utilizing a fuse link is about 1 to 1.6 mil2.
The current needed to blow the fuse link for programming is quite high because of the necessity of completely blowing out the fuse link and because of the inherently high conductivity of the material of the fuse link. Typical currents are 50 milli-amps and the power required is approximately 250 to 400 milliwatts. Also, the fuse link which is a narrow portion of a conductor deposited on a sub-strate, must have a precise dimension to ensure thecomplete and programmable blow out thereof. In this respect, photolithography and etching tech-niques required to fabricate such a fuse link re-quire that such a fuse link be made with very crit-ical tolerances.

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Another major problem with fuse link type PROM
devices is that the small gap in the blown fuse can become closed with accumulation of conductive ma-terial remaining adjacent to the gap by difusion or otherwise.
The fuse link technology also has been util-ized in field programmable logic arrays, gate ar-rays and die interconnect arrays. These arrays are utilized to provide options for the integrated v~>/v~e circuit user between the standard high ~e~hnmmi, low cost logic arrays and the very expensive hand-crafted custom designed integrated circuits. These arrays allow a user to program the low cost array for the users specific application at a substan-lS tially reduce cost from the cost of a custom ap-plication circuit.
Heretofore it has also been proposed to pro-vide an EEPROM (electrically erasible programmable read only memory) device, a vertically disposed memory region or cell in a memory circuit which is vertically coupled at and between an upper Y axis conductor and a lower X axis conductor in a memory matrix. Such an EEPROM system provides a rela-tively high packing density.

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EEPROM devices are known which include a ma-trix of X and Y axis conductors where a memory circuit, including a memory region and an isolating device is located at each cross over point and S extends generally perpendicularly to the cross over conductors thereby to provide a relatively high packing density.
The memory region utilized in such EEPROM
devices have typically been formed of a tellurium-based chalcogenide material and more specificallyan amorphous material such as amorphous germanium and tellurium. Other materials which have rather highly reversible memory regions include a GeaTeb wherein a is between 5 and 70 atomic percent and b is between 30 and 95 atomic percent. Some of these materials also include other elements in various percentages from 0 to 40 in atomic percent such as antimony, bismuth, arsenic, sulfur and/or selenium.
Amorphous materials of the type described above have good reversibility and have sufficient thermal stability such that they will not deteri-orate under the usual temperature conditions in which they are utilized. The crystalline s~ate is reset into its amorphous state by a high resetting current.

A preferred EEPROM material has (a) good re-versibility of up to or greater than 106 cycles, (b) a maximum processing temperature of about 200C, (c) a maximum storage temperature of about S 100C, (d) a threshold voltage of 8 volts, (e) a SET resistance of 300 ohms and (f) an OFF resis-tance (at 175C) of at least approximately 104 ohms.
Heretofore it has also been known to provide isolating devices which are coupled in series with a memory region or cell between the cross over conductors, such isolating devices typically having been formed by diffusing various dopant materials into a single crystal silicon substrate to form a rectifier, transistor, or MOS device, e.g., a field effect transistor. Such a diffusion process re-c~; ~f6~ S ~ 0~1 sults in lateral ~e~ n of the doped materialinto the substrate material and as a result the cell packing densities of such prior memory systems have been limited by the degree of lateral diffu-sion of the dopant materials and by the margin of error required for mask alignment.
The devices herein utilize for each isolating device a unidirectional isolating device like a Z

rectifier or transistor which provides isolation by a high impedance P-N junction in one direction of current flow thereby to provide very high OFF re-sistance.
It has been proposed to form a P N junction by vacuum depositing, either an N or P type amorphous semiconductor film on an oppositely doped silicon chip substrate. In this respect, reference is made to U.S. Patent No. 4r062,034 which discloses such a thin film transistor having a P-N junction. It has not been proposed to use such a thin film deposited amorphous semiconductor film for forming an iso-lating device in a memory circuit which also in-cludes a memory region in a programmable array.
Also, it has not been previously proposed to utilize an amorphous allOy which includes silicon and fluorine ~nd which may also contain hydrogen to provide a thin film rectifier or transistor in the memory circuits of a programmable array. It has heretofore been proposed to utilize silicon and fluorine materials in a solar cell which is essen-tially a photosensitive rectifier. In this re-spect, reference is made to U.S. Patent No. ~,217,374 Stanford R. Ovshinsky and Masatsugu Izu entitled:

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AMORPHOUS SEMICONDUCTORS EQUIVALENT TO CRYSTALLINE
SEMICONDUCTQRS and U.S. Patent No. 4~226,898 Stanford . Ovahinsky and Arun Madan, of the same title.
We have found that these disadvantages may be overcome by providing a programmable cell having an amorphous cell body including at least a portion having a non-volatile highly non-conductive state settable and substantially non-resettable into a non-volatile highly conductive state. We also provide a programmble electronic array of these cells. The cells can be utilized to replace the fuse links in programmable arrays such as PROM
devices, logic arrays, gate arrays and die inter-connect arrays to increase the programming relia-bility and packing density while substantiallyreducing the overall cost of the arrays.
The cells have a non~conductive state or OFF
resistance of 10,000 to 1,000,000 ohms or more.
The cells are settable into the conductive state by a threshold voltage of 10 to 20 volts or less, a programming current of 5 to 25 milliamps or less and a programming time of 10 to 1000 microseconds or less. The cells have a maximum permittable processing temperature tolerance of 200 to 500 centigrade or more.
_g _ The cells are designed for the particular characteristics desired such as high processing temperature or high OFF reslstance and low SET
resistance. The increase in some of the desirable characteristics over the EEPROM type chalcogenide materials are obtained by substantially eliminating reversibility in the cells. In contrast to the reversibility of 106 cycles in the EEPR~M devices, the cells have a reversibility of 10 to 100 cycles or less.
The cells can be formed from chalcogenide elements, such as germanium~ tellurium and selenium or combinations thereof. The cells also can be formed from tetrahedral elements, such as silicon, germanium and carbon or combinations thereof and can include other elements such as oxygen, hydrogen or fluorine. The cells can be deposited by sput-tering, chemical vapor deposition (CVD), evapo-ration (such as electron beam epitaxy) or by plasma deposition techniques. Reference can be made to the aforementioned U.S. Patents 4,217,374 and 4,~26,898 for such deposition techniques.
Each cell is deposited in an array with an isolating device and associated addressing cir-~s~

cuitry. The isolating devices and addressing cir-cuitry can be bipolar or MOS devices or thin film diodes or transistors in MOS or V-MOS configu~
rations or combinations thereof. The cells have a cell area of less than 1 syuare mil which provides a high cell packing density in the arrays.
The preferred embodiments of this invention will now be described by way of example~ with ref-erence to the drawings accompanying this speci-fication in which:

'7~3;2 Fig. 1 is a fragmentary plan view of the de-posited film side of a silicon chip substrate of a programmable array such as a memory matrix of a prior art type PROM device.
Fig. 2 is a sectional view through one memory circuit of the PROM device shown in Fig. 1 and is taken along line 2-2 of Fig. 1.
Fig. 3 is a schematic circuit diagram of a portion of the PROM device shown in Fig. 1.
Fig. 4 is a fragmentary plan view of the de-posited film side of a programmable array such as a PROM device which is made in accordance with the teachings of the present invention, which is de-posited on a silicon chip substrate and which in cludes a plurality of memory circuits, each includ-ing a cell or memory region in series with an iso-lating Schottky barrier diode formed in the sub-strate.
Fig. 5 is a sectional view through one cell or memory region and isolating device of a memory circuit shown in Fig. 4 and is taken along line 5-5 of Fig. 4.
Fig. 6 is a schematic circuit diagram of a portion of the PROM device shown in Fig. 4.

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FigO 7 is a fragmentary plan view of the de-posited film side of a silicon chip substrate form-ing one cell of a programmable array constructed in accordance with the teachings of the present in-vention, the array including a plurallty ofmemory circuits each having a cell or memory region in series with a fiel~ effect transistor type iso-lating device formed in the substrate.
Fig. 8 is a sectional view of one memory cir-cuit of the array shown in Fig. 7 and is takenalong line 8-8 of Fig. 7.
Fig. 9 is a schematic circuit diagram of a portion of the array shown in Fig. 7 and shows a memory circuit of the PROM device.
Fig. 10 is a fragmentary plan view of the deposited film side of a substrate of an array including a plurality of array circuits each having a cell or memory region and an isolating device that are ormed with thin film depositing tech-niques in accordance with the teachings of the present invention.
Fig. 11 is a sectional view through the array shown in Fig. 10 and is taken along line 11-11 of Fig. 10.

-Fig. 12 is a schematic circuit diagram of the array circuits shown in Figs. 10 and 11.
Fig. 13 is a sectional view through an all thin film deposited array cell including a circuit having a cell and a thin film, field effect tran-sistor isolating device constructed in accordance with the teachings of the present invention.
Fig~ 14 is a schematic circuit diagram of a plurality of circuits shown in Fig. 13.
Fig. 15 is a plan view of a substrate or a portion thereof upon one side of which are de-posited array circuits, such as memory circuits which are all thin film deposited, memory regions and isolating devices, together with addressing circuitry which is formed by thin film deposition techniques.
Fig. 16 is a plan view of a silicon chip or portion thereof wherein the array circuits are all or ~artially thin film deposited memory regions and isolating devices together with addressing cir-cuitry formed on the chip by doped and diffused regions within the silicon chip substrate.
Referring now to the drawings in greater de-tail there is illustrated in Figs. 1 and 2 a por-~ ~8`7~

tion of a prior art pro~rammable array such as a PROM device 10 including an X-Y memory matrix in-cluding X axis aluminum conductors 12 and Y axis N~
doped silicon conductors 14. As shown, the N+
doped silicon Y axis conductor 14 is separated from adjacent Y axis conductors 14 by isolation channels 16. The aluminum X axis conductor 12 has short legs 18 which extend in the Y direction to make contact with one side of a metallic fuse link 20.
As shown in Fig. 2, the fuse link 20 is de-posited on a layer 22 of silicon oxide which in turn is deposited or grown on a layer 23 of N epi-taxial material in which the isolation channel 16 is formed. The layer 23 is formed on a P type silicon substrate 24 and N doped Y axis conductor 14 is formed therebetween.
As best shown in Fig. 1, each fuse link 20 extends laterally and has a reduced width portion 26 which must have critical dimensions (thickness and width) in order to provide a fuse link which car. be blown with a predetermined amount of cur-rent. The other side of the fuse link 20 on the layer 22 of SiO2 has an aluminum conductor 28 de-posited thereon. The SiO2 layer first had been cut away so that an aluminum silicon Schottky barrier diode 30 can be formed at an exposed surface of the silicon substrate layer 24. Then the aluminum conductor 2~ is deposited over the silicon oxide layer 22 and over the aluminum/silicon Schottky barrier diode 30 to form a conductive path from one side of the fuse link 20 to the barrier diode 30 which is electrically coupled to the N~ Y
axis conductor 14. The fuse link 20 and the diode 30 form an array circuit 32 here a memory circuit.
Each of the crystal silicon substrates and devices formed thereon utilize conventional litho-graphy processing steps except where specified otherwise. For example, in Fig. 2, the P-type substrate 24 has the X conductor or buried layer 14 deposited thereon utili~ing photolithography to expose the desired areas. The layer 14 typically arsenic or phosphorus can be diffused by heat dur-ing processing or can be formed by ion implanta-tion. The epitaxial N-layer 23 is then grown on the substrate ~4 over the conductors 14. The iso-lation channels 16 can be junction or oxide chan-nels. For a junction channel the layer 23 is mask-ed and P-type material is deposited and diffused ~5~t~2 into the layer 23 down to the substrate 24. For an oxide channel the channels are masked and then partially etched into the layer 23 and then ther-mally oxidized to grow the channels down to the substrate 24.
For other devices in the array, a base typi-cally P-type layer is then diffused into the layer 23 between the channels 16 for a diode or tran sistor, such as for the addressing circuitry or other programmable elements. Then a resistor dif-fusion step is performed. To form transistor then an emitter step is performed by masking off a por-tion of the base diffusion areas and diffusiny typically N-type material into it. The oxide layer 22 then is deposited over the entire layer 23 in-cluding the diffusion areas. Then with photo-lithography an oxide cut such as for the diode 30 is made through each portion of the oxide 23 where contact with the diodes, transistorsl etc. is de-'' 3a //~
sired. Platinum,-palli~#~ or aluminum is then sputtered or evaporated onto the oxide and exposed silicon areas which is then heat treated, such as at 450 centigrade for thirty minutes. This forms a metal silicide diode with the silicon but does z not change the metal on the oxide layer 23. An etchant such as Aqua Regia is utilized to etch away the platinum from the oxide layer, but the metal silicides are not affected.
S The fuse links 20 are then patterned and form-ed on the oxide ~. The fuse links of about 200 Angstroms are vertically and critically dimen-sioned. The conductors 12 and 28 are then pat-terned and laid down upon the oxide 22, fuse links 20 and diodes 30. An oxide layer (not shown) is then deposited over the whole array, which is then etched to make contact with the conductors ~first metal) where desired. Then a second metal ~not shown) is patterned onto the oxide and openings.
Another oxide layer is then formed over the second metal, which oxide is etched to the second metal to form the array bonding pads in a conventional man-ner.
The schematic circuit diagram of the prior art array device 10 is shown in Fig. 3.
From the foregoing description of the prior art array or PROM device 10 illustrated in Figs. 1,

2 and 3, and from an inspection of Figs. 1 and 2 it is readily apparent that the lateral disposition of the fuse link 20, the need for isolation channels 16 and the lateral arrangement of the 5chottky barrier diode 30 create limitations on the packing density of the memory circuits 32 (memory cells) formed by each fuse link 20 and diode 30 located at and extending between the X and Y axis cross over conductors 12 and 14 at each cross over. As shown, the center-to-center distance between adjacent memory circuits 32 (cells) is typically 40 microns utilizing five micron lithography. The packing density and hence overall cell size is extremely important because the cost of the cell portion of the arrays is exponentially related to cell area.
A reduction in size of a factor of two is an effec-tive cost reduction of a factor of five or six.
Referring now to Figs. 4 and 5 there is illus-trated therein a portion of a programmable array 50 which can also be a PROM device, including a plu-rality of connection or memory ctrcuits 52 con-structed in accordance with the teachings of the present invention on a P type silicon substrate 54.
As shown in Fig. 5, each circuit 52 extends between an N~ Y axis conductor 56 in the substrate 54 and --lg--37~

an X axis metallic conductor 58 which can be made of suitable metal, such as aluminum.
Briefly, the circuit 52 includes a diode such as a platinum silicide Schottky diode 60 between isolation channels 62 in an N epitaxial layer 64 formed on the upper surace of the P type silicon substrate 54. Above the epitaxial layer 64 is a layer of insulating materi.al 66 which can be sil-icon dioxide and which may be formed by chemical vapor, vacuum deposition, or thermal oxidation techniques. A portion of the layer of insulating material 66 is cut away above the platinum silicide Schottky diode 60 and a layer of phase change amor-phous material 68 is deposited in the open space to form a cell or memory region 68 of the circuit 52.
Above the cell 68 is a thin conductive barrier layer 70, preferably made of a refractory metal or metal alloy like Ti-W. Above this thin conductive barrier layer is the layer of highly conductive metal such as aluminum forming the X axis conductor 58.
The portion of the array 50 shown in Figs. 4 and 5 is formed as described above on a selectively doped crystal semiconductor substrate 54 which can -2~-~5b~'7t~

be a silicon chip. As stated above, the substrate 54 is shown as a P-type silicon substrate having the epitaxial layer 64 of N-type silicon formed on the top of the substrate 54. Also as shown, ex-tending through the epitaxial layer 64 is a pair ofisolation channels 62, one pair for each row of circuits 52 which serve to divide the epitaxial layer 64 into electronically isolated regions be-tween which the epitaxial layer 64 forms part of the Y axis conductors 56 of the array.
Low resistance connections are made to the ends of the N+ Y axis conductors 56 in a conven-tional well-known manner by diffusing N+ regions into the epitaxial layer directly above the lower N+ regions. Conductors (not shown) may be added over insulating layers deposited over the sections shown in Figs. 4 and 5 with conductive fingers making connection to spaced N+ diffused regions (not shown) between the various cells in each ver-tical row of cells shown in Fig. 4. This addi-tional technique for lowering the resistance of the connections to the N+ Y axis conductors 56 are not shown to avoid unduly complicating the drawings.

The lateral extent of each memory circuit which reduces the packing density is one reason why an all deposited film memory makrix of memory cir-cuits to be described in connection with the de-scription of Fig. 11 and utilizing a thin filmrectifying device or a transistor isolating device as illustrated in Figs. 13 and 14 has a much great-er packing density than that readily achievable with the array shown in Figs. 4 and 5. In this respect, the center-to-center distance between ad~acent circuits or cells 52 is 30 microns which is, however, less than the 40 microns in distance for the cells in the prior art device 10 shown in Figs. 1-3, utilizing the same lithography tech-niques for each device.
Further with respect to the formation of thememory circuit 52 shown in Fig. 5I the layer of insulating material 66 is formed by chemical vapor deposition, sputtering, plasma deposition or ther-mal oxidation techniques, in an opening72 therein, under the memory region 68 which is formed using conventional photo-resist masking and etching techniques.
The barrier layer 70 serves to limit ionic migration from the aluminum layer forming the X

axis conductor 58 which would tend to degrade the non-resettable amorphous material forming the cell 68 as well as exposed diodes 60 elsewhere in the array. In this way bands of aluminum forming the X
axis conductors 58 make electrical connection through the underlying bands of barrier layer 70 to esta-blish electrical contact with the cells 68 of the various circuits 52. The layer 70 also allows a higher processing temperature for the cells 6~.
Setting or read current pulses are fed through selected circuits 52 by applying suitable threshold voltages of positive polarity across the X and Y
axis conductors 58 and 56 so that current passes in a low resistance direction through the Schottky barrier diode 60 formed at the interface between the associated platinum silicide region and the epitaxial layer 64 below.
With the construction just described o~ a circuit 52, the packing density o~ the circuit 52 is ~imited by the spacing of the isolation channels which as shown in Fig. 5 is approximately 30 microns. The distance of 30 microns between isola-tion channels is also the center-to-center distance -~3-between adjacent circuits 52 in the array 50. This distance, it will be noted, is less than the 40 micron distance between the isolation channels 70 in the conventional prior art device 10 utilizing a lateral fuse on a bipolar substrate as shown in Figs. 1-3.
In accordance with the teachings of the pre-sent invention, the memory region 68 is made of a settable-substantially non-resettable phase change material having desired thermal and electrical characteristics. These materials can be selected as desired from the group of chalcogenides, ger-manium, tellurium and selenium as described below.
With GeTe as a starting material for cell regions of circuits in an array, various Ge:Te materials were developed having low reversibility and resettability and having desirable thermal and electrical characteristics. Such non-resettable materials have the formula Gea:Teb where a is 30 to 100 atomic percent and b is 70 to 0 atomic percent, one material being Ge70Te30. Such a film of cell material was deposited to form a cell or memory region with a thickness of 1000 ~ngstroms. Such cell region was set in a permanently conductive 7~

state by a 5 milliamp current pulse having a width of 7 to 17 milliseconds. This current pulse raises the temperature of the cell above its crystalline temperature which is 340C causing a rapid forma-tion of conductive crystalline filament. The bulkmaterial melting point is in excess of 750C so that there is no chance of the material becoming reset to an amorphous state, and an extremely ther-mally stable, radiation resistant cell region is provided.
For a lower SET current and higher OFF resis-tance than the above material, a cell region can be formed of GE60Te40. This material has a lower crys-tallization temperature of 270C resulting in a lower SET current to place the material of the cell in its crystalline form where it is highly con-ductive, and the temperature stability thereof is still in excess of 725C. The OFF state resistance of this material is higher than the Ge70Te30 mate-rial.
A further cell material, amorphous Ge4sTe4sSelohas desirable characteristics for use in the pro-grammable arrays. This material has a limited number oE reversals on the order of ten or less.

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The maximum processing temperature has been found to be approximately 250C and the maximum storage temperature has been found to be about 200C. Oth-er chalcogenide materials can be utilized in ac-cordance with the invention.
Also according to the invention, the phase change material or alloy can be a tetrahedral mate-rial containing at least one of silicon, germanium or carbon which also can contain hydrogen, oxygen and/or fluorine. One of the materials from which the cells can be formed is silicon and carbon with a range of 0 to 100 atomic percent silicon and 100 to 0 atomic percent carbon. When the amorphous material is 100 atomic percent amorphous carbon, at least a portion of this material forming the cell is converted, by an appropriate current pulse with an appropriate threshold voltage imposed across the memory region, into conductive graphite.
One preferred material from which the cell or memory region can be formed is SisoCso. A cell made of this material is substantially irrevers-ible, i.e., substantially non-resettable. This cell material has a ma~imum processing temperature of up t32 to 500C and a maximum storage ~emperature of from 200C up to approximately 400C. Devices made from this material can have a threshold voltage of eight volts~ The SET resistance can be less than 500 ohms and an OFF resistance of up to 106 ohms.
Silicon or germanium alloys produced by glow discharge or plasma deposition technique, have properties and characteristics similar to those of the Si50Cso material. One such material is a sil-icon oxygen material wherein the silicon is 95 to100 atomic percent and the oxygen is from 5 to 0 atomic percent with one preferred material being Sig5O5. Other materials or alloys can be formed from compound gases such as silane, silicon tetra-fluoride and hydrogen.
In forming cell 68, the opening 72 is firstmasked by a conventional photoresist. The amor-phous phase change material is then deposited into the opening to the desired thickness. The de-position techinques can be those described in U.S.Patent Nos. 4,217,374 and 4,226,898. One exemplary deposition process is a plasma deposition from 5iH4 which can include a diluent such as argon gas in about a one to one ratio. The substrate is Z

heated to below the melting temperature of the photoresist, for example less than 150 centigrade.
Between 500 and 20no angstroms of cell mate-rial is deposited at an operating frequency of about 30 kilohertz, with about 800 angstroms pro-ducing a threshold voltage of eight volts. The photoresistance is then stripped off and the bar-rier layer 70 is deposited as previously described.
Varying the thickness of the cell 68 varies the threshold voltage required to set the phase change material into the conductive state. The silicon material described essentially can not b~ reset.
Setting the amorphous material forming the cell region 68 into the crystalline-conductive state for the Ge:Te:Se alloys or the Si compound alloys, is typically accomplished by passing a current through the material having a value of between lO microamps and lO milliamps with a threshold voltage of about 8 volts applied thereto for a period of between 1 microsecond and 1 mil-lisecond.
The materials or alloys described above pro~
vide cell or memory region materials which have a stable, highly conductive state and a stable, high-ly non-conductive state. The non-conductive state is substantially non-resettably switchable into the stable, highly conductive state by applying a cur-rent limited voltage pulse or a voltage limited current pulse across the cell region exceeding a predetermined threshold level. The cell remains in the highly conductive state even in the absence of an applied voltage or current and under all oper-ating conditions.
Referring now to Figs. 7 and 8, there is il-lustrated therein another embodiment of a program-mable array 100 made in accordance with the teach-ings of the pres~nt invention. The array 100 in-cludes circuits 102 each of which includes a cell 104 made of amorphous alloy material of the typ~
described above and an isolating device 105 which is a field effect transistor device 105 of the MOS
type which is formed in a P-type silicon substrate 106 on which circuits 102 are formed.
The array 100 includes an X axis aluminum conductor 108 which is connected to one side of the cell or memory region 104. The other side of the cell is coupled to an N~ diffused drain-forming 37~

region 110 in the substrate 106. The substrate 106 has a Y axis conductor 111 thereon above a source region 112 of the field effect transistor 105 dif-fused in the substrate 106. In addition, a Y axis gate forming conductor 114 is deposited on an insu-lating layer 116 on top of the substrate 106.
As shown, in the construction of the array 100 including the cell 104 and field effect MOS-type transistor 105 is formed in the substrate 106.
Spaced apart parallel N+ conductivity bands 110 and 112 are diffused in the upper region of the sub-strate 106 thereby to form respectively parallel MOS-type device source-forming regions 112 and drain-forming regions 110 each of which is used in common with a circuit 102.
Continuing the formation of the circuit 102, parallel gate insulating regions are formed on the substrate 106, such as the gate insulating layer 116. Such insulating layer may be silicon oxide or silicon nitride.
Using a suitable photo-resist masking and etching technique, the Y-axis conductor 111 is formed for making electrical connection to the source-forming region 112 and the Y-axis gate-8~

forming conductor 114 i5 ormed by vacuum deposi-ting or otherwise on the insulating layer 116.
Such conductors 111 and 114 can be formed of var-ious materials and are typically formed of poly silicon. Low resistance connections are made to the Y axis conductor 111 and ~ axis gate conductor 114 in a conventional manner.
Continuing with the formation of the array 100, an ins~lating layer 122 is now vacuum depos-ited or otherwise formed on the top surface of the substrate 106, and a portion thereof is cut a~ay to leave an open area 120 above the drain regions 110.
A layer of platinum is then deposited in the open area between portions of the layer of insulator 122 and on the top surface of the substrate 10~ which is then heated to form a platinum silicide region 12~ forming an ohmic (rather than a Schottky bar-rier diode) region. ~n etchant like Aqua Regia is then us~d to remove the excess platinurn, but not the platinum silicide region 124. A layer of the memory material 104 is then deposited in and about each opening 120 in the layer of insulating mate-rial 122 so as to make good electrical contact with the platinum silicide region 124. A thin barrier z layer 126 is then deposited over the insulating layer 122 and the drain region material 104, such thin barrier 126 preferably being made of a mate-rial-like Ti-W. Then a thicker layer of conductive metal such as aluminum is deposited to form the X
axis conductor 108.
As shown in Fig. ~, this array 100 including a cell region 104 made of amorphous material of the type described above and a MOS-type field effect transistor 105 forming the isolating device of the memory circuit 102 has a lateral extent of 21 mi-crons which is very much smaller than the 40 mi-crons of the prior art lateral fuse-type PRO~ de-vice 10 shown in Figs. 1 and 2.
A schematic equivalent circuit of the circuit 10~ shown in Fig. 8 is illustrated in Fig. 9.
Referring now to Figs. 10 and 11, there is illustrated therein two cells in an all-deposited thin film array 154 made in accordance with the teachings of the present invention which eliminates the previously described diffusion channels. As shown, the circuits 152 of the PROM device 154 are formed on a main substrate 156 illustrated in Fig.

7t~

11. On top of this main substral:e is deposited a layer of an insulating material 158. In thîs re-spect, the main substrate material 156 can be a metal substrate and the insulating layer 158 can be very thin so that heat generated in other portions of the memory circuits 152 deposited on the insu-lating layer 158 can be dissipated in the heat sink formed by the metal substrate 156. Such insulating layer 158 can be made of silicon dioxide. On top of the layer of insulating material 158 are depos-ited parallel conductor bands 160 which form the Y
axis conductors 160 of the memory matrix of the array 154.
In accordance with the teachings of the pre-sent invention, a P-N junction device made of lay-ers of amorphous semiconductor material or alloy are deposited on top of the conductor bands 160.
In this respect, an isolating rectifier device 162 is formed from successively doped N~ and P+ layers 164 and 166 of amorphous alloy. Then a layer of insulating material 170 is deposited over the sub-strate 158 and the layers of material 160, 164 and 166 thereon. Next, an open space 169 is cut out in the area where the platinum silicide region 168 is to be formed and such platinum silicide region 168 is formed in the manner described above.
Then a film of phase change subskantially non-resettable amorphous material is deposited to form a cell or memory region 172 in the manner described above. Then, a thin layer of refractory barrier-forming material like molybdenum or a TiW alloy 174 is deposited on the insulating layer 170 and the memory regions 172. Next, a thicker layer 176 of conductive metal such as aluminum is deposited over the refractory barrier-forming layer 174 to form an X axis conductor 176. The platinum silicide region 168 may form an ohmic contact or Schottky barrier interface with a lightly doped outer amorphous alloy layer.
As shown in Fig. 11, the center-to-center distance between the all-film deposited circuits 152 is 8 microns which provides a very high packing density, e.g., a memory cell density of approxi-mately 0.1 mil2. This is accomplished as shown inFig. 11 and as described above by having each cir-cuit extend substantially vertically between the X
axis conductor 176 and the Y axis conductor 160.

Z
The diocle 162 utilized as an lsolati.ng device can h~ve a Eirst reCJioll and a second region, the regions abu-tting each other to form a junction therebetween and the first region being made of an amorphous a].loy including silicon and fluorine.
PreEerably, the amorphous material also contains hydrogen and is amorphous SiaFbEIC where a is between 80 and 98 atomic percent, b is between 0 and 10 atomic percen-t and c is between 0 and 10 atomic percen-t. The amorphous material or alloy of the diode 162 can be formed in a manner described in U.S. Patent Nos. 4,217,374 and 4,226,898. It appears that the chalcogenide materials form a high resis-tance phase change cell 172 which can be set without affecting the amorphous diode 162. When the plasma deposited tetrahedral phase change cells 172 are utilized it appears ~hat they have a large resistance and also form one or more reverse biased diodes to that of diode 162 again allowing -them to be set without affecting the forward biased diode 162~
The first re~ion cf amorphous alloy in the diode can be doped with a dopant ma-terial chosen from an element of Group V of the Periodic Table .
,~, ~ .cm / ~;

'78~

such as, for example, phosphorus or arsenic, and an amount of dopant material constituting between a few parts per million and five atomic percent.
Preferably, the first region is doped by amount of dopant material constituting 10 to 100 parts per million.
The second region can be a metal, a metal alloy or a metallic like material having a high barrier height on the first region so as to create a Schottky barrier. Such a metal can be chosen from the group consisting of gold, platinum, palla-dium or chrome.
The amorphous alloy of the first region can alternatively be doped with a dopant material cho-sen from an element of Group III of the PeriodicTable such as boron or aluminum in an amount con-stituting between a few parts per million and five atomic percent.
Also alternatively, the second region can be made of a material dissimilar to the amorphous alloy material such as to form a heterojunction.
Referring now to Figs. 13 and 14, there is illustrated therein another programmable array 210 made in accordance with the teachings of the pre~

~IL~7~:

sent invention and which includes a circuit 212 extending between an X axis metal conductor 214 and a Y axis conductor 216. As shown, in this embodi- :
ment, the circuit 212 includes a cell or memory region 218 having an amorphous material therein and an isolating device 220 which is a thin film, field effect transistor 220.
As shown, the conductor 216 is a band of con-ductive material forming a source region 216 for the thin film transistor which also includes a drain region 222 and a gate conductor 224.
In forming the circuit 212, a band of source material 216 is first laid down on an insulated or insulator substrate 226. The material of which the band of source material 216 is made can be a metal (as shown), an N doped semiconductor alloy, or a P
doped semiconductor alloy. After the band of source material 216 has been laid down on the substrate 226, regions of drain material 222 are deposited on the substrate 226. Again, the regions 222 af drain material can be made of a metal (as shown), an N
doped semiconductor alloy material or a P doped semiconductor material. Next, a layer 228 of amor-phous silicon alloy which preferably contains hy--37~

drogen and/or fluorine is deposited on the sub-strate 226 between the source band forming con-ductor 216 and the drain region 222.
This amorphous silicon alloy is preferably amorphous SiaFbHC where a is between 80 and 98 atomic percent, b is between 0 and 10 atomic per-cent and c is between 0 and 10 atomic percent.
After the amorphous silicon layer 228 has been laid down, a layer of gate insulating material such as a gate oxide 230 is laid down on top of the amorphous silicon layer 228. Next a layer of gate conductor material 224 is laid down in a band ex-tending parallel to the band 216 on top of the gate insulating material. The gate conductor 224 can be made of a metal (as shown), an N doped semicon-ductor or a P doped semiconductor. Next, a layer of insulating material 232 is laid down over the substrate 226, the band of source material 216, the layers 228, 230 and 224 described above and the regions 222 of drain material. Next, the insu-lating material above the drain region is removed to form an opening 233 in which is deposited a layer of cell material 218. Lastly, a band of mate-rial, typically a metal such as aluminum, is laid down over the insulating material 232 and in con-tact w.1.th the memory region 218 and parallel to the X axis to form the X axis conductor 214. A barrier layer (not shown) can be deposited before the con-ductor 214.
A schematic circuit diagram of some of the circuits 212 of the array 210 is illustrated in Fig. 14.
It will be noted that the circuit 212 of the array 210, by reason of the spacing of the source region 216 from the drain region 222 has a greater lateral extent than the circuits 152 wherein the regions 164 and 166 of the diode 162 are in line or stacked in line with the memory region 172 between . 15 the X axis conductor 176 and the Y axis conductor . 160. Nonetheless, where MOS-type field effect transistors are desired for use as the isolating device, the array 210 is preferred.
From the foregoing description it is apparent that the cell of the present invention having an amorphous phase change material which is settable in one state and then substantially non resettable, and which has desirable thermal and electrical ~SI~'7~3~

characteristics as described above, in conjunction with one of several isolating devices, provides programmable arrays which can be easily set in a minimum amou~t of time and which, depending upon the phase change material chosen, can provide a circuit which has low set current, a fast setting time, a relatively high processing temperature, a relatively high storage temperature, a low SET
resistance and a high OFF resistance.
Also r the isolating devices can be of conven-tional single crystal silicon bi-polar Schottky diode type or bipolar P-N junction type. Alter-natively, such isolating devices can be of the MOS-type, either the planar MOS type or the V-MOS type.
Additionally, and preferably, the isolating devices are formed by a thin film depositing technique and in a most-preferred form the diode or field effect transistor forming the isolating device is made of an amorphous vacuum deposited silicon alloy which also contains hydrogen and/or fluorine. The pre-ferred all-thin film circuit formed arrays are preferred since they have the highest packing den-sity and at the same time provide an array wlth a ~llS~li7~2 substantially non-resettable phase change material cell and thin film diodes or transistors that are vertically arranged between crossover X and Y axis - conductors at the crossover points.
In addition, it will be apparent that the various arrays having the various cell configura-tions illustrated in the previous figures can be utilized with addressing circuitry which select a particular X or Y axis conductor for supplying setting or reading currents and such addressing circuitry can be formed by deposited films. In this respect, an all deposited film memory matrix for example and addressing circuitry is deposited on the same substrate as illustrated diagramatically in Fig. 15 and includes a memory matrix or array 250 with associated addressing circuitry 252 de-posited on a substrate 254. Also it is to be noted that the addressing circuitry 252 and the memory matrix 250 can be deposited on the same side of the substrate 254 or on opposite sides of the substrate 254. Additionally, the array and the memory matrix 250 can be partially or all-thin film deposited in the manner described above. Preferably, however, in addition to forming the memory region o~ each ~5i3'~2 :;

memory circuit in a thin-film manner from an amor-phous alloy material, the isolating devices and the addressing circuitry 252 are also formed by a thin-film depositing technique.
Since most presently utilized data storage and handling systems operate through integrated cir-cuits formed in silicon chip substrates, it is believed that the initially marketed arrays made according to the teachings of the present inven-tion, would probably have memory matrices where some portion of the memory matri~ involved such as the isolating device and/or addressing circuitry utilized therewith will be formed within a silicon chip substrate.
In Fig. 16 there is diagramatically illus-trated a silicon chip substrate 300 with an all or partially deposited thin film memory matrix or array 302 having memory circuits therein and asso-ciated addressiny circuitry 304 which are incor-porated into the silicon chip substrate 300 by forming the various elements of the circuit from dopant-diffused areas therein.
It is to be noted that an all-thin film array including circuits formed in accordance with the ;~S~7~
;

teachings of the present invention and utilizing thin film deposited isolating devices, together with addressing circuitry formed by thin film de-positing technique provides substantial advantages since a number of such memory systems can be stack-ed one above the other with ins~lating layers sepa-rating the same. Also, thin metal, heat sink-forming substrates can be provided between insu-lating layers and have heat radiating fins on the outer edges thereof.
From the foregoing d~scription, it will be apparent that the arrays 50, 100, 154 or 210 dis-closed herein having incorporated therein con-ventional or new thin-film deposited isolating devices and utilized with conventional or new thin-film deposited addressing circuitry provide a num-ber of advantages, some of which have been des-cribed above and others of which are inherent in the arrays of the present invention. Most im-portantly, such arrays can be made with a materialhaving desirable thermal and electrical charac-teristics with extremely high packing densities of the cells and with a very high OFF resistanceO

-~3-: The amorphous cells such as 68, can have nu-: merous sizes and shapes and could be deposited in the form of the fuse link 20. (By the term "amor-.: phous" is meant an alloy or material which has long : 5 range disorder, although it can have short or in-termediate order or even contain at times cry-stalline inclusions). Further, the cells such as 68, do not have to be deposited on top of the diode layers but can instead be between the two metal layers 58 and the second metal layer (not shown).
Also the cell 218 could be between the gate 224 and the X conductor 214.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A programmable cell comprising an amor-phous cell body said body including at least a portion having settable substantially non-reset-table means said means having a highly nonconduc-tive settable state settable structurally into a highly conductive state.

2. The cell according to claim 1 wherein said means is settable into said conductive state by a threshold voltage of twenty volts or less.

3. The cell according to claim 1 wherein said means is settable into said conductive state by a threshold of ten volts or less.

4. The cell according to claim 1 wherein said means is settable into said conductive state by a programming current of twenty-five milliamps or less.

5. The cell according to claim 1 wherein said means is settable into said conductive state by a programming current of five milliamps or less.

6. The cell according to claim 1 wherein said means in said highly conductive state has a resistance of five hundred ohms or less.

7. The cell according to anyone of claims 1, 3 and 5 wherein said means in said highly con-ductive state has a resistance of one hundred ohms or less.

8. The cell according to claim 1 wherein said means in said highly nonconductive state has a resistance of ten thousand ohms or greater.

9. The cell according to anyone of claims 1, 3 and 5 wherein said means in said highly non-conductive state has a resistance of one million ohms or greater.

10. The cell according to claim 1 wherein said body has a maximum permittable processing temperature tolerance of two hundred degrees cen-tigrade or greater.

11. The cell according to anyone of claims 1, 3 and 5 wherein said cell body has a maximum permittable processing temperature tolerance of five hundred degrees centigrade or greater.

12. The cell according to claim 1 wherein said cell body has a long term storage temperature of one hundred and seventy-five degrees centigrade or greater.

13. The cell according to anyone of claims 1, 3 and 5 wherein said cell body has a long term storage temperature of two hundred degrees centi-grade or greater.

14. The cell according to claim 1 wherein said means is settable into said conductive state in one thousand microseconds or less.

15. The cell according to anyone of claims 1, 3 and 5 wherein said means is settable into said conductive state in ten microseconds or less.

16. The cell according to claim 1 wherein said means is resettable less than one hundred times.

17. The cell according to anyone of claims 1, 3 and 5 wherein said means is resettable less than ten times.

18. The cell according to claim 1 wherein said means is an amorphous phase change material which is settable into a crystalline highly con-ductive state.

19. The cell according to claim 1 wherein said means is set into a non-volatile highly con-ductive state.

20. The cell according to claim 1 wherein said cell body is formed from one or more chalco-genide elements.

21. The cell according to claim 20 wherein said chalcogenide elements are germanium and one of tellurium and selenium.

22. The cell according to claim 20 wherein said chalcogenide elements are germanium, telluri-um and selenium.

23. The cell according to claim 22 wherein said cell body is formed by sputtering said ele-ments.

24. The cell according to claim 1 wherein said cell body is formed from material containing tetrahedral elements including at least one of the group consisting of silicon, germanium and carbon.

25. The cell according to claim 24 wherein said cell body also includes one or more of the group consisting of fluorine, hydrogen and oxygen.

26. The cell according to claim 24 wherein said cell body is formed by plasma deposition from a plasma containing at least silicon and hydrogen.

27. The cell according to claim 24 wherein said cell body is formed by plasma deposition from a plasma containing at least silicon and fluorine.

28. A programmable electronic array of cells comprising a plurality of amorphous cell bodies, each of said bodies including at least a portion having settable substantially non-resettable means, said means having a highly non-conductive state settable structurally into a highly conduc-tive state.

29. The array according to claim 28 wherein each of said cells is formed on a substantially planar substrate, each of said cells coupled be-tween at least a pair of conductors and formed in a substantially perpendicular direction to said planar substrate to provide a high cell packing density on said substrate.

30. The array according to claim 28 wherein each of said cells includes isolating means for isolating said cells from at least a pair of con-ductors.

31. The array according to claim 30 wherein each cell including isolating means has a cell area of less than one square mil.

32. The array according to claim 30 wherein said isolating means include bipolar rectifying means formed by single crystal techniques.

33. The array according to claim 32 wherein said bipolar rectifying means includes a Schottky diode.

34. The array according to claim 30 wherein said isolating means include rectifying means hav-ing at least first and second regions, said re-gions abutting one another and forming a junction therebetween, at least one of said regions being formed from an amorphous material including at least silicon.

35. The array according to claim 34 wherein the second one of said regions is formed from a metal metal alloy or a metallic-like material forming a Schottky barrier with said first region.

36. The array according to claim 28 wherein each of said cells is a thin film deposited cell.

37. The array according to claim 30 wherein each of said isolating means include a field ef-fect transistor.

38. The array according to claim 37 wherein each of said field effect transistors is a planar-MOS type transistor.

39. The array according to claim 37 wherein each of said field effect transistors is a V-MOS
type transistor.

40. The array according to claim 37 wherein each of said transistors is a thin film amorphous transistor formed from at least silicon.

41. The array according to claim 30 wherein said isolating means are coupled to bipolar ad-dressing means formed by single crystal tech-niques.

42. The array according to claim 30 wherein said isolating means are coupled to MOS addressing means.

43. The array according to claim 30 wherein said isolating means are coupled to thin film amorphous transistor addressing means.

44. The array according to claim 28 wherein said pluarlity of cells are stacked in at least two groups one upon another.

45. The array according to claim 44 wherein each of said cells is formed from at least one of the group consisting of germanium, tellurium and selenium.

46. The array according to claim 28 wherein each of said cells is formed from material con-taining tetrahedral elements, said elements being at least one of the group consisting of silicon, germanium and carbon.

47. The array according to claim 46 wherein said cells form the programmable cells in a PROM
device.

48. The array according to claim 47 wherein said cells form at least some of the fuse elements in a programmable logic array.

49. The array according to claim 48 wherein said cells form at least some of the fuse elements in a gate array.

50. The array according to claim 28 wherein said cells form at least some of the die intercon-nection elements in a set of integrated circuits.