CA1165899A - Lateral insulated gate field effect transistor device - Google Patents

Lateral insulated gate field effect transistor device

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Publication number
CA1165899A
CA1165899A CA000379555A CA379555A CA1165899A CA 1165899 A CA1165899 A CA 1165899A CA 000379555 A CA000379555 A CA 000379555A CA 379555 A CA379555 A CA 379555A CA 1165899 A CA1165899 A CA 1165899A
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Prior art keywords
layer
channel region
epitaxial
field effect
region
Prior art date
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Expired
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CA000379555A
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French (fr)
Inventor
Sel Colak
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Koninklijke Philips NV
Original Assignee
Sel Colak
North American Philips Corporation
Philips Electronics N.V.
Koninklijke Philips Electronics N.V.
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Publication of CA1165899A publication Critical patent/CA1165899A/en
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/901—MOSFET substrate bias

Abstract

ABSTRACT:

A lateral, for example, double-diffused DMOS
insulated gate field effect transistor includes a field-shaping semiconductor layer which serves to improve the breakdown voltage and/or series resistance characteristics of the device. The field-shaping layer redistributes the electrical field strength in the device during operation in order to eliminate too large an electrical field strength in portions of the device where breakdown would otherwise first occur. The field shaping layer may be a buried layer, a surface layer, or a combination of a buried layer and a surface layer.

Description

P~ 21035 "Lateral insulated gate field e~fect transistor device".

The invention is in the field of semiconductor insulated gate field-effect devices, a~d relates specific-ally to lateral ~MOS insulated gate field effect transis-tors.
Such transistors are well-known in the art and a typical high-voltage DMOS transistor is described on pages 1325-1326 of the "IEEE Transactions on Electron Devices", ~ol. ED 25, No. ll, November 197~, in a paper entitled "Tradeoff Between Threshold Voltage and Breakdown in High-Voltage Double-Diffused MOS Transistors", by Pocha et al. This device includes a semiconductor substrate of a first conductivity type (p-type), an epitaxial surface layer o~ a second conductivity type (n-type) on the sub-strate, a surface-adjoining channel region of the first conductivity type in the epitaxial layer, which forms a p-n junction therewith, a surface-adjoining source region of the second conductivity type in the channel region~ and a surface-adjoining drain region of the second conductivity type in the epitaxial layer and spaced apart from the channel region. An insulating layer is provided on the epitaxial surface layer and covers at least that portion of the channel region located between the source and drain regions. A gate electrode is provided on the insulating layer, over a portion of the channel region between the source and drain regions and is electrically isolated from the epitaxial surface layer, while source and drain electrodes are connected respectively to the source and drain regions of the transistor. Such prior art high-volt-age DMOS transistors typically have a relatively thick epitaxial layer~ in the order o~ about 25-30 micrometers at a breakdown voltage of about 250~, as indicated in the Pocha et al paper.

Generalized techniques for improving the high-voltage breakdown characteristics of p-n junctions are disclosed in U.S. Patent Application Serial No. 913,026, filed June 6, 1978, by V. Temple which corresponds to published Netherlands patent application No. 7904444.
Subsequently, it was found that the breakdown characteris-tics of high-vol-tage semiconductor devices could be im-proved using the REduced SURface Field strength (or RESURF) technique, as described in "~Iigh Voltage Thin Layer Devices ~RESURF Devices)", "International Electronic Devices Meeting Technical Digest", December, 1979, pages 238-240, b~ Appels et al, and U.S. Patent 4,292,642 which issued on September 29, 1981, by Appels et al, and which corresponds to published Netherlands patent application Nos. 780058~
and 7807835. Essentially, the improved breakdown character-istics of RESURF devices are achieved by employing thinner but more highly doped epitaxial layers to reduce surface field strength.
The RESURF technique was applied to lateral DMOS
transistors, as reported in "Lateral DMOS Power Transistor Design", "IEEE Electron Device Letters", Vol. EDL-l, pages 51-53, April, 1978, by Colak et al, and the result was a substantial improvement in device characteristics. It should be understood that in high-voltage DMOS devices, there is always a trade-off between the breakdown voltage and the series resistance in the conductive state (so-called-"on-resistance") with the goal being to increase the breakdown voltage level while maintaining a relatively low on-resistance. Using the prior art RESURF technique, and assuming a constant breakdown voltage, an improvement (e.g. decrease) in on-resistance by a factor of about 3 may be obtained in a device occupying the same area as a conven-tional (thick epitaxial layer) DMOS device. Nevertheless, a $urther improvement in the breakdown voltage and/or on-resistance characteristic of such devices is extremelydesirable, in particular for high-voltage power devices where both breakdown voltage and on-resistance are important P~IA 21035 ~3~

parameters. Alternatively, it would also be ~dvantageous to provide DMOS devices with the same characteristics as prior art devices but which occupy a smaller area and are thus less expensive to produce.
It is therefore one of the objects of the pre-sent invention to provide a lateral DMOS insulated gate field effect transistor which features improved character-istics in the area of breakdown voltage and/or on-resistance.
It is a further object of the invention to pro-vide lateral DMOS insulated gate field effect transistors with breakdown voltage and on-resistance characteristics comparable to those of prior-art devices, but which occupy a smaller area and thus cost less to manufacture.
In accordance with the invention, these object-ives are achieved by a lateral DMOS insulated gate field effect transistor of the type described above which is characterized in that a field-shaping semiconductor layer of the first conductivity and having a doping level greater than that of the substrate is provided adjacent but spaced apart from the channel region. This semiconductor layer serves to redistribute the electrical field strength in the device during operation by reducing the field strength in a first part of the epitaxial layer mainly located between the source and drain regions and adjacent the ~-n junction between the epitaxial layer and the channel region, while increasing the electrical field strength in a second part of the epitaxial layer mainly located adjacent the drain region. This field-shaping semiconductor layer may be advantageously employed in devices in which the epitaxial layer is provided in accordance with the said RESURF tech-nique in which the epitaxial layer is depleted throughout its thickness already at a drain electrode voltage which is smaller than the breakdown uoltage, although other more con-ventional DMOS devices will also be improved by -PHA 21035 -4- 2-4-1g81 the invention. The semiconductor la~er whio'h serves -to redistribute the electrical field may either be a buried layer provided subs-tantially in the substrate beneath the channel region or a surface layer provided in the epitaxial layer alongside the drain region. In a further embodiment o~ the invention, the semiconductor Layer includes both a buried layer portion and a surface layer portion.
~ach of the embodiments mentioned above serves to reduce the electrical field strength during operation in those parts of the device where reverse avalanche break-down would normally occur first, thus enabling these devices to achieve a higher 'breakdown voltage. In particula~
transistor-s in accordance with the present invention are 15 theoretically capable of providing a factor if improvement in on-resistance of about 1,5 to 2.0 for a constant break-down voltage, as compared to conven-tional DMOS transistors employing the RESURF technique. ~lternatively, devices in accordance with the invention are capable of providing 20 an improvement in breakdown voltage for a constant on-resistance.
The invention will now be described in grea-ter detail with reference to a few em'bodiments and the drawing.
Fig. 1 is a cross-sectional view of a lateral 25 double-diffused MOS transistor of conventional design;
Fig. 2 is a cross-sectional view of a lateral double-diffused MOS transistor in accordance with a ~irst embodiment of the invention;
Fig. 3 is a cross-sectional view of a lateral 30 double-di~fused MOS transistor in accordance with a second embodiment of the invention, and Fig. 4 is a cross-sectional view of a lateral double-diffused MOS transistor in accordance with a -third embodiment of the invention.
- 35 Fig. l of the drawing shows a typical prior art double-diffused MOS transistor suitable for high-voltage applications. It should be noted that Fig. l, as well as .

;

P~IA 21035 5 2-L~-1g81 the remaining ~igures o~ the drawing~ are not drawn to scale~ and in particular the vertical dimensions are exaggerated ~or improved clarity. Additionally, like par-ts are designated with like reference numerals in the various figures, and semiconductor regions of the same conduc~
tivity type are shown hatched in the same direction.
In ~ig. l, a D~OS transistor l has a semi-eonductor substrate 10 of a first eonductivity type, typically p-type, with an epitaxial surface layer 12 of a seeond eonductivity type opposite to that of -the first, typically n-type, on a major surface ll of the substrate.
A surfaee-adjoining ehannel region 16 of the ~irst con-duciivity type is provided in the epitaxial layer and forms a p-n junetion 17 therewith. A surface-adjoining source region 14 of the second conductivity type is provided in the channel region 16, while a surface-adjoining drain region 20, also of the seeond conductivity type, is pro-vided in the epitaxial layer 12 at a loeation which is spaeed apart ~rom the channel region 16. The channel region 16 has a surface-adjacent portion 18 located between the source and drain regions of the device which forms the ehannel of the device . An insulating layer 22 is provided on the epitaxial surface layer 12 and covers at leas-t that portion of the channel region 16 located between the source and drain regions o~ the transistor. While insulating layer 2Z is shown as a stepped layer and is of silicon oxide, other eon~igurations and insulating materials can be used without departing from the seope of the invention. A gate eleetrode 24 is provided on the insula-ting layer 22 over the channel 18, and source (26) and drain (28) electrodes provide electrical connections, respectively, to the source and drain regions of the transistor.
Devices of the general type shown in Fig. l are well known in the art, and hence will not be deseribed in further detail. As noted above, the epitaxial surface layer 12 in such prior-~art devices is typieally a relatively thick layer, having a thickness in th ~ rd~r of about 25 to 30 micrometers at breakdown voltages o~ about 250 Volts.

s~

Such rela-~ively thic]c epitaxial layers tend to make these devices subject to reverse avalanche breakdown of the p-n junction 17 in the curved area o the junction beneath the gate electrode 24 due to field crowding in this area.
This characteristic is particularly undesirable in high-voltage applications because it limits the maximum operating voltage of the transistor.
The REduced SUREace Field strength (RESU~F) tech-nique, as applied to lateral DMOS transistors in the previously-men~ioned Colak et al paper, serves to partially overcome this problem. By substantially reducing the epit-axial layer thickness, down to about 3 to 15 micrometers, while at the same time increasing the doping level in the epitaxial layer to maintain an acceptable on-resistance value, a substantial improvement in high-voltage breakdown characteristics can be obtained. Thus, Fig. 1 may also represent a prior art RESURF DMOS transistor, assuming that the appropriate thickness and resistivity values for the epitaxial layer 12 are selected in such manner that the layer 12 is at least locally depleted throughout its thickness already at a voltage lower than the breakdown voltage. In accordance with the RESURF technique, the product of doping concentration and epitaxial layer thickness (Nepixdepi) should for that purpose typically be approximately 1012 atoms/cm2. Using this technique, on~resistance can be reduced by a factor of about 3 for a device occupying the same area as a conventional device, while maintaining the same breakdown voltage. Alternatively, a like improvement in breakdown voltage can be obtained for the same on-30 resistance, or, as a third alternative, more moderate im- -provements in both breakdown voltage and on-resistance can be obtained.
The present invention is based upon the recogni-tion of the fast that by redistributing the electrical field strength within a lateral DMOS transis~or by using a field-shaping semiconductor layer, in either conventional or RESURF DMOS devices, a substantial improvement in breakdown voltage and/or on-resistance may be .

- - \
PH~ 21035 -7 2-~ 1981 ob-tained, While the invention may be applied to oon-ven-tional DMOS transistors, optimum performance is obtained by providing the field-shaping semiconductor layer of -the invention in devices in which the thickness and the doping of the epitaxial layer is selected in accordance with the RESURF technique, as described above. In both cases the invention is charac-terized in that the electrical field strength redistribution is accomplished by a field-shaping semiconductor layer of the first conductivi-ty type which has a doping level greater than that of the substrate and is provided adjacent but spaced apart from the channel region of the device. This field-shaping semiconduc-tor layer serves to reduce the electrical field strength in a ~irst part of the epitaxial layer mainly located adjacent the p-n junction 17 and between the source and drain regions of the device, while increasing the electrical field strer~h in a second part of the epitaxial layer mainly located adjacent the drain region 20. In this manner, a more homogeneous electrical field strength distribution ls obtained, and the (two) large electrical field strength in the curved area of the p-n junction where reverse avalanche brea~down previously occurred is reduced, Using a field-shaping semiconductor layer in aeeordance wi-th the present invention, devices can be fabricated having a further improvement in breakdown voltage and/or on-resistance (i.e. an overall improvement factor) of about 1.5-2.0 times, as compared to RFSURF
D~IOS devices having a like area. This improvement is ob-tained by using a selected field-shaping layer configurat-ion and appropriate values for the epitaxial layer thicknessand doping level, as described below.
Fig. 2 of the drawing shows a DMOS transistor
2 in which the field-shaping semiconductor layer of the first conductivity type is a buried layer 30a which is provided substantially in the subs-trate 10 at its major surface ll. Buried layer 30a ex-tends beneath the channel region 16 and the part of the epitaxial layer between the source and drain re~ons 14 and 20 which is adjacen-t to the PHA 21035 -8~ 19~1 p-n junction l7. As shown in Fig. 2, the buried layer 30a will typicall~ extend across the entire area below the gate electrode 24 ancl s-top shortly therea~ter. The field-~aping buried semiconductor layer 30a is o~ the same conductivity type as that of the subs-trate 10, so that a typical device with a p-type substrate would have a p-type buried layer 30a. However, the doping level of the buried layer 30a is greater than that of the substrate. For example, devices have been fabricated in which the buried l layer is formed in the substrate by ion implantation, although the invention is not limited to this technique, with a thickness in the range of about 3.0 to 5.0 micro-meters and a doping level of` abou-t 1.0 ~ 1.5 x 10 atoms/cm . Due to the nature of the ion implantation process, a small portion of the buried layer 30a extends into the epitaxial layer 12.
In the device described above, the doping level of the epita~ial layer 12 is about 3.0 x 1015 atoms/cm3 and its thickness is about 6 micrometers, while the dop ng 20 level of the substrate is about 4.0 x 10 atoms/cm3.
The substrate 10, the buried layer 30a and the channel region 16 are all of p-type material, while the epitaxial layer 12, the source region 14 and the drain region 20 are of n-type material.
In the ~irst devices manufactured in accordance with the embodiment described above and shown in Fig. 2 breakdown voltages in the order of about 370 volts were measured with normalized on-reslstance values i.e. the on-resistance per mm of` active area of` about 5,0 ohms-mm .
30 These initial results represent an overall improvement f`actor of about 1.5 over prior-art DMOS devices made at the same facility and employing the RESURF principle, and an overall improvement factor of about 4~5 over conventional lateral double-diffused MOS transistors with thick 35 epitaxial layers.
In the embodiment shown in Fig. 3, the field-shaping semiconductor layer o~ a DMOS transistor 3 is a surface layer 30b which is provided in a surface-adjo:ining ..
' ' :

P~A 2l035 -9~

region of the epitaxial layer l2 alongside the drain region 20, which surface layer 30b extends from the drain region toward -the channel region 16 of the device transis-tor 3, although the surface layer 30b does not extend so 6 far as to contact the channel region. In this case, the doping concentration of the surface layer is approximately 1.0 x 10 atoms/cm2, while the thickness of the surface layer is about 1.0 to 1.5 micrometers. The surface layer may be provided in the epitaxial layer by ion implantation, and the epitaxial layer thickness and doping level, as well as the doping level of the substrate, are approximately -the same as for -the device shown in Fig. 2.
ln the embodiment shown in Fig. 4, bo-th a bu-ried layer 30a and a surface layer 30b are provided in a single DMOS transistor 4. Using this configuration, the dopin~ level in each of the field-shaping layer portions 30a and 30b is about one-half of the value previously mentioned for the corresponding layer in the single~layer embodiments of ~igs. 2 and 3. In other respects, the embodiment o~ Fig. l~ is generally similar to the previous-ly-described devices, and thus this embodiment will not be described in further detail.
Thus, by providing a field-shaping semiconduc-tor layer in a DMOS transistor adjacent to its channel region, the present invention serves to redistribute the electrical field density in the epitaxial layer of the device during operation, thereby providing improved high-voltage breakdown and/or on-resistance characteristics.
Alternatively, the invention may be used to obtain ~MOS
devices with characteristics comparable to those of prior art devices, but which occupy a smaller area and are thus less expensive to manufacture.
Finally, while the inven-tion has been particu-larly shown and described with reference to certain pre-ferred embodiments thereof) it will be understood bythose ski~led in the art that various changes in form and detail may be made without depar-ting from the spirit and scope of the inven-tion.

:

PHA 21035 10- ~-4-19~1 Although the embodiments always mention double-dif~used DMOS transistors the region 14, or the two regions 14 and 16 may o~ course also be provided by ion implantation.

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Claims (8)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A lateral DMOS insulated gate field effect trans-istor having a semiconductor substrate of a first conduc-tivity type, an epitaxial surface layer of a second conduc-tivity type opposite to that of the first on a major sur-face of said substrate, a surface-adjoining channel region of the first conductivity type in the epitaxial layer and forming a p-n junction therewith, a surface-adjoining source region of the second conductivity type in the channel region, a surface-adjoining drain region of the second con-ductivity type in the epitaxial layer and spaced apart from the channel region, an insulating layer on the epitaxial surface layer and covering at least that portion of the channel region located between the source region and the drain region, a gate electrode on the insulating layer, over said portion of the channel region and electrically isolated from the surface layer, and source and drain regions of the transistor, characterized in that a field-shaping semicon-ductor layer of said first conductivity type and having a doping level greater than that of said substrate is provided adjacent but spaced apart from said channel region.
2. A lateral field effect transistor as in Claim 1, wherein the doping concentration and thickness of said epitaxial surface layer are so small that at drain electrode voltage which is smaller than the breakdown voltage, the epitaxial layer is depleted throughout its thickness.
3. A lateral field effect transistor as in Claim 1, wherein said field-shaping semiconductor layer is a buried layer provided substantially in said substrate at said major surface thereof and extends at least beneath said channel region and said first part of the epitaxial layer.
4. A lateral field effect transistor as in Claim 3, wherein said buried layer has a thickness of about 3.0 to 5.0 micrometers and a total doping of about 1.0 to 1.5 x 1012 atoms/cm2, and said epitaxial layer has a thickness of about 6.0 micrometers and a doping concentration of about 3.0 x 1015 atoms/cm3.
5. A lateral field effect transistor as in Claim 1, wherein said field-shaping semiconductor layer is a surface layer provided in a surface-adjoining region of said epi-taxial layer alongside said drain region and extending from said drain region toward, but not contacting, said channel region.
6. A lateral field effect transistor as in Claim 5, wherein said surface layer has a thickness of about 1.0 to 1.5 micrometers and a total doping of about 1.0 x 1012 atoms/cm2, and said epitaxial layer has a thick-ness of about 6.0 micrometers and a doping concentration of about 3.0 x 1015 atoms/cm3.
7. A lateral field effect transistor as in Claim 1, wherein said field-shaping semiconductor layer comprises a buried layer portion provided substantially in said sub-strate at said major surface and extending at least beneath said channel region and said first part of the epitaxial layer, and a surface layer portion provided in a surface-adjoining region of said epitaxial layer alongside said drain region and extending from said drain region toward, but not contacting, said channel region.
8. A lateral field effect transistor as in Claim 7, wherein said buried layer portion has a thickness of about 3.0 to 5.0 micrometers and a total doping of about 0.5 to 0.75 x 1012 atoms/cm2, said surface layer portion has a thickness of about 1.0 to 1.5 micrometers and a total dop-ing of about 0.5 x 1012 atoms/cm2, and said epitaxial layer has a thickness of about 6.0 micrometers and a doping con-centration of about 3.0 x 1015 atoms/cm3.
CA000379555A 1980-06-16 1981-06-11 Lateral insulated gate field effect transistor device Expired CA1165899A (en)

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US06/159,883 US4300150A (en) 1980-06-16 1980-06-16 Lateral double-diffused MOS transistor device

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JPS6338867B2 (en) 1988-08-02
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DE3122768C2 (en) 1987-12-10
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US4300150A (en) 1981-11-10
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FR2484707B1 (en) 1983-11-18
JPS5727071A (en) 1982-02-13

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