CA1167118A - Means for subdividing a baud period into multiple integration intervals to enhance digital message detection - Google Patents
Means for subdividing a baud period into multiple integration intervals to enhance digital message detectionInfo
- Publication number
- CA1167118A CA1167118A CA000344918A CA344918A CA1167118A CA 1167118 A CA1167118 A CA 1167118A CA 000344918 A CA000344918 A CA 000344918A CA 344918 A CA344918 A CA 344918A CA 1167118 A CA1167118 A CA 1167118A
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- Prior art keywords
- signal
- baud
- period
- intervals
- interval
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
- H04L27/2335—Demodulator circuits; Receiver circuits using non-coherent demodulation using temporal properties of the received signal
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Abstract of the Disclosure A carrier signal bearing digital data which varies a characteristic of the carrier signal during each baud period in a predetermined manner to identify the baud valve during the period is demodulated by subdividing each baud period into n intervals, converting the carrier signal character-istic to a DC signal which is integrated over each of the intervals and summing the integrated DC signal attained at the end of each interval with the integrated DC signals attained at the end of the previous n-l intervals.
Description
PATENT APPLICATION
ON
MEANS FOR SUBDIVIDING A BAUD PERIOD INTO MULTIPLE
BY
GEORGE C. CAGLE
Background of the Invention The invention herein pertains generally to digital communications and specifically to the detection of baud values where the data bauds are conveyed by an AC car-rier signal.
.
The transmission of digital data by varying some characteristic of~ an AC carrier signal, such as its phase or frequency, commonly referred to as phase shift and frequency shift keying, respectively, is widely practiced. Intrinsic to this mode of communications is the need to establish appropriate symbol timing at the receiver to identify the beginning and termination of each baud period (also known as symbol period), wherein a single unit of data comprising one or more data bits is transmitted, to permit the detection thereof. As is well documented in the technical literature, including ' .~:
: . .. . .
U.S. Patent No. 3,368,036 entitled "Demultiplexing and Detecting System for Predicted Wave Phase Pulse Data Transmission System" owned by the same assignee herein, a common technique to detect the value of each data baud is one known as "integrate and dump" wherein a DC signal is allowed to linearly vary over the baud period with a polarity which is a function of the carrier signal char-acteristic vis-a-vis some reference signal, thereby de-fining the baud value. The ef-ficacy of this detection technique is based on encompassing each integration period within the associated transmitted baud period so that it does not overlap into the next baud period, and consequently the need for developing appropriate symbol timing in the receiver~
One conventional method for affording appropriate symboL timing is to transmit along with the carrier sig-nal a pilot tone so that the receiver timing can be syn-chronized to that employed in the transmitter. In some communications media, however, this tone and its associ-ated equipment can be eliminated by employing a synchro-nizing signal which is intrin~ically available at both the transmitter and receiver. For example, in the evolving technical field of power lina communications for permitting electric utility companies to transmit communication signals over their distribution power lines to remotely control customer loads and monitor energy consumption, symbol timing can be derived from the 60 hertz power system itself since the transmitter and receiver are both connected thereto. Relying on the 60 hertz power signal as a synchronizing agent, however, - creates a problem in selecting the proper cycle during a given baud period as well as the point of the AC cycle to which to synchronize. Since the zero crossing of an AC signal is the most discernible and therefore most logical point to which to synchronize, this is the ~7~
01 _ 3 _ 03 common practice. However, ambiguities arise, the severity of 04 which is dependent on the baud rate. As an example, if one were 05 to transmit at a data rate of 60 baud/second, there would be one 06 60 hertz AC cycle and concomitantly two zero crossings per baud 07 between which to choose for synchronization. At a lower rate, 08 for instance 20 baud/second, there would be three 60 hertz AC
09 cycles and concomitantly six zero crossings per baud to contend with. If the integration period corresponding to an individual 11 baud were to be initiated on the wrong zero crossing, it then 12 would overlap into the consecutive baud period, rendering it 13 more difficult to accurately detect data by adding to or 14 subtracting from the integrated value which would have been obtained if the integration had been initiated at the right zero 16 crossing.
18 In two copending U.S. patent applications owned by the 19 same assignee as the instant one, two different techniques are disclosed for retrieving the digital data borne by a carrier 21 signal through the use of the zero crossings of a system ~C
22 signal. Application No. 015,672 entitled "Detection Means for 23 Providing Multiple Baud Values Per Individual Baud Period of a 24 Carrier Signal to Obviate Baud Timing Ambiguities", now U.S.
Patent No. 4,225,964 delineates an approach which entails 26 detecting digital data from the carrier signal for each of the 27 zero crossings that occur during a single baud period and then 28 selecting which of the multiple group of data is the correct 29 one, while the other application No. 015,014 entitled "Means for Deriving Baud Timing From an Available AC Signal", now U.S.
31 Patent No. 4,216,543 describes a technique for identifying the 32 correct zero crossing to which to synchronize the baud timing 33 or data detection. Both of the two foregoing techniques 34 engender the aforementioned integration process and are therefore prime candidates for any improvement in that process.
''' ~' .., 7~:~8 With the foregoing in mind, it is a primary object of the present invention to provide a new and improved integration technique for detecting digital data con-veyed by the varying characteristic of a carrier signal I-t is a urther object of the present invention to provide such a new and improved integration technique for use in conjunction with an AC signal having multiple zero crossings during each baucl period that can be used for baud timing synchronization.
It is still a further object of the presen~ inven-tion to provide such a new and improved integration technique which affords speed of operation and minimizes requisite hardware.
The foregoing objects, as well as others, and the means by which they are achieved through the present invention may best be appreciated by referring to the Detailed Description of the Preferred Embodiment which follows together with the appended drawings.
Summary of the Inven lon In accordance with the stated objects, the invention herein develops the baud timing for demodulating a carrier signal bearing digital data which varies a char-acteristic of the carrier signal during each baud period in a predetermined manner to identify the baud value during the period by subdividing each baud period into n intervals, converting the carrier signal characteristic to a DC signal which is integrated over each of the intervals, and summing the integrated DC signal attained at the end of each interval with the integrated DC
signals attained at the end of the previous n-l inter-vals. When the transmitted baud period is synchronized 01 5 _ 03 to the zero crossing of an available systemwide AC signal, such 04 as the electric power system frequency, n is made equal to the 05 number of zero crossings which occur during a single baud 06 period and each integration interval is initiated at a zero 07 crossing. The multiple (n~ integrals obtained during each baud 08 period may then be used to obtain multiple baud values from 09 which to select the transmitted digital data or to identify the correct zero crossing for synchronization to detect the data 11 which, as mentioned previously, are the subjects of the 12 aforenoted U.S. Patents, Nos. 4,225,964 and 4,216,543 13 respectively. The integration intervals are efficiently 14 provided -through the use of a pair oE integrators with each integrating the DC signal during alternate intervals while the 16 other is initialized to a predetermined state preparatory to an 17 integration cycle.
19 ~ Brief Description of the Drawings _ ~, . . _ Figure 1 consists of waveforms expository of the 21 invention.
23 Figure 2 depicts the integration and associated timing 24 circuitry of the invention.
26 Figure 3 depicts the digital components of the 27 invention for storing and combining the various digital signals 28 to derive the multiple baud values for the individual data 29 bauds.
31 Figure 4 consists of timing waveforms for use in 32 conjunction with Figures 2 and 3 to facilitate an understanding 33 of the invention.
0~
03 Figure 5 shows circuitry supplementary to that of 04 Figure 2 for afEording full-wave integration rather than 05 half-wave in the detection process.
07 Detailed Description of the Preferred Embodiment 08 Only for purposes of e~:emplification, the subject 09 invention will be described in connection with a commercial communications system developed by the assignee herein known as 11 KINEPLEX~ which entails transmitting digital data via a carrier 12 signal employing 4 ~ differential phase keying (DPSK) so that 13 two bits of data correspond to eac:h baud period and the phase 14 of the carrier signal acts as a reference to the consecutive baud period. This system is described at length in V.S. Patent 16 3,368,036, previously alluded to, and therefore will be treated 17 only briefly herein as is necesary to afford an understanding ~8 of the subject invention. Also, once again only for exemplar~
19 purposes, the invention will be described in conjunction with one of its specific applications, namely the acquisition of 21 multiple data baud values per baud period from which to select 22 the data specifically addressed by the aforenoted patent 23 entitled "Detection Means For Providing Multiple Baud Values 24 Per Individual Baud Period of a Carrier Signal to Obviate Baud Timing Ambiguities".
27 As delineated in the '036 patent, the phase angle of a 28 carrier signal is advanced 45 or some odd multiple thereof 29 during each baud period from the previous baud period, with the change being dependent on which one of the four combinations of 31 two binary data bits is engendered in the digital information 32 to be transmitted during that period. The data contained in 33 the baud period is detected at the receiver by mixing with the 34 carrier signal two AC signals of like frequency equal to that of 36 ~ Trade Mark . .
the carrier, but differing in phase angle by 90, which produces two output signals having respective DC
components whose polarities are a function of the sine of the carrier phase angle, when referenced to some S fixed angle for one of the signals (quadrature compo-nent) and its cosine for the other signal (in phase com-ponent). These signals are separately integrated over the baud period, at the end o~ which they are combined with their counterparts for the previous baud period to yield the in phase (cosine) ancl quadrature phase (sine) components of the phase difference in the carrier signal between two consecutive baud periods which then defines the two data bit values by viture of the respective trigonometric signs.
The foregoing is represented as the first integra-tion waveform (a) in Figure l designated prior art.
~his waveform (a) corresponds to only one of the DC com-ponents being integrated and it is to be realized that the second component needed to define a baud comprising two bits is not shown since it would not contribute to the understanding of the reader. Assuming that the sym-bol timing was derived from waveform (b) designated Fs for the system frequency AC signal, it will be observed that each baud period, and consequently each integration period, corresponds to three full cycles of Fs.
Specifically, Fs could be a system frequency such as found on the 60 hertæ electric power system in the United States (limited in amplitude so as to produce the depicted square wave) with three cycles thereof then representing a data ra-te of 20 baud/second. Further assuming that a data period designated baud period one was transmitted coincident with the first zero crossing of Fs, at point A, the detector in the receiver would properly begin integrating at point A and terminate at point A' to afford an integrated value equal to kT where k canl be any real numbler and T is the baud period (Baud Rate or 50 ms = 2~ herein). Now, through error, assume that rather than the first zero crossing shown for Fs at point A in waveform b, the third zero cross-ing commencing with the second cycle designated point B,is chosen on which to begin the integration process. In this case, the integrated signal would linearly increase to a value of k(2/3T) at point A' and then decrease to a value of kT/3 at B' ~assuming the value for baud period two would result in a negative DC trigonometrlc compo-nent) because of the overlap of the integration opera-tion for baud period one into baud period two. Thus, instead of generating the proper value of kT for baud period one, kT/3 would be realized. Even though it is the polarity of tbe integrated value which determines the baud value, deviations in the magnitude thereof ren der the detection process more difficult to effectuate and, in fact, can introduce data errors created by a degradation in signal/noise ration for the integrated signal. As an example, were the integration period for baud period one to begin on the fifth zero crossing of Fs at point C, tbe integrated value attained would be -kT/3, clearly erroneous because of the negative, rather than positive sign.
The subject invention contributes to obviating the foregoing problem by subdividi~g the baud period into n intervals, such as six shown in waveform ~c) of Figure 1, for the system frequency signal Fs having six zero crossings per baud period. Rather than integrate over the entire period as represented by waveform ~a), the integration process is separately applied to each of the n intervals wherein each integration is initiated at the beginning of the interval- and terminated at its end.
Thus, as shown by waveform (c), six separate integra-tions are performed during baud period one, rather than ~ ~ ~` 7~
g the single one of waveform (a). The integrated value attained at the end of each interval is then added to the corresponding values for the preceding n-l intervals or five in in the example of waveform (c). Thus, at the end of interval 6 its value is added to that for inter-vals 1-5 to yield kT. Similarly, the integrated value attained at the end of interval 7 is added to the values corresponding to intervals 2 6. The foregoing inte-grated value summation is repeated at the end oE each of the subsequent intervals by adding the integrated value attained to the previous five intervals. Consequently, each baud period gives rise to n or in the depicted example six integrated value summations indicative of the baud value rather than the single value of waveform (a). ~hese six values can then be arithmetically pro-cessed in various ways to optimize the validity of the detected data. For example, a very simple preferred way to be described hereinafter merely entails storing the n baud values in n registers on a cyclical basis and then selecting the first recognizable digital message via predetermined bit patterns.
It is recogni~ed that the multiple integrals per baud period could be generated in conventional fashion by sequentially initiating a single integration cycle extending over an entire baud period at each AC signal zero crossing. ~owever, as will be appreciated herein-after, this would require much more integration hardware than the present invention, necessitating six integra-tion circuits rather than the two to be described forthe instant case. Although the copious hardware could be eliminated by monitoring a single zero crossing per baud period from which to generate the integrated DC
signai, this results in the penalty of extended data time periods for obtaining baud synchronization since n baud periods would then have to transpire to permit all '7~
n æero crossings to be analyzed (e.g. looking at the first zero crossing of Fs in baud period one, the eighth zero crossing of Fs in baud period two~ etc.).
When an absolute reference frequency is employed, the integration process in performed after mixing the carrier signal with the reference frequency so that the polarity of each integrated value and consequently inte-grated value summation automatically determines the baud value. ~owever, when the modulation is not predicated on an absolute reference, but rather DPSK where the reference signal during each baud period is derived from the carrier signal ~or the immediately preceding baud period, the carrier signal phase in the detected baud period is relative and therefore the integrated value summation attained at the end of each interval must be compared wit~ its counterpart for the preceding period.
Accordingly, the summations are stored for an additional period of time subsequent to their development so that they can be used as references against which to compare successive summations. For example, in deriving the baud value corresponding to interval 12, the integra~ed value summation for the six intervals 7-12 is compared with that for tbe six intervals 1-6. Similarly, the baud value corresponding to interval 13 is derived by comparing the integrated value summation for the six intervals 8-13 with that for the six intervals 2-7.
Referring now to Figure 2, the preferred apparatus for providing the individual integration values will be described. As shown therein, the apparatus designated generally by the reference numeral 10, receives the AC
carrier signal Fc in which the data bauds are conveyed and the system frequency signal Fs over lead 12 which would be connected to the electric power system where the carrier signal Fc was transmitted ~hereover and 7~
Fs corresponded to the 60 hertz power line frequency.
Fc is passed through a bandpass filter 14, whose band-pass is centered about the carrier frequency, and then amplified by amplifier 16 whose output is then the pure S carrier signal Fc defined as Sin ~ct~e) where~c =
ON
MEANS FOR SUBDIVIDING A BAUD PERIOD INTO MULTIPLE
BY
GEORGE C. CAGLE
Background of the Invention The invention herein pertains generally to digital communications and specifically to the detection of baud values where the data bauds are conveyed by an AC car-rier signal.
.
The transmission of digital data by varying some characteristic of~ an AC carrier signal, such as its phase or frequency, commonly referred to as phase shift and frequency shift keying, respectively, is widely practiced. Intrinsic to this mode of communications is the need to establish appropriate symbol timing at the receiver to identify the beginning and termination of each baud period (also known as symbol period), wherein a single unit of data comprising one or more data bits is transmitted, to permit the detection thereof. As is well documented in the technical literature, including ' .~:
: . .. . .
U.S. Patent No. 3,368,036 entitled "Demultiplexing and Detecting System for Predicted Wave Phase Pulse Data Transmission System" owned by the same assignee herein, a common technique to detect the value of each data baud is one known as "integrate and dump" wherein a DC signal is allowed to linearly vary over the baud period with a polarity which is a function of the carrier signal char-acteristic vis-a-vis some reference signal, thereby de-fining the baud value. The ef-ficacy of this detection technique is based on encompassing each integration period within the associated transmitted baud period so that it does not overlap into the next baud period, and consequently the need for developing appropriate symbol timing in the receiver~
One conventional method for affording appropriate symboL timing is to transmit along with the carrier sig-nal a pilot tone so that the receiver timing can be syn-chronized to that employed in the transmitter. In some communications media, however, this tone and its associ-ated equipment can be eliminated by employing a synchro-nizing signal which is intrin~ically available at both the transmitter and receiver. For example, in the evolving technical field of power lina communications for permitting electric utility companies to transmit communication signals over their distribution power lines to remotely control customer loads and monitor energy consumption, symbol timing can be derived from the 60 hertz power system itself since the transmitter and receiver are both connected thereto. Relying on the 60 hertz power signal as a synchronizing agent, however, - creates a problem in selecting the proper cycle during a given baud period as well as the point of the AC cycle to which to synchronize. Since the zero crossing of an AC signal is the most discernible and therefore most logical point to which to synchronize, this is the ~7~
01 _ 3 _ 03 common practice. However, ambiguities arise, the severity of 04 which is dependent on the baud rate. As an example, if one were 05 to transmit at a data rate of 60 baud/second, there would be one 06 60 hertz AC cycle and concomitantly two zero crossings per baud 07 between which to choose for synchronization. At a lower rate, 08 for instance 20 baud/second, there would be three 60 hertz AC
09 cycles and concomitantly six zero crossings per baud to contend with. If the integration period corresponding to an individual 11 baud were to be initiated on the wrong zero crossing, it then 12 would overlap into the consecutive baud period, rendering it 13 more difficult to accurately detect data by adding to or 14 subtracting from the integrated value which would have been obtained if the integration had been initiated at the right zero 16 crossing.
18 In two copending U.S. patent applications owned by the 19 same assignee as the instant one, two different techniques are disclosed for retrieving the digital data borne by a carrier 21 signal through the use of the zero crossings of a system ~C
22 signal. Application No. 015,672 entitled "Detection Means for 23 Providing Multiple Baud Values Per Individual Baud Period of a 24 Carrier Signal to Obviate Baud Timing Ambiguities", now U.S.
Patent No. 4,225,964 delineates an approach which entails 26 detecting digital data from the carrier signal for each of the 27 zero crossings that occur during a single baud period and then 28 selecting which of the multiple group of data is the correct 29 one, while the other application No. 015,014 entitled "Means for Deriving Baud Timing From an Available AC Signal", now U.S.
31 Patent No. 4,216,543 describes a technique for identifying the 32 correct zero crossing to which to synchronize the baud timing 33 or data detection. Both of the two foregoing techniques 34 engender the aforementioned integration process and are therefore prime candidates for any improvement in that process.
''' ~' .., 7~:~8 With the foregoing in mind, it is a primary object of the present invention to provide a new and improved integration technique for detecting digital data con-veyed by the varying characteristic of a carrier signal I-t is a urther object of the present invention to provide such a new and improved integration technique for use in conjunction with an AC signal having multiple zero crossings during each baucl period that can be used for baud timing synchronization.
It is still a further object of the presen~ inven-tion to provide such a new and improved integration technique which affords speed of operation and minimizes requisite hardware.
The foregoing objects, as well as others, and the means by which they are achieved through the present invention may best be appreciated by referring to the Detailed Description of the Preferred Embodiment which follows together with the appended drawings.
Summary of the Inven lon In accordance with the stated objects, the invention herein develops the baud timing for demodulating a carrier signal bearing digital data which varies a char-acteristic of the carrier signal during each baud period in a predetermined manner to identify the baud value during the period by subdividing each baud period into n intervals, converting the carrier signal characteristic to a DC signal which is integrated over each of the intervals, and summing the integrated DC signal attained at the end of each interval with the integrated DC
signals attained at the end of the previous n-l inter-vals. When the transmitted baud period is synchronized 01 5 _ 03 to the zero crossing of an available systemwide AC signal, such 04 as the electric power system frequency, n is made equal to the 05 number of zero crossings which occur during a single baud 06 period and each integration interval is initiated at a zero 07 crossing. The multiple (n~ integrals obtained during each baud 08 period may then be used to obtain multiple baud values from 09 which to select the transmitted digital data or to identify the correct zero crossing for synchronization to detect the data 11 which, as mentioned previously, are the subjects of the 12 aforenoted U.S. Patents, Nos. 4,225,964 and 4,216,543 13 respectively. The integration intervals are efficiently 14 provided -through the use of a pair oE integrators with each integrating the DC signal during alternate intervals while the 16 other is initialized to a predetermined state preparatory to an 17 integration cycle.
19 ~ Brief Description of the Drawings _ ~, . . _ Figure 1 consists of waveforms expository of the 21 invention.
23 Figure 2 depicts the integration and associated timing 24 circuitry of the invention.
26 Figure 3 depicts the digital components of the 27 invention for storing and combining the various digital signals 28 to derive the multiple baud values for the individual data 29 bauds.
31 Figure 4 consists of timing waveforms for use in 32 conjunction with Figures 2 and 3 to facilitate an understanding 33 of the invention.
0~
03 Figure 5 shows circuitry supplementary to that of 04 Figure 2 for afEording full-wave integration rather than 05 half-wave in the detection process.
07 Detailed Description of the Preferred Embodiment 08 Only for purposes of e~:emplification, the subject 09 invention will be described in connection with a commercial communications system developed by the assignee herein known as 11 KINEPLEX~ which entails transmitting digital data via a carrier 12 signal employing 4 ~ differential phase keying (DPSK) so that 13 two bits of data correspond to eac:h baud period and the phase 14 of the carrier signal acts as a reference to the consecutive baud period. This system is described at length in V.S. Patent 16 3,368,036, previously alluded to, and therefore will be treated 17 only briefly herein as is necesary to afford an understanding ~8 of the subject invention. Also, once again only for exemplar~
19 purposes, the invention will be described in conjunction with one of its specific applications, namely the acquisition of 21 multiple data baud values per baud period from which to select 22 the data specifically addressed by the aforenoted patent 23 entitled "Detection Means For Providing Multiple Baud Values 24 Per Individual Baud Period of a Carrier Signal to Obviate Baud Timing Ambiguities".
27 As delineated in the '036 patent, the phase angle of a 28 carrier signal is advanced 45 or some odd multiple thereof 29 during each baud period from the previous baud period, with the change being dependent on which one of the four combinations of 31 two binary data bits is engendered in the digital information 32 to be transmitted during that period. The data contained in 33 the baud period is detected at the receiver by mixing with the 34 carrier signal two AC signals of like frequency equal to that of 36 ~ Trade Mark . .
the carrier, but differing in phase angle by 90, which produces two output signals having respective DC
components whose polarities are a function of the sine of the carrier phase angle, when referenced to some S fixed angle for one of the signals (quadrature compo-nent) and its cosine for the other signal (in phase com-ponent). These signals are separately integrated over the baud period, at the end o~ which they are combined with their counterparts for the previous baud period to yield the in phase (cosine) ancl quadrature phase (sine) components of the phase difference in the carrier signal between two consecutive baud periods which then defines the two data bit values by viture of the respective trigonometric signs.
The foregoing is represented as the first integra-tion waveform (a) in Figure l designated prior art.
~his waveform (a) corresponds to only one of the DC com-ponents being integrated and it is to be realized that the second component needed to define a baud comprising two bits is not shown since it would not contribute to the understanding of the reader. Assuming that the sym-bol timing was derived from waveform (b) designated Fs for the system frequency AC signal, it will be observed that each baud period, and consequently each integration period, corresponds to three full cycles of Fs.
Specifically, Fs could be a system frequency such as found on the 60 hertæ electric power system in the United States (limited in amplitude so as to produce the depicted square wave) with three cycles thereof then representing a data ra-te of 20 baud/second. Further assuming that a data period designated baud period one was transmitted coincident with the first zero crossing of Fs, at point A, the detector in the receiver would properly begin integrating at point A and terminate at point A' to afford an integrated value equal to kT where k canl be any real numbler and T is the baud period (Baud Rate or 50 ms = 2~ herein). Now, through error, assume that rather than the first zero crossing shown for Fs at point A in waveform b, the third zero cross-ing commencing with the second cycle designated point B,is chosen on which to begin the integration process. In this case, the integrated signal would linearly increase to a value of k(2/3T) at point A' and then decrease to a value of kT/3 at B' ~assuming the value for baud period two would result in a negative DC trigonometrlc compo-nent) because of the overlap of the integration opera-tion for baud period one into baud period two. Thus, instead of generating the proper value of kT for baud period one, kT/3 would be realized. Even though it is the polarity of tbe integrated value which determines the baud value, deviations in the magnitude thereof ren der the detection process more difficult to effectuate and, in fact, can introduce data errors created by a degradation in signal/noise ration for the integrated signal. As an example, were the integration period for baud period one to begin on the fifth zero crossing of Fs at point C, tbe integrated value attained would be -kT/3, clearly erroneous because of the negative, rather than positive sign.
The subject invention contributes to obviating the foregoing problem by subdividi~g the baud period into n intervals, such as six shown in waveform ~c) of Figure 1, for the system frequency signal Fs having six zero crossings per baud period. Rather than integrate over the entire period as represented by waveform ~a), the integration process is separately applied to each of the n intervals wherein each integration is initiated at the beginning of the interval- and terminated at its end.
Thus, as shown by waveform (c), six separate integra-tions are performed during baud period one, rather than ~ ~ ~` 7~
g the single one of waveform (a). The integrated value attained at the end of each interval is then added to the corresponding values for the preceding n-l intervals or five in in the example of waveform (c). Thus, at the end of interval 6 its value is added to that for inter-vals 1-5 to yield kT. Similarly, the integrated value attained at the end of interval 7 is added to the values corresponding to intervals 2 6. The foregoing inte-grated value summation is repeated at the end oE each of the subsequent intervals by adding the integrated value attained to the previous five intervals. Consequently, each baud period gives rise to n or in the depicted example six integrated value summations indicative of the baud value rather than the single value of waveform (a). ~hese six values can then be arithmetically pro-cessed in various ways to optimize the validity of the detected data. For example, a very simple preferred way to be described hereinafter merely entails storing the n baud values in n registers on a cyclical basis and then selecting the first recognizable digital message via predetermined bit patterns.
It is recogni~ed that the multiple integrals per baud period could be generated in conventional fashion by sequentially initiating a single integration cycle extending over an entire baud period at each AC signal zero crossing. ~owever, as will be appreciated herein-after, this would require much more integration hardware than the present invention, necessitating six integra-tion circuits rather than the two to be described forthe instant case. Although the copious hardware could be eliminated by monitoring a single zero crossing per baud period from which to generate the integrated DC
signai, this results in the penalty of extended data time periods for obtaining baud synchronization since n baud periods would then have to transpire to permit all '7~
n æero crossings to be analyzed (e.g. looking at the first zero crossing of Fs in baud period one, the eighth zero crossing of Fs in baud period two~ etc.).
When an absolute reference frequency is employed, the integration process in performed after mixing the carrier signal with the reference frequency so that the polarity of each integrated value and consequently inte-grated value summation automatically determines the baud value. ~owever, when the modulation is not predicated on an absolute reference, but rather DPSK where the reference signal during each baud period is derived from the carrier signal ~or the immediately preceding baud period, the carrier signal phase in the detected baud period is relative and therefore the integrated value summation attained at the end of each interval must be compared wit~ its counterpart for the preceding period.
Accordingly, the summations are stored for an additional period of time subsequent to their development so that they can be used as references against which to compare successive summations. For example, in deriving the baud value corresponding to interval 12, the integra~ed value summation for the six intervals 7-12 is compared with that for tbe six intervals 1-6. Similarly, the baud value corresponding to interval 13 is derived by comparing the integrated value summation for the six intervals 8-13 with that for the six intervals 2-7.
Referring now to Figure 2, the preferred apparatus for providing the individual integration values will be described. As shown therein, the apparatus designated generally by the reference numeral 10, receives the AC
carrier signal Fc in which the data bauds are conveyed and the system frequency signal Fs over lead 12 which would be connected to the electric power system where the carrier signal Fc was transmitted ~hereover and 7~
Fs corresponded to the 60 hertz power line frequency.
Fc is passed through a bandpass filter 14, whose band-pass is centered about the carrier frequency, and then amplified by amplifier 16 whose output is then the pure S carrier signal Fc defined as Sin ~ct~e) where~c =
2~ fc with fc being the carrier frequency and ~ the phase angle, the characteristic of the carrier signal which defines the baud value. In other modulation schemes, the characteristic could just as well be either the frequency or amplitude of the carrier signal. The output of amplifier 16 is connected to a pair of inte grating circuits 18 and 20, each of which comprises a pair of operational amplifiers, 22 and 24 for circuit 18, and 26 and 28 for integrating circuit 20. These four operational amplifiers 22-28 are arranged exactly the same so as to function as integrators and, as such, respectively comprise four capacitors 30-36 inter-connecting their respective outputs with their inverting (-) inputs, ~our resistors 38~44 connecting their non-inverting (+) inputs to ground and symbolically de-picted four switches 44-50 respectively connected across capacitors 30-36. The output of amplifier 16, Fc is applied to the inverting inputs of amplifiers 22-28 through series connected resistors 52 and 54, 56 and 58, 60 and 62, and 64-66, respectively. The interconnection point of each pair of the foregoing series resistors is connected to ground through switches 68-74, respectively associated with amplifiers 22-28. These switches, which are depicted symbolically, would normally be implemented through a solid state design.
As is well known, cyclically controlling by a square wave the closure of a switch such as 68 which is con-nected to a signal path in synchronous detection pro-duces the product of the signal entering the path andthe Fourier sinusoidal components of the square wave at ' '7 the output of the switch. Consequently, applying to switch 68 a square wave signal whose fundamental component is cos (Wct+QR) where ~C=2~fC~ c being the carrier frequency, and ~R is some fixed reference phase angle, S produces a siGnal to the inverting input of amplifier 22 equal to sin (~ct+~) cos (~ct~R) which has a DC component that is proportional to sin (9-~R) [which in this case is equal to sin (a-aR) since the sinusoidal signals are assumed to have unity amplitude]. This result is clearly described in the '036 patent, previously referred to, ln connection with Figure 1 thereof, where it will be recognized that mixer 18 for producing the requisite product has been preferably supplanted by electronic switch 68 of the subject invention as shown in Figure 2 herein. None of the other products of the carrier signal and Fourier componetns produce a DC signal and are therefore of no interest. With switch 44 open and switch 6~
operational in accordance with the control square wave signal represented by its fundamental component cos ~JCt+~R), applied thereto, the DC voltage applied to the inverting input of amplifier 22 will cause the voltage developed across capaciter 30 to linearly vary, thus providing at the output of amplifier 22 the integrated value of the DC component with a like polarity. Since switch 68 is closed during every other half cycle for Fc, which time am~lifier 22 cannot integra~e, this half-wave integra-tion process does not produce a smooth ramp as shown by waveform (c) of Figure 1 but rather a sequence of ramps separated by steps. This, of course, only affects the integrated value attained at the end of the integration interval and not the integration principle. If a smooth ramp over the full integration interval is desired, then the circuitry of Figure 2 can be supplemented with that of Figure 5 to be exaplained shortly. If the integration period is made equal tG one of the ,:
intervals corresponding to waveform (c) of Figure 1, the value attained at the end of the integration interval will be equal to KT/12 sin (~ ). By going through the same steps as the foregoin~, it will be readily seen that the application to switch 70 of a control square wave signal whose fundamental component is sin (~lct~R) will produce at the output of amplifier 24 at the end of an integration interval KT/12 cos ~ R) so long as switch 46 remains open for the interval.
When an absolute reference signal separate and apart from the carrier signal is employed such as in absolute modulation schemes, the control signals sin (~ct+~R) and cos (~ct+~R) would be derived directly from the reference signal so that ~R would normally be 0 and the signs of sin (~) and cos (~) would automatically define the baud value. However, when DPSK is employed such as herein, the baud value is determined by elimin-ating 6 ~ and developing the sin and cos of (~2_61), where the subscript 2 corresponds to the baud period being detected and the subscript corresponds to the preceding baud period. This will be explained later on.
In a similar fashion to the foregoing, cos (~t+6R) and sin (~ct~R) are applied respectively to-switches 72 and 74 to produce at the output~ of amplifiers 26 and 28 KT/12 -sin (~-~R) and KT/12 cos (~-~R) for also defining the carrier phase angle during some interval (vis-a-vis a fixed reference phase angle ~ R). While one of the integrating circuits 18 and 20 is integrating, the other one is initialized (but only after an analog to digital conversion is performed as explained hereinafter) to prepare it for its integrating interval by discharging the associated capacitors through the associaked '6'~7~
switches connected thereacross. For example, if switches 44 and 46 were open during interval 1 for wave form (c) of Figure l, while switches 68 and 70 were operational, integrating circuit 18 would in fact be integrating, during which time switches 48 and 50 would be closed to discharge their respective capacitors 34 and 36 to prepare integrating circuit 20 for its integration cycle during integration interval two. Of course, during interval two, switches 44 and 46 would be closed to permit their respective capacitors 30 and 32 to discharge so as to prepare integrating circuit 18 for its next integrating cycle during interval three. Thus, it is seen that integrating circuit 18 integrates during the odd numbered intervals and discharges during the even numbered intervals, while integrating circuit 20 conversaly integrates during the even numbered intervals and discharges during the odd numbered intervals.
The foregoing switch operations are reflected in the timing waveforms depicted in Figure 4 wherein the Eirst four waveforms are associated with con-trolling the oper-ation of switches 68-74, respectively, and the next two waveEorms control switches 44 together with 46 and 48 together with 50, respectively. A high level signal for the waveforms of Figure 4 corresponds to a switch being open, while a low level signifies that the switch is closed. The waveforms of Figure 4 are generated from the system frequency signal Fs by first passing it through a low-pass filter 76 shown in Figure 2 which eliminates unwanted frequencies such as the carrier signal Fc and then, through a limiter 78, to provide an output signal which is a square wave whose frequency and phase are consonant with Fs. The output of limiter 78 is applied to a phase lock loop circuit 80 to produce at its output a square wave whose frequency is four times that of the carrier signal frequency Fc . .
~7~
which i5 locked together with the phase to the system frequency Fs. Thus as Fs varies in frequency, as it may do so under adverse conditions, so does the fre-quency 4 fc at the output of phase lock loop circuit 80. The output of phase lock loop circuit 80 is applied to a divide by 4 circuit 82 having two outputs which have a frequency equal to that of the carrier signal frequency fc and a phase angle ~R wi.th reference thereto, and which are reprec;ented mathematically only by their respective fundament:al sinusoidal components.
The two outputs have a phase angle difference of 90 so that one constitutes a sine function with the other constituting a cosine function. The cosine output of divide by 4 circuit 82 is connected as a first input to an AND gate 84 having a second input from the output of limiter 78 so that the gate is enabled to pass the square wave to its output s68 during the first inte-gration interval f Fs shown in Figure 4, as well as all successive odd integration intervals. During these odd integration intervals when AND gate 84 is enabled, the signal s68 is applied to switch 68 to cause it to synchronously open and close which as already mentioned is equivalent to the mixing function of mixer 18 of Figure 1 of the '036 patent previously alluded to. Con-sequently, the product of sin (~ct+~) and cos(~ct~R) is formed at the interconnection of the switch 68 with resistors 52 and 54. During this time it is to be noted that switches 44 and 46 are open to per-mit their respective capacitors 30 and 32 to linearly build up voltage during the integration interval. Since switch 68 is closed half the time during the integration interval, which inhibits the capacitor from receiving any charging current, as mentioned earlier the integra-tion waveform would not be a smooth ramp as depicted in Figure l, but rather a sequence of little ramps (when switch 68 is open during the high level half cycles of 7~
the square wave) connected by flat portions when switch 68 is closed (during low level portions of the square wave s68).
If integration throughout an integration interval is desired, for example to generate a high integration signal, then each of the operational amplifiers 22~28 can be supplemented with additional ci~cuitry as shown in Figure S in connectlon with operational amplifier 22. It will be seen therein that the mixing and inte-grating functions have been totally separated by con-necting the synchronous switch 68 to the interconnection point of a pair of resistors 86 and 88, with resistor 88 being connected to the noninverting input of another operational amplifier 90. The carrier signal Fc is applied to the noninverting input of operational ampli-fier 90 through the series resistors 86 and 88 as well as to the inverting input via a resistor 92. With another resistor 94 interconnecting the output and the inverting input of operational amplifier 90, a full-wave mixer with a gain of one is provided, by making resis-tors 92 and 94 the same value, and 86 and 88 as well.
So long as a new switch 97, connected to the inter-connection of resistors 52 and 54 associated with opera-tional amplifier 22, is left open during the full inte-gration interval, a smooth linear ramp will be obtained at the output of amplifier 22 without any steps in the waveform.
At the end of the first integration interval, the output of operational amplifier 22 is the integrated value of the DC component for the product of the sin (~ct+~l) and cos (~ct~gR), namely KT sin ~ R) In a similar fashion it will be seen that the output of operational amplifier 24 at this time is KT/12 cos (6l_~R) because of the application to , 7.~
switch 70 of sin (ll!ct+ ~) via an AND gate 96 having a secojnd input derived from the output of limiter 78.
Furthermore, it will be seen that the outputs of opera-tional amplifiers 26 and 28 at the end of the second integration interval are respectively 12 sin (~2- ~) and 12 cos (~2-~R) by virtue of the application of cos (~ct+~R) to switch 72 via an AND
gate 98 and sin (~ct+~R) to switch 74 via an AND
gate 100. Both AND gates 98 and 100 have a second input which is derived from the output of limiter 78 after first inverting the signal through inverter lC2. Con-sequently, these AND gates are enabled to pass their respective square waves during the eve~ integratio~
intervals associated with the system frequency signal Fs.
The outputs of amplifiers 22-28 are connected to an analo~/digital (A/D) converter 104 via four individual switches 106-112 respectively associated therewith. The analog integrated value outputs of amplifiers 22-28 are thus converted to digital equivalents at the output of A/D converter 104 on bus 113 (which prefera~ly comprises multiple leads for parallel bit operation) in multiplex fashion by sequentially closing switches 106-112. For example, switch 106 is closed upon the termination of the first integration interval by a low level signal generated at the output of a one shot multivibrator 114 which is triggered by the falling edge of the output of - limiter 78, namely Fs. After sufficient time has transpired for the conversion to be efected, switch 106 is opened at the end of the one shot period and switch 108 is closed by the same output from one shot 114 via a delay circuit 116. Following the A/D conversions for the outputs of amplifiers 22 and 24, their respective capacitors 30 and 32 are discharged by the closure o the switches 44 and 46. The signal for this operation is derived by triggering a one shot multivibrator 118 by the falling edge output from delay circuit 116. In similar fashion, switch 110 is closed during each odd integration interval, after its associated integrating circuit 20 even integration interval, by the output of a one shot multivibrator 120, which is triggered by the rising edge of the output of limiter 78. Switch 112 is thereafter closed by first passing the output of one shot 120 through a delay circuit 122. Switches 48 and 50 are closed to discharge their respective capacitors 34 and 36 through a one shot multivibrator 124 which is activated by the falling edge of the output of delay circuit 122. The timing wave ~orms corresponding to the foregoing discharge and conversion operations are shown in Figure 4.
As shown in Figure 3, the storage circuitry for retaining the digital integrated value outputs of A/D
converter 104 on lead 113 comprises one group of six series connected registers 126 corresponding to the quadrature (sine) component, and another set of six series connected registers 128 corresponding to the in phase (cosine) compo~ent. Each time a new integrated digital value Ic (the subscript c denoting current interval) is generated at the output of A/D converter 104, it is stored in the first register of a register group, the quadrature component being placed into reg-ister 130 of group 126, and the in phase component into register 132 of group 128. Just prior thereto the value in each register is shifted to the next register in the series chain so that the value that had been stored in register 130 is passed to register 134 and likewise, the value that had been stored in register 132 is passed to the next register (not shown) in the chain for group 128. The values stored in the last registers of the register groups, namely 138 for group 126 and 140 for group 128, are no longer retained when supplanted by the ilB
new value received from the preceding register. The foregoing is represented by the notation Ic 1 through c 5 for the registers in groups 126 and 128. The registers of register group 126 corresponding to the quadrature component are clocked by the output of a one shot multivibrator 131, shown in Figure 2, which is triggered at the end of an A/D conversion operation by the lagging edge of the A/D control pulses (Figure 4 waveform~ for controlling quadrature component switches 106 and 110 via an OR gate 133 whose inputs are con-nected to the outputs of one shot multivibrators 114 and 120. Likewise, the registers of register group 128 cor-responding to the in phase component are clocked by the output of a one shot muLtivibrator 135 by the lagging edge of the A/D control pulses for controlling in phase component switches 108 and 112 via an OR gate 135 whose inputs are connected to the outputs of delay circuits 116 and 122.
Upon receipt of each new integrated digital value Ic, the outputs of the registers in each register group 126 and 128 constituting the corresponding inte-grated values for the previous five intervals tc-l to c-5) are digitally summed by respective digital adders 25 140 and 142. The digital integrated value summations of adders 140 and 142, denoted ~ ~ , are then applied to registers 144 and 146 respe~ctl~vèly, each of which is the first register of a group of seven series connected registers 148 and 150 respectively. As with the reg-30 ister group~ 126 and 128, each register in groups 148 and 150 passes the digital value stored therein to the next succeeding register prior to receiving the digital stored value in the preceding register under the clock output of one shot multivibrators 131 and 135, respec-tively. Since there are seven registers in each group 148 and 150, ~he summations of 5iX integrated values ~;'7~
entered into the first registers 144 and 14~ are eventu-ally stored in the last registers 152 and 154 of groups 148 and 150 respectively, six integration intervals later. Also, since differential phase shift keying en-tails comparing each baud period wi-th the previous baud period acting as a reference, and since six integration intervals constitute a full baud period cycle herein, the output of register 144, which is proportional to sin (~2- ~)~ is compared with the output oE register 152, which is proportional to sin (G1-~R) where, the subscript 2 denotes a current summation period and the subscript 1 denotes the preceding summation period.
Similarly, the outputs of registers 146 and 154, respec-tively, proportional to cos (~2 ~R) and cos (~ ) are employed in the comparison to eliminate the reference angle ~R and obtain the phase angle ad-~2 1 in consecutive baud period Thus, as delineated in the '036 patent, the outputs of registers 144 and 152 are multiplied in digital multi-plier 156 and summed with the product of the outputs ofregisters 146 and 154 appearing at the output of digital multiplier 158 in digital adder 160 to render the term cos (B2 el~- The term sin (~ 1) is obtained by adding the product of the outputs of registers 152 and 146, available at the output of digital multiplier 162, to the negative value of the product of the outputs of registers 144 and 154, available at the output of digital multiplier 164, in digital adder 166. The signs of the output signals for-adders 160 and 166 define the two bit values engendered by the baud as represented by the summation of integrated values corresponding to the six integration intervals, appearing serially at the output of decoder 168 with the designated format. Since there are six such intervals during each baud period it is readily apparent that there will be six values of baud data, each consisting of two bits, for selecting the 7~
proper baud value. These six values are stored in a group of six registers 170 by cyclical sequential appli-cation thereto under control of a register enable cir-cuit 172 having a count of six which is triggered from the output at limiter 78 once during each integration interval. During each interva] the two data bits defin-ing the baud value are serially clocked from the output of decoder 168 into the enabled register 170 in their proper order. The two clock pulses for entering the two serial bits in each of the registers 170 can simply be provided from register enable circuit 172 through a ring counter having a count of six whose output leads are individually connected to the registers 170 via a pair of one shot multivibrators for each lead (not shown).
After two bits are entered in the last register 170, such as the bottom register, the next two bits are entered in the first register 170, such as the top register. In this fashion, the transmitted message con-sisting of any number of serial bits is formulated in the six registers 170. Although different methods are available for selecting which one or ones of the registers is most apt to have an error free message, the simplest and preferred way to select one of the registers for accessing the message is merely to monitor the entire message for a recognizable bit pattern in specified portions thereof, such as the preamble and address fields. The first register 170 to display the requisite bit pattern is the one considered to have an acceptable error-free mes;sage. The foregoing is effec-tuated with the use of a group of six comparators 174,each containing the same bit pattern against which to compare the contents of a different one of the registers 170. As soon as a successful compariso~ occurs, the comparator involved generates an output signal which may be used to transfer the message in its associated reg-ister to a permanent storage device for subsequent utilization (not shown).
01 - 2~ -03 As may be readily apparent, the retention of each 04 integrated value summation for n subsequent intervals following 05 its development for reEerence purposes, may be accomplished in 06 ways other than just described in connection with Figure 3.
07 For example, in lieu of each group of seven registers 148 and 08 150, one could substitute six registers for storing the 5iX
09 integrated values corresponding to the seventh through twelfth integration intervals previous to the current integration 11 interval and a digital adder for summing same. The output of 12 this adder, would, of course, be equal to the output of 13 register 152 for the quadrature component or register 154 for 14 the in phase component to provide a reference against which to respectively compare the outputs of adders 140 and 142.
17 As demonstrated by the foregoing, the subject invention 13 affords an improved integration technique for use in detecting 19 digital data conveyed by a carrier signal having a character-istic which is varied during each baud period in a predetermined 21 manner in accordance with the data. Minimal apparatus is 22 employed without sacrificing message reception times. Although 23 the invention has been presented in conjunction with a specific 24 application, namely developing multiple baud values per baud period from which to select a valid message for obviating zero 26- crossing ambiguity problems in data detection which is specific-27 ally addressed by U.S. patent 4,225,969, other applications 28 therefore are discernible. For example, the subject integration 29 technique could just as well be used to identify a particular one of the AC signal crossings to which to synchronize for baud 31 timing purposes which is an alternative solution to the data 32 detection ambiguity problem specifically addressed by U.S.
33 Patent 4,216,543 entitled "Means for Deriving Baud ~ ~ ;
Timing ~rom An Available AC ~ig-nal~" Since modifica-tions which do not necessarily depart from the scope and spirit of the invention herein may very well occur to those skilled in the art, the foregoing detailed de~
scription should be construed as merely exemplary and not circumstriptive of the invention as it will now be claimed hereinbelow.
As is well known, cyclically controlling by a square wave the closure of a switch such as 68 which is con-nected to a signal path in synchronous detection pro-duces the product of the signal entering the path andthe Fourier sinusoidal components of the square wave at ' '7 the output of the switch. Consequently, applying to switch 68 a square wave signal whose fundamental component is cos (Wct+QR) where ~C=2~fC~ c being the carrier frequency, and ~R is some fixed reference phase angle, S produces a siGnal to the inverting input of amplifier 22 equal to sin (~ct+~) cos (~ct~R) which has a DC component that is proportional to sin (9-~R) [which in this case is equal to sin (a-aR) since the sinusoidal signals are assumed to have unity amplitude]. This result is clearly described in the '036 patent, previously referred to, ln connection with Figure 1 thereof, where it will be recognized that mixer 18 for producing the requisite product has been preferably supplanted by electronic switch 68 of the subject invention as shown in Figure 2 herein. None of the other products of the carrier signal and Fourier componetns produce a DC signal and are therefore of no interest. With switch 44 open and switch 6~
operational in accordance with the control square wave signal represented by its fundamental component cos ~JCt+~R), applied thereto, the DC voltage applied to the inverting input of amplifier 22 will cause the voltage developed across capaciter 30 to linearly vary, thus providing at the output of amplifier 22 the integrated value of the DC component with a like polarity. Since switch 68 is closed during every other half cycle for Fc, which time am~lifier 22 cannot integra~e, this half-wave integra-tion process does not produce a smooth ramp as shown by waveform (c) of Figure 1 but rather a sequence of ramps separated by steps. This, of course, only affects the integrated value attained at the end of the integration interval and not the integration principle. If a smooth ramp over the full integration interval is desired, then the circuitry of Figure 2 can be supplemented with that of Figure 5 to be exaplained shortly. If the integration period is made equal tG one of the ,:
intervals corresponding to waveform (c) of Figure 1, the value attained at the end of the integration interval will be equal to KT/12 sin (~ ). By going through the same steps as the foregoin~, it will be readily seen that the application to switch 70 of a control square wave signal whose fundamental component is sin (~lct~R) will produce at the output of amplifier 24 at the end of an integration interval KT/12 cos ~ R) so long as switch 46 remains open for the interval.
When an absolute reference signal separate and apart from the carrier signal is employed such as in absolute modulation schemes, the control signals sin (~ct+~R) and cos (~ct+~R) would be derived directly from the reference signal so that ~R would normally be 0 and the signs of sin (~) and cos (~) would automatically define the baud value. However, when DPSK is employed such as herein, the baud value is determined by elimin-ating 6 ~ and developing the sin and cos of (~2_61), where the subscript 2 corresponds to the baud period being detected and the subscript corresponds to the preceding baud period. This will be explained later on.
In a similar fashion to the foregoing, cos (~t+6R) and sin (~ct~R) are applied respectively to-switches 72 and 74 to produce at the output~ of amplifiers 26 and 28 KT/12 -sin (~-~R) and KT/12 cos (~-~R) for also defining the carrier phase angle during some interval (vis-a-vis a fixed reference phase angle ~ R). While one of the integrating circuits 18 and 20 is integrating, the other one is initialized (but only after an analog to digital conversion is performed as explained hereinafter) to prepare it for its integrating interval by discharging the associated capacitors through the associaked '6'~7~
switches connected thereacross. For example, if switches 44 and 46 were open during interval 1 for wave form (c) of Figure l, while switches 68 and 70 were operational, integrating circuit 18 would in fact be integrating, during which time switches 48 and 50 would be closed to discharge their respective capacitors 34 and 36 to prepare integrating circuit 20 for its integration cycle during integration interval two. Of course, during interval two, switches 44 and 46 would be closed to permit their respective capacitors 30 and 32 to discharge so as to prepare integrating circuit 18 for its next integrating cycle during interval three. Thus, it is seen that integrating circuit 18 integrates during the odd numbered intervals and discharges during the even numbered intervals, while integrating circuit 20 conversaly integrates during the even numbered intervals and discharges during the odd numbered intervals.
The foregoing switch operations are reflected in the timing waveforms depicted in Figure 4 wherein the Eirst four waveforms are associated with con-trolling the oper-ation of switches 68-74, respectively, and the next two waveEorms control switches 44 together with 46 and 48 together with 50, respectively. A high level signal for the waveforms of Figure 4 corresponds to a switch being open, while a low level signifies that the switch is closed. The waveforms of Figure 4 are generated from the system frequency signal Fs by first passing it through a low-pass filter 76 shown in Figure 2 which eliminates unwanted frequencies such as the carrier signal Fc and then, through a limiter 78, to provide an output signal which is a square wave whose frequency and phase are consonant with Fs. The output of limiter 78 is applied to a phase lock loop circuit 80 to produce at its output a square wave whose frequency is four times that of the carrier signal frequency Fc . .
~7~
which i5 locked together with the phase to the system frequency Fs. Thus as Fs varies in frequency, as it may do so under adverse conditions, so does the fre-quency 4 fc at the output of phase lock loop circuit 80. The output of phase lock loop circuit 80 is applied to a divide by 4 circuit 82 having two outputs which have a frequency equal to that of the carrier signal frequency fc and a phase angle ~R wi.th reference thereto, and which are reprec;ented mathematically only by their respective fundament:al sinusoidal components.
The two outputs have a phase angle difference of 90 so that one constitutes a sine function with the other constituting a cosine function. The cosine output of divide by 4 circuit 82 is connected as a first input to an AND gate 84 having a second input from the output of limiter 78 so that the gate is enabled to pass the square wave to its output s68 during the first inte-gration interval f Fs shown in Figure 4, as well as all successive odd integration intervals. During these odd integration intervals when AND gate 84 is enabled, the signal s68 is applied to switch 68 to cause it to synchronously open and close which as already mentioned is equivalent to the mixing function of mixer 18 of Figure 1 of the '036 patent previously alluded to. Con-sequently, the product of sin (~ct+~) and cos(~ct~R) is formed at the interconnection of the switch 68 with resistors 52 and 54. During this time it is to be noted that switches 44 and 46 are open to per-mit their respective capacitors 30 and 32 to linearly build up voltage during the integration interval. Since switch 68 is closed half the time during the integration interval, which inhibits the capacitor from receiving any charging current, as mentioned earlier the integra-tion waveform would not be a smooth ramp as depicted in Figure l, but rather a sequence of little ramps (when switch 68 is open during the high level half cycles of 7~
the square wave) connected by flat portions when switch 68 is closed (during low level portions of the square wave s68).
If integration throughout an integration interval is desired, for example to generate a high integration signal, then each of the operational amplifiers 22~28 can be supplemented with additional ci~cuitry as shown in Figure S in connectlon with operational amplifier 22. It will be seen therein that the mixing and inte-grating functions have been totally separated by con-necting the synchronous switch 68 to the interconnection point of a pair of resistors 86 and 88, with resistor 88 being connected to the noninverting input of another operational amplifier 90. The carrier signal Fc is applied to the noninverting input of operational ampli-fier 90 through the series resistors 86 and 88 as well as to the inverting input via a resistor 92. With another resistor 94 interconnecting the output and the inverting input of operational amplifier 90, a full-wave mixer with a gain of one is provided, by making resis-tors 92 and 94 the same value, and 86 and 88 as well.
So long as a new switch 97, connected to the inter-connection of resistors 52 and 54 associated with opera-tional amplifier 22, is left open during the full inte-gration interval, a smooth linear ramp will be obtained at the output of amplifier 22 without any steps in the waveform.
At the end of the first integration interval, the output of operational amplifier 22 is the integrated value of the DC component for the product of the sin (~ct+~l) and cos (~ct~gR), namely KT sin ~ R) In a similar fashion it will be seen that the output of operational amplifier 24 at this time is KT/12 cos (6l_~R) because of the application to , 7.~
switch 70 of sin (ll!ct+ ~) via an AND gate 96 having a secojnd input derived from the output of limiter 78.
Furthermore, it will be seen that the outputs of opera-tional amplifiers 26 and 28 at the end of the second integration interval are respectively 12 sin (~2- ~) and 12 cos (~2-~R) by virtue of the application of cos (~ct+~R) to switch 72 via an AND
gate 98 and sin (~ct+~R) to switch 74 via an AND
gate 100. Both AND gates 98 and 100 have a second input which is derived from the output of limiter 78 after first inverting the signal through inverter lC2. Con-sequently, these AND gates are enabled to pass their respective square waves during the eve~ integratio~
intervals associated with the system frequency signal Fs.
The outputs of amplifiers 22-28 are connected to an analo~/digital (A/D) converter 104 via four individual switches 106-112 respectively associated therewith. The analog integrated value outputs of amplifiers 22-28 are thus converted to digital equivalents at the output of A/D converter 104 on bus 113 (which prefera~ly comprises multiple leads for parallel bit operation) in multiplex fashion by sequentially closing switches 106-112. For example, switch 106 is closed upon the termination of the first integration interval by a low level signal generated at the output of a one shot multivibrator 114 which is triggered by the falling edge of the output of - limiter 78, namely Fs. After sufficient time has transpired for the conversion to be efected, switch 106 is opened at the end of the one shot period and switch 108 is closed by the same output from one shot 114 via a delay circuit 116. Following the A/D conversions for the outputs of amplifiers 22 and 24, their respective capacitors 30 and 32 are discharged by the closure o the switches 44 and 46. The signal for this operation is derived by triggering a one shot multivibrator 118 by the falling edge output from delay circuit 116. In similar fashion, switch 110 is closed during each odd integration interval, after its associated integrating circuit 20 even integration interval, by the output of a one shot multivibrator 120, which is triggered by the rising edge of the output of limiter 78. Switch 112 is thereafter closed by first passing the output of one shot 120 through a delay circuit 122. Switches 48 and 50 are closed to discharge their respective capacitors 34 and 36 through a one shot multivibrator 124 which is activated by the falling edge of the output of delay circuit 122. The timing wave ~orms corresponding to the foregoing discharge and conversion operations are shown in Figure 4.
As shown in Figure 3, the storage circuitry for retaining the digital integrated value outputs of A/D
converter 104 on lead 113 comprises one group of six series connected registers 126 corresponding to the quadrature (sine) component, and another set of six series connected registers 128 corresponding to the in phase (cosine) compo~ent. Each time a new integrated digital value Ic (the subscript c denoting current interval) is generated at the output of A/D converter 104, it is stored in the first register of a register group, the quadrature component being placed into reg-ister 130 of group 126, and the in phase component into register 132 of group 128. Just prior thereto the value in each register is shifted to the next register in the series chain so that the value that had been stored in register 130 is passed to register 134 and likewise, the value that had been stored in register 132 is passed to the next register (not shown) in the chain for group 128. The values stored in the last registers of the register groups, namely 138 for group 126 and 140 for group 128, are no longer retained when supplanted by the ilB
new value received from the preceding register. The foregoing is represented by the notation Ic 1 through c 5 for the registers in groups 126 and 128. The registers of register group 126 corresponding to the quadrature component are clocked by the output of a one shot multivibrator 131, shown in Figure 2, which is triggered at the end of an A/D conversion operation by the lagging edge of the A/D control pulses (Figure 4 waveform~ for controlling quadrature component switches 106 and 110 via an OR gate 133 whose inputs are con-nected to the outputs of one shot multivibrators 114 and 120. Likewise, the registers of register group 128 cor-responding to the in phase component are clocked by the output of a one shot muLtivibrator 135 by the lagging edge of the A/D control pulses for controlling in phase component switches 108 and 112 via an OR gate 135 whose inputs are connected to the outputs of delay circuits 116 and 122.
Upon receipt of each new integrated digital value Ic, the outputs of the registers in each register group 126 and 128 constituting the corresponding inte-grated values for the previous five intervals tc-l to c-5) are digitally summed by respective digital adders 25 140 and 142. The digital integrated value summations of adders 140 and 142, denoted ~ ~ , are then applied to registers 144 and 146 respe~ctl~vèly, each of which is the first register of a group of seven series connected registers 148 and 150 respectively. As with the reg-30 ister group~ 126 and 128, each register in groups 148 and 150 passes the digital value stored therein to the next succeeding register prior to receiving the digital stored value in the preceding register under the clock output of one shot multivibrators 131 and 135, respec-tively. Since there are seven registers in each group 148 and 150, ~he summations of 5iX integrated values ~;'7~
entered into the first registers 144 and 14~ are eventu-ally stored in the last registers 152 and 154 of groups 148 and 150 respectively, six integration intervals later. Also, since differential phase shift keying en-tails comparing each baud period wi-th the previous baud period acting as a reference, and since six integration intervals constitute a full baud period cycle herein, the output of register 144, which is proportional to sin (~2- ~)~ is compared with the output oE register 152, which is proportional to sin (G1-~R) where, the subscript 2 denotes a current summation period and the subscript 1 denotes the preceding summation period.
Similarly, the outputs of registers 146 and 154, respec-tively, proportional to cos (~2 ~R) and cos (~ ) are employed in the comparison to eliminate the reference angle ~R and obtain the phase angle ad-~2 1 in consecutive baud period Thus, as delineated in the '036 patent, the outputs of registers 144 and 152 are multiplied in digital multi-plier 156 and summed with the product of the outputs ofregisters 146 and 154 appearing at the output of digital multiplier 158 in digital adder 160 to render the term cos (B2 el~- The term sin (~ 1) is obtained by adding the product of the outputs of registers 152 and 146, available at the output of digital multiplier 162, to the negative value of the product of the outputs of registers 144 and 154, available at the output of digital multiplier 164, in digital adder 166. The signs of the output signals for-adders 160 and 166 define the two bit values engendered by the baud as represented by the summation of integrated values corresponding to the six integration intervals, appearing serially at the output of decoder 168 with the designated format. Since there are six such intervals during each baud period it is readily apparent that there will be six values of baud data, each consisting of two bits, for selecting the 7~
proper baud value. These six values are stored in a group of six registers 170 by cyclical sequential appli-cation thereto under control of a register enable cir-cuit 172 having a count of six which is triggered from the output at limiter 78 once during each integration interval. During each interva] the two data bits defin-ing the baud value are serially clocked from the output of decoder 168 into the enabled register 170 in their proper order. The two clock pulses for entering the two serial bits in each of the registers 170 can simply be provided from register enable circuit 172 through a ring counter having a count of six whose output leads are individually connected to the registers 170 via a pair of one shot multivibrators for each lead (not shown).
After two bits are entered in the last register 170, such as the bottom register, the next two bits are entered in the first register 170, such as the top register. In this fashion, the transmitted message con-sisting of any number of serial bits is formulated in the six registers 170. Although different methods are available for selecting which one or ones of the registers is most apt to have an error free message, the simplest and preferred way to select one of the registers for accessing the message is merely to monitor the entire message for a recognizable bit pattern in specified portions thereof, such as the preamble and address fields. The first register 170 to display the requisite bit pattern is the one considered to have an acceptable error-free mes;sage. The foregoing is effec-tuated with the use of a group of six comparators 174,each containing the same bit pattern against which to compare the contents of a different one of the registers 170. As soon as a successful compariso~ occurs, the comparator involved generates an output signal which may be used to transfer the message in its associated reg-ister to a permanent storage device for subsequent utilization (not shown).
01 - 2~ -03 As may be readily apparent, the retention of each 04 integrated value summation for n subsequent intervals following 05 its development for reEerence purposes, may be accomplished in 06 ways other than just described in connection with Figure 3.
07 For example, in lieu of each group of seven registers 148 and 08 150, one could substitute six registers for storing the 5iX
09 integrated values corresponding to the seventh through twelfth integration intervals previous to the current integration 11 interval and a digital adder for summing same. The output of 12 this adder, would, of course, be equal to the output of 13 register 152 for the quadrature component or register 154 for 14 the in phase component to provide a reference against which to respectively compare the outputs of adders 140 and 142.
17 As demonstrated by the foregoing, the subject invention 13 affords an improved integration technique for use in detecting 19 digital data conveyed by a carrier signal having a character-istic which is varied during each baud period in a predetermined 21 manner in accordance with the data. Minimal apparatus is 22 employed without sacrificing message reception times. Although 23 the invention has been presented in conjunction with a specific 24 application, namely developing multiple baud values per baud period from which to select a valid message for obviating zero 26- crossing ambiguity problems in data detection which is specific-27 ally addressed by U.S. patent 4,225,969, other applications 28 therefore are discernible. For example, the subject integration 29 technique could just as well be used to identify a particular one of the AC signal crossings to which to synchronize for baud 31 timing purposes which is an alternative solution to the data 32 detection ambiguity problem specifically addressed by U.S.
33 Patent 4,216,543 entitled "Means for Deriving Baud ~ ~ ;
Timing ~rom An Available AC ~ig-nal~" Since modifica-tions which do not necessarily depart from the scope and spirit of the invention herein may very well occur to those skilled in the art, the foregoing detailed de~
scription should be construed as merely exemplary and not circumstriptive of the invention as it will now be claimed hereinbelow.
Claims (10)
1. Demodulation means for demodulating a carrier signal bearing digital data which varies a specific characteristic of the carrier signal during each baud period in a predetermined manner to identify the baud value during the period, comprising:
means for converting the carrier signal characteristic to a DC signal;
timing means for subdividing each baud period into n intervals;
means for integrating the DC signal over each of said intervals, and means for summing the integrated DC signal attained at the end of each interval with the integrated DC signals attained at the end of the previous n-l intervals.
means for converting the carrier signal characteristic to a DC signal;
timing means for subdividing each baud period into n intervals;
means for integrating the DC signal over each of said intervals, and means for summing the integrated DC signal attained at the end of each interval with the integrated DC signals attained at the end of the previous n-l intervals.
2. The demodulator means of Claim 1 including means for storing the integrated DC signal summations.
3. The demodulator means of Claim 2 wherein said integrating means comprises a pair of integrators, each for integrating the DC signal during alternate intervals while the other is initialized to a predetermined state preparatory to an integrating cycle.
4. The demodulator means of claim 2 or 3 wherein said timing means is controlled by an AC signal and n is equal to the number of zero crossings of said AC signal during each baud period, and whereby each interval is initiated at one of the zero crossings.
5. The demodulator means of claim 2 wherein said timing means is controlled by an AC signal and n is equal to the number of zero crossings of said AC signal during each baud period, whereby each interval is initiated at one of the zero crossings, wherein the AC signal corresponds to the frequency of an electric power system over which the carrier signal is transmitted.
6. A method for demodulating a carrier signal bearing digital data which varies a characteristic of the carrier signal during each baud period in a predetermined manner to identify the baud value during the period, comprising:
converting the carrier signal characteristic to a DC
signal;
subdividing each baud period into n intervals, integrating the DC signal over each of said intervals, and summing the integrated DC signal attained at the end of each interval with the integrated DC signals attained at the end of the previous n-l intervals.
converting the carrier signal characteristic to a DC
signal;
subdividing each baud period into n intervals, integrating the DC signal over each of said intervals, and summing the integrated DC signal attained at the end of each interval with the integrated DC signals attained at the end of the previous n-l intervals.
7. The method of claim 6 including storing the integrated DC signal summations.
8. The method of claim 7 wherein said subdividing is controlled by an AC signal and n is equal to the number of zero crossings of said AC signal during each baud period, and whereby each interval is initiated at one of the zero crossings.
9. The method of claim 8 wherein the AC signal corresponds to the frequency of an electric power system over which the carrier signal is transmitted.
10. The demodulator means of claim 3 wherein said timing means is controlled by an AC signal and n is equal to the number of zero crossings of said AC signal during each baud period, whereby each interval is initiated at one of the zero crossings, wherein the AC signal corresponds to the frequency of an electric power system over which the carrier signal is transmitted.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US015,276 | 1979-02-26 | ||
| US06/015,276 US4218769A (en) | 1979-02-26 | 1979-02-26 | Means for subdividing a baud period into multiple integration intervals to enhance digital message detection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1167118A true CA1167118A (en) | 1984-05-08 |
Family
ID=21770504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000344918A Expired CA1167118A (en) | 1979-02-26 | 1980-02-01 | Means for subdividing a baud period into multiple integration intervals to enhance digital message detection |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4218769A (en) |
| AT (1) | AT368308B (en) |
| CA (1) | CA1167118A (en) |
| DE (1) | DE3006790A1 (en) |
| DK (1) | DK78080A (en) |
| FR (1) | FR2454234A1 (en) |
| GB (1) | GB2045033B (en) |
| NO (1) | NO800461L (en) |
| SE (1) | SE8001416L (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4455664A (en) * | 1981-12-07 | 1984-06-19 | Motorola Inc. | Carrier data operated squelch |
| US4556866A (en) * | 1983-03-16 | 1985-12-03 | Honeywell Inc. | Power line carrier FSK data system |
| US4730267A (en) * | 1985-10-03 | 1988-03-08 | General Electric Company | Combination integrate and dump filter and level detector |
| DE4024593A1 (en) * | 1990-08-02 | 1992-03-05 | Sgs Thomson Microelectronics | METHOD AND DEVICE FOR DEMODULATING A BIPHASE-MODULATED SIGNAL |
| US5631924A (en) * | 1995-06-19 | 1997-05-20 | Motorola, Inc. | Method and apparatus for baud rate detection in an FM receiver using parameters unrelated to baud rate as confirmation |
| US5691691A (en) * | 1997-01-06 | 1997-11-25 | Motorola, Inc. | Power-line communication system using pulse transmission on the AC line |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3909599A (en) * | 1973-11-23 | 1975-09-30 | Teledyne Ind | Digital FM discriminator |
| US4071821A (en) * | 1976-04-28 | 1978-01-31 | Honeywell Inc. | Quadrature correlation phase determining apparatus |
| US4163218A (en) * | 1976-09-13 | 1979-07-31 | Wu William I L | Electronic multiple device control system |
| US4079329A (en) * | 1976-11-11 | 1978-03-14 | Harris Corporation | Signal demodulator including data normalization |
-
1979
- 1979-02-26 US US06/015,276 patent/US4218769A/en not_active Expired - Lifetime
-
1980
- 1980-02-01 CA CA000344918A patent/CA1167118A/en not_active Expired
- 1980-02-05 GB GB8003779A patent/GB2045033B/en not_active Expired
- 1980-02-20 NO NO800461A patent/NO800461L/en unknown
- 1980-02-22 SE SE8001416A patent/SE8001416L/en not_active Application Discontinuation
- 1980-02-22 DK DK78080A patent/DK78080A/en not_active Application Discontinuation
- 1980-02-22 DE DE19803006790 patent/DE3006790A1/en not_active Withdrawn
- 1980-02-26 AT AT0105980A patent/AT368308B/en not_active IP Right Cessation
- 1980-02-26 FR FR8004154A patent/FR2454234A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| AT368308B (en) | 1982-10-11 |
| DE3006790A1 (en) | 1980-09-04 |
| ATA105980A (en) | 1982-01-15 |
| FR2454234B1 (en) | 1984-04-20 |
| US4218769A (en) | 1980-08-19 |
| NO800461L (en) | 1980-08-27 |
| GB2045033B (en) | 1983-03-23 |
| DK78080A (en) | 1980-08-27 |
| SE8001416L (en) | 1980-08-27 |
| FR2454234A1 (en) | 1980-11-07 |
| GB2045033A (en) | 1980-10-22 |
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