CA1186728A - Solid state frequency converter - Google Patents

Abstract

SOLID STATE FREQUENCY CONVERTER

ABSTRACT
A plurality of SCR diamond bridge circuits are coupled in series to generate frequencies higher than the individual operating frequencies of the SCR's. The series chain of diamond circuits is preferably coupled in parallel with the series combination of a DC blocking capacitor and an induc-tive load. The chain is provided with current from a sub-stantially ripple-free constant current source, and the firing times of individual SCR's can be controlled to mini-mize the di/dt in each SCR.

Description

SOLID STATE ~REQU~CY CON~R~ER

~1~ o~
This inve~ation relates to frequent:y conversion from a souree :~res~uency to a de_ir~3d frequency~ and more particu~
larly from D~ tQ a de~ixed fre5~uency.
Still more particularly, ~lhe pre~ent i~e2l~ion i~
directed ~o a ~olid ~ta~2 freguency con~er~er which rec~ives a constant DC ~urrent and generates ~lectric power of a de~ired fre~auency ar~d voltage tg be ~lapplied for ~e in an :induction heatillg appara~u~, induc:tion melting apparat~ls, u:Ltra~on:Lc transducer or o~her device~ re~uiring high fxe~
~ueney power.

SU~ARY OF ~ INVENTION
~ t is an obj ect of this ln~ntion to provide an econom icalt high powex, high :Ere~uency, 601iâ state power ~ourc:e.
It is a :Eu.rther obj~::t of this invention to provide a hi~h ~reç~ency power source which ~oe~ not ha~e it~ maximum :requency of opera~ion determined by the tu~off time o~
th2 electxonic ~itche~ used.
~ 't i8 a f~u:i: ther ob; ect o ~is in~7ention ~o provide high f:requency inverter that i~ not 6U8C:e!p~ e to ~ailure in ~e event ~ynchxonism wi~ an osc:illat~ tank circllit i~
lo~t due to load or transmissio~ ~ransients.

.. ~

~;
~ ., It is a further object of ll;hi~ ention to proYide a hish fre~erlcy inverter in whicll the po~sib:Llty of damage to ~e swi~ching elements due to t:urrerlt surge i~ tantially reduced .
I k is a ~ature of thi~ in~iention tha'c a highl freg[uency solid s~ate power æource i~ provided whereixl ~he commutating capas~itor is used ~or the dual purpose o commu~ating the swikches ancl delivering a narrow r~onant transmis~ion half sin2 wave pulse to ~he load wi~hout j~opardizing the lo~g ~u~n~o~f time required by the thyri~tors.
It i~ a ~urther feature of this i~en~ion ~hat a high freguency i~exter is provided havi~g ~ ~el-protecting, sel~ ~iring ne~work which precludes failure due to over voltage in the event control is lo~t upon pow~r failure or ~he like~ .
It i5 a feature of thi6 i~vention ~hat a freguency co~erker is provided that can ~raw ener~y rom power lines at uni~y power fac~or without cau~i~g interference with other elec~ronic equipment on ~he power line~.
It is a ur~her feature of ~hi~ învention ~hat ~he tlming of ~he firing of individual switching elements is controlled in order to minimize current suxge ~hrough the switching element~.
Bxiefly~ th~se and o~her objects are ach eved according to the pxesent i~ention by a 601ld state ~re~uen~y co~ver ~er compri~ing a current ~ouxce and a ~eries chain of dia~
mond commutatincJ elements coupled to ~he current ~ourc~.
E~ch diamond element includ~ first and second SCR's having ~heir anodes coupled toge~her to foxm a ~i~mond element input termi~al, and third and fourth Sc~'~ haYing ~heir cath~des coupled together to foxm a di~mond element output ,~

;` ~
, ~ ~

~erminal . One ternninal of a con mutatlIlg eapaeitor is coupled in conmon to the cathode an~ an~de of t~ first and third SCR ' 5 ~ respectively, and ~e o~he~e cap~ci ~:ox te~ninal is coupled in col[mon to the cathode and anode of the ~econd ~nd ~ourth SCR's, respectively. ~ A resonant load can ~ither ~e coupled in seri~s with the chain o diamond circuit~, or i lt can }: e coupled in ~rie~ wi~h a DC bl ocking capacitor, wi~h the sarie~ combination of the blocking c:apac:L tor and re~onant load coupled in parallel wi~ ~e di~ond chairl.
l'he vol t:age appearing across a ~ingle diaYnond group will be a ~awto~th wave with a frequency e~al to twice the switching rate of its SCRI ~ . EIowever, ~:he volt~ge appearinç
across the ~eries chain of ~7 di~mond bridge circuits will be ~ ~awtootkl having a fres~ency N times the requency of each individual }: ridge . SiIlce the turn-off time applied to each SCR is detenni~ed by the low . fre~ency ~awtoot;h of it~ own :Ibridge, SCR 7~ requiring long turn-off times, e .g, ~ 40 micro-~econds, can be u~ed to generate freguens~ies o~E 50 k~z or higher ~
Reverse current ~pike~ through individual SCR'~ can be prevented by i~luding a small s~turable reactor in serie~
wi~h each ~witching element ~o that the current during ~uxn-off of ~he SCR will not be exce~sive. Fur~her, khe current through any individual SCR during i~s l'on'l time will fluctuate through more than one cycle of a sub~tantially sinusoidal wave form~ If the ~iring times of the 5CR' s are controlled ~uch ~hat each SCR will be fired when it~ orward current is at a minimum level, the turn~of time ~nd di~dt will be minimized and damage to the SCR'~ can be reduced.

,1 ., "

~ ub~tantl ally ri~pple~free source of eons ~.ant current i~ pre~ided to ~ diamond chain by firs t and æecond con ~tant eurrent sour~es each of which ir~elude~ chopper SCR ' ~
~ired at a ~ubmultiple o~ the firing frequen~y o:E ~e SCR' &
in ~he diamond ehai~a. The chopp~rs irl ~e :fix~t con~tant currenk source are :Eired appro:Rima~ely 180~ ou~:~of~pha~
~om those in the ~econd con~tant curr~nt ~ourc in urder to substantially eliminate ripple.

BRIEF DESCRIPTION OF TH:E DRAWIN~S
The iIlveIltion will be more clearly under~ tood wi th re:erence to the iEollowin~ desGription in cosljunction wi~
the ~ccompanyiIlg drawings in which Figure 1 is a brief diagram of the es~enkial component~
OI a conv~ntional 6eries inverter circuit;
~ isure ~ is a bri~f dia5s:ram o a con~entional ~hunlt co~uTutated impulse circuit;
Figure 3 is a ~chematic diagram of a fr~ueney conver-ter circuit accQrding to ~he E)resent inven~ion;
Fi~ures 4A and 4B are wave ~orm~ illustratir~sJ khe operatiorl o~ any one of the individual diamond circuit~ in F:igure 3;
P'igures 5A-5E are wave fo~ms illustrating khe c~mbiIled op2ration of ~e diamond cir::uiks in Figure 3, Figure 6 is a schematic diagram of a ~ouxce of c~rlstant curren~ suitabl~ for use in con; unction wi ~ ~he ~Erequency conver~er circuilt of ~igure 3;
Figure 7 is a sehematic di~gram o a suitable power ~ouxce for t;he switchirlg elements and for the timing and logi~ circ~ ry for controlling t~e firing ~ime~ o khe swits:hing eleDIents in Figmres 3 and 6;

i J

Fl~re 8 is a ~chematie diagram of a ps~lse ~nplifier which may be u~ed to trigger the ~witc:hing e:Lements used in ~e pre~eTlt inve~tion;
Fisure 9 is a ~chematic diagram of logie circuitry used in ~ontrollillg the fi;~iny times of ~e switehing e~lemerltæ in F:igure 3;
~igU:rl@ lOA iB a ~chematic diagram of ~n o~cillator for use in ~ontrol cireuitry of the presen~ invention;
Figure lOB is a schematic diagram oiE a fr~uency di-vider which~ in col~junction with the o~cillator of Fig-ure lOA, provldes phase-displaced timirlg S:l.~lal5 necessaxy ~o mplement proper f iring time~; of the 6witc!hing elements ~n Figure 3;
~ igure 11 is a 6chematic diagram of a âi ~er ~ircuit used t~ maintain the frequency converter circuitry of Fig ure 3 in a ~tandby condition;
Fi~lres 12A and 12~ are ~chematic di~gr~ns o~ ehoppex ena~ling clrcu.its for the first and ~econd . onst2nt ~urrent ~ource~, respectively;
~ i~res 13A and 13B are schematic diagram~ of current monitoring circuits used in t~he ~irst and second constant curreIlt sources of Figure 6;
Fi~re 14 i8 a schematiG diagram of feedback cir~uitry wh ' ch as~is ts in ~ontrolling the value of coIl~tarlt current :in acc~rdance with the levels of current ~upplied lby each of ~e constaIlt current ~ources and in -aGc~xda:tlce with t:he vo:Ltage acros~ the dia3nond chaill of Figure 3~
Figur~s 15A and 15B are schematic diagrams of drcuitry us~d to ge~erate iring signals for the c:hc:pper SCR' ~ in the :Eir~t and second constant current sources;

Figu.res ï6~ and ~6P, are $chematic: diagr~ns o~ circuit~
used ~.o g~nerate out~of-pha~e reset ~igrnals :Eor chopper SC~ 9 s in ~he firs~ and sec:ond con~an~ curren~ SOUXCeE;, re~pectively; and F:L~ure 17 illustrates t:he walv~ ~oran o~ :~o~ar~l curre ~hrough an irl~ividual ~yristor irl a two-diamond configllra-~ion; and Fi~re 18 is a brie~ sliagr~n of ~tlit~le eircui~y for ::ontroll~ g ~e timing of the fixing pulæes ~o inc?ivid-lal ~yris~or~ O
13ACKGROUND OF Tt~ IP~ENTION
~ .
~ requency conversion through the u~e of e:l ectrorlic swi tc:hes is widely known, and typical elec~ronic swi~ches have been ~park gap~ hyratrons, vacu~n Itubes, traIlsistors and ^~hyri~or~, P.t the pres~rlt ~ime, thyxis tor~ axe px~
:~err2d ~ox gerlerating high fxequenc:y pow~r up ~o 10 ~12 due ~s: their unlimited lifei low cost and high energy :witching capacity per switch, ~ thyristor, or ~ilicon controlled reeti~Fier ~SCR~ will conduc t iIl response to a c:on~rol pulse when it is ~orward bia~ed and will contirlue c:ondu~til~ until a r~verse ~oltage is applied a~ros~ the SCR . 5ystems employing SC~ ' ~ in ~e k~Iz r2nge are most often resonant circuits, wherein the re~uir2merlt of the ~CR to have a reverse voltage applied for approximately 10 to 60 microseconds in order ~o tur~ it o~f :IL5 met. by ~he natural re~rersal o~ the c:urrerl~ in the reso~
naa~ cix~uit. A common circui~ which opera~tes in thi~
manner is ~he ~erie~ inverter shown in Figure 1~ wherein or:l:Ly ~he main power components axe hown. 5~herl s~ s 10 and 1.2 are swi tched Oll, the series s:~ircuit colls:is~ing of the capaci~or 14 and transforsaer primary 16 having a substantial leakage reactance is resonantly charged to approximately 1.5 ~o 2 . 0 times the ~ourc:e voltage. The ~apaitor ~en causes . .

current to ~low ba::k to the source ~ria dio~e~ 18 and 20, thu~ cau~ing SCR1~ 10 a~d 1~ ~o ~urn off~ ~en 5C~'~ 10 and 12 ha~e ~urned Dff, SCR'~ ~2 and 24 a~re fired.
With a circuit operating in this manner, ~e tuxn off tiare avail~le to ~e SCR'~ nly a fraction o:F one~hal~
cycle o:E opera~ion and, even i OD.l~ a lû microse ond turn o: ~'me i~ .reguired, it is difficult to achieve freg;ll2Ilcies :in e~cess of lû ~z.
Some variatic)n~ of the ~:ircuit of Figure 1, ~llch as replaeing diode~ 18, 20, 26 and 28 with resonant l,C net~
works, make it possible to turn off the ~hyri~tors wi~ a reve.rse vol~age which lasts longer than a hal~ ~ycle of l:he re~on~t :Load, but the resorlant load decays irl amplitude be~ore i~ can again be energized via SCR ' ~ 22 and 24 .
~nducti~Il hea~ing device~ pre~erably u~ilize SO kHz power andt in ~:uch a case, ~e load would be a 50 k~z re~onant circuit. If thi~ resonant circuit is only supp:Lied with a pulse o energy at a 10 3~Rz repetition rate, the voltage of ~he ioad will decay be~weerl pulse~ and optimum heating canxlot be achieved.
A urthe.r apprc~ach to obltaining high frequenc~ power is ~e u~e of a ~hunt commutated impul~e circui t a~ shown in ~igure 2 ~ In the circult of Figure 2, SCRi ~ 30 and 32 conduc t and charqe the commutating capacitor 34 O When a predete~i~ed voltag~ i~ reac:hed~ the ou~put SC~3~ i.s fired ~and the cur:rent ~;ource 38 feeds the loadO ~t a 3ubsequ~nt time, SCR ~ ~ 40 and 42 can be fired to connec~ the charged capacitor in~7ersely in the circuit, thus rever~e ~i~sing the O~ U~: ~C:~ and terminating the pul~;e ~upplied to ~e load.
Wi~ ~e cir~uitry of ~igure 2, an C~U~llt pul~e can be achieved which i~ narrow enough to excite a h ' gh frequency ;;
~.~ 7 ~ank ::ircui~ wever, a relatively long ~ime mu~t elapse while the commutatirlg capacitc~r 34 c:harge~ up be:fore ~he ¢ircui~ can de~iver ~nother pulse and, therefore, khe amE~
t7lde in the xesonant load c:ircuit ~will d~cay !between pul~es.
:~y co~ecking a number of the Figu:re 2 circuiks in parallel~
~he tan~ load ca~ ~e excited at the pxoper fre~uen~y, but each pul5e will require a separate s:urrent ~ouxce, ~eparate outpuk SC~ and separake cs~mmu~ating circ~ui It O ~a~hls becomes e~cesslvely ~o~tly.
- An addit:ional problem with the circuit of ~i~ure 2 i~
that the commutating c:apacitor will only p:rovide turn-off time to the output SCR as long as it i~ more negative 3:han ~e tank t::il'CUi-k, but the tank circuit i~ ring.insT both positiYe and negati~e. ~s ~ result, lower operating vol-tages must be used in order to en~ure ~ufficiellt turn~off time ~
A further te~hni~ue for generating high fresauency power :i~ di~closed in U.S. Pakent 3,29û,581 to ~ooper. ~s shown in Figure 3 of ltha~ patent, a plurali ~ of SCR diamond commu~atiIlg clrcuit~ ara used to achieve a type of :Erequency multiplication. Eal of the diamond circuits are connect~d irl par~llel l:o one ~ide of a transformer primary while the other ha:L ar~3 connected in parallel to the other side o~
t~e t.raIIs~or~ner primary and the firing order of ~e diamond cireult~ can be shifted in phase ~o a~ to a6~is~ alternate and opposite directions of current ~low through the pximary, While t:he ~ooper ~ircuitry is an improvement over lt;hR pre-viously discusAsed freguency gen~ration cireui~s, it has s till no~ prove~ entirely satisfactory~ Turn o:f time is a~sured by virtue o$ firing alternate pair~ of cross corner thyri~tor~ in a gi~en diamond~ If the cro~ cor~2r pair i~

no~ i~Tmeùiately fired, the ini1:ial thyri~tor curxen~ 6~ill go to zero ~ince khe capac:itor caNno~ conduct d. c: . currerlt~
Turn of~ pulses are also supplied by virt:ue of adjacent diamonds, a~d after the adj acent diamonds have fired~ ~e flring order return6 to the initial diamond and ~e opposite croxs corn r pair is f ired, there:by providing an additional tllrn of pulse to the initial pa:ix ~onsidered. ~hus, turll o:f time is rlo loIlger the limiting factor :in ~e ~ooper sy~tem~ Elowever, ~e diamonds and ~eir cap~acitors are not u~ed in a ~ontinuous current mode, nor are ~he pximary windings of 9the transfonnerO Tunirlg out of iIlductance inh2rPnt in the construction of the equipme~t i~ not po~.ible ill ~i~contimlous current. The ~oopex system also employs a voltage ~ourre to ~upp:Ly energy to ~e diamond array~ and does not enjoy the protecti~fe advantages of ~sei~g ~upplied with a current ~ource, to be de~cribed.
C:anadian Patent 1,079,363 discloæe~ a high fre~uency pow~r generation circuit utilizirlg a pluralil~y of diamond brie~ge circ~lit~ cormected in parallel wit~ one ano~her and also irl paxallel with a load. While this may be pre~erable to the high fre~enc:y voltage generatirlg circuits di~cus~ed abo~e, it i~ ~till not ~ntirely ~a~isfac~ory at very high f.re~encies and high power, e.SI. on the order of 100 k~2 and 100 kWc ~ach diamond bridge circult includes a cvmm-ltating capaci~or whl~h n~ t be repea~edly charged and di~charged A't cu~rent~ well in esYce6~ . o 1000 ampere~ and at very high ~res~uencies ~his eharging and discharging may encounter substantial in~pedlanc~ from the panel inductance whiGh is iIIhererlt in each of the diamond bxidge circuitæ. ~hus7 with t:lle ci.rc~ con.iguration illustrated in Canad:ian Patent 1~ 079,363, the individual diamond~ are 21D~ opexati~g in continuou~ current, and the ~nductive impeda~ee within th~
diamond in series with eac:h c:apacitor carmot be tu~ed out~
:~ur:i ng conduction, vol~age from ~he capaci~or is lo~t in ovexcomillg this inductive iner~ia, which i~ ~igni~iGant when OIlly 5 S:~E 1~ seconds are available for delivexing a high energy pul eO mis ~i~ua~io~ i~; aggrav~ted by ~e :~act that thyristor~ are rela~iv~ly high curren~ low voltage devi~e~, i.e. 1000 AMPS, 600 volts c:omparecl to vacuum tubes ~hi~h may operate at 10, ooo Yolts or high~r. Thu~ ~ G~ray inductarl~e which stoxes energy as Li~ i~ a greater problem a~ hi~
eurren$ and low volt~ge.

DETP~ILED DESCRIPTION OF TE~ PREFESRREI:) EMBODIM3~TS
Shown in ~igure 3 i~ a brief schematic ~lia~ram o~ the essexltial compone~t~ of a fresluency converter according to ~e present invent1on. The 1:ircuit includes a c:on6~allt current source (not shown ~, and coupled across ~e output ~e~minals 50 and 52 of the constant current ~ource 50 i8 a series c:hain ~ ~iamond bridge circuits 60, 70 ~ 80 and 90 0 Diamond circuit 6û comprises SCR ' s 62, 64, 66 and 68 and an interllal commutating capa~itor 69 and ~he remaining diamond clrcuits ax~ similarly co~figured. As is well known, e~h diamond in~rerter group is normally operated :by simult~e~
ously firing opposit~ SCR I 5 . ~or example, SCR ' ~ 62 aIld 68 w.ill corlduct during a first period of time o~10wed by SCR'~ 64and66.
~ or the purpose of khe following descriptiorl, it will 3:e as~umed that ~e SCR's in each diamond inverte.r group are pulsed at tbeir maximum switching frequency, e. g., 10 k:EIz .
With this t~pe of operationl th0 voltage acro~ ~e capa~i -~or ~ in bridge 60 will be ~ ched a~ a 10 ~Iz ra~e and i8 , .

i:l' '`' il:Lus-trated in Figure 4A. W~ile SCR ' s 62 arld 6d are con-duc-ting, the capacitor 69 will be gradually chaxged with plus on the ~ eft an~ minus on the righ~, ~snd when ~e SCR I s 64 and 66 are conducting the capacitor 69 will grad-ually be char~ed to the opposite polarity with plus on the right and minus on the le:Et~ When SCR' s 64 and 66 are turned on, SCR's 62 and 68 will be re~rerse biased fox the period af time xe~ired for capacitor 6g tc) change back to a "zerol' potential , i . e ., from time ~0 to time t1 in ~igure ~A
which is about 2$ microseconds.
'~ile the poter~tial ac:ross commutating capacitor 69 changes at; a 10 kHz rate as ~hown in Figure 4A, the poten-tlal as viewed rom the top and bottom terminals of the di~norld bridge 60 will be as shown in Figure 4Bo Each klme ~he condu~tion~ of the SCR' s are switched, the capacltor wi~ Lnstantaneously be ~onnected in reverse po:lari~ and wil~ then gradualïy charge to the proper positive polarity at which time tlle conductions will again be swi tched . A8 can be seen from a comparison of Figures 4A ans~ 4B, the po-tenkial at the top and bottom terminals of the bridge circuit 60 will ~witch at a 20 k~I2 rate eve~ hough the switchlng réç[uency of the individual SCR's is only 10 kHz.
In the next bridge 70, SCR' s 72 and 78 are conducti~lg du:rin~ a first period and SCR's~ 74 and 76 are conducting during a second period in the same mamler as in bridge circuit 60. I the :Eiring times of the SCR' s in respective bridge circuit~ 60, 70, 80 and 90 are phase~lisplaced by 90~, th2 voltage~ as seen from the ~op and bo~om (input and out~ut;) $erminals of e~ch of the respeckive bridge circuits will be as shown in Figures 5~-5D. Since these cliamoIld bridge cixcui ts are com~ected in ~erie~, their 1~

'7~

top~to-bottom voltayes will be added and the Volt:aCJe as seen from the input to inverter S0 to the ou~put o~ inver~er 90 will ~3e as showIl in Figure 513 and will have a :~requency of 4 x 20 ~æ - 80 l~Iz. The ramp in Figure SE is four times a~
s ~eep as ~he vol ~age r~mp for any i.ndividual bridge, SiIlCP
the series chain of four e~[ual capacitors 69, 7g, Bg and 99 ill haYe an effe~tive c`apaci~ance o:E one-:~ourth ~ha~ o any individual capaci tor . Thus, although no switching eïement s~pera~;e~ a~ a rate greater than lû k~z, an 80 k~Iz supply is genera~ed.
~ lthoug.h our diamond circuits have been u~ed in the embodi-ment sho~m, it should be ~ppreciated that the prirlci~
ple8 o:f the pre~erlt invention are applicable to an~ series connect.ion of N diamond circuits, where N is any integer gr~ate:r than ~ O The f iring of each diagonally opposi te pair :in a~ one diamond circuit would be substazltially simul-tane-ous and 180 out-of-phase with the firiny of the opposite di.agonal pair, and the Eiring times o:E correspo~ding ~hyxi6~
tors in di:fferent di~unond circuits would be pha~e~offse~c by 180~fN. The resulti~g re$Iue~cy would then be 2N times the operat;ing f:re~uenc~ of any individual thyristorO
~ n the e~odiment of Figure 3, the high :Erequency v~l ~age acros~ the ~eries chain is used to drive a tank ci:~cuit load 109 represente~ by capaci~or 110, inductor 112 and resistox 114. The high fre~ency voltaye is coupled to -~hi~ ~e~onarlt load through capacitor 116 and a transmission induc~ance :1.18. Cal?acitor 116 i~ a DC blocking capacitor and ~hould have a value larger than the equivalent capaci-tance o: the diamond chain, and inductor 118 ~hould bematched to the e~:livalent c:apacitance of ~he diamond c:hain 1~!

z~

so ~ha~ ~ey will ring together at appxoximately -~he reso-naIlt frequellcy of the ta~lk circuit 109 . Thus ~ a resonanlt hal:~ ~ine wave pulse ~ill be supplie;l to the tank circuit e~ch timP one of the ~sridges i~ switched. It should be appreciated that the prasence of capacitor 116 and indllc-tor 118 will slightly distort the linear charging of the capacitors shown in Fi~ures 4 and 5, but the overall opera-~ion is essentially unchanged.
The requency at the load will be xelatively high and i t is therefore necessary to compensate for induc tanee that exis~ be~ween the fre5~ency converter and th2 load. Fur-thex, the :Load is oten an inductive load such as a coil.
Since this load may be as much as 25 :Eeet or more away from the power supply, tbe tank circuit lOg i8 provided to reduce ~he volt amperes that must be delivered from the power supply to the work coil. The leading power factor eurrent of the capa~itors in parallel with the load canc:els all of the inductive cuxrent drawn by the coil. The power supl?ly will theIl see only the resistive component of the load which is 5 percent of the coil volt amperes, so tha t the SCR ' s need only be 5 percent as larg~ a~ ~hey ~ould be with no load capacitors.
~ s described above, it is desirable to e~ci te the resonant tank circuit on a regular basis with a relatively narrow cuxrent pU15e!. ~owever, as ~ practical matter, the ~vailable voltage 2nd the minimum transmission inductance are such that it i.s no-t possible to create large discontin-uous current pulse~ wi~hout exce~ive voltage, and thiB iS
especia~ly txue at higher power levels. The half sine wave ~urrent pulse created by the fre~ueney corl~7erter sy~t~m according to ~he present invention has a char~c teri tic impedaIlce of:

2 ~

where C is t}le e~ivalent capacitance oiE the diamond chain.
C mus~ be fairly large in order to store high ener~y because the vol tage is limited by the SCR ' s to a rarlge of 600 to 1000 vol~s divided by a saety factox. ~iven such a commlltating capacitance, L must be extremely low to c:reate a txansmission pulse that is narrow, i . e ~, a sine wave half c~cle whos2 natural fre~[uency is:

~or example, t~ create a half sine wave pulse o:E current which is 10 microsec:otld~ w:ide with an e~uivalent c:apacitance of 10 microfarad~ requires a total con~t.ruction and t~ans-mission inductan~e o~E 1 mierohenry. This satisfles a 50 kHz load. At. 100 k~Iz and the ~ame power, the e~uivalent C i~
5~1fd and L is 05 ,u~. Such a low inductance is difficul~ to achieveO
Instead7 with the DC blocking capacitor lt6, a cog~tillu~
ous sine wave current throu~ the diamond cllain panel inductance, the transmissic)n inductance 118 and blocking calpacitcr 116 and the diamond chain equivalerlt capacitance ean be gen~rated ~inee the nonnal reactance ~L = jw~, 72~

is compen~ated by X~
~.
Thus, by operating ~he diamo:nd chain in continuous current a full sine w~ve current flow~ by ~superposition through the di~nond c:hain. The cuxrent is aIl 80 k~z wave in ~e ~ase of 4 diamonds wi~ ~CI~ ' ~ fired ~t 10 klE~z, the 80 k~Iz current reduce~ the total current through the SCR I s to near ze:ro prior to firing of 2ny SCR, reduci:llg sw:Ltching losse~ .
ïn pre?aratioal or start-up, all o:E the SCîR'~ on the left-hand side of the ~ridge circuit~ are ~urned on and th~
cornmutaking capacit~r~ 69, 79, 89 and 99 are all charged wi th a higher potential on ~he ri~ht and a lower potential on the left~ The charging of ~hese capaci~oxs is accom-pli~hed via resis tive charging circuits coupled be tween thlS
positive and negative d . c . bus lines . For exampl~ ~ capaci~
tor g9 i5 charged ~hrouyh diode 140, xesistor 142, resis-tor 14~ ~nd ~iode 1~6. The vol~age on thP xigh~ ide of capaci~or g9 will be determirled by the voltage divider compri~ing re~ ors 142 and 148, a~d the p~tential on the :1 eft~haIld side of capacitor 99 will be substantially the po~ential o ~he negative bus line 52. Similar chargirlg circuits are coup:Led to the remaining three ~alpaci-l:oxs 69, 79 and 8~, but ~hese have been omit~ed ~rom ~:igure ~ in the .interest o simplification.
When ~he inviSxter is ~arted, SC~' s 62 aIld ~8 will be ired di~charging the charge on the riyht side of capaci--~or 69 ~rough ~he coIlduct:ing SCR ' ~ on ~he le:~ side~ ~3f ~5 each of bridge circuits 70, 80 and 9û~ The negative poten-~ial on the le:t side of capacitor 6g will inst~ t~neously drag down the potential on line 50, ~nd this po~e~ ial will -~hen be gradLIally replenished by the constarlt current 50urce. Once the capaci~or ~9 has :become fully c:haxged with positive on the left and mi~us on the rlght, SCR's 1;4 aald 66 could be ired to r verse the process, and ~he xesulting pot;erltlal on line 5û would be ~ t~tially as shown in Figure 4B. However, th~ operation o~ the remai~in~ bridse circuits 70, 80 and 90 will furkher increase th~ resulti:ng ~re~lency a~ will now be described.
Ater SCR's 62 -and 68 have been fired a-t time to~
SC~'s 72 and 78 are fired 45 degrees later and the positive charge on the xight side of capacitor 79 is discharged to the negative bus line 52 while the negative ~harge on the le~t ~ide of capacitor 79 will instantaneously drop the poten-~lal on ~he positiv~ bus line 50 ~hrough conducting SCR's 7~, 68 and ~2 and capacitor ~9. ~his resul~s in a drop o ~h~ voltage on the posi~ive bu~ at ~ime ~ ime t~ SCRI~ 8~ and 88 ar~ fired, and at time t3 ~CR9S 92 and 98 are fired. The second half of the cycle beg.ins at time t5 when SCR~s 64 and 66 are fired discharging ~he positive charge on the le~t ~ide o~ capacitor 69 through ~he lower three bridge circuits and instantaneously coupling ~he low potenkial on the right sid~ of capacitor 69 ~o ~he posi~ive bus t}lrough the conducting SCR 64. SCR'~ 74 and 76, B4 and 86, and 94 and g6 are subseguently fired at 45 degree inter-~als as in ~he first hal cycle of operation, and the re~ult is a poten~ial across ~he upper and lower ~erminal~ of the ~iamond change which appear~ as ~hown in Figure S O

~ ach thyristor firing results in a ~ ine wave pulse ~hich is ~ed to ~he tank load. During the îirs t half cycle the curr~nt from the ~ource and ~he load flow through the di.amond chain~ Durin~ the second half cycle -~e :Load currenk ~ubtrac~s fxom the d. c . curren~ source reducing ~e net thyristor current to near zeroO The tank circuit rings wi~h ~ very nearly symmetrical sirle wave. As shown in F.igure 4B, ~le tur~off time provided for each diamond SCR
i6 -the period o: time during which the voltage of Figure 4B
is negative. With four diamond circuits being used as in Figure 4, the fre~uency of each diamo~d bridge will be one~fourth of the ~xequency oî ~e tank circu1 t, and the turn-of:E time for each SCR will thus be two complete cyc1e~
o:E th~ tank circuit osci11ation. For examp:Le, if the ~rn--off time required fox each SC~ is 40 microseconds, the tank cs~c1e can be 20 microseconds, or 50 ki10cyc1es~ If the SCE~ turn~ time re~uireme~t is only 1~ microseco~ds , e , g., with ~: C394 SCR's, four series-connected diamond bridges can gener~te a tank reguency o (1/705~ = 133 k~z.
Since the circuitry o Figure 4 p~rmits such a long ~urn-o:E ~ime, eveIl with an open circui~ r a short cir~uit, or a purely re~istiv~, inductive or capacit~e load, the in~erter SCR's are assured of adequate turn-off time.
The inverter circuit of Fisure 3 is intended to operate a d.c. bus vo1tage of between 600 and 1,000 vo1ts.
~owever, ik is pos~ib1e tha~ some ma1function may re~u1t in an ov~r vo1tage on -the posikive bus line, e.g., a disconti~
nuity in the diamond chain current, and such ~n over ~o1tage may damage the SCR's i.n the diamond chain. ~ccordiny1y, over vo1tage protection cir¢uitry i provided in the ~orm of 6'7~
an additional SC~ 160 which will turn on and shor-t out the positive and negative bus lines whenever the voltage between those t:wo lines ex~eeds a predetermirled value. A voltage divider formed by re~;istors 162 and 164 and poten-~iome-ter 16~ determine~ ~e value at which the SCR 160 will turn on. When this excessive level is reached, di~c 168 will fire thereby turning on SCR 170 which, in turn, will txigg~r S~R 160. SCR 170 will never be reverse bias d and will mairltain SCR 160 in conduction even if the bus pots~nti~l su:bse~uently decreases to an accep~table level.
~ lthough shown only in c~nnection with SCR 96, it should be noted that small ~erri~e ~aturatiny reactorg 172 are provide~ in series with all SCR'~ in ^the diamond chain.
rhe pr-imary purpose of ~ach such saturating xeac tor is to limi t the reverse current through the SCR ' s wh~n an event occur~ which creates a rever~e voltage across these devices.
For example, when SCR' s 64 and 66 are fired, the voltage stored on capacitor 69 is instantaneously connected in reverse polarity across SCR's 6~ and 68, and it is possible that a high current spike could damage these SCR ' s Imles~
the saturable xeactors are pxovided.
Although in the ~bove description the resonant load is to be pulsed once during ever~ oscillation cycle by firing diagonally opposite SCR's in each bridget it is al50 possi-ble to hold the charge on some or all of the bridg~ capaci-tvrs by firing onl~ one SCR of a particular bridge. For example, in F.igure 3, SCR's 64 and 66 may have eharged their capaci~or wi~h a plus po~ential on the right and minus on the left, and if only SCR 62 is subseguently fired, SCR 64 will ~e turned off and SC~' 3 ~2 and 66 will conduct. The po~itive charge on the right side of capaci~ox ~9 will be , ~e~, ~&6~21~
held and the source current will be provided to ~e remain~
ing bridges via SCR' s 62 and 66. II~ this manner, eners~y sent to khe tanlc circuit may be SIUickly ~tarted or s topped, or a pulse caIl be clelivered every slecond or ~ixd oscilla-tion of a very high fre~auency tank . I f the commu-tating capacitances and transmission inductance are selected such kha-t the half sine wave pulse is very narrow, a very high fre~ency tank can be us~d while maintairling even lower SCR
switching speed~;.
The constant current sollrce which faeds line 50 and 52 may be any one of a wide variety ~ known sources, but a current source ound particularly suitable for ~he inver~er circuitry of the present invention is shown in ~igure 6.
Three phase power is supplied to texminals 200, 202 and 204, and this three~phase voltage i~ supplied through rectifying diodes 206 to an upper line 207 and the negative DC bus line 52. The input line reactors 208 and the smalJL capaci-tors 210 in parallel with each of *he rectifying diodes are provided ~r the purpose of suppresslng transien~s which may occur due to other e~uipment coIme ::ted to the power li nes .
~he ~oltage ~n line 207 is coupled through inductor 21~ ~o one side of d. c ~ bus capacitor 214 . DC bus capacitors 214 and ~16 are therl ~harged via resi~tor 218 for a short period o time after which switch contacts to 220 are connected to short out the resistor ~18, leaving a substantially constant ~00 vol~ po~ential on the left side o~ fuse 222.
~ he constant current source of Figure 6 includes two di:Eferen~ circuits 230 ~ and 232 each of which essentially compxises a separate constant current sourc:e, and the ~wo circuits are operated at a subs~aIl~ially 90 degree phase difference to minimize ripple in the current supplied.

67;~
Initially, control circuitry to be described in more detail lat~r preverlts firing o INC--l until commutatin~
r~apac:i~or ~4 is ully charged. With both I:~C~l and DEC~l non~conducti:ng, the capacitor 234 is charged through diode 235 and resistor 237 rom the positive bus line and diode ~39 in resistor 241 to the negative ~us lineD When the po ~ential across capacitor 234 xeaches a pr determined level wi~ plu~ on the left and minus on the right, INC-l is fixed ar3d current is supplied through dlode 236 and in~uctor 23~ to the currexl~ source output terminal 50. ~ ~his time, ~he positive charge on the let side o commultating capaci-tor 234 iLS wrung around through irlductor 240 and diode 242 until capacitor 23aJ~ r~ache6 a charging state ~Jith plu~; 011 -~e righ~ side and minu~ on the l~ft side.
Cuxrent throu~h the main inductor 238 is measured by currenLt measuring dè~ric2 244 (HALL-2 ) . The ~en~ed current i~; fed to a current regulator which controls the OIl off .ratio o INC c:o~Lduction time within a carrier frequency period which is a submultiple of ~he high fre~ency irl~er~er frequency. A c:ontrol circuit fires DEC-l and the capacitor .~34 atke~np~ to discharge backward through INC-l, therel: y ~urning of I~tC~l. With DEC-l conducting, the posltive c:harge on the right side of capacitor 234 will then d:iLscharge throllgh the main inductor 238.
When the c:harge on ~he capacitox 23~ decrea~e~ to the level of the negative bus, c:urrent will cvntinue to :Elow ~hrough induc~or 23~ ~nd will be pro~rided by the free-wheeling, diode 246. With DEC-l conducting and INC-l non-conducting, t}le current supplied through inductor 238 will begin to decay until it reaches a prede termined value ~ $~

b~lr)w ~he de~ired constant current, at which time I~C~:I will again be fired and the cycle will be repeated.
The circui~ 232 unctions in a sub~tantially id~ntical marmex with ~e firing of INC-2 and D~:C~2 beirly contro:l led in accordance with the aurrent level detected l~y currenk moni tor 248 (:E~ALL~l ~ . The operation of circui~ ~30 and 232 are main-tained substantially 90 degrees out-of~pha~e E;O that the current at the output oiE ind~ctor 238 will be inc:rea~ing while -the current at the output of inductor 250 i~ decxeas-ing; and vic:~ ~ersa, and the ~wo currerlt output~ are super posed OIl one another at the output terminal 50.
~ s described above, small saturable reactors axe pro-vided in series with all SCR ' s and in series wi th ree-wheeling diode~ 2~1j and 252 in order to prevent ins~antane~
ow~ly large rever~e currents ~rom burning out the ~micon-ductor~ For example, when INC~l is ired, ~he fre~
wheel.ing diode 246 becomes reverse biased and, ~ince the diode doe~ not immediately bl ock xeverse voltage, something is need2d to lin~it the reverse current for a few microset::-onds. Similarly, the` saturable reactor coupled to ~he ca~hode of INC~l :Limit~ the reverse current thrc)llgh I21C~l wlhe~ DEC~ fired, and saturable :reactor 254 will limit the reverse current through l)~:C~l when INC-l is :~ired~
Capacitors ~56 and 258 are provided for the purpose of o~er vol~aLge protection and~ also serve to some exterlt to fuxther red~ce thl ripple in the constant c:u~rent. For e~c~ple, i:E a baclc emf is generated at terminal 50 due to some occurrence at; the load or some loss of synchronization, th2 currerlt being supplied through inductor 238 will gener-ate a very high vo~ age at terminal 50 which may damage the , , 7~
diamond chain~ Accordingly! capacitor 256 is cou~pled be~
tween the ~o inductors 2381 and 2382 ~ and ~e size of capacitor 256 is made very large so that it is capable of absorbing a subs tantial charge without generatin~ an e~cces~
slve vol~:age. Capaci~or 258 ~nc:tlon~; in a similar manner.
Figures 7 = 16 illus~rate coIltrol circuitry for ope:ratirlg ~he inverter shown in Figure 3 and the constant current ~ource o:f ~igure 6.
Figure 7 illus trates one example of pswer supp:l y cir ::uitry which can be used to generate supply ~oltage~ for the control circuitry. Substantially xegulated il5v is gener-ated at the out~ut terminals 300 and 302, and a filtered ~24v supply for the SCR pul~e amplifiers i~ pxovided at ~enminal.304.
E'igu.re B illustr~tes a typical pul~e ~mpliier used to generate ~ixing pulæes ~or each of the SCR'~. ~ separate pulse ~mplifier such as tha~ ~hown in Figure 8 will be re~lired or each SCR in the ~y~tem, and a pulse signal receiv~d at input terminal 305 will be amplified and ~up-pl.ied from output terminals 306, 308 to a well-known pulse transfo~mer which, in turn, will supply ~he firing pulse to the appropriat~ SCR.
Figure 9 illustrakes logic cîrcuitry for delivering the timing pu~e~ to the appropriat~ SCR pulse ampli~iers, wikh -~he output~ of NA~D gates 310 being coupled to ~he pulse amplifier input 305 (Figure 8~ o an appr~pria~e SCR. When the in~erter is o~, switch 312 is in its downwar~ positivn as shown, and the output of NAND gate 314 is low, This will result in a high level output from eac~ o NAND
ga~e5 316~330~ ~ low level signal a~ ~he ou~pu-t of gate 31 wlll also resul t in a high level output from gat:e 331, 80 'chat a di ther signal applied to termin~l 332 will !be passed thxollgkl gate 334. Thi~ dither si~al will b~ pas~;ed through altexIlat~ NAND gates 31û to maintairl all SCRI ~ on t:he left side of the diamond chain i~ conduckion. The dither sigTlal is synchronized with the firing tinnes o~ ~le IP~ and DEC
SC~I s in each corlstant current circuit ~o ~ha~ a coIlduc~ion pa~:h :Eor the 5C~'s is maintained.
The dither signal to tenninal 332 in Figure 9 can be pro~visled by a fiimple oscillator circuit ~uch ~ hown in Fi~re 11 which is driven by the fixing of the curr~nt ~ource chopper SCR's.
Whell th~ in~erter is tuxned on, ~e switch 31;2 is moved to i ts upw~rd po~ition an~ a high level si~al will be present at the OUtpllt of gate 314, thu~ b~ocking the dither anà maintaining a constant high level outpul: si~al from cJa~e 33~L. Under ~his condition, the firirlg of opposite SCR ' s 62 and 68 will be determined by the lower inpu t to ate 316, the firing of opposite SCR' s 64 and 66 will be de-termined by the signal applied to the lower input of N~ gate 318, etc., with diagonally opposite SCRI~ in each diamond ~e.g. ~ SCRis 62 and 68~ always being :Eired simul-taneously. In ~he embodiment shown, each of gates 316~330 i~ provided with a 12 . 5 kEIz si~al with tlle si~als applied to yates 316 and 318, 320 and 322, 324 and 326, and 328 an~
330 being 180 degrees out~of~phase with respect to one another and the signal~ app:l ied to gates 316, 3~0, 324 and 328 ~eing successlvely off~et by 45 deS~rees with respect to one ano~er as ds~scribed above in comlectiorl with F:lgu.re 3.
~ igures 10~ ~nd lOB illus~ra~e oscilla tor and divider circul try which may be used ~o supply the enabiing signals 2~

to gat~es 31~ 330. Figure lOA illu~trates a high :Ere~ency oscill~tor wh.ich provides a 100 kHz ~ignal a~ it~ QUtpUt terminal 340, and this signal i~ used to c~ oek our JK
:~lip~flops 342 ~ 3~4, 346 and 348 . With the circui try con-nec~d as sho~m, ~he output of eaf~h of the ~our flip~flop~
will change a~ a 12 . 5 ~Iz rate and the Q and Q ou~pu~s o~
each flip~ïop will :be 180 d~grees out-of-phase. According-~y, ~he Ql and Q1 ou~uts of flip-fïop 342 can be provided ~:Q gate~ 316 and 318, respectively, the Q2 and ~ ou~puts of flip~Elop 344 can be supplied ~o gate~ 320 and 3~2, respec~
tc.
Flgure 12A illustrates a circuit ~uitable for detecting the ~oltage across capacitor 234 in ~igure ~. ~hen ~h~
voltage reache~ a pxedetermined level, an enabling signal i~
prov.ided at term.inal 350 so that INC~l may be fired when appropria~e. ~n identical v~ltage detection and ~NC~2 enabling cixcuit as shown i~ Figure 12B axe pxo~ided in ~h~
second portion 232 of the constant current supply~
Figures 13A and 13~ illu~trate ~uit~ble curre~t detec~
tion circuits 248 and 244, respectively~ of Figure 6.
small semiconductor element, e.~ dium pho~phide~ 354 will measure the flux in ~he air gap of a small core and genera-~e a corre~ponding voltage which is applled to the inpllt te~inals of an operational amplifier. The sig~al at ~le outpu i: o:F amplifiex 35~ in Figure 13A will be propox ~ional to ~he current supplied through inductor 250 to the outpu~ kenminal 50 in Figur~ 6, and the siynal at th~ out~ut of amplifler 358 in Figure 13B will be proportional to the cu.rrent ~upplied t~lrough inductor 238 to the output ~ermi-nal 50 in Figure 6.

72~

Fi.gure 14 illustrates feedback circuitry for control-lirlg ~he :Eiring times of the eurrent source chopper SCR ' s .
,~3npli:Eier 360 provides an ou~put prcporkional to the voltage ~F~.3 across ~he dic~nond chain in Figure 3. This is compared in ampli:ier 362 with a reference pot:e~tial from potentiome~
~er 364, and the output o ampl if ier 362 i5 ~hll5 propor-kional to the differeIlce betweerl fhe desired and actual potential across the inverter. A portion o:~ thi5 signal iB
compa:red in amplifier 366 with an output from current sen ~or 248 in E'igure 6 ~ and is al~o compared in amplifier 368 wi th an ou tput from curren~ ~ensor 244 in Figu:re 6 . The outputs of these two amplifiers 366 a:nd 368 constikute error s:ignals for indicating when the current provided through ei~her of circuits 232 or 230, respectively, should be increased or decxeased.
Figures 15A and 15B illus~rate circuitry for generating fixing pulses to ~he consta~t current source chopper SC~' 8 .
The ou~put of amplifier 370 in Figure 15A will be a ~aw ~oo~h, and amplifier 372 will provide a square wave ou~put by performing a thxeshold detection on ~he saw~ooth. The threshold is vari~ble in accordan~e with the error ~ignal -I ~ xom the output of ampli~ier 366 in Figure 14~ ~ that ~he duty cycle of ~he square wave output rom amplifier 372 can be adjusted :in accordance with ~his error si~nal~
AssumLng -~.hat INC-l has been ~nabled by the ~ircuitry of E'i~uxe 12~, a high output ~rom amplifier 37~ will result in a ~iring sîgnal being provided from NAND gate 374. At ~he end o the INC-l firing pulse, the low level signal .~rom the I~C-l pulse amplifier will then result in a high le~el signal at the output of gate 376 so that a subseg~ent DEC

2~

~SET-:l pu:Lse will ~ire DEC 1. The RESET~l pulse is gene~
rat~d by the circuit shown in Figure 16A, with ~he input s.ignal to ~he pulse ampliier in Figllre 16A being provided from terminal 380 in Figure 10B.
~ he operation of ~he cir~uitry i.~ ~igure 15B is similar to that ~hown in ~igur~ 15A with the DEC R13SET-2 pulse being provlded by ~he pulse amplifier of Figure 16B~ The input to the pulse amplifier in Figure 16B is provided :Erom the output 3~2 in Figure lOB and is ~hifted by 90 degrees with respect to th~ i~put to the pulse amplifier of Figuxe 16A~
As desc:ribed above, small saturable reactors are pro-~ided in series with each of the thyristors irl order to p.revent substantial reverse current spi]ces from damaging the ~h~ristors. ~he possibiLity of current damage to the t~y ristors can be ~ubstantially f~lrther xeduced by Q novel ~ixing control technique which will now be described. One o~F the limitatioll~ in u~:ing thyristor switching elemexlts i~
the di,/dt which an~ given thyristor is capable o ha~dling.
~rhis is most serious when the ~yristor is in a ull forward conduction mode and it is turned off by applying a reverse lbias across the thyris ~or . With the thyri~tor condllcting a large forward curxent vaîue, there is a relatively high concentratlon of carriers availak:le, and these carriers c:an be instantly made to conduct a high rev~rse current in the olppQSite direction i:E a rever~e p~tential i~ applied as is conventional in SCR inverters. ~t high current and pow~r leve!l8, this phenomerlon can be extremely tro-lble~om~.
Applican~ has devis~d a techniqu~ fGr firing one pair o:f the cliamond SCR9 s at a time when t:h~ ma~itude o~ the :Eorward curren~ of khe other conduc~ing pair is at a minimum, thu~

decreasing the number of carriers av~ilable for reverse cur.rent conduction at the time the reverse potential is applied. This makes the SCR much asier to turn off and reduces the magnitucle of a po~sible reverse current spike.
As discussed above, the voltage across the entire series diamond chain will have a frequ~ncy o 2N ~imes ~he switching freguency of any individual thyri~tor~ where N is th~ number of diamond ircuits in the chain. Thus, assuming a substantially 50 percent duty cycle for each individual thyristor, ~he voltage across the diamond chain will fluc-tuate N time~ during the "on" time of each thyristor, as can be seen by comparing igures 5A and 5E~ Due to ~his vari~
tion, the current through each SCR will fluctuate, and appl:icant has found that by firirlg an SC~ when its orward current flow has fluctuated to a minimum value, the di/dt resu:Lting fxom the application of a reve~se ~oltage will be minimizecl and the SCR can be turned off more quickly, and .reverse recover~ currents minimi~ed.
Figure 17 illustr~tes an approximate current waveform or an individual thyri6tor in a dia~ond chain inverter having two diamond circuits. The SCR i6 turned vn at time t~ at which time the current is at a substantially zero level, and ~he forward cuxrent flow through ~he thyristor ~hen fluctuates according to a waveform substantially de-fined by 1 ~ cos wt. At time tl in Figure 17, the forward current flow through the thyristor will have ~ecreased to a minim~ value, and firing t.he thyristor at this time will result in ~he smallest possible di/dt and the quickest turn~off time.
A ~imple techni~ue for implementing this firing con-trol is br.iefly illustrated in ~igure la. If, for example, the 6~o~

resona:rlt :requency of the load is approxirnately 50 kHz I and if -the diamond chain consists o:E two diamond circults con-nec ted in serie~;, the operating fre~auency o each individual thyristor will be substantially 12 . 5 kEIz . 3Foir the sak~ o simplici-ty, figllre 18 illustrates the timing control cir-cui try for only a single one of the thyristors in the dia~
mond chain. In fi~re 18, an oscillator 400 having a rela-tivel~y high operating fre~uenc:y, e . ~. lO0 ~s~z, will provide a source o:E pulses to the cloclc te~minal input of a cnun-ter 402. The ou~ut of counter 402 is provided to a de coder 404 which provides an output pulse each time the couIlter ~02 reaches a value of eight, so that the outpu~
pulse .~rom decoder 404 will occur at a rate o:E 12 . 5 kHz .
T}lis output pulse will be pxovided through 0~ gate 406 to the pulse amplifier of the appropriate SCR. ~hus, absent any furth~r controls/ thc SCR will be ~witched at a 1205 kH2 xaLte and the overall diamond chain freauency wil:L be 50 k~Iz.
A sensor 408 can be used to monitor the current ~hrough the appropriat:e thyristor and provide an output si~al each time the current begin~ to increase, thus indicating that the 13w point in the forward current level has ju~t been reached~ Thi~ se~sor output signal could be provided thxough a ~uitable di~ide-by-two circuit for 10, e O g. a simple flip-flop, so tha~ a firing pulse signal will be provided through th~ gate 406 to the appropria~;e puls~
ampïifier, and the counter 402 is simultaneously reset to provide syrlchronization betwee~ ~he sensor and counterO It is pre:Eexable to have the oscillator 400 operate at a fre-qUeTlcy slightly below 100 k~z so that ~he outpu~ :Erom divi-der 410 will rese~ the counter and provide the proper firing 7:2~

pulse immediately before the counter reaches the :iring value of eiqht, and in this way the operating fxe~ency of the diamond chain will be self~controlled, i . e O it will :b~
automatically controlled to operat~ at substarltially the resonant frequency of the load.
While on.ty a single embodiment of the irlvention has been described and illustrated, it should be appreciated tha-t a vari~ of chaxlges could be made without d~partiny ~xom khe spirit and scope o the imventiorl. For example, the series chain of diamond circu~ts could be coupled in series w.ith a transformer primary, with the sec:ondary o the transformer supplying the current pulse~ to ~ xesonant load. As long as a series di~ond chain is employed as d.isclosed above, conventional SCR ' s can be used to generate very high fre~uency pulses to a resonant load while mini-mizing circuit complexity and cost.

~9

Claims (18)

WHAT IS CLAIMED IS:

1. A solid state frequency converter comprising:
a diamond chain including a plurality of N diamond circuits coupled in series, each said diamond circuit com-prising a capacitor having first and second terminals and first through fourth unidirectional switching elements each having input, output and control terminals and conducting from input to output in response to a control terminal signal, the input terminals of said first and third switch-ing elements being coupled together to form a diamond cir-cuit input terminal, the output terminals of said second and fourth switching elements being coupled together to form a diamond circuits being connected in series;
constant current source means for providing a substan-tially constant current to said diamond chain;
means for providing control signals to said switching elements, the control signals to said first and second switching elements in any one diamond circuit being substan-tially simultaneous, the control signals to said third and fourth switching elements in said one diamond circuit being substantially simultaneous and 180° out-of-phase with re-spect to said first and second switching element control signals, and the control signals in each said diamond cir-cuit being shifted in phase with respect to the control signals provided to the switching elements in the remaining diamond circuits, thereby generating a voltage across the input and output terminals of said diamond chain which has a frequency of 2N times the switching frequency of any one switching element; and a resonant load coupled to said diamond chain.

2. A solid state frequency converter as defined in claim 1, wherein said resonant load is coupled in series with a DC blocking capacitor having a capacitance value greater than the equivalent capacitance of said diamond chain capacitors whereby said DC blocking capacitor will pass to said resonant load only an AC component of the voltage across said diamond chain, the series connection of said DC blocking capacitor and resonant load being coupled in parallel with said diamond chain.

3. A solid state frequency converter as defined in claims 1 or 2, further comprising means for preventing the build-up of excessive voltage across said diamond chain.

4. A solid state frequency converter as defined in claim 1, wherein said protection means comprises an over voltage protection switching element having input, output and control terminals and conducting from input to output in response to an over voltage control signal; and means for generating said over voltage control signal in response to an excessive voltage across said diamond chain.

5. A solid state frequency converter as defined in claim 4, wherein said means for generating continues to generate said over voltage control signal even after the voltage across said diamond chain drops below said excessive voltage.

6. A solid state frequency converter as defined in claims 1 or 2, wherein the control signals to corresponding switching elements in different diamond circuits are offset in phase by 180/N degrees.

7. A solid state frequency converter as defined in climes 1 or 2, wherein said resonant load is a tank circuit having a resonant frequency of M times the frequency of the voltage generated across said diamond chain, where M is an integer greater than 0.

8. A solid state frequency converter as defined in claims 1 and 2, further comprising saturable reactors in series with each of said switching elements.

9. A solid state frequency converter as defined in claims 1 or 2, wherein said constant current source means includes a first constant current circuit comprising a first inductor and first and second chopper thyristors for con-trolling the current through said first inductor, said chopper thyristors being fired at substantially an integer submultiple of the frequency of the control signal applied to one of said switching elements in said diamond chain.

10. A solid state frequency converter as defined in claims 1, or 2, further comprising monitoring means for monitoring the voltage across said diamond chain; and control means for controlling the value of said con-stant current in accordance with said monitored voltage.

11. A solid state frequency converter as defined in claims 1 or 2, further comprising means for inhibiting the control signal applied to one of said first or third switching elements in at least one of the diamond circuits of said diamond chain to thereby hold the charge on the capacitor in said at least one diamond circuit.

12. A solid state frequency converter as defined in claims 1 or 2, further comprising means for monitoring the current level through said first through fourth switching elements, said means for providing control signals being responsive to said monitoring means to provide control signals to said first and third switching elements when the current level through said second and fourth switching elements is at a substantially minimum value, and to provide said control signals to said second and fourth switching elements when the current level through said first and third switching elements is at a substantially minimum value.

13. A solid state frequency converter as defined in claims 1 or 2 wherein N=4, with pairs of diamond bridges operating in unison, i.e., two diamonds firing as a group and two other diamonds as a second group to obtain a chain voltage that is twice as high at half the frequency of four phase shifted diamonds.

14. An inverter to convert D.C. to high frequency A.C.
for use with induction heating equipment, said inverter com-prising: a diamond chain including a plurality of N diamond circuits coupled in series, each said diamond circuit com-prising a capacitor having first and second terminals and first, second, third and fourth unidirectional switching elements each having input output and control terminals and conducting from input to output in response to a control terminal signal, the input terminals of said first and third switching elements being coupled together to form a diamond circuit input terminal, the output terminals of said second and fourth switching elements being coupled together to form a diamond circuit output terminal, the output terminal of said first switching element and input terminal of said fourth switching element being coupled to said first capacitor ter-minal, and the output terminal of said third switching element and input terminal of said second switching element being coupled to said second capacitor terminal, said N diamond circuits being connected in series; power supple means for providing a substantially constant current to said diamond chain; trigger means for providing control signals to said switching elements; and, a generally resonant load coupled to said diamond chain.

15. An inverter as defined in claim 14 wherein said trigger means includes a sensor circuit for crating a sense signal at a time of low current flow through a portion of one of said diamond circuits, and means responsive to said sense signal for crating control signals to change the current flow through said one of said diamond circuits.

16. An inverter to convert D.C. to high frequency A.C., for use with induction heating equipment forming a resonant load having a given frequency, said inverter comprising N
capacitors formed into a series circuit, wherein N is an integer greater than one; current source means for charging each of said N capacitors to a predetermined voltage level in either of two opposite directions by current flow through said series circuit; switching means for selectively con-trolling the direction of the current flow through each of said N capacitors between said opposite directions in re-sponse to a trigger signal whereby the voltage across said series circuit is pulsated; control means for producing a series of trigger signals in a preselected controlled se-quence for each of said capacitor switching means; and means for coupling said pulsating series circuit across said re-sonant load.

17. An inverter as defined in claim 16 wherein said switching means in response to said control means changes the direction of said current flow through each of said N
capacitors once during the period in which the direction of said current flow through all of said N capacitors is changed once.

18. An inverter as defined in claim 16 wherein said switching means in response to said control means, changes the direction of said current flow through a group of at least two of said N capacitors substantially simultaneously once during the period in which the direction of said current flow through all of said N capacitors is changed once.