CA1187962A - Matrix screening and grounding arrangement and method - Google Patents
Matrix screening and grounding arrangement and methodInfo
- Publication number
- CA1187962A CA1187962A CA000401393A CA401393A CA1187962A CA 1187962 A CA1187962 A CA 1187962A CA 000401393 A CA000401393 A CA 000401393A CA 401393 A CA401393 A CA 401393A CA 1187962 A CA1187962 A CA 1187962A
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- CA
- Canada
- Prior art keywords
- conductors
- conductor
- address
- potential
- reference potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
- G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
Abstract
Abstract of the Disclosure A capacitance keyboard matrix screening and grounding arrangement and method are disclosure in which scanning drive means and scanning sense means sequentially address drive and sense conductors in drive and sense conductor arrays respectively and maintain a reference potential on all conductors except for individual conductors while they are being addressed. The scanning drive and sense means are implemented with demultiplexers whose output terminals are each connected to a drive or sense conductor through an inverter.
Description
MATR~X SCREENING AND GROUNDING ARRANGEMENT AND METHOD
~/~CKORO~NO O- Tlil INVENTION
The inYention disclosed herein relat~s generally to a technique and impiementation foe p~eventing ~noesire~
in~erconductor coupling and spurious signals in a switching matrix, and more particularly to apparatus and a technique for eliminating cross talk, electrical interference and sensing ambiguities in a capacitive keyboar~d.
- Electronic keyboards have long comprised a primary form f inpu~ device for information handling and data processing f systems. With the proliferationtand technological advances such systems has come increased demands on the performance and durability of keyboard input devices~ Further, the rapid recent proliferation of smaller and less expensive systems requiring ~ J ~ n d keyboard inp~t devices has increased the --~s~e for less expensive keyboards.
Capacitive keyboards are well known in the field of da~a input devices~ They provide certain inherent advantages over electrical con~act keyboards. These advantages particularly include mechanical simplicity, long life and absence of electri-cal signal problems caused by contact bounce and corrosion.
However, as set forth in numerous publications, includ-ing U.S. patent 3,750,113 issued to J Cencel on July 31, 1973, and U.S. paten~ 3,921,166 issued to J. Volpe on November 18 1975, capacitive keyboards have suffered from another problem which is particularly significant in capacitively coupled sys~ems~ This problem stems from the fact that there is inherent capacitive coupling between every pair of elements in a keyboard.
Thus in a typical capacitive keyboard having a matrix of .' ~
C
conductors including drive signal and sense signal conductors, a signal on any conductor will normally appear to some extent on every other conductor. Obviously, this pheriomenon complicates the task of detecting which of an array of ~ariable capacitors between pairs of conductor~ in ;che matri~ is actuat~d, thus varyiny the capacitive coupling it provides.
As noted in the above~identified paten~s, a variety o techniques have been employed in an attempt to minimize problems caused by stray capacitive coupling~ These techniques include the use of ground lines interleaved between the drive and/or sense conductors, ground planes and various forms of shielding.
In addition, various electronic signal detection, verification and processing techniques have been employed to improve the reliability of detecting and distinguishing valid key actuation signals Erom signals caused by stray coupling. Some techniques represen~ative of this approach are disclosed in U.S. patent 3,931~610 issued to R. Marin, et al on Jan~ary 5, 1976, U.S.
patent 4 J 163,222 issued to D. Gove on July 31, 1979 and U.SO
patent ~l211,915 issued to D. Miller, et al on July 8, 1980, as well a~ previously identified patent 3,921,166.
All o the foregoing techniques involve the addition of elemen~s to either the basic keyboard matrix or the signal detection, veriflcation and processing circuitry~ Accordingly, these ~echniques are undesirable to the extent that they contrib-ute to ~he complexity, size, cost and potential unreliabllity of the keyboard systems.
~ In addition, all of these techniques suffer to some extent from an inability to effectively eliminate the basic problem of stray coupling and/or its effects on signal detec~ion Specifically9 although screening lines, ground planes and shielding do provide a degree of isolation oE individual conduc-Cr ~ g~
tors in ~he keyboard matrix, such isolation is not complete ands~ray coupling is not totaIly eliminated. With or without the use of conve~tional screening and shielding, electronic signal detection and verification is only effective to the extent that sigr.a'_ due ~c s a~ _oup'ins anc other eie-trica; interfelence difer from valid signals and to the extent that such differences can be feasibiy detected.
The present invention ;avoids-many of the principal disadvan~ages of the above-described techniques through the use of electronic grounding of inactive conductors in the basic keyboard matrix. Electronic grounding is simply accomplis~ed with a minimal addition o~ common electronic components. No elements are required to be added to the basic keyboard matrixO
Stray coupling is effectively totally eliminated. Finally, the O~o e, r cct~ c present invention inherently provides N-key rollover ~ee-~
SUMMARY OF THE_INVENTION
The present invention comprises apparatus and a methodfor effectively eliminating cross talk and interference in a capaci~ive keyboard of the type in which first and second sets of conductors are coupled by an array of key actuated variable capacitors such thât each capacitor couples a ~i-ffe~r~t pair of conduc~ors comprising one conductor from each set; and in which ~he sets o~ conductors are scanned to detect actuated capacitors.
In its most basic form, apparatus according to the invention comprises means for normally maintaining the conductors in at least the first set of conductors at a reference potential and sequentially permitting individual conductors in the set to assume a potential different from the reerence potential. The apparatus also includes a scanning detector for sequentially sensing the potentials on individual conductor~s and means for coordina-tillg operatioll so that the signa:l on each conduc-tor is sensed oll]y durirlg the time interval in which the conductor is permitted to assume a po-teiltial d-i-fferent from the reference potential. Pre-ferably both sets of conductors are normally maintained at the reference potential, and conductors in the second set are sequentially impressed with a po~ent;.al different :Erom the reference potential.
The method of the present invention basically comprises sequent-ially addressing individual conductors in the first and second sets of conductors by selectively supplying a drive signal to individual concluctor5 in one set and selecti-vely receiving a signal from inclividual conductors in the other set, while maintaini.ng a reference potential on all collductors except :Eor indiviclual conductors while they are being adclressed.
In accordance with the present :i.nvention there is provided capac:it:ive l<eyboa.rcl appara-tus comprising:
a matrix of capacitive key switches having first alld second sets of conduc-tors ancl a pl~lrality o:E capacitors, each capacitor havillg :fixed and movclble p:Lates, the fixed plates being connected to the :f:irst set of conductors and the movable plates being connected to the second set of conductors so that each capacitor is connected to a ~miclue pai.r of conductors n comprising one conductor from each oE the first and second sets of conductors;
scanning drive means for sequentially supplying a drive signal to individual conductors of one of the first and second sets o:E conductors while maintaining all other conductors of the set at a re-Eerence potential;
a first digital demultiplexer having a plurality o:f output terminals which are normally at a logical high state and are selec-tively caused to go to a log:ical low state in response to an address signa:l supplied -to address signal means thereon;
~ _ a plurality o:f inverters, each connecting an output terminal o:E said fi-rst d;gital demultiplexer to a separate conductor of -the other o-E the ~irs-t and second sets of conductors, whereby individual conductors of said other set are normally at -the reference potential, and are selectively permi.tted to go to a di-Eferent potential to permit sensing of capacitive COUp ling wi-th conductors of said one of the first and second sets;
an analogue multiplexer having a plurality of input terminals each colmected -to a separate conductor i.n the set of conductors on which capacitive coupling is sensed, said analogue multiplexer being operable to trans-Eer the signal from a selected conductor to an output terminal in response to an address signal suppLied to address signal means; and an address generator Eor supplying coordi.nated address signals -to sa;.d -Eirst cligi.tal demultiplexer and said analogue muLtil~:lexer so that the conductor pe:rmitted to assume a potent:ial d:i:E:ferell-t From the reference po-~ellt:ial is the concluctor whose signal is transferred by saicl analogue mu:ltiplexer, the:reby precluding any transfer of signals betweell conductors other than the concluctor receiving the drive signal and the conductor on whicll capacitive coupling is sensed.
In accordance with another aspect oE the present invention there is provided in combination:
an array of key actuable variable capacitors, each having :Eirst and second plates;
a -Eirst plurality of electrical conductors, eacll connected to the first pla-tes o-E a separate :row of said capacitors;
a seconcl plurality of electrical conductors, each connected to the second plates oE a separate column o:f sai.d capacitors;
sensing means Eor sequentially addressing incliviclllal conductors i.n one of said Eirst and second pluralities of electrical conductors to receive signal.s there:Erom;
3n a :Eirst digital demultiplexer having a plurality o:E output terminals which are normally at a logical high state and which can be selectively caused -to go to a logical low state in response to an address signal . - 4a -suppl-iecl to address terminal means thereon;
mealls ~Eor supplying address s;.gnals to said -fi.rst digi~al demultiplexer -to causc? -the ou-tput terminals thereof to sequelltia:LIy go to a logical low sta-te;
a -f:irst plura.l.ity of inverters, each connecting one outpu-t -terminal o-f said firs-t digital demultiplexer to one of the conductors in the other of said first and second pluralities of electrical conductors; and bias means tending to maintain -the conductors in the plurality o-E
electrical conductors addressed by said first digital demul-tiplexer at a po-ten-tial higher than a reference potential, whereby the conductors are normally mai.ntained at the re:Eerence potential and whereby -the higher potential ;s select:ively inpressed on individual concluctors.
[n accordance with another aspect o-E the presellt -;nvelltion -there is provicled in a capac;-tive keyboard appara-tus of -the -type in wh:ich f:i.rs-t ancl second sets o-E conductors are coupled by an array o-E ]cey actlla-tecl variable capacitors such that each capacitor couples a differen-t pai.r of conduc-tors comprising one conductor from each set~ and the sets of conductors are scanned to detect actuated capacitors, improved screening apparatlls whicll comprises;
a :first digi.tal demultiplexer having a plurality of output terminals which are normally at a logical high state and which can be selectively caused to go to a logical low state in response to an address signal supplied to address terminal means thereon;
a plurality of inverters, each co7mecting our output terminal of said digi.-tal demultiplexer to a separate conductor in the -f:irs-t set of conductors, w]lerehy the conductors in the first set o:E conductors are normally maintained at a re:ference potential and are sequentially permit-tecl-to assume a potential clif:Eerent from the re:Eerence potential;
- ~b -3~
a scannillg detector for sequentially sensing the potentials on indivi-clual conductors ;n the -fi.rst set of conductors; and contro:l means -for providing coordinated operation o-f said first digital demultiplexer and sai.d scanning detector so that said scanning detector senses -the potential on each conductor in -the first set o:f conduc-tors only during the ti.me interval in which the conductor is permitted -to assume a potential di-fferent from the reference potential.
In accordance with another aspect of the present invention there is provided capacitive keyboard apparatus comprising:
a first plurality of electrical conductors;
a second plurality of electrical conductors;
all array of key actuable variable capacitors mean~s for ;.n-terconnecting sa-icl capaci-tors and said -first and second pluralities of conductors such -that each capac:i-tor is connected between a diEferent pair o-f conductors compr:isi.ng one conductor from said first plurality of conductors and one condllc-tor from said second plurality of conductors, whereby variable capacitive coupling is provided between conductors in a pair; the magnitude o:f the capacitive coupling being dependent on the state of actuation of the associated capacitor, a first digital demultiplexer having address terminal means and a plurali-ty of output terminals, said first clemultiplexer providing a logi.cal high state at its output terminals except for any output termi.nal during -the time it is addressed by an address signal supplied -to the address term;nal means;
a first plurality of inverters, each connecting an output terminal of said firs-t digi-tal demultiplexer to a separate conductor o:f said first plurality of conductors whe-reby the conduc-tors of said -first plurality of conductors, except for the conductor associated with t~Le add:ressed ou-tput terminal, are maintained at a reference poten-tial;
an ana10gue mul-tip1exer having a plurality o-f input terminals each conl1ec-ted -to a separate conductor of said :Eirst plurality o:E conductors, al1 ou-tput terminal and address terminal means, said multiplexer being operahle to transfer the signal from any selected input -terminal to its output terminal in response to an address signal supplied to -the address terminal mea.ns;
a scanning address generator for supplying address signals which cause said analogue multiplexer to transfer signals only from the conductor associa-ted with the addressed output terminal of said first digital l() demultiplexer; and scanning drive means for supplying a drive potential to i.ndiv;dua.l conductors o-E said second plurality of conductors in sequel-ce and main-taining al'L conductors o:E said second plurality conductors excep-t the conductor to which the drive potential is suppliecl at a re:Eerence potent:icLl.
nESCRTPTION OF T~IE DRAWING
'L'he sing1e Eigure of the drawing is a genera-L schematic block d:iagram of capacitive keyboard apparatus i.n accordance w:ith the present inven-tion .
DESCRIPTION OF T}lE PREFERRED E~IBODIMENT
Schematically illustrated in the Figure is an 8 by 8 matrix of capacitive keyboard conductors. Although an 8 by ~ matrix is shown, the apparatus and method oE the present invention may be easily applied to a matrix of any size. The ma-trix includes a first set or plurality of conductors ll to which drive signals are supplied and a second se-t or plurali-ty o:L' conductors 12 on which signals are sensed. Although the conductors a-re represented by sets o:E parallel horizon-tal and vertical lines :Eor illus-trative purposes, it is pointed out -tha-t condu-- 4d --~l15~)-571 `~,~
-tors in an actual heyboard matr:ix may follow a cons;clerably more complex and irrcgul.lr pattern.
,\s illustrLted in the figure, a capacitor is locate~ at each cross-ing of conduc-tors itl the first and second sets. Accordingly, the capacitors are ShOliII and may be described as an array of capacitors comprisillg a plural-i-ty of rows and a plurality of columns of capacitors. Ior purposes of the following description, the terms "rows" and "columns" refer to an idealized electrical layout of a keyboard. ~he terms are intended to cover a range of physical configurations regardless of whether or not the capacitors are physically arranged in regular columns and rows. Although only a few capaci-tors are illustrated, it should be understood -that, :in fac-t, -there is such a capacitor at each crossing of a conductor in one set with a conduc-tor in the other set of concluctors.
CaDclcitors 13 are key actuated variable capac:itors each having a fixecl plate and a movable plateJ and may be referred to iLS cap.lci-tive key switches. One of the plates of each of the capacitors is connected to one of concluctors ll. The othcr plate of each capacitor is connectecl to one of concluctors 12. Accordingly, each capacitor provides variable capacitive coupling between a unique pair of conductors comprising one conductor from each set of conductors. It may also be observed that unless suitable provi-sions are made, there will be stray capacitive coupl:ing to some degree be-tween each conductor and every other conductor in the first and second sets of concluctors.
Conductors 11 are sequentially supplied with a drive s:ignal by scanning drive means including a first decoder or demultiplexer 14 having a plurality of outpu-t terminals 15 and address terminal mealls 16. Demulti-plexer 14 may be one of various suitable commercially available demulti-ple~ers, such as a 74154 4-line to 16-line decoder/demultiplcAcer manufac--turccl by ~ 3~3~
Aas lns~rume~ts Inc. Tne 0U~pUt ~ermlllais of Sucn demultiplexer are normally at a logical high state? and may be selectively caused to go ~o a logical low state in zesponse to a suitable address supplied to address terminal means i60 A bias means or network identified by reference numeral 17 is connec~ed to each of conductors 11, and tends to maintain the conductors at a poten~ial higher than electrical g~ound.
Only two of the conductors are shown with the bias means for illustra~ive purposes. However, it should be understood that each of conductors 11 is biased to a potential different from ground.
Each of the output terminals 15 oE demultiplexer 14 is connected to a separate one of conductors 11 through a separate one of a plurality of inverters 18. Each oE inverters 18 operates such that when supplied with a logical high input signal, its output is at a reference potential, which is typically~ electrical ground. The combination of the demultiplexer and inverters may be considered as grounding means~
When an inverter 18 is supplied with a logical low input signal, the potential on its output terminal and the conductor connected thereto is determined by the associated bias networkO
Accordingly, the conductor then assumes a supply potential different from the reference potential.
The address signals for demultiplexer 1~ are generated by a microprocessor or other address generator 190 ~icroprocessor 13 is typically programmed to generate a sequence of addresses such that individual output terminals of demuLtiplexer 14, and hence individual conductors 11 are selec~ively addressed in sequence. Accordingly, individual con~
ductors 11 are normally maintained at the reference potential or ground~ and ~he conductors in sequence are periodi.cally impressed w-;~h a higher poténtial~
Individual conductors 12 in the second set of conduc-" p~
tors are connected to the ~ terminals of an analogue multiplexer 20~ One such suitable commercially available multiplexer is a 4051 8-channel multiplexer rnanufac~ured by RCA
or MotorQla~ In addition to the plurality of input terminals to which conductors 12 are connected, multiplexer 20 has an output terrninal 21 and address terminal means 22. Multiplexer 20.
opera~es ~o trans~er the signal rom a selected one of its in~ut terminals ~o its output terminal. The selected input terminal is determined by an address signal supplied to address terminal means 72. This address signal is also generated by micro processor 19 which typically generates a sequence of address signals such that multiplexer 20 transfers the signals on each of conductors 12 in sequence to ou~put terminal 21.
A second demultiplexer 24 and plurality oE inverters ~5, similar to demultiplexer 14 and inverters 18 are connected to conductors 12O Demultiplexer 24 is shown having address terminal means 26 and a plurality of output terminals 27. As with conductors 11, conductors 12 are normally maintained at a reference potential or electrical ground, and are selectively permit~.ed to assume a potential different from the reference potential. However, no bias potential is supplied to the outputs of inverters 25 or conductors 12. Therefore, the signal on any of conductors 12 during the time that it is addressed by demultiplexer 24 i.s determined by the magnitude of the capacitive coupling between it and conductors 11~ Since only one of dr~ v~
conductors 11 is impressed with a potential differellt from ~he reference potentlal at any one time, the signal on the addressed one of conductors 12 depends on the state of actuation of the capacitor connecting it and the addressed drive conduc~orO
Demultiplexer 24 receives its addrPss signals from microprocessor 19 As shown for illustrative purposes in the figure~ both multiplexer 20 and demultiplexer 24 are connected to the same address terminals of microprocessor 19, and therefore receive the s~ne address signal. Accordingly, the signal transferred by multiplexer 20 a~ any ~ime is the signal from the one of conductors 12 which is permitted to assume a potential different from the reference potential.
Under the control of microp~ocessor 19~ the drive and sense conductors are scanned sufficientLy rapidly to address every capacitor 13 in the array of capacitors durinq an interval shorter ~han any intentional key actuation of a capacitor. Only the pair of conductors connected to a single capacitor are address~d a~ any one time. All other conductors are maintained at the reference potential. Accordingly, none of the drive conductors except for the addressed conductor can con~ribute to the signal on the sense conductors. Similarly, the signal on the addressed sense conductor cannot be affected by potentials on any other sense conductGr, nor can it transfer a signal through coupling with any other sense conductor.
In normal operation the only parameter which can affect a signal on the addressed sense conductor is the state of ac~uation ~f the capacitor coupling the addressed sense and drive conductoxs. Accordingly, stray capacitive coupling and cross talk are efectively eliminated. In addition, spurious siqnals due to electrica:L interference from other sources are virtually elimina~ed ~rom conductors in the matrix. Finally, arnbiquities in ~he de~ec~ed signal which may result from simultaneous actuation of more than one capacitor key switch, known as A
rollover, is ef-Eectively precluded. Since only one capaci-tor in -the capaci-tor array is addressecl at any one time, N-key rollover opera-tion is inher-ently provided.
In accordance with the applicant's invention, no elemen-ts in addi-lion to the basic capacitive keyboard elements are required -in or o-n the key-board. ~Vithout the necessity of ground planes, intramatrix ground lines, or other elements not basic to the keyboard, the keyboard matrix can be simply and inexyensively fabricated using elementary circuit board fabrication tech-niclues. The need for bridging elements, of which an example is disclosed in previously identified United Sta-tes patent 4,234,871, issued to N. Guglielmi, et al on November 18, 1980, multilayer circuit boards, extensive feedthroughs or other extraordinary provisions is avoided. Furthcrmore~ eLec-tronic grounding of the inactive matrix conductors is simply accomplished with only a minimal addition to the scanning circu:itry common to conventional capaci--tive keyboards.
I`he signal OJl output terminal 21 of multiplexer 20 is supplied -to a rekltively conventional detector circuit 30 which inclucles an amplifier 31 wi-th a Eeedback circuit 32, a threshold limiter 33, a pulse stretcher 34 and an outpu-t stage 35. The combination of mul-tiplexer 20 and detector circuit 30 may be considered a scanning detector.
The output signal of detector circuit 30 is fulnishecl to any suit-able utiliza-tion apparatus, which may be any of a variety of information handling or data processing equipments. The operation of the u-tilization de-vice may be synchronized with scanning of the keyboard either -through a con-nection ~no-t shown) with microprocessor 19, or by means of supplying -the address signals to the keyboard as necessary to iden-cti~y the addressed point in the keyboard matrix.
In accord~llce wi-th the foregoing description, the applicant has provided a capaci-tive keyboard with a unique scanning and screelling arrange-ment which provides exceptional immunity to cross talk and electrical inter-Eercnce. 'l~lesc functional capabl.lit:ies are providecl by apparatus which isexce~Jtiorlally simE31e and inexpensive relative to othe:r converltional capaci--ti-vc Iceyboard designs. Although a specifi.c embodiment is shown cmd des-cribed for :il].ùstra-tive purposes, a numbe:r of variations and modifi.cations wil:l be apparerlt -to those familiar with the relevant ar-ts. It :i.s in-tended that coverage of the invention not be limi.ted to the embodimen t shown, but only by the terms oF the following claims:
~/~CKORO~NO O- Tlil INVENTION
The inYention disclosed herein relat~s generally to a technique and impiementation foe p~eventing ~noesire~
in~erconductor coupling and spurious signals in a switching matrix, and more particularly to apparatus and a technique for eliminating cross talk, electrical interference and sensing ambiguities in a capacitive keyboar~d.
- Electronic keyboards have long comprised a primary form f inpu~ device for information handling and data processing f systems. With the proliferationtand technological advances such systems has come increased demands on the performance and durability of keyboard input devices~ Further, the rapid recent proliferation of smaller and less expensive systems requiring ~ J ~ n d keyboard inp~t devices has increased the --~s~e for less expensive keyboards.
Capacitive keyboards are well known in the field of da~a input devices~ They provide certain inherent advantages over electrical con~act keyboards. These advantages particularly include mechanical simplicity, long life and absence of electri-cal signal problems caused by contact bounce and corrosion.
However, as set forth in numerous publications, includ-ing U.S. patent 3,750,113 issued to J Cencel on July 31, 1973, and U.S. paten~ 3,921,166 issued to J. Volpe on November 18 1975, capacitive keyboards have suffered from another problem which is particularly significant in capacitively coupled sys~ems~ This problem stems from the fact that there is inherent capacitive coupling between every pair of elements in a keyboard.
Thus in a typical capacitive keyboard having a matrix of .' ~
C
conductors including drive signal and sense signal conductors, a signal on any conductor will normally appear to some extent on every other conductor. Obviously, this pheriomenon complicates the task of detecting which of an array of ~ariable capacitors between pairs of conductor~ in ;che matri~ is actuat~d, thus varyiny the capacitive coupling it provides.
As noted in the above~identified paten~s, a variety o techniques have been employed in an attempt to minimize problems caused by stray capacitive coupling~ These techniques include the use of ground lines interleaved between the drive and/or sense conductors, ground planes and various forms of shielding.
In addition, various electronic signal detection, verification and processing techniques have been employed to improve the reliability of detecting and distinguishing valid key actuation signals Erom signals caused by stray coupling. Some techniques represen~ative of this approach are disclosed in U.S. patent 3,931~610 issued to R. Marin, et al on Jan~ary 5, 1976, U.S.
patent 4 J 163,222 issued to D. Gove on July 31, 1979 and U.SO
patent ~l211,915 issued to D. Miller, et al on July 8, 1980, as well a~ previously identified patent 3,921,166.
All o the foregoing techniques involve the addition of elemen~s to either the basic keyboard matrix or the signal detection, veriflcation and processing circuitry~ Accordingly, these ~echniques are undesirable to the extent that they contrib-ute to ~he complexity, size, cost and potential unreliabllity of the keyboard systems.
~ In addition, all of these techniques suffer to some extent from an inability to effectively eliminate the basic problem of stray coupling and/or its effects on signal detec~ion Specifically9 although screening lines, ground planes and shielding do provide a degree of isolation oE individual conduc-Cr ~ g~
tors in ~he keyboard matrix, such isolation is not complete ands~ray coupling is not totaIly eliminated. With or without the use of conve~tional screening and shielding, electronic signal detection and verification is only effective to the extent that sigr.a'_ due ~c s a~ _oup'ins anc other eie-trica; interfelence difer from valid signals and to the extent that such differences can be feasibiy detected.
The present invention ;avoids-many of the principal disadvan~ages of the above-described techniques through the use of electronic grounding of inactive conductors in the basic keyboard matrix. Electronic grounding is simply accomplis~ed with a minimal addition o~ common electronic components. No elements are required to be added to the basic keyboard matrixO
Stray coupling is effectively totally eliminated. Finally, the O~o e, r cct~ c present invention inherently provides N-key rollover ~ee-~
SUMMARY OF THE_INVENTION
The present invention comprises apparatus and a methodfor effectively eliminating cross talk and interference in a capaci~ive keyboard of the type in which first and second sets of conductors are coupled by an array of key actuated variable capacitors such thât each capacitor couples a ~i-ffe~r~t pair of conduc~ors comprising one conductor from each set; and in which ~he sets o~ conductors are scanned to detect actuated capacitors.
In its most basic form, apparatus according to the invention comprises means for normally maintaining the conductors in at least the first set of conductors at a reference potential and sequentially permitting individual conductors in the set to assume a potential different from the reerence potential. The apparatus also includes a scanning detector for sequentially sensing the potentials on individual conductor~s and means for coordina-tillg operatioll so that the signa:l on each conduc-tor is sensed oll]y durirlg the time interval in which the conductor is permitted to assume a po-teiltial d-i-fferent from the reference potential. Pre-ferably both sets of conductors are normally maintained at the reference potential, and conductors in the second set are sequentially impressed with a po~ent;.al different :Erom the reference potential.
The method of the present invention basically comprises sequent-ially addressing individual conductors in the first and second sets of conductors by selectively supplying a drive signal to individual concluctor5 in one set and selecti-vely receiving a signal from inclividual conductors in the other set, while maintaini.ng a reference potential on all collductors except :Eor indiviclual conductors while they are being adclressed.
In accordance with the present :i.nvention there is provided capac:it:ive l<eyboa.rcl appara-tus comprising:
a matrix of capacitive key switches having first alld second sets of conduc-tors ancl a pl~lrality o:E capacitors, each capacitor havillg :fixed and movclble p:Lates, the fixed plates being connected to the :f:irst set of conductors and the movable plates being connected to the second set of conductors so that each capacitor is connected to a ~miclue pai.r of conductors n comprising one conductor from each oE the first and second sets of conductors;
scanning drive means for sequentially supplying a drive signal to individual conductors of one of the first and second sets o:E conductors while maintaining all other conductors of the set at a re-Eerence potential;
a first digital demultiplexer having a plurality o:f output terminals which are normally at a logical high state and are selec-tively caused to go to a log:ical low state in response to an address signa:l supplied -to address signal means thereon;
~ _ a plurality o:f inverters, each connecting an output terminal o:E said fi-rst d;gital demultiplexer to a separate conductor of -the other o-E the ~irs-t and second sets of conductors, whereby individual conductors of said other set are normally at -the reference potential, and are selectively permi.tted to go to a di-Eferent potential to permit sensing of capacitive COUp ling wi-th conductors of said one of the first and second sets;
an analogue multiplexer having a plurality of input terminals each colmected -to a separate conductor i.n the set of conductors on which capacitive coupling is sensed, said analogue multiplexer being operable to trans-Eer the signal from a selected conductor to an output terminal in response to an address signal suppLied to address signal means; and an address generator Eor supplying coordi.nated address signals -to sa;.d -Eirst cligi.tal demultiplexer and said analogue muLtil~:lexer so that the conductor pe:rmitted to assume a potent:ial d:i:E:ferell-t From the reference po-~ellt:ial is the concluctor whose signal is transferred by saicl analogue mu:ltiplexer, the:reby precluding any transfer of signals betweell conductors other than the concluctor receiving the drive signal and the conductor on whicll capacitive coupling is sensed.
In accordance with another aspect oE the present invention there is provided in combination:
an array of key actuable variable capacitors, each having :Eirst and second plates;
a -Eirst plurality of electrical conductors, eacll connected to the first pla-tes o-E a separate :row of said capacitors;
a seconcl plurality of electrical conductors, each connected to the second plates oE a separate column o:f sai.d capacitors;
sensing means Eor sequentially addressing incliviclllal conductors i.n one of said Eirst and second pluralities of electrical conductors to receive signal.s there:Erom;
3n a :Eirst digital demultiplexer having a plurality o:E output terminals which are normally at a logical high state and which can be selectively caused -to go to a logical low state in response to an address signal . - 4a -suppl-iecl to address terminal means thereon;
mealls ~Eor supplying address s;.gnals to said -fi.rst digi~al demultiplexer -to causc? -the ou-tput terminals thereof to sequelltia:LIy go to a logical low sta-te;
a -f:irst plura.l.ity of inverters, each connecting one outpu-t -terminal o-f said firs-t digital demultiplexer to one of the conductors in the other of said first and second pluralities of electrical conductors; and bias means tending to maintain -the conductors in the plurality o-E
electrical conductors addressed by said first digital demul-tiplexer at a po-ten-tial higher than a reference potential, whereby the conductors are normally mai.ntained at the re:Eerence potential and whereby -the higher potential ;s select:ively inpressed on individual concluctors.
[n accordance with another aspect o-E the presellt -;nvelltion -there is provicled in a capac;-tive keyboard appara-tus of -the -type in wh:ich f:i.rs-t ancl second sets o-E conductors are coupled by an array o-E ]cey actlla-tecl variable capacitors such that each capacitor couples a differen-t pai.r of conduc-tors comprising one conductor from each set~ and the sets of conductors are scanned to detect actuated capacitors, improved screening apparatlls whicll comprises;
a :first digi.tal demultiplexer having a plurality of output terminals which are normally at a logical high state and which can be selectively caused to go to a logical low state in response to an address signal supplied to address terminal means thereon;
a plurality of inverters, each co7mecting our output terminal of said digi.-tal demultiplexer to a separate conductor in the -f:irs-t set of conductors, w]lerehy the conductors in the first set o:E conductors are normally maintained at a re:ference potential and are sequentially permit-tecl-to assume a potential clif:Eerent from the re:Eerence potential;
- ~b -3~
a scannillg detector for sequentially sensing the potentials on indivi-clual conductors ;n the -fi.rst set of conductors; and contro:l means -for providing coordinated operation o-f said first digital demultiplexer and sai.d scanning detector so that said scanning detector senses -the potential on each conductor in -the first set o:f conduc-tors only during the ti.me interval in which the conductor is permitted -to assume a potential di-fferent from the reference potential.
In accordance with another aspect of the present invention there is provided capacitive keyboard apparatus comprising:
a first plurality of electrical conductors;
a second plurality of electrical conductors;
all array of key actuable variable capacitors mean~s for ;.n-terconnecting sa-icl capaci-tors and said -first and second pluralities of conductors such -that each capac:i-tor is connected between a diEferent pair o-f conductors compr:isi.ng one conductor from said first plurality of conductors and one condllc-tor from said second plurality of conductors, whereby variable capacitive coupling is provided between conductors in a pair; the magnitude o:f the capacitive coupling being dependent on the state of actuation of the associated capacitor, a first digital demultiplexer having address terminal means and a plurali-ty of output terminals, said first clemultiplexer providing a logi.cal high state at its output terminals except for any output termi.nal during -the time it is addressed by an address signal supplied -to the address term;nal means;
a first plurality of inverters, each connecting an output terminal of said firs-t digi-tal demultiplexer to a separate conductor o:f said first plurality of conductors whe-reby the conduc-tors of said -first plurality of conductors, except for the conductor associated with t~Le add:ressed ou-tput terminal, are maintained at a reference poten-tial;
an ana10gue mul-tip1exer having a plurality o-f input terminals each conl1ec-ted -to a separate conductor of said :Eirst plurality o:E conductors, al1 ou-tput terminal and address terminal means, said multiplexer being operahle to transfer the signal from any selected input -terminal to its output terminal in response to an address signal supplied to -the address terminal mea.ns;
a scanning address generator for supplying address signals which cause said analogue multiplexer to transfer signals only from the conductor associa-ted with the addressed output terminal of said first digital l() demultiplexer; and scanning drive means for supplying a drive potential to i.ndiv;dua.l conductors o-E said second plurality of conductors in sequel-ce and main-taining al'L conductors o:E said second plurality conductors excep-t the conductor to which the drive potential is suppliecl at a re:Eerence potent:icLl.
nESCRTPTION OF T~IE DRAWING
'L'he sing1e Eigure of the drawing is a genera-L schematic block d:iagram of capacitive keyboard apparatus i.n accordance w:ith the present inven-tion .
DESCRIPTION OF T}lE PREFERRED E~IBODIMENT
Schematically illustrated in the Figure is an 8 by 8 matrix of capacitive keyboard conductors. Although an 8 by ~ matrix is shown, the apparatus and method oE the present invention may be easily applied to a matrix of any size. The ma-trix includes a first set or plurality of conductors ll to which drive signals are supplied and a second se-t or plurali-ty o:L' conductors 12 on which signals are sensed. Although the conductors a-re represented by sets o:E parallel horizon-tal and vertical lines :Eor illus-trative purposes, it is pointed out -tha-t condu-- 4d --~l15~)-571 `~,~
-tors in an actual heyboard matr:ix may follow a cons;clerably more complex and irrcgul.lr pattern.
,\s illustrLted in the figure, a capacitor is locate~ at each cross-ing of conduc-tors itl the first and second sets. Accordingly, the capacitors are ShOliII and may be described as an array of capacitors comprisillg a plural-i-ty of rows and a plurality of columns of capacitors. Ior purposes of the following description, the terms "rows" and "columns" refer to an idealized electrical layout of a keyboard. ~he terms are intended to cover a range of physical configurations regardless of whether or not the capacitors are physically arranged in regular columns and rows. Although only a few capaci-tors are illustrated, it should be understood -that, :in fac-t, -there is such a capacitor at each crossing of a conductor in one set with a conduc-tor in the other set of concluctors.
CaDclcitors 13 are key actuated variable capac:itors each having a fixecl plate and a movable plateJ and may be referred to iLS cap.lci-tive key switches. One of the plates of each of the capacitors is connected to one of concluctors ll. The othcr plate of each capacitor is connectecl to one of concluctors 12. Accordingly, each capacitor provides variable capacitive coupling between a unique pair of conductors comprising one conductor from each set of conductors. It may also be observed that unless suitable provi-sions are made, there will be stray capacitive coupl:ing to some degree be-tween each conductor and every other conductor in the first and second sets of concluctors.
Conductors 11 are sequentially supplied with a drive s:ignal by scanning drive means including a first decoder or demultiplexer 14 having a plurality of outpu-t terminals 15 and address terminal mealls 16. Demulti-plexer 14 may be one of various suitable commercially available demulti-ple~ers, such as a 74154 4-line to 16-line decoder/demultiplcAcer manufac--turccl by ~ 3~3~
Aas lns~rume~ts Inc. Tne 0U~pUt ~ermlllais of Sucn demultiplexer are normally at a logical high state? and may be selectively caused to go ~o a logical low state in zesponse to a suitable address supplied to address terminal means i60 A bias means or network identified by reference numeral 17 is connec~ed to each of conductors 11, and tends to maintain the conductors at a poten~ial higher than electrical g~ound.
Only two of the conductors are shown with the bias means for illustra~ive purposes. However, it should be understood that each of conductors 11 is biased to a potential different from ground.
Each of the output terminals 15 oE demultiplexer 14 is connected to a separate one of conductors 11 through a separate one of a plurality of inverters 18. Each oE inverters 18 operates such that when supplied with a logical high input signal, its output is at a reference potential, which is typically~ electrical ground. The combination of the demultiplexer and inverters may be considered as grounding means~
When an inverter 18 is supplied with a logical low input signal, the potential on its output terminal and the conductor connected thereto is determined by the associated bias networkO
Accordingly, the conductor then assumes a supply potential different from the reference potential.
The address signals for demultiplexer 1~ are generated by a microprocessor or other address generator 190 ~icroprocessor 13 is typically programmed to generate a sequence of addresses such that individual output terminals of demuLtiplexer 14, and hence individual conductors 11 are selec~ively addressed in sequence. Accordingly, individual con~
ductors 11 are normally maintained at the reference potential or ground~ and ~he conductors in sequence are periodi.cally impressed w-;~h a higher poténtial~
Individual conductors 12 in the second set of conduc-" p~
tors are connected to the ~ terminals of an analogue multiplexer 20~ One such suitable commercially available multiplexer is a 4051 8-channel multiplexer rnanufac~ured by RCA
or MotorQla~ In addition to the plurality of input terminals to which conductors 12 are connected, multiplexer 20 has an output terrninal 21 and address terminal means 22. Multiplexer 20.
opera~es ~o trans~er the signal rom a selected one of its in~ut terminals ~o its output terminal. The selected input terminal is determined by an address signal supplied to address terminal means 72. This address signal is also generated by micro processor 19 which typically generates a sequence of address signals such that multiplexer 20 transfers the signals on each of conductors 12 in sequence to ou~put terminal 21.
A second demultiplexer 24 and plurality oE inverters ~5, similar to demultiplexer 14 and inverters 18 are connected to conductors 12O Demultiplexer 24 is shown having address terminal means 26 and a plurality of output terminals 27. As with conductors 11, conductors 12 are normally maintained at a reference potential or electrical ground, and are selectively permit~.ed to assume a potential different from the reference potential. However, no bias potential is supplied to the outputs of inverters 25 or conductors 12. Therefore, the signal on any of conductors 12 during the time that it is addressed by demultiplexer 24 i.s determined by the magnitude of the capacitive coupling between it and conductors 11~ Since only one of dr~ v~
conductors 11 is impressed with a potential differellt from ~he reference potentlal at any one time, the signal on the addressed one of conductors 12 depends on the state of actuation of the capacitor connecting it and the addressed drive conduc~orO
Demultiplexer 24 receives its addrPss signals from microprocessor 19 As shown for illustrative purposes in the figure~ both multiplexer 20 and demultiplexer 24 are connected to the same address terminals of microprocessor 19, and therefore receive the s~ne address signal. Accordingly, the signal transferred by multiplexer 20 a~ any ~ime is the signal from the one of conductors 12 which is permitted to assume a potential different from the reference potential.
Under the control of microp~ocessor 19~ the drive and sense conductors are scanned sufficientLy rapidly to address every capacitor 13 in the array of capacitors durinq an interval shorter ~han any intentional key actuation of a capacitor. Only the pair of conductors connected to a single capacitor are address~d a~ any one time. All other conductors are maintained at the reference potential. Accordingly, none of the drive conductors except for the addressed conductor can con~ribute to the signal on the sense conductors. Similarly, the signal on the addressed sense conductor cannot be affected by potentials on any other sense conductGr, nor can it transfer a signal through coupling with any other sense conductor.
In normal operation the only parameter which can affect a signal on the addressed sense conductor is the state of ac~uation ~f the capacitor coupling the addressed sense and drive conductoxs. Accordingly, stray capacitive coupling and cross talk are efectively eliminated. In addition, spurious siqnals due to electrica:L interference from other sources are virtually elimina~ed ~rom conductors in the matrix. Finally, arnbiquities in ~he de~ec~ed signal which may result from simultaneous actuation of more than one capacitor key switch, known as A
rollover, is ef-Eectively precluded. Since only one capaci-tor in -the capaci-tor array is addressecl at any one time, N-key rollover opera-tion is inher-ently provided.
In accordance with the applicant's invention, no elemen-ts in addi-lion to the basic capacitive keyboard elements are required -in or o-n the key-board. ~Vithout the necessity of ground planes, intramatrix ground lines, or other elements not basic to the keyboard, the keyboard matrix can be simply and inexyensively fabricated using elementary circuit board fabrication tech-niclues. The need for bridging elements, of which an example is disclosed in previously identified United Sta-tes patent 4,234,871, issued to N. Guglielmi, et al on November 18, 1980, multilayer circuit boards, extensive feedthroughs or other extraordinary provisions is avoided. Furthcrmore~ eLec-tronic grounding of the inactive matrix conductors is simply accomplished with only a minimal addition to the scanning circu:itry common to conventional capaci--tive keyboards.
I`he signal OJl output terminal 21 of multiplexer 20 is supplied -to a rekltively conventional detector circuit 30 which inclucles an amplifier 31 wi-th a Eeedback circuit 32, a threshold limiter 33, a pulse stretcher 34 and an outpu-t stage 35. The combination of mul-tiplexer 20 and detector circuit 30 may be considered a scanning detector.
The output signal of detector circuit 30 is fulnishecl to any suit-able utiliza-tion apparatus, which may be any of a variety of information handling or data processing equipments. The operation of the u-tilization de-vice may be synchronized with scanning of the keyboard either -through a con-nection ~no-t shown) with microprocessor 19, or by means of supplying -the address signals to the keyboard as necessary to iden-cti~y the addressed point in the keyboard matrix.
In accord~llce wi-th the foregoing description, the applicant has provided a capaci-tive keyboard with a unique scanning and screelling arrange-ment which provides exceptional immunity to cross talk and electrical inter-Eercnce. 'l~lesc functional capabl.lit:ies are providecl by apparatus which isexce~Jtiorlally simE31e and inexpensive relative to othe:r converltional capaci--ti-vc Iceyboard designs. Although a specifi.c embodiment is shown cmd des-cribed for :il].ùstra-tive purposes, a numbe:r of variations and modifi.cations wil:l be apparerlt -to those familiar with the relevant ar-ts. It :i.s in-tended that coverage of the invention not be limi.ted to the embodimen t shown, but only by the terms oF the following claims:
Claims (9)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Capacitive keyboard apparatus comprising:
a matrix of capacitive key switches having first and second sets of conductors and a plurality of capacitors, each capacitor having fixed and movable plates, the fixed plates being connected to the first set of conductors and the movable plates being connected to the second set of conductors so that each capacitor is connected to a unique pair of conductors comprising one conductor from each of the first and second sets of conductors;
scanning drive means for sequentially supplying a drive signal to individual conductors of one of the first and second sets of conductors while maintaining all other conductors of the set at a reference potential;
a first digital demultiplexer having a plurality of output terminals which are normally at a logical high state and are selectively caused to go to a logical low state in response to an address signal supplied to address signal means thereon;
a plurality of inverters, each connecting an output terminal of said first digital demultiplexer to a separate conductor of the other of the first and second sets of conductors, whereby individual conductors of said other set are normally at the reference potential, and are selectively permitted to go to a different potential to permit sensing of capacitive coupling with conductors of said one of the first and second sets;
an analogue multiplexer having a plurality of input terminals each connected to a separate conductor in the set of conductors on which capacitive coupling is sensed, said analogue multiplexer being operable to transfer -the signal from a selected conductor to an output terminal in response to an address signal supplied to address signal means, and an address generator for supplying coordinated address signals to said first digital demultiplexer and said analogue multiplexer so that the conductor permitted to assume a potential different from the reference potential is the conductor whose signal is transferred by said analogue multiplexer, thereby precluding any transfer of signals between conductors other than the conductor receiving the drive signal and the conductor on which capacitive coupling is sensed.
a matrix of capacitive key switches having first and second sets of conductors and a plurality of capacitors, each capacitor having fixed and movable plates, the fixed plates being connected to the first set of conductors and the movable plates being connected to the second set of conductors so that each capacitor is connected to a unique pair of conductors comprising one conductor from each of the first and second sets of conductors;
scanning drive means for sequentially supplying a drive signal to individual conductors of one of the first and second sets of conductors while maintaining all other conductors of the set at a reference potential;
a first digital demultiplexer having a plurality of output terminals which are normally at a logical high state and are selectively caused to go to a logical low state in response to an address signal supplied to address signal means thereon;
a plurality of inverters, each connecting an output terminal of said first digital demultiplexer to a separate conductor of the other of the first and second sets of conductors, whereby individual conductors of said other set are normally at the reference potential, and are selectively permitted to go to a different potential to permit sensing of capacitive coupling with conductors of said one of the first and second sets;
an analogue multiplexer having a plurality of input terminals each connected to a separate conductor in the set of conductors on which capacitive coupling is sensed, said analogue multiplexer being operable to transfer -the signal from a selected conductor to an output terminal in response to an address signal supplied to address signal means, and an address generator for supplying coordinated address signals to said first digital demultiplexer and said analogue multiplexer so that the conductor permitted to assume a potential different from the reference potential is the conductor whose signal is transferred by said analogue multiplexer, thereby precluding any transfer of signals between conductors other than the conductor receiving the drive signal and the conductor on which capacitive coupling is sensed.
2. The capacitive keyboard apparatus of claim 1 wherein said scanning drive means comprises:
bias means tending to maintain individual conductors of the set of conductors to which drive signals are supplied at a potential higher than the reference potential;
a second digital demultiplexer having a plurality of output terminals which are normally at a logical high state and which may be selectively caused to go to a logical low state by address signals supplied to address terminal means thereon; and a plurality of inverters, each connecting an output terminal of said second digital demultiplexer to a separate conductor of the set of conductors to which drive signals are supplied, whereby the conductors are normally maintained at the reference potential, and are sequentially caused to go to the potential determined by said bias means.
bias means tending to maintain individual conductors of the set of conductors to which drive signals are supplied at a potential higher than the reference potential;
a second digital demultiplexer having a plurality of output terminals which are normally at a logical high state and which may be selectively caused to go to a logical low state by address signals supplied to address terminal means thereon; and a plurality of inverters, each connecting an output terminal of said second digital demultiplexer to a separate conductor of the set of conductors to which drive signals are supplied, whereby the conductors are normally maintained at the reference potential, and are sequentially caused to go to the potential determined by said bias means.
3. In combination:
an array of key actuable variable capacitors, each having first and second plates;
a first plurality of electrical conductors, each connected to the first plates of a separate row of said capacitors;
a second plurality of electrical conductors, each connected to the second plates of a separate column of said capacitors;
sensing means for sequentially addressing individual conductors in one of said first and second pluralities of electrical conductors to receive signals therefrom;
a first digital demultiplexer having a plurality of output terminals which are normally at a logical high state and which can he selectively caused to go to a logical low state in response to an address signal supplied to address terminal means thereon;
means for supplying address signals to said first digital demultiplexer to cause the output terminals thereof to sequentially go to a logical low state;
a first plurality of inverters, each connecting one output terminal of said first digital demultiplexer to one of the conductors in the other of said first and second pluralities of electrical conductors; and bias means tending to maintain the conductors in the plurality of electrical conductors addressed by said first digital demultiplexer at a potential higher than a reference potential, whereby the conductors are normally maintained at the reference potential and whereby the higher potential is selectively impressed on individual conductors.
an array of key actuable variable capacitors, each having first and second plates;
a first plurality of electrical conductors, each connected to the first plates of a separate row of said capacitors;
a second plurality of electrical conductors, each connected to the second plates of a separate column of said capacitors;
sensing means for sequentially addressing individual conductors in one of said first and second pluralities of electrical conductors to receive signals therefrom;
a first digital demultiplexer having a plurality of output terminals which are normally at a logical high state and which can he selectively caused to go to a logical low state in response to an address signal supplied to address terminal means thereon;
means for supplying address signals to said first digital demultiplexer to cause the output terminals thereof to sequentially go to a logical low state;
a first plurality of inverters, each connecting one output terminal of said first digital demultiplexer to one of the conductors in the other of said first and second pluralities of electrical conductors; and bias means tending to maintain the conductors in the plurality of electrical conductors addressed by said first digital demultiplexer at a potential higher than a reference potential, whereby the conductors are normally maintained at the reference potential and whereby the higher potential is selectively impressed on individual conductors.
4. The combination of claim 3 wherein said sensing means comprises:
an analogue multiplexer having a plurality of input terminals, each input terminal being connected to a separate conductor in the plurality of electrical conductors addressed by said sensing means, said analogue multiplexer being operable to transfer the signal from a selected conductor to a detector output terminal in response to an address supplied to address terminal means;
a second digital demultiplexer having a plurality of output terminals which are normally at a logical high state and can be selectively caused to go to a logical low state in response to a signal supplied to address terminal means thereon;
a second plurality of inverters, each connecting an output terminal of said second digital demultiplexer to one of the conductors in the plural ity of electrical conductors addressed by said sensing means, whereby the conductors are normally maintained at the reference potential and whereby individual conductors are selectively permitted to assume a potential other than the reference potential; and means connecting the address terminal means of said analogue multiplexer and said second digital demultiplexer so that they substantially simultan-eously address the same conductor.
an analogue multiplexer having a plurality of input terminals, each input terminal being connected to a separate conductor in the plurality of electrical conductors addressed by said sensing means, said analogue multiplexer being operable to transfer the signal from a selected conductor to a detector output terminal in response to an address supplied to address terminal means;
a second digital demultiplexer having a plurality of output terminals which are normally at a logical high state and can be selectively caused to go to a logical low state in response to a signal supplied to address terminal means thereon;
a second plurality of inverters, each connecting an output terminal of said second digital demultiplexer to one of the conductors in the plural ity of electrical conductors addressed by said sensing means, whereby the conductors are normally maintained at the reference potential and whereby individual conductors are selectively permitted to assume a potential other than the reference potential; and means connecting the address terminal means of said analogue multiplexer and said second digital demultiplexer so that they substantially simultan-eously address the same conductor.
5. The combination of claim 4 wherein said reference potential is electrical ground.
6. In a capacitive keyboard apparatus of the type in which first and second sets of conductors are coupled by an array of key actuated variable capacitors such that each capacitor couples a different pair of conductors comprising one conductor from each set, and the sets of conductors are scanned to detect actuated capacitors, improved screening apparatus which comprises a first digital demultiplexer having a plurality of output terminals which are normally at a logical high state and which can be selectively caused to go to a logical low state in response to an address signal supplied to address terminal means thereon;
a plurality of inverters, each connecting one output terminal of said digital demultiplexer to a separate conductor in the first set of conductors whereby the conductors in the first set of conductors are normally maintained at a reference potential and are sequentially permitted to assume a potential different from the reference potential;
a scanning detector for sequentially sensing the potentials on individu-al conductors in the first set of conductors; and control means for providing coordinated operation of said first digital demultiplexer and said scanning detector so that said scanning detector sense the potential on each conductor in the first set of conductors only during the time interval in which the conductor is permitted to assume a potential different from the reference potential.
a plurality of inverters, each connecting one output terminal of said digital demultiplexer to a separate conductor in the first set of conductors whereby the conductors in the first set of conductors are normally maintained at a reference potential and are sequentially permitted to assume a potential different from the reference potential;
a scanning detector for sequentially sensing the potentials on individu-al conductors in the first set of conductors; and control means for providing coordinated operation of said first digital demultiplexer and said scanning detector so that said scanning detector sense the potential on each conductor in the first set of conductors only during the time interval in which the conductor is permitted to assume a potential different from the reference potential.
7. The capacitive keyboard apparatus of claim 6 further comprising:
a second digital demultiplexer having a plurality of output terminals which are normally at a logical high state and which can be selectively caused to go to a logical low state in response to an address signal supplied to address terminal means thereon;
a plurality of inverters each connecting one output terminal of said digital demultiplexer to a separate conductor in the second set of conductors; and bias means tending to maintain the conductors in the second set of conductors at a potential different from the reference potential whereby the conductors in the second set of conductors are normally maintained at the reference potential and are sequentially impressed with a potential different from the reference potential.
a second digital demultiplexer having a plurality of output terminals which are normally at a logical high state and which can be selectively caused to go to a logical low state in response to an address signal supplied to address terminal means thereon;
a plurality of inverters each connecting one output terminal of said digital demultiplexer to a separate conductor in the second set of conductors; and bias means tending to maintain the conductors in the second set of conductors at a potential different from the reference potential whereby the conductors in the second set of conductors are normally maintained at the reference potential and are sequentially impressed with a potential different from the reference potential.
8. Capacitive keyboard apparatus comprising:
a first plurality of electrical conductors;
a second plurality of electrical conductors;
an array of key actuable variable capacitors;
means for interconnecting said capacitors and said first and second plur-alities of conductors such that each capacitor is connected between a different pair of conductors comprising one conductor from said first plurality of conductors and one conductor from said second plurality of conductors whereby variable capacitive coupling is provided between conductors in a pair, the magnitude of the capacitive coupling being dependent on the state of actuation of the associated capacitor;
a first digital demultiplexer having address terminal means and a plurality of output terminals, said first demultiplexer providing a logical high state at its output terminals except for any output terminal during the time it is addressed by an address signal supplied to the address terminal means;
a first plurality of inverters, each connecting an output terminal of said first digital demultiplexer to a separate conductor of said first plurality of conductors, whereby the conductors of said first plurality of conductors, except for the conductor associated with the addressed output terminal, are maintained at a reference potential;
an analogue multiplexer having a plurality of input terminals each connected to a separate conductor of said first plurality of conductors, an output terminal and address terminal means, said multiplexer being operable to transfer the signal from any selected input terminal to its output terminal in response to an address signal supplied to the address terminal means;
a scanning address generator for supplying address signals which cause said analogue multiplexer to transfer signals only from the conductor associated with the addressed output terminal of said first digital demultiplexer; and scanning drive means for supplying a drive potential to individual conductors of said second plurality of conductors in sequence and maintaining all conductors of said second plurality conductors except the conductor to which the drive potential is supplied at a reference potential.
a first plurality of electrical conductors;
a second plurality of electrical conductors;
an array of key actuable variable capacitors;
means for interconnecting said capacitors and said first and second plur-alities of conductors such that each capacitor is connected between a different pair of conductors comprising one conductor from said first plurality of conductors and one conductor from said second plurality of conductors whereby variable capacitive coupling is provided between conductors in a pair, the magnitude of the capacitive coupling being dependent on the state of actuation of the associated capacitor;
a first digital demultiplexer having address terminal means and a plurality of output terminals, said first demultiplexer providing a logical high state at its output terminals except for any output terminal during the time it is addressed by an address signal supplied to the address terminal means;
a first plurality of inverters, each connecting an output terminal of said first digital demultiplexer to a separate conductor of said first plurality of conductors, whereby the conductors of said first plurality of conductors, except for the conductor associated with the addressed output terminal, are maintained at a reference potential;
an analogue multiplexer having a plurality of input terminals each connected to a separate conductor of said first plurality of conductors, an output terminal and address terminal means, said multiplexer being operable to transfer the signal from any selected input terminal to its output terminal in response to an address signal supplied to the address terminal means;
a scanning address generator for supplying address signals which cause said analogue multiplexer to transfer signals only from the conductor associated with the addressed output terminal of said first digital demultiplexer; and scanning drive means for supplying a drive potential to individual conductors of said second plurality of conductors in sequence and maintaining all conductors of said second plurality conductors except the conductor to which the drive potential is supplied at a reference potential.
9. The capacitive keyboard apparatus of claim 7 wherein said scanning drive means comprises:
a second digital demultiplexer having address terminal means and a plurality of output terminals, said second demultiplexer providing a logical high state at its output terminals except for any output terminal during the time it is addressed by an address signal supplied to the address terminal means; and a second plurality of inverters, each connecting an output terminal of said second digital demultiplexer to a separate conductor of said second plurality of conductors, whereby the conductors of said second plurality of conductors, except for the conductor associated with the addressed output terminal, are maintained at the reference potential.
a second digital demultiplexer having address terminal means and a plurality of output terminals, said second demultiplexer providing a logical high state at its output terminals except for any output terminal during the time it is addressed by an address signal supplied to the address terminal means; and a second plurality of inverters, each connecting an output terminal of said second digital demultiplexer to a separate conductor of said second plurality of conductors, whereby the conductors of said second plurality of conductors, except for the conductor associated with the addressed output terminal, are maintained at the reference potential.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/258,248 US4405917A (en) | 1981-04-28 | 1981-04-28 | Matrix screening and grounding arrangement and method |
| US258,248 | 1981-04-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1187962A true CA1187962A (en) | 1985-05-28 |
Family
ID=22979728
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000401393A Expired CA1187962A (en) | 1981-04-28 | 1982-04-21 | Matrix screening and grounding arrangement and method |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4405917A (en) |
| EP (1) | EP0063800B1 (en) |
| JP (1) | JPS57193830A (en) |
| CA (1) | CA1187962A (en) |
| DE (1) | DE3268368D1 (en) |
Families Citing this family (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4758829A (en) * | 1982-06-04 | 1988-07-19 | Smith Iii William N | Apparatus for stimulating a keyboard |
| JPS6029969B2 (en) * | 1982-06-18 | 1985-07-13 | 富士通株式会社 | touch detection device |
| EP0107898B1 (en) * | 1982-09-29 | 1987-07-08 | EMI Limited | A tactile array sensor |
| JPS60175077A (en) * | 1984-02-22 | 1985-09-09 | 株式会社日立製作所 | Information holder |
| JPH07109572B2 (en) * | 1984-02-29 | 1995-11-22 | 東京プレス工業株式会社 | Capacity keyboard |
| IL72736A0 (en) * | 1984-08-21 | 1984-11-30 | Cybertronics Ltd | Surface-area pressure transducers |
| US4651133A (en) * | 1984-12-24 | 1987-03-17 | At&T Technologies, Inc. | Method and apparatus for capacitive keyboard scanning |
| US4706068A (en) * | 1985-01-30 | 1987-11-10 | Wyse Technology, Inc. | Four wire keyboard interface |
| JPS61185876A (en) * | 1985-02-14 | 1986-08-19 | 松下電器産業株式会社 | Electrostatic capacitance substrate |
| FR2581491A1 (en) * | 1985-05-02 | 1986-11-07 | Lewiner Jacques | IMPROVEMENTS TO ELECTRONIC IDENTIFICATION ASSEMBLIES OF CAPACITIVE KEYBOARDS |
| US4779094A (en) * | 1985-11-23 | 1988-10-18 | Lee Doo S | Apparatus for remotely determining the angular orientation, speed and/or direction of rotary objects |
| JPS62144223A (en) * | 1985-12-18 | 1987-06-27 | Matsushita Electric Ind Co Ltd | Electrostatic capacity type keyboard switch |
| US4728931A (en) * | 1986-07-25 | 1988-03-01 | Honeywell Inc. | Charge redistribution capacitance detection apparatus |
| US4728932A (en) * | 1986-07-25 | 1988-03-01 | Honeywell Inc. | Detector for capacitive sensing devices |
| JP2970914B2 (en) * | 1988-09-14 | 1999-11-02 | 富士通株式会社 | Switch matrix input detector |
| DE8900946U1 (en) * | 1988-09-30 | 1990-02-08 | Siemens Ag, 1000 Berlin Und 8000 Muenchen, De | |
| US5254989A (en) * | 1988-12-20 | 1993-10-19 | Bull S.A. | Garbling the identification of a key of a non-coded keyboard, and circuit for performing the method |
| US5070330A (en) * | 1989-01-12 | 1991-12-03 | Acer Incorporated | Keyboard scanning matrix |
| US5189417A (en) * | 1990-10-16 | 1993-02-23 | Donnelly Corporation | Detection circuit for matrix touch pad |
| US5572205A (en) * | 1993-03-29 | 1996-11-05 | Donnelly Technology, Inc. | Touch control system |
| US5594222A (en) * | 1994-10-25 | 1997-01-14 | Integrated Controls | Touch sensor and control circuit therefor |
| US5796183A (en) * | 1996-01-31 | 1998-08-18 | Nartron Corporation | Capacitive responsive electronic switching circuit |
| JP4162717B2 (en) | 1996-12-10 | 2008-10-08 | タッチ センサー テクノロジーズ，エルエルシー | Differential touch sensor and control circuit thereof |
| US6320282B1 (en) | 1999-01-19 | 2001-11-20 | Touchsensor Technologies, Llc | Touch switch with integral control circuit |
| US7906875B2 (en) * | 1999-01-19 | 2011-03-15 | Touchsensor Technologies, Llc | Touch switches and practical applications therefor |
| US8144125B2 (en) | 2006-03-30 | 2012-03-27 | Cypress Semiconductor Corporation | Apparatus and method for reducing average scan rate to detect a conductive object on a sensing device |
| US8059015B2 (en) * | 2006-05-25 | 2011-11-15 | Cypress Semiconductor Corporation | Capacitance sensing matrix for keyboard architecture |
| US8040321B2 (en) * | 2006-07-10 | 2011-10-18 | Cypress Semiconductor Corporation | Touch-sensor with shared capacitive sensors |
| US8350733B2 (en) * | 2006-10-13 | 2013-01-08 | Infineon Technologies Ag | Keyboard scan for human interface devices |
| US8350730B2 (en) * | 2006-10-13 | 2013-01-08 | Infineon Technologies Ag | Keyboard scan |
| US8058937B2 (en) * | 2007-01-30 | 2011-11-15 | Cypress Semiconductor Corporation | Setting a discharge rate and a charge rate of a relaxation oscillator circuit |
| US8144126B2 (en) | 2007-05-07 | 2012-03-27 | Cypress Semiconductor Corporation | Reducing sleep current in a capacitance sensing system |
| US8258986B2 (en) | 2007-07-03 | 2012-09-04 | Cypress Semiconductor Corporation | Capacitive-matrix keyboard with multiple touch detection |
| JP2016095759A (en) * | 2014-11-17 | 2016-05-26 | 東プレ株式会社 | Electrostatic capacitance type keyboard |
| JP6420661B2 (en) * | 2014-12-26 | 2018-11-07 | 東プレ株式会社 | Capacitive keyboard |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3750113A (en) * | 1971-11-12 | 1973-07-31 | Becton Dickinson Co | Capacitive keyboard |
| US3921166A (en) * | 1972-09-15 | 1975-11-18 | Raytheon Co | Capacitance matrix keyboard |
| IT975280B (en) * | 1972-10-18 | 1974-07-20 | Olivetti & Co Spa | CAPACITIVE KEYBOARD |
| GB1464912A (en) * | 1973-02-26 | 1977-02-16 | Casio Computer Co Ltd | Information input device |
| US3931610A (en) * | 1973-11-29 | 1976-01-06 | Teletype Corporation | Capacitive keyswitch sensor and method |
| US4037225A (en) * | 1975-11-25 | 1977-07-19 | Xerox Corporation | Keyboard encoding system with electronic hysteresis |
| US4163222A (en) * | 1976-02-27 | 1979-07-31 | Amkey, Incorporated | Synchronous phase detected keyboard |
| US4234871A (en) * | 1978-06-06 | 1980-11-18 | Ing. C. Olivetti & C., S.P.A. | Capacitive keyboard for data processing equipments |
| US4211915A (en) * | 1978-12-04 | 1980-07-08 | General Electric Company | Keyboard verification system |
| US4274752A (en) * | 1979-04-02 | 1981-06-23 | International Business Machines Corporation | Keyboard multiple switch assembly |
| US4305135A (en) * | 1979-07-30 | 1981-12-08 | International Business Machines Corp. | Program controlled capacitive keyboard variable threshold sensing system |
-
1981
- 1981-04-28 US US06/258,248 patent/US4405917A/en not_active Expired - Lifetime
-
1982
- 1982-04-21 CA CA000401393A patent/CA1187962A/en not_active Expired
- 1982-04-23 EP EP82103448A patent/EP0063800B1/en not_active Expired
- 1982-04-23 DE DE8282103448T patent/DE3268368D1/en not_active Expired
- 1982-04-28 JP JP57072503A patent/JPS57193830A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| EP0063800A3 (en) | 1983-04-06 |
| EP0063800A2 (en) | 1982-11-03 |
| US4405917A (en) | 1983-09-20 |
| JPS6259325B2 (en) | 1987-12-10 |
| EP0063800B1 (en) | 1986-01-08 |
| DE3268368D1 (en) | 1986-02-20 |
| JPS57193830A (en) | 1982-11-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |