CA1196108A - Special instruction processing unit for data processing system - Google Patents
Special instruction processing unit for data processing systemInfo
- Publication number
- CA1196108A CA1196108A CA000426296A CA426296A CA1196108A CA 1196108 A CA1196108 A CA 1196108A CA 000426296 A CA000426296 A CA 000426296A CA 426296 A CA426296 A CA 426296A CA 1196108 A CA1196108 A CA 1196108A
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- Prior art keywords
- bus
- data
- lines
- control
- instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
Abstract
Abstract of the Disclosure A special instruction processor, such as a floating point accelerator processor, that processes a special class of instructions. Each instruction identifies the number of operands to be processed as well as the number of data words required to be transferred for each operand. The central processing unit retrieves and decodes each instruction, and transfers the special instructions to the special instruction processor. Both processors decode the special instructions to determine the numbers of operands and data words to be transferred. The central processing unit retrieves the data words from memory and transmits them to the special instruction processor. The special instruction processor processes the instruction and signals the central processor when finished. The central processor then causes the special instruction processor to transmit the processed data back to the central instruction processor.
Description
Backgr~und of the Invention Field ~f the Invention This invention relates to electronic digital da~a processing systems incorporating a special instruction processor such as a floating point accelerator processor.
More specifically, the inventlon relate~ ~o a new and impr~ved interconnection arrangement between ~e floating -~ point processor and a central processor unit.
~escription ~f the Prior Art A digital data processing system comprises three elements: namely, a memory element, an input/output element, and a processor element. The memory element steres information in addressable storage locations, wi~h each location having a unique address. The infoxmat ion stored in the memory includes data, or "operands", and instr~ctions for processing the operands. The processor element transfers information to and from the memory element 9 interprets the information as either instructions or operands and processes the operands in accordance with the associated instructions.
The input~outp~t element, undel- centrol of the processor unit, also communicates with ~he memory element in order to transfer operands and instructions into the system and obtain processed data from it.
Operands processed by a processing unit may take a number of formsO In many processing operat ions, ~perands are in the form of integers or whole numbers. In other operations, operands are in a floating point format, that is, ~3-276 in what is typically known as "scientific notati~n". In this fQrm~ an operand has two parts, including an exponent ~nd a mantissa In a binary~based system used in most computers, the mantissa is a fraction with a binary point to the immediate left of the most significan~ digit, and the exponent repre~ents the power of two to which the mantissa must be taken to ~btain the value of the number. Each of the mantissa and the exponent may contain a sign, either p~sitive or negative.
Simllarly, operands for trigonometric functi~ns may have a different form frem both integer and ~loating poi~t operands. F~r instance, some trigonometric functions may be repetltive for each multiple of three hundred and sixty degrees, if the operands are expressed in degrees, or may represent or require specif1c operations with respect te "pi"
if the operands are expressed in radian n~tationO In additi~n to the scientific notation or special trigonometric functi~n, other special operand notations are conceivable.
Each of these special classes of operands may require 2Q special handling by the processor. With respect particularly to floating point instructions, a number of arrangements for processing such operands have ~een attempted in the prior art. In some data processing systems, the central processing unit contains special control circuitry for executing the ~5 sp~cial instructions. Even with this hardware approach, floating point instruc~ions usually require significantly more time to complete than do instructions on conventlonal intege~ operands. ~s a central processor unit executes all instructions, including the floatin~ point instructions, in seriatum, the execution of floating point instructions by the central processor can significantly increase the overall time to complete a given program.
In another approach, the operands are processed using subroutines comprising sets of the machine instructions -to imple-ment the floating point ~unctions. The central processor unit merely uses a floating point instruction as an instruction direct-lng the processor to execute the appropriate subroutine. Thisapproach enables the functions performed by the special class of instructions to be altered relatively simply. However, this approach is considerably slower than the hardware approach, as the mantissas and exponents of the operands must be handled separately.
In other prior data processing systems, separate functional modules operating in parallel execute the instructions of the data processing system. In some cases, each module can execute all of the instructions on the different classes of operands, or specific modules may be assigned to process instructions on selected classes of operands. In either case, each module operates independently by retrieving data from or storing data in the memoxy unit directly. A controlling module may retrieve the instructions in seriatum and transfer it to either an idle module, or to the module designed to execute the instruction on the specified class of operand.
~ .
Since the modules ~perate in parallel, they may operate simultaneously, within the constraint tlrat normally one instruction cannot be executed until a previous instruction has been executed.
While tile time required -to perform a single operation is about the same as in the prior hardware approach, the parallel nature of the modules significantly reduces the time to execute a program contained in the special instructions, as a free central processor unit module may be used to process interrupts. However, as each module must be capa~le oE operating independently, circuit redundancy is necessary.
Each module usually performs only one function, and is not readily converted into other functions.
In a :Eourth arrangement, used on conjunction with certain *PDP-ll data processing systems, a separate module, termed a "float-ing point accelerator", processes instructions in conjunction with floating point operands. The instruction indicates whether the operand is floa-ting point or integer, and if the instruction indicates that the operand is floating point, the central processor unit passes the instruction to the floating point accelerator. The floating point accelerator then decodes the instruction, and requests the cen-tral processing unit to retrieve operands from the memory unit Eor memory, and to store the processed data in the memory. While this approach allol~s the central processing unit the freedom to process such things as interrupts while the -floating point accelerator is in the process of executing the floating point instruction, the required interaction *Trade Mark between ~he central pr~cessing unit and the floating point accelerator unnecessarily complicates both units.
It is ~herefcre an object of this invention to provide a new and improved floating point accelerator.
S It is yet another object of this invention to pxovide a new interconnec~ion arrangement between the floating point accelerator and the central processing unit.
Summary In brief, this invention provides a new and improved interconnection arrangement between the central processing unit and a processing m~dule f~r processing a special class of instructions that operate on a uniquely defined class of operands. The central processing unit retrieves all of the instructions, in series~ in a conventlcnal manner, and decodes the instructi~ns~ An image of each instruct1on is passed to the special instruction processor. When an instruction is received which requires processing rf one of the special class of operands, the central processing unit then retrieves the data words comprising the operands fr~m the memory and passes them to the special instruction processor.
After receiving the instruction ~he special instruction processor also decodes the instructi~n and proceeds to receive the data words comprising the operands. The ~pecial instruction process~r then processes the operands in a conventional manner, and prepares to transmit the results of 3~3 processing, namely the processed data and the condition codes, back to the central processing unit. When the eentral processing unit is signalled b-y the special instruction processor that it has finished processing, it signals the special instruction proces-sor to transmit the data. The special instruction processor then transmits the data and the condition codes. The central proces--sing unit then can transmit the processed data back into s-torage in the memory.
In addition, the invention provides certain maintenance and diagnostie fea-tures in which the eentral proeessing unit can foree the speeial instruetion processor to a seleeted state, and it can also determine the state of the special instruction proces-sor.
In summary, the present invention provides a special instruction processor for processing a predetermined class of instructions on a predetermined class oE operands each containing a predetermined number of data words, the special instruetion processor for connection to bus that also eonneets to a central processing unit that retrieves instruc-tions and operands from, and transmits results of processing to, a memory, the instrue-tions in said predetermined class each containing an operation code identifying the operation to be performed and the number o:E operands required to process the instruction, -the bus including lines for transferring instruetion operation codes, data words and eontrol signals ineluding timing signals defining sueeessive bus eyeles between the eentral processing unit and the special instruction proeessor, the speeial instruetion proeessor compri-3~
sing: A. means arranged to be connected to the instruc-tion opera-tion code and control lines o:E the bus Eor receiving instructions of said predetermined class transmit-ted from the central proces-sing unit and for decoding the instructions to determine the num-ber of data words required to be received in order to process the operand; B. means connected to said decoding means and arran-ged to be connected to the data and control lines of the bus for iteratively receiving data words over the data lines in succes-sive bus cycles, the number of da-ta words received being deter-mined by said decoding means' C. means connected to said decodingmeans and said receiving means and arranged to ~e connected to the control lines of the bus for processing the operands in accor-dance with the operation defined in the operation code and for transmitting a control signal to the central processlng unit when the processing has been completed; and D. means connected to said decoding means and arranged to be connected to the data and control lines of the bus for transmitting the results of processing -to the central processing unit over the data lines in successive bus cycles in response to a control signal from the central pro-cessing unit.
The invention will now be described in grea-ter detail with reference to the accompanying drawings, in which:
FIGURE 1 is a block diagram of a digi-tal data processing system constructed in accordance with this invention;
FIGURE 2 is a detailed block diagram of a portion of the central processing unit shown in FIGURE l;
-~a-FIGURE 3 is a detailed block diagram of a special in-struction processing unit shown in FIGURE 1, specifically a float--ing point accelerating unit;
-6b-Figure 4 depicts a detailed circuitry in a porti.o.n of the con~rol block shown in Figure 3;
Flgure 5 is a flow diagram depicting transfers between the central processing unit and special ins~ruction processing unit shown in ~igure 1.
Description of an Illustrative Embodiment I. General Description A. Data Processing System Referring to Figure 1, the basic elements of a data pro-cessing system that embody this invention comprise a central pro-cessor unit 10, memory unit 11, and input/output units 12, which include terminals 13. The central processor unit communicates directly with certain of the input/output units 12 over an accel-erator bus 14. The central processor unit 10 communicates with memory unit 11 over a memory bus 15, and the memory unit in turn communicates directly with others o~ input/output units 12 over an input/output bus 16. The central processor unit 10 communicates with terminals 13 over a terminal bus 17.
The central processor unit comprises a data processor 20, and control store 21 which are connected to memory bus 15, and a console processor 22. The console processor receives sig~
nals ~rom terminal bus 17, and transfers them through control store 21 to data processor 2~. Data ' ~
: "
process 20 then operates on the information from console processor 22 and may transfer the information to the memory unit 11 for future processing, or it may process information directly. Similarly, data processor 2~ may transfer information through control store 21 to the console processor 2~, which may then transmit the information to terminal bus 17 for transfer to one of terminals 13. The data processor also performs all communications over the accelerator bus 14 with those input/
output units 12 connected there~oO The communications with input/
output units 12 over accelerator bus 14 are described in copending Canadian Patent Application Serial No. 426,295, filed April 20, 1983.
As described below, the data processor communicates directly with the memory unit 11 over memory bus 15, and indirectly with the input/output bus 16 through memory unit 11.
The control store 21 contains all of the microinstruction sequences that are used for processing the instructions that are received and e~ecuted by data processor 20, and steps through the microinstruction sequences based on sequencing information from the data processor and timing information from a timing signal generator which i-t maintains.
Memory unit 11 contains a memory controller 3~ having one connection, or port, to memory bus 15, and a second connection to input/output bus 16. One or more memory arrays 31 connect to memory controller 3y and contain the ~3-276 addressable memory storage locations that may be accessed directly by ~he memory controller.
In addition to central processor unit 1~, a floating point accelerator processor 23 may be connected to S accelerator bus 14. A floating poin~ accelerator processor 23 useful in the data processing system of FIG. l, and the accelera~or bus 14 are described herein. Floating point accelerator processor 23 receives floating point instructions from data processor 2~ and is specially designed to process such instructions generally more rapidly than data processor
More specifically, the inventlon relate~ ~o a new and impr~ved interconnection arrangement between ~e floating -~ point processor and a central processor unit.
~escription ~f the Prior Art A digital data processing system comprises three elements: namely, a memory element, an input/output element, and a processor element. The memory element steres information in addressable storage locations, wi~h each location having a unique address. The infoxmat ion stored in the memory includes data, or "operands", and instr~ctions for processing the operands. The processor element transfers information to and from the memory element 9 interprets the information as either instructions or operands and processes the operands in accordance with the associated instructions.
The input~outp~t element, undel- centrol of the processor unit, also communicates with ~he memory element in order to transfer operands and instructions into the system and obtain processed data from it.
Operands processed by a processing unit may take a number of formsO In many processing operat ions, ~perands are in the form of integers or whole numbers. In other operations, operands are in a floating point format, that is, ~3-276 in what is typically known as "scientific notati~n". In this fQrm~ an operand has two parts, including an exponent ~nd a mantissa In a binary~based system used in most computers, the mantissa is a fraction with a binary point to the immediate left of the most significan~ digit, and the exponent repre~ents the power of two to which the mantissa must be taken to ~btain the value of the number. Each of the mantissa and the exponent may contain a sign, either p~sitive or negative.
Simllarly, operands for trigonometric functi~ns may have a different form frem both integer and ~loating poi~t operands. F~r instance, some trigonometric functions may be repetltive for each multiple of three hundred and sixty degrees, if the operands are expressed in degrees, or may represent or require specif1c operations with respect te "pi"
if the operands are expressed in radian n~tationO In additi~n to the scientific notation or special trigonometric functi~n, other special operand notations are conceivable.
Each of these special classes of operands may require 2Q special handling by the processor. With respect particularly to floating point instructions, a number of arrangements for processing such operands have ~een attempted in the prior art. In some data processing systems, the central processing unit contains special control circuitry for executing the ~5 sp~cial instructions. Even with this hardware approach, floating point instruc~ions usually require significantly more time to complete than do instructions on conventlonal intege~ operands. ~s a central processor unit executes all instructions, including the floatin~ point instructions, in seriatum, the execution of floating point instructions by the central processor can significantly increase the overall time to complete a given program.
In another approach, the operands are processed using subroutines comprising sets of the machine instructions -to imple-ment the floating point ~unctions. The central processor unit merely uses a floating point instruction as an instruction direct-lng the processor to execute the appropriate subroutine. Thisapproach enables the functions performed by the special class of instructions to be altered relatively simply. However, this approach is considerably slower than the hardware approach, as the mantissas and exponents of the operands must be handled separately.
In other prior data processing systems, separate functional modules operating in parallel execute the instructions of the data processing system. In some cases, each module can execute all of the instructions on the different classes of operands, or specific modules may be assigned to process instructions on selected classes of operands. In either case, each module operates independently by retrieving data from or storing data in the memoxy unit directly. A controlling module may retrieve the instructions in seriatum and transfer it to either an idle module, or to the module designed to execute the instruction on the specified class of operand.
~ .
Since the modules ~perate in parallel, they may operate simultaneously, within the constraint tlrat normally one instruction cannot be executed until a previous instruction has been executed.
While tile time required -to perform a single operation is about the same as in the prior hardware approach, the parallel nature of the modules significantly reduces the time to execute a program contained in the special instructions, as a free central processor unit module may be used to process interrupts. However, as each module must be capa~le oE operating independently, circuit redundancy is necessary.
Each module usually performs only one function, and is not readily converted into other functions.
In a :Eourth arrangement, used on conjunction with certain *PDP-ll data processing systems, a separate module, termed a "float-ing point accelerator", processes instructions in conjunction with floating point operands. The instruction indicates whether the operand is floa-ting point or integer, and if the instruction indicates that the operand is floating point, the central processor unit passes the instruction to the floating point accelerator. The floating point accelerator then decodes the instruction, and requests the cen-tral processing unit to retrieve operands from the memory unit Eor memory, and to store the processed data in the memory. While this approach allol~s the central processing unit the freedom to process such things as interrupts while the -floating point accelerator is in the process of executing the floating point instruction, the required interaction *Trade Mark between ~he central pr~cessing unit and the floating point accelerator unnecessarily complicates both units.
It is ~herefcre an object of this invention to provide a new and improved floating point accelerator.
S It is yet another object of this invention to pxovide a new interconnec~ion arrangement between the floating point accelerator and the central processing unit.
Summary In brief, this invention provides a new and improved interconnection arrangement between the central processing unit and a processing m~dule f~r processing a special class of instructions that operate on a uniquely defined class of operands. The central processing unit retrieves all of the instructions, in series~ in a conventlcnal manner, and decodes the instructi~ns~ An image of each instruct1on is passed to the special instruction processor. When an instruction is received which requires processing rf one of the special class of operands, the central processing unit then retrieves the data words comprising the operands fr~m the memory and passes them to the special instruction processor.
After receiving the instruction ~he special instruction processor also decodes the instructi~n and proceeds to receive the data words comprising the operands. The ~pecial instruction process~r then processes the operands in a conventional manner, and prepares to transmit the results of 3~3 processing, namely the processed data and the condition codes, back to the central processing unit. When the eentral processing unit is signalled b-y the special instruction processor that it has finished processing, it signals the special instruction proces-sor to transmit the data. The special instruction processor then transmits the data and the condition codes. The central proces--sing unit then can transmit the processed data back into s-torage in the memory.
In addition, the invention provides certain maintenance and diagnostie fea-tures in which the eentral proeessing unit can foree the speeial instruetion processor to a seleeted state, and it can also determine the state of the special instruction proces-sor.
In summary, the present invention provides a special instruction processor for processing a predetermined class of instructions on a predetermined class oE operands each containing a predetermined number of data words, the special instruetion processor for connection to bus that also eonneets to a central processing unit that retrieves instruc-tions and operands from, and transmits results of processing to, a memory, the instrue-tions in said predetermined class each containing an operation code identifying the operation to be performed and the number o:E operands required to process the instruction, -the bus including lines for transferring instruetion operation codes, data words and eontrol signals ineluding timing signals defining sueeessive bus eyeles between the eentral processing unit and the special instruction proeessor, the speeial instruetion proeessor compri-3~
sing: A. means arranged to be connected to the instruc-tion opera-tion code and control lines o:E the bus Eor receiving instructions of said predetermined class transmit-ted from the central proces-sing unit and for decoding the instructions to determine the num-ber of data words required to be received in order to process the operand; B. means connected to said decoding means and arran-ged to be connected to the data and control lines of the bus for iteratively receiving data words over the data lines in succes-sive bus cycles, the number of da-ta words received being deter-mined by said decoding means' C. means connected to said decodingmeans and said receiving means and arranged to ~e connected to the control lines of the bus for processing the operands in accor-dance with the operation defined in the operation code and for transmitting a control signal to the central processlng unit when the processing has been completed; and D. means connected to said decoding means and arranged to be connected to the data and control lines of the bus for transmitting the results of processing -to the central processing unit over the data lines in successive bus cycles in response to a control signal from the central pro-cessing unit.
The invention will now be described in grea-ter detail with reference to the accompanying drawings, in which:
FIGURE 1 is a block diagram of a digi-tal data processing system constructed in accordance with this invention;
FIGURE 2 is a detailed block diagram of a portion of the central processing unit shown in FIGURE l;
-~a-FIGURE 3 is a detailed block diagram of a special in-struction processing unit shown in FIGURE 1, specifically a float--ing point accelerating unit;
-6b-Figure 4 depicts a detailed circuitry in a porti.o.n of the con~rol block shown in Figure 3;
Flgure 5 is a flow diagram depicting transfers between the central processing unit and special ins~ruction processing unit shown in ~igure 1.
Description of an Illustrative Embodiment I. General Description A. Data Processing System Referring to Figure 1, the basic elements of a data pro-cessing system that embody this invention comprise a central pro-cessor unit 10, memory unit 11, and input/output units 12, which include terminals 13. The central processor unit communicates directly with certain of the input/output units 12 over an accel-erator bus 14. The central processor unit 10 communicates with memory unit 11 over a memory bus 15, and the memory unit in turn communicates directly with others o~ input/output units 12 over an input/output bus 16. The central processor unit 10 communicates with terminals 13 over a terminal bus 17.
The central processor unit comprises a data processor 20, and control store 21 which are connected to memory bus 15, and a console processor 22. The console processor receives sig~
nals ~rom terminal bus 17, and transfers them through control store 21 to data processor 2~. Data ' ~
: "
process 20 then operates on the information from console processor 22 and may transfer the information to the memory unit 11 for future processing, or it may process information directly. Similarly, data processor 2~ may transfer information through control store 21 to the console processor 2~, which may then transmit the information to terminal bus 17 for transfer to one of terminals 13. The data processor also performs all communications over the accelerator bus 14 with those input/
output units 12 connected there~oO The communications with input/
output units 12 over accelerator bus 14 are described in copending Canadian Patent Application Serial No. 426,295, filed April 20, 1983.
As described below, the data processor communicates directly with the memory unit 11 over memory bus 15, and indirectly with the input/output bus 16 through memory unit 11.
The control store 21 contains all of the microinstruction sequences that are used for processing the instructions that are received and e~ecuted by data processor 20, and steps through the microinstruction sequences based on sequencing information from the data processor and timing information from a timing signal generator which i-t maintains.
Memory unit 11 contains a memory controller 3~ having one connection, or port, to memory bus 15, and a second connection to input/output bus 16. One or more memory arrays 31 connect to memory controller 3y and contain the ~3-276 addressable memory storage locations that may be accessed directly by ~he memory controller.
In addition to central processor unit 1~, a floating point accelerator processor 23 may be connected to S accelerator bus 14. A floating poin~ accelerator processor 23 useful in the data processing system of FIG. l, and the accelera~or bus 14 are described herein. Floating point accelerator processor 23 receives floating point instructions from data processor 2~ and is specially designed to process such instructions generally more rapidly than data processor
2~ would normally ~e able to.
Several types of input/output units 12 ~re shown in FI~. l. A communica~ions adapter 4~ can connect to synchronous and~or asynchronous data COmmUniCa~iDnS lines to transfer information over, for example, conventional telephone lines, or to enable connection of the data processing system as one element in a local distributed processing networkO Specific signals for the synchronous and asynchronous conncction to communications adapter 4~ are not shown; however, such signals would depend on the particular signal protocols used in such transmission, and are not a part of this invention. The communications adapter 4~
normally would include circuitry for buffering inEormation during the synchronous or asynchronous transfers, and for ~5 generating control signals over the synchronous and asynchronous communications paths to enable the Lnformation to be transferred. The communications adapter 4~ also contains circuitry for transferring information over input/output bus 16. Since the communications adapter forms no part of this invention, it will not be described further herein.
~ hree other input/output units 12 provide a secondary storage facility for the data processing system. They include a tape controller 41 connected to a tape drive 42, and two disc controllers 43 and 44. Disc controller 43 is connected to a plurality o~ disc drives 45, while disc controller 44 may be connected to a disc drive 46 and to a plurality of disc drives 47. Disc controller 44 is connected to accelerator bus 14, and is described in the afore-mentioned copending Canadian Patent Application Serial No. 426,295. Units 41 and 43, and their respective storage elements may be constructed as described in U.S. Patent No~ 3,999,163.
Terminals 13 may include a tape drive 5~, or a system console 51, which are directly connec-ted to terminal bus 17. ~n optional remo-te console 52 may be provided to transfer signals with terminal bus 17 over telephone lines through conventional modems (not shown). The remote console 52 can ~ ~ 83-276 be used for remote diagnosis of system failure5 or for remote maintenance~ The tape drive 5~ may be used for local maintenance or for transferring information into or out of the system~ The system console may be used to provide direct S operator control of the system, and may permit the operator to turn the system on or off, to initialize the system, and to step through a program sequence step-by-step.
Before proceeding further, it may be useful to establish some definitions for terms that have already been used an~
will be used throughout the remainder of this description.
"Information" i5 intelligence that con~rols and provides the basis for data processing. It includes address, data, control and status information.
"Data" includes information which i5 the object of or re5ult of processing.
I'Address" information identifies a particular storage location in which other information, such as data information, control or sta~us information or other address information, is stored.
"Control" informa~ion identifies particular operations to be performed. It includes commands between units of a data processing system that certain operations be performed, instructions to be performed by the central processor 1~ or floating point accelerator processor 23, and i~ also includes i~formation that modifies a unit's performance of an operation or execution of an instruction so as to enable certain astions to occur or disable actions from occurring.
8 3- 27 ~
An "instruction" is a step in a program that is executed by the central processox unit 1~ or floating point accelerator processor 23. Each step may be executed by the respective processor executing one or more microinstructions.
Each microinstruction is stored in a speciic location, which is identified as a micro-address. Other units~ for example, memory controller 3~, also perform operations in response to and as defined in seguences of microinstructions.
"Status" information identifies the condition of various signals generated by a unit at varivus times during the processing of an operation or execution of an instruction.
B. Central Processor ~nit 1~
FIG. 2 illustrates, in ~eneral block diagram form, portions of central processor 1~, including data processor 2 and control store 21, that may be useful in the data processing system of FIG~ 1.
Dat~ processor 2~ includes a data pa~h 6~ ~hat includes an arithmatic logic unit and a plurality of general purpose registers (not shown)~ In one ~pecific embodiment of this invention, one of the general purpose registers is used as a program counter to identify the storage location in memory containing the next instruction to be executed by the processor 1~ and another register is used as a stack pointer used during the servicing of interrupts and subroutines, as 2S described in U.S. Patent No. 3,71~,324. The data pa~h 6~
receives information from, or transfers information to, the accelerator bus 14, the memory bus 15, or from a plurality of console registers 61 that in turn receive and store information from, or transfer information to, console ~rocessor 22 over a console bus 620 Operations performed by data path 6~ are controlled by instructions stored in an instruc~ion buffer 63, which receives each instruction fetched from memory unit 11 iden~ified by the program counter register in data path 6~.
Alternatively, the operations performed by data path 6~ can be controlled by an interrupt processor 64 which receives requests for interrupt service from accelerator bus 14, console bus 62 (through console registers 61) and from the input/output bus 16. The interrupt processor 64 also receives the interrupt priority level at which the processor 1~ is then operating and, if the interrupt request has a \~, ~\
:- 15 higher priority~ acknowledges the interrupt and causes the processor 1~ to service the interrupt request. A
microsequencer 65 generates a microaddress that is used by a micro control store 66 in control store 21 to access a microinstruction depending on the instructions stored in instruction buffer 63, or the interrupt being serviced by interrupt processor S4. The microsequencer 65 yenerates the microaddress in response to the particular instruction in instruction buffer 63 then being processed, and the acknowledgement of an interrupt by interrupt processor 64, as 25 well as timing signals generated by a clock generator 67 in conkrol store 210 ~ 13 -6~
C. Floating Point Accelerator 23 A general block diagr~m of a floating point accelerator 23 is shown in FIG. 3. A floa~in~ poin~ instr~e~ion as transferred to the floating point accelerator by the central processing unit 1~ specifically by the data path 2~, is received in an instruction decoder 1~1~ One specific embodiment of floating point accelerator 23 is microprogrammed. The instruction decoder is thus connected to a microaddress sequencer 1~2 in a conventional manner, which in turn supplies microaddresses to a con~rol store 1~3.
The control store contains microinstructions that control the operations of floating point accelerator 23, including a data path 1~4. The data path contain5 operand storage registers and an arithmetic and logic unit that processes the operan~s that are received from the central processor unit 1~ through a transceiver buffer 1~5.
The microaddress sequencer 1~2, using conventional microinstruction addressing techniques, supplies a '~next microaddress" to the control store 1~3. The microaddress sequencer 1~2 also receives signals from the control store 1~3 and from a branch logic 1~6, and generates the next microaddress that is then transmitted to the control store.
The control store thus genera~es microinstructions that control the data path logic 1~4 based on a predetermined microinstruction sequence. The specific sequence i~
determined by the instruction from central processor unit 1~, ~3-276 as modified by certain conditions in the floating point aocelerator 23 as reflected by branch logic 1~60 Data path logic 1~4 also uses conventional data paths to process floating point instructions~ The data path contains separate data paths for the exponent and for the mantissa, and operates on each according to the microinstructions from control store 1~3. In one specific embodiment, the data path logic comprises conventional A~D 29~1 bit slice microprocessors sold by Advanced Micro Devices, Inc.
Floating point accelerator 23 also includes interface control circuitry 1~7 that also receives signals from the central processing unit and assists in synchronizing the transfer of operands and processed data between the central processor unit 1~ and floating poin~ accelerator 23. A
detailed description of circuitry in control circuitry 1~7 is presented in FIG. 4.
In accordance with the invention, the central processing unit serially retrieves each instruction from the memory unit 11. Each instruction is loaded into instruction buffer 63 (FIG. 2). ~he ins~ruction buffer and the associa~ed processor then decode the instruction. If the instruction is a floating point instruction, that is, an instruction that indicates that the operands are in floating point format, it transmits the instruction to the floating point accelerator over the BUS IB D(7~ 8 (FIG 3.~l simultaneously asserting a synchronizing IRD STATE instruction read signal 1~9.
The instruction proce~sor 63 (FIG. 2) in central processor unit 1~ fur~her decodes the instructiOn and proceeds to retrieve the operands from the memory unit 11.
Each instruction may require one or more operands, and an operand may comprise sne or more data words in the memory depending on the required degree of arithmetic precision, each data word requiring a memory retrieval9 Each data word i5 ~ransferred through the ALU Ç~ (FIG. 2) o the central processor unit 1~, and transmitted over BUS Y D(31:0~
(FIG 3), the data section of accelerator bus 14. Each transfer over BU~ Y (D31~ is synchronized to the assertion of a CPU DATA AVAIL CPU data available signal 111.
The floating point ~ccelerator 23 receives each data word, in buffer l~S, and transfers it onto a BUS FPA floating 1~
l; point accelerator busl. The control s~ore 1~3 determin~s \~to which registers of data path logic 1~4 each transferred data word is to be stored ~t depending on whether the word forms part of the mantissa or the exponent. The instruction previously transferred into instruction decoder 1~1 also identifies the number of operands and th~ number of data words, required to process the instruction. Control store 1~3 causes the data words to be transferred through bufEer l~S and into registers in data path logic 1~4 in accordance with the numher of words to be received. After all the operands have been received, the data path logic 1~4, under control of control store 1~3, executes the instruction in a conventional manner.
~3-276 After the instruction has been executed, the control store 1~3 transmits an ACC S~NC accelera~or synchronization si~nal over line 12~ (FIG. 3) to central processor unit 1~
This signal is a signal in the microinstruction generated ~y control store 1~3 following exec~tion o~ each instruction.
The central processing unit 1~ receives ~he signal and services it as an interrupt service request. When it is ready to receive the processed data from the floa~ing point accelerator, it asserts a READ PORT signal on a line 121 and a SEL ACC IN select acce:Lerator in signal on line 122. Since several units may be connected to accelerator bus 14, the SEL
ACC IN select accelerator in signal serves to enable the floating point accelerator 23 to transmit on the BUS Y
D(31:0~ and prevents other attached units from transmittiny data over those lines. Tn successive clock cycles, the floating point accelera~or 23 transmits the condition codes and data words comprising the processed data from data path logic 1~4 across B~S FPA 112 through buffer 1~5 and across BUS Y D(31~ . The central processor unit 1~, specifically data path 2~, receives the condition codes and data words and transmits them to the memory unit 11 .
The arrangement according to the invention provides a much less complex interconnection arrangement be~ween central processor unit 1~ and a floating point accelerator 23. The special instruction, in one specific embodiment of a floating point instruction~ is ~ransmitted by the central processing ~ 17 -unit 10 to floating point accelerator processor 23, and the operands are then automatically and sequentially retrieved by data processor 2~ and transmitted directly to floating point accelerator 23 with no fllrther interaction between them. When the condition codes and pro-cessed data are ready, the floating point accelerator signals the cen-tral processing unit. When the central processing unit is ready to receive the processed data, it signals the :Eloating point accelerator, which responds with successive data words in successive clock cycles.
Both the central processor unit and floating point accelerator deter-LO mine the number of data words to be transferred in both directions, as operands and processed data, based on the contents of the instruc-tions. rherefore, the only communication back and forth as to the number of data words to be transferred is by way of the instruction.
This simplifies the floating point accelerator and the communications therebetween.
The central processing unit 10 and floating point acceler-ator also provide maintenance and diagnostic features in which the central processor unit 10 may transmit a "next microaddress" to the floating point accelerator control store 103 to place the control store in a specific and known address condition. Furthermore, the central processor unit may read, or retrieve, the "ncxt microaddress"
that is supplied by microaddress sequencer 102 to control store 103.
The operation by which the central processor unit forces the control store 103 to a known address condition will be ~3-276 ~ J ~
described in connection with FI~. 3. The central processor unit transmits a micr~address over BUS Y D(31:0~ t and asserts a TR~P ACC trap accelerator signal on line 123. The TRAP ACC trap accelerator signal is reoeived in control circuitry 1~7, which inhibits ~he microaddress se~uencer 1~2 from transmitting a next microaddress onto the control s~ore, and enables the signals on the BUS Y D(3100~) to be transmitted through buffer 1~5 and to the "next microaddress"
input to control store 1~3. The control s~ore 1~3 then transmits the microins~ruction iden~ified by the supplied signals, forcing a shift to the sequence defined by the address transmitted on B~S Y ~D31:0~) 11~.
The operation in which the ~entral processor unit 1 retrieves the microaddress transmitted by microaddress sequencer 1~2 will be explained in connection with FIG. 3.
The central processor unit first transmits a READ ACC UPC
read accelerator microprogram counter signal on line 124 to control circuitry 1~7. This conditions the floating point accelerator 23 to transfer the next microaddress generated by microaddress sequencer 1~2 to transceiver 132 in ~uffer 1~5.
During the next succeeding clock cycle, the central processor unit asserts the READ PORT signal Ol line 1~1~ At that time, the "next microaddress" is transmitted through buffer 1~5 onto BUS Y D(31:0~) in synchronism with the control store's assertion of the ACC SYNC accelerator sync signal on line 12 from control store 1~3. At ~he end of the clock cycle, the e'nex~ ~icroaddress" is removed from the BUS Y Dt31.0~
-and the floating point accelerator 23 returns to normal operation.
FIG. 4 depi.cts certain circuitry in control 107 that en-ables the floating point accelerator 23 to recelve the READ PORT, SEL
ACC IN select accelerator in signal$ READ ACC UPC read accelerator microprogram counter signal, and TRAP ACC trap accelerator signal and enables it to transmit and receive the associated signals over BUS Y
D(31:00).
The READ PORT and SEL ACC IN select accelerator in signals are received in the control circuit 107 and coupled to an AND gate 131. The coincidence of these signals causes the assertion of an CPU
RCV DAl'A central processing unit receive data signal which is coupled to branch logic 106. The branch logic enables the microaddress sequencer 102 to shift control store 103 to a sequence that causes the floating point accelerator 23 to transmit processed data and the condition codes to central processor unit 10. This signal also condi-tiOTIs a transceiver 132 in buffer 105 bet~een BUS FPA 112 and BUS Y
D~31:00) 110 to transmit data from floating point accelerator 23 to central processor unit 10.
The CPU RCV DATA central processing lmit receive data signal also energizes OR gates 134, 135 and one input to AND gate 136, which is also energi~ed by a CPU P~10 clocking signal :Erom centra.l pro-cessor unit 10, and an ALLOW CPU Y BUS signal :Erom control store 103 to enable transceiver 132.
When the TRAP ACC trap accelerator signal is asserted, neither the READ PORT nor the SEL ACC IN select accelerator , ~' 6 ~ ~ ~
in signals are assertedO Therefore, the CPU RCV DATA centra processor unit receive da~a signal is not asserted.
Transceiver 132 is thus conditioned to trans~er signals from BUS Y D(31:0~ to BUS FPA 112 through buffer 1~5. The transceiver is enabled by the TRAP ACC trap accelerator signal through OR gates 134 and 135, and AND gate 136 when the CPU PH0 timing signal and ALLOW CPU Y ~S signal from control store 1~3 are asserted.
The TRAP ~CC trap accelerator signal also causes a flip-flop 14~ to be set through AND gate 141 at ~he coincidence of the CPU PH~ and CLK OFF timing signals. The se~ting of flip-flop 14~ causes a ~ORCE UADRS force microad~ress signal to be asserted~ As shown in FIG. 3, this signal is transmitted from control 1~7 to microaddress sequencer 1~2. When the FORCE UADRS force microaddress signal is asserted, th2 address from microaddress sequencer 1~2 is no~ transmitted to control store 1~30 The FORCE UADRS force microaddress signal enables a transceiver ~ to transfer a next microaddress from the BUS FPA 112 to control store 1~3. The transceiver~
141 ~e enabled ~hrough an OR gate 143. The flip-flop 14~ is reset at the assertion of the next CPU PH~ timing signal but through an AND gate 144~
The control 1~7 receives the READ ACC UPC read accelerator microprogram counter signal in a flip-flop 15~, which generates a READ UADRS read microaddress signal, This READ VADRS read microaddress signal is coupled through OR
gate 143 to enable trans~eiver 142. However, since the EORCE
UADRS force microaddress signal is not asserted, the transceiver 1~2is conditioned to transmit the next microaddress signal from micro-address sequencer 102 onto BUS FPA 112. The flip-flop 15~ is then re-set through ~ND gate 151 at the next CPU PH~ clocking signal.
FIG. 5 depicts detailed sequences of the operations of transferring instructions, operands, and processed data, as well as microaddresses, between CPII 10 and floating point accelerator 23.
The sequences depicted in FIG. 5 are self-explanatory and a detailed description of these operations is not required here for an under-standi.ng of the inven-tion.
The foregoing description is limited to a specific embodi-ment of this invention. It will be apparent, however, that this invention can be practiced in systems having diverse basic construc-tion or in systems that use different internal circuitry than is des-cribed in this specification with the attainment of some or all of the foregoing objects a.nd advantages of this invention. It is the object of the appended claims to cover all such variations and modi-fi.cations as come within the true spirit and scope of this invention.
Several types of input/output units 12 ~re shown in FI~. l. A communica~ions adapter 4~ can connect to synchronous and~or asynchronous data COmmUniCa~iDnS lines to transfer information over, for example, conventional telephone lines, or to enable connection of the data processing system as one element in a local distributed processing networkO Specific signals for the synchronous and asynchronous conncction to communications adapter 4~ are not shown; however, such signals would depend on the particular signal protocols used in such transmission, and are not a part of this invention. The communications adapter 4~
normally would include circuitry for buffering inEormation during the synchronous or asynchronous transfers, and for ~5 generating control signals over the synchronous and asynchronous communications paths to enable the Lnformation to be transferred. The communications adapter 4~ also contains circuitry for transferring information over input/output bus 16. Since the communications adapter forms no part of this invention, it will not be described further herein.
~ hree other input/output units 12 provide a secondary storage facility for the data processing system. They include a tape controller 41 connected to a tape drive 42, and two disc controllers 43 and 44. Disc controller 43 is connected to a plurality o~ disc drives 45, while disc controller 44 may be connected to a disc drive 46 and to a plurality of disc drives 47. Disc controller 44 is connected to accelerator bus 14, and is described in the afore-mentioned copending Canadian Patent Application Serial No. 426,295. Units 41 and 43, and their respective storage elements may be constructed as described in U.S. Patent No~ 3,999,163.
Terminals 13 may include a tape drive 5~, or a system console 51, which are directly connec-ted to terminal bus 17. ~n optional remo-te console 52 may be provided to transfer signals with terminal bus 17 over telephone lines through conventional modems (not shown). The remote console 52 can ~ ~ 83-276 be used for remote diagnosis of system failure5 or for remote maintenance~ The tape drive 5~ may be used for local maintenance or for transferring information into or out of the system~ The system console may be used to provide direct S operator control of the system, and may permit the operator to turn the system on or off, to initialize the system, and to step through a program sequence step-by-step.
Before proceeding further, it may be useful to establish some definitions for terms that have already been used an~
will be used throughout the remainder of this description.
"Information" i5 intelligence that con~rols and provides the basis for data processing. It includes address, data, control and status information.
"Data" includes information which i5 the object of or re5ult of processing.
I'Address" information identifies a particular storage location in which other information, such as data information, control or sta~us information or other address information, is stored.
"Control" informa~ion identifies particular operations to be performed. It includes commands between units of a data processing system that certain operations be performed, instructions to be performed by the central processor 1~ or floating point accelerator processor 23, and i~ also includes i~formation that modifies a unit's performance of an operation or execution of an instruction so as to enable certain astions to occur or disable actions from occurring.
8 3- 27 ~
An "instruction" is a step in a program that is executed by the central processox unit 1~ or floating point accelerator processor 23. Each step may be executed by the respective processor executing one or more microinstructions.
Each microinstruction is stored in a speciic location, which is identified as a micro-address. Other units~ for example, memory controller 3~, also perform operations in response to and as defined in seguences of microinstructions.
"Status" information identifies the condition of various signals generated by a unit at varivus times during the processing of an operation or execution of an instruction.
B. Central Processor ~nit 1~
FIG. 2 illustrates, in ~eneral block diagram form, portions of central processor 1~, including data processor 2 and control store 21, that may be useful in the data processing system of FIG~ 1.
Dat~ processor 2~ includes a data pa~h 6~ ~hat includes an arithmatic logic unit and a plurality of general purpose registers (not shown)~ In one ~pecific embodiment of this invention, one of the general purpose registers is used as a program counter to identify the storage location in memory containing the next instruction to be executed by the processor 1~ and another register is used as a stack pointer used during the servicing of interrupts and subroutines, as 2S described in U.S. Patent No. 3,71~,324. The data pa~h 6~
receives information from, or transfers information to, the accelerator bus 14, the memory bus 15, or from a plurality of console registers 61 that in turn receive and store information from, or transfer information to, console ~rocessor 22 over a console bus 620 Operations performed by data path 6~ are controlled by instructions stored in an instruc~ion buffer 63, which receives each instruction fetched from memory unit 11 iden~ified by the program counter register in data path 6~.
Alternatively, the operations performed by data path 6~ can be controlled by an interrupt processor 64 which receives requests for interrupt service from accelerator bus 14, console bus 62 (through console registers 61) and from the input/output bus 16. The interrupt processor 64 also receives the interrupt priority level at which the processor 1~ is then operating and, if the interrupt request has a \~, ~\
:- 15 higher priority~ acknowledges the interrupt and causes the processor 1~ to service the interrupt request. A
microsequencer 65 generates a microaddress that is used by a micro control store 66 in control store 21 to access a microinstruction depending on the instructions stored in instruction buffer 63, or the interrupt being serviced by interrupt processor S4. The microsequencer 65 yenerates the microaddress in response to the particular instruction in instruction buffer 63 then being processed, and the acknowledgement of an interrupt by interrupt processor 64, as 25 well as timing signals generated by a clock generator 67 in conkrol store 210 ~ 13 -6~
C. Floating Point Accelerator 23 A general block diagr~m of a floating point accelerator 23 is shown in FIG. 3. A floa~in~ poin~ instr~e~ion as transferred to the floating point accelerator by the central processing unit 1~ specifically by the data path 2~, is received in an instruction decoder 1~1~ One specific embodiment of floating point accelerator 23 is microprogrammed. The instruction decoder is thus connected to a microaddress sequencer 1~2 in a conventional manner, which in turn supplies microaddresses to a con~rol store 1~3.
The control store contains microinstructions that control the operations of floating point accelerator 23, including a data path 1~4. The data path contain5 operand storage registers and an arithmetic and logic unit that processes the operan~s that are received from the central processor unit 1~ through a transceiver buffer 1~5.
The microaddress sequencer 1~2, using conventional microinstruction addressing techniques, supplies a '~next microaddress" to the control store 1~3. The microaddress sequencer 1~2 also receives signals from the control store 1~3 and from a branch logic 1~6, and generates the next microaddress that is then transmitted to the control store.
The control store thus genera~es microinstructions that control the data path logic 1~4 based on a predetermined microinstruction sequence. The specific sequence i~
determined by the instruction from central processor unit 1~, ~3-276 as modified by certain conditions in the floating point aocelerator 23 as reflected by branch logic 1~60 Data path logic 1~4 also uses conventional data paths to process floating point instructions~ The data path contains separate data paths for the exponent and for the mantissa, and operates on each according to the microinstructions from control store 1~3. In one specific embodiment, the data path logic comprises conventional A~D 29~1 bit slice microprocessors sold by Advanced Micro Devices, Inc.
Floating point accelerator 23 also includes interface control circuitry 1~7 that also receives signals from the central processing unit and assists in synchronizing the transfer of operands and processed data between the central processor unit 1~ and floating poin~ accelerator 23. A
detailed description of circuitry in control circuitry 1~7 is presented in FIG. 4.
In accordance with the invention, the central processing unit serially retrieves each instruction from the memory unit 11. Each instruction is loaded into instruction buffer 63 (FIG. 2). ~he ins~ruction buffer and the associa~ed processor then decode the instruction. If the instruction is a floating point instruction, that is, an instruction that indicates that the operands are in floating point format, it transmits the instruction to the floating point accelerator over the BUS IB D(7~ 8 (FIG 3.~l simultaneously asserting a synchronizing IRD STATE instruction read signal 1~9.
The instruction proce~sor 63 (FIG. 2) in central processor unit 1~ fur~her decodes the instructiOn and proceeds to retrieve the operands from the memory unit 11.
Each instruction may require one or more operands, and an operand may comprise sne or more data words in the memory depending on the required degree of arithmetic precision, each data word requiring a memory retrieval9 Each data word i5 ~ransferred through the ALU Ç~ (FIG. 2) o the central processor unit 1~, and transmitted over BUS Y D(31:0~
(FIG 3), the data section of accelerator bus 14. Each transfer over BU~ Y (D31~ is synchronized to the assertion of a CPU DATA AVAIL CPU data available signal 111.
The floating point ~ccelerator 23 receives each data word, in buffer l~S, and transfers it onto a BUS FPA floating 1~
l; point accelerator busl. The control s~ore 1~3 determin~s \~to which registers of data path logic 1~4 each transferred data word is to be stored ~t depending on whether the word forms part of the mantissa or the exponent. The instruction previously transferred into instruction decoder 1~1 also identifies the number of operands and th~ number of data words, required to process the instruction. Control store 1~3 causes the data words to be transferred through bufEer l~S and into registers in data path logic 1~4 in accordance with the numher of words to be received. After all the operands have been received, the data path logic 1~4, under control of control store 1~3, executes the instruction in a conventional manner.
~3-276 After the instruction has been executed, the control store 1~3 transmits an ACC S~NC accelera~or synchronization si~nal over line 12~ (FIG. 3) to central processor unit 1~
This signal is a signal in the microinstruction generated ~y control store 1~3 following exec~tion o~ each instruction.
The central processing unit 1~ receives ~he signal and services it as an interrupt service request. When it is ready to receive the processed data from the floa~ing point accelerator, it asserts a READ PORT signal on a line 121 and a SEL ACC IN select acce:Lerator in signal on line 122. Since several units may be connected to accelerator bus 14, the SEL
ACC IN select accelerator in signal serves to enable the floating point accelerator 23 to transmit on the BUS Y
D(31:0~ and prevents other attached units from transmittiny data over those lines. Tn successive clock cycles, the floating point accelera~or 23 transmits the condition codes and data words comprising the processed data from data path logic 1~4 across B~S FPA 112 through buffer 1~5 and across BUS Y D(31~ . The central processor unit 1~, specifically data path 2~, receives the condition codes and data words and transmits them to the memory unit 11 .
The arrangement according to the invention provides a much less complex interconnection arrangement be~ween central processor unit 1~ and a floating point accelerator 23. The special instruction, in one specific embodiment of a floating point instruction~ is ~ransmitted by the central processing ~ 17 -unit 10 to floating point accelerator processor 23, and the operands are then automatically and sequentially retrieved by data processor 2~ and transmitted directly to floating point accelerator 23 with no fllrther interaction between them. When the condition codes and pro-cessed data are ready, the floating point accelerator signals the cen-tral processing unit. When the central processing unit is ready to receive the processed data, it signals the :Eloating point accelerator, which responds with successive data words in successive clock cycles.
Both the central processor unit and floating point accelerator deter-LO mine the number of data words to be transferred in both directions, as operands and processed data, based on the contents of the instruc-tions. rherefore, the only communication back and forth as to the number of data words to be transferred is by way of the instruction.
This simplifies the floating point accelerator and the communications therebetween.
The central processing unit 10 and floating point acceler-ator also provide maintenance and diagnostic features in which the central processor unit 10 may transmit a "next microaddress" to the floating point accelerator control store 103 to place the control store in a specific and known address condition. Furthermore, the central processor unit may read, or retrieve, the "ncxt microaddress"
that is supplied by microaddress sequencer 102 to control store 103.
The operation by which the central processor unit forces the control store 103 to a known address condition will be ~3-276 ~ J ~
described in connection with FI~. 3. The central processor unit transmits a micr~address over BUS Y D(31:0~ t and asserts a TR~P ACC trap accelerator signal on line 123. The TRAP ACC trap accelerator signal is reoeived in control circuitry 1~7, which inhibits ~he microaddress se~uencer 1~2 from transmitting a next microaddress onto the control s~ore, and enables the signals on the BUS Y D(3100~) to be transmitted through buffer 1~5 and to the "next microaddress"
input to control store 1~3. The control s~ore 1~3 then transmits the microins~ruction iden~ified by the supplied signals, forcing a shift to the sequence defined by the address transmitted on B~S Y ~D31:0~) 11~.
The operation in which the ~entral processor unit 1 retrieves the microaddress transmitted by microaddress sequencer 1~2 will be explained in connection with FIG. 3.
The central processor unit first transmits a READ ACC UPC
read accelerator microprogram counter signal on line 124 to control circuitry 1~7. This conditions the floating point accelerator 23 to transfer the next microaddress generated by microaddress sequencer 1~2 to transceiver 132 in ~uffer 1~5.
During the next succeeding clock cycle, the central processor unit asserts the READ PORT signal Ol line 1~1~ At that time, the "next microaddress" is transmitted through buffer 1~5 onto BUS Y D(31:0~) in synchronism with the control store's assertion of the ACC SYNC accelerator sync signal on line 12 from control store 1~3. At ~he end of the clock cycle, the e'nex~ ~icroaddress" is removed from the BUS Y Dt31.0~
-and the floating point accelerator 23 returns to normal operation.
FIG. 4 depi.cts certain circuitry in control 107 that en-ables the floating point accelerator 23 to recelve the READ PORT, SEL
ACC IN select accelerator in signal$ READ ACC UPC read accelerator microprogram counter signal, and TRAP ACC trap accelerator signal and enables it to transmit and receive the associated signals over BUS Y
D(31:00).
The READ PORT and SEL ACC IN select accelerator in signals are received in the control circuit 107 and coupled to an AND gate 131. The coincidence of these signals causes the assertion of an CPU
RCV DAl'A central processing unit receive data signal which is coupled to branch logic 106. The branch logic enables the microaddress sequencer 102 to shift control store 103 to a sequence that causes the floating point accelerator 23 to transmit processed data and the condition codes to central processor unit 10. This signal also condi-tiOTIs a transceiver 132 in buffer 105 bet~een BUS FPA 112 and BUS Y
D~31:00) 110 to transmit data from floating point accelerator 23 to central processor unit 10.
The CPU RCV DATA central processing lmit receive data signal also energizes OR gates 134, 135 and one input to AND gate 136, which is also energi~ed by a CPU P~10 clocking signal :Erom centra.l pro-cessor unit 10, and an ALLOW CPU Y BUS signal :Erom control store 103 to enable transceiver 132.
When the TRAP ACC trap accelerator signal is asserted, neither the READ PORT nor the SEL ACC IN select accelerator , ~' 6 ~ ~ ~
in signals are assertedO Therefore, the CPU RCV DATA centra processor unit receive da~a signal is not asserted.
Transceiver 132 is thus conditioned to trans~er signals from BUS Y D(31:0~ to BUS FPA 112 through buffer 1~5. The transceiver is enabled by the TRAP ACC trap accelerator signal through OR gates 134 and 135, and AND gate 136 when the CPU PH0 timing signal and ALLOW CPU Y ~S signal from control store 1~3 are asserted.
The TRAP ~CC trap accelerator signal also causes a flip-flop 14~ to be set through AND gate 141 at ~he coincidence of the CPU PH~ and CLK OFF timing signals. The se~ting of flip-flop 14~ causes a ~ORCE UADRS force microad~ress signal to be asserted~ As shown in FIG. 3, this signal is transmitted from control 1~7 to microaddress sequencer 1~2. When the FORCE UADRS force microaddress signal is asserted, th2 address from microaddress sequencer 1~2 is no~ transmitted to control store 1~30 The FORCE UADRS force microaddress signal enables a transceiver ~ to transfer a next microaddress from the BUS FPA 112 to control store 1~3. The transceiver~
141 ~e enabled ~hrough an OR gate 143. The flip-flop 14~ is reset at the assertion of the next CPU PH~ timing signal but through an AND gate 144~
The control 1~7 receives the READ ACC UPC read accelerator microprogram counter signal in a flip-flop 15~, which generates a READ UADRS read microaddress signal, This READ VADRS read microaddress signal is coupled through OR
gate 143 to enable trans~eiver 142. However, since the EORCE
UADRS force microaddress signal is not asserted, the transceiver 1~2is conditioned to transmit the next microaddress signal from micro-address sequencer 102 onto BUS FPA 112. The flip-flop 15~ is then re-set through ~ND gate 151 at the next CPU PH~ clocking signal.
FIG. 5 depicts detailed sequences of the operations of transferring instructions, operands, and processed data, as well as microaddresses, between CPII 10 and floating point accelerator 23.
The sequences depicted in FIG. 5 are self-explanatory and a detailed description of these operations is not required here for an under-standi.ng of the inven-tion.
The foregoing description is limited to a specific embodi-ment of this invention. It will be apparent, however, that this invention can be practiced in systems having diverse basic construc-tion or in systems that use different internal circuitry than is des-cribed in this specification with the attainment of some or all of the foregoing objects a.nd advantages of this invention. It is the object of the appended claims to cover all such variations and modi-fi.cations as come within the true spirit and scope of this invention.
Claims (7)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A special instruction processor for processing a pre-determined class of instructions on a predetermined class of operands each containing a predetermined number of data words, the special instruction processor for connection to bus that also connects to a central processing unit that retrieves instructions and operands from, and transmits results of processing to, a memory, the instructions in said predetermined class each con-taining an operation code identifying the operation to be per-formed and the number of operands required to process the instruc-tion, the bus including lines for transferring instruction operation codes, data words and control signals including timing signals defining successive bus cycles between the central processing unit and the special instruction processor, the special instruction processor comprising:
A. means arranged to be connected to the instruction operation code and control lines of the bus for receiving instruc-tions of said predetermined class transmitted from the central processing unit and for decoding the instructions to determine the number of data words required to be received in order to process the operand;
B. means connected to said decoding means and arranged to be connected to the data and control lines of the bus for itera-tively receiving data words over the data lines in successive bus cycles, the number of data words received being determined by said decoding means;
C. means connected to said decoding means and said receiving means and arranged to be connected to the control lines of the bus for processing the operands in accordance with the operation defined in the operation code and for transmitting a control signal to the central processing unit when the processing has been completed;
and D. means connected to said decoding means and arranged to be connected to the data and control lines of the bus for transmitting the results of processing to the central processing unit over the data lines in successive bus cycles in response to a control signal from the central processing unit.
A. means arranged to be connected to the instruction operation code and control lines of the bus for receiving instruc-tions of said predetermined class transmitted from the central processing unit and for decoding the instructions to determine the number of data words required to be received in order to process the operand;
B. means connected to said decoding means and arranged to be connected to the data and control lines of the bus for itera-tively receiving data words over the data lines in successive bus cycles, the number of data words received being determined by said decoding means;
C. means connected to said decoding means and said receiving means and arranged to be connected to the control lines of the bus for processing the operands in accordance with the operation defined in the operation code and for transmitting a control signal to the central processing unit when the processing has been completed;
and D. means connected to said decoding means and arranged to be connected to the data and control lines of the bus for transmitting the results of processing to the central processing unit over the data lines in successive bus cycles in response to a control signal from the central processing unit.
2. A special instruction processor as defined in claim 1 wherein the central processing unit transmits an instruction operation code over the instruction operation code lines of the bus and an instruction read enabling signal over a control line of the bus when the instruction is one of the predetermined class of instructions, said decoding means comprising means arranged to be connected to the instruction operation code lines and the instruction read enabling signal line for receiving and decoding the instruction operation code in response to the receipt of said instruction read enabling signal.
3. A special instruction processor as defined in claim 1, the central processing unit including means for transmitting data words over the data lines of the bus and a data available signal over the control lines of the bus when it is transmitting the data words, said receiving means comprising:
A. buffer means arranged to be connected to the data lines of the bus for receiving data words over the data lines; and B. transfer control means connected to said decoding means and said buffer means and arranged to be connected to the data and control lines of the bus for enabling, in response to the data available signal, said buffer means to iteratively receive data words from the data lines during successive bus cycles.
A. buffer means arranged to be connected to the data lines of the bus for receiving data words over the data lines; and B. transfer control means connected to said decoding means and said buffer means and arranged to be connected to the data and control lines of the bus for enabling, in response to the data available signal, said buffer means to iteratively receive data words from the data lines during successive bus cycles.
4. A special instruction processor as defined in claim 1, the central processing unit includes means for receiving data words from the data lines of the bus and means for transmitting a read enabling signal over a control line of the bus, wherein said transmitting means includes:
A buffer means arranged to be connected to the data lines of the bus for transmitting data words over the data lines; and B. transfer control means connected to said decoding means and said buffer means and arranged to be connected to the data and control lines of the bus for enabling, in response to the read enabling signal, said buffer means to iteratively transmit data words from the data lines during successive bus cycles.
A buffer means arranged to be connected to the data lines of the bus for transmitting data words over the data lines; and B. transfer control means connected to said decoding means and said buffer means and arranged to be connected to the data and control lines of the bus for enabling, in response to the read enabling signal, said buffer means to iteratively transmit data words from the data lines during successive bus cycles.
5. A special instruction processor as defined in claim 4 wherein a plurality of units can be connected to the bus and the central processing unit includes means for transmitting a selec-tion signal over a control line in the bus, said transfer control means enabling said buffer means to transmit in response to the receipt of a selection signal from the bus identifying the special instruction processor.
6. A special instruction processor as defined in claim 1 wherein said processing means processes each instruction in a series of states each identified by a state address, the central processing unit including means for transmitting a state address over the data lines and a trap signal over the control lines of the bus, said special instruction processor further including:
A. buffer means arranged to be connected to the data lines of the bus for receiving and storing the state address received from the data lines;
B. means connected to said buffer means and to said pro-cessing means for transferring the contents of the buffer means to said processing means to force said processing means to a state identified by the state address; and C control means connected to said buffer means and said transfer means and arranged to be connected to the control lines of the bus for enabling said buffer means to receive the state address from the data lines and said transfer means to transfer the state address from said buffer means to said processing means in response to the receipt of a trap signal from the control lines.
A. buffer means arranged to be connected to the data lines of the bus for receiving and storing the state address received from the data lines;
B. means connected to said buffer means and to said pro-cessing means for transferring the contents of the buffer means to said processing means to force said processing means to a state identified by the state address; and C control means connected to said buffer means and said transfer means and arranged to be connected to the control lines of the bus for enabling said buffer means to receive the state address from the data lines and said transfer means to transfer the state address from said buffer means to said processing means in response to the receipt of a trap signal from the control lines.
7. A special instruction processor as defined in claim 1 wherein said processing means processes each instruction in a series of states each identified my a state address, the central processing unit including means for receiving a state address over the data lines and a read signal over the control lines of the bus, said special instruction processor further including:
A. buffer means arranged to be connected to the data lines of the bus for storing data signals and transmitting them over the data lines;
B. means connected to said buffer means and to said processing means for transferring the state address from said processing means for storage in said buffer means; and C. control means connected to said buffer means and said transfer means and arranged to be connected to the control lines of the bus for enabling said transfer means to transfer the state address from said processing means to said buffer means and for enabling said buffer means to transmit the state address over the data lines in response to the receipt of a read signal from the control lines.
A. buffer means arranged to be connected to the data lines of the bus for storing data signals and transmitting them over the data lines;
B. means connected to said buffer means and to said processing means for transferring the state address from said processing means for storage in said buffer means; and C. control means connected to said buffer means and said transfer means and arranged to be connected to the control lines of the bus for enabling said transfer means to transfer the state address from said processing means to said buffer means and for enabling said buffer means to transmit the state address over the data lines in response to the receipt of a read signal from the control lines.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/370,390 US4509116A (en) | 1982-04-21 | 1982-04-21 | Special instruction processing unit for data processing system |
| US370,390 | 1982-04-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1196108A true CA1196108A (en) | 1985-10-29 |
Family
ID=23459435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000426296A Expired CA1196108A (en) | 1982-04-21 | 1983-04-20 | Special instruction processing unit for data processing system |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4509116A (en) |
| EP (1) | EP0092429B1 (en) |
| JP (1) | JPS5916072A (en) |
| AU (1) | AU562479B2 (en) |
| CA (1) | CA1196108A (en) |
| DE (1) | DE3382305D1 (en) |
Families Citing this family (57)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4554630A (en) * | 1981-08-24 | 1985-11-19 | Genrad, Inc. | Control apparatus for back-driving computer memory and forcing execution of idle loop program in external memory |
| US4715013A (en) * | 1983-04-18 | 1987-12-22 | Motorola, Inc. | Coprocessor instruction format |
| US5021991A (en) * | 1983-04-18 | 1991-06-04 | Motorola, Inc. | Coprocessor instruction format |
| EP0525831B1 (en) * | 1983-04-18 | 1998-07-01 | Motorola, Inc. | Method and apparatus for enabling a processor to coordinate with a coprocessor in the execution of an instruction which is in the intruction stream of the processor. |
| US4758978A (en) * | 1983-04-18 | 1988-07-19 | Motorola, Inc. | Method and apparatus for selectively evaluating an effective address for a coprocessor |
| US4811274A (en) * | 1983-04-18 | 1989-03-07 | Motorola, Inc. | Method and apparatus for selectively evaluating an effective address for a coprocessor |
| US4914578A (en) * | 1983-04-18 | 1990-04-03 | Motorola, Inc. | Method and apparatus for interrupting a coprocessor |
| US4758950A (en) * | 1983-04-18 | 1988-07-19 | Motorola, Inc. | Method and apparatus for selectively delaying an interrupt of a coprocessor |
| US4821231A (en) * | 1983-04-18 | 1989-04-11 | Motorola, Inc. | Method and apparatus for selectively evaluating an effective address for a coprocessor |
| US4750110A (en) * | 1983-04-18 | 1988-06-07 | Motorola, Inc. | Method and apparatus for executing an instruction contingent upon a condition present in another data processor |
| US4731736A (en) * | 1983-04-18 | 1988-03-15 | Motorola, Inc. | Method and apparatus for coordinating execution of an instruction by a selected coprocessor |
| US4729094A (en) * | 1983-04-18 | 1988-03-01 | Motorola, Inc. | Method and apparatus for coordinating execution of an instruction by a coprocessor |
| JPH081604B2 (en) * | 1983-07-25 | 1996-01-10 | 株式会社日立製作所 | Microprocessor |
| US5165033A (en) * | 1983-07-25 | 1992-11-17 | Hitachi, Ltd. | Microprocessor and data processor using the former |
| US5193204A (en) * | 1984-03-06 | 1993-03-09 | Codex Corporation | Processor interface circuitry for effecting data transfers between processors |
| JPS6184740A (en) * | 1984-10-03 | 1986-04-30 | Hitachi Ltd | Generating system of general-use object code |
| US4707783A (en) * | 1984-10-19 | 1987-11-17 | Amdahl Corporation | Ancillary execution unit for a pipelined data processing system |
| JPH0766365B2 (en) * | 1985-03-08 | 1995-07-19 | 株式会社日立製作所 | Co-processor control system |
| US4860194A (en) * | 1985-06-04 | 1989-08-22 | Plus Development Corporation | A method for using a modular unitary disk file subsystem |
| US4639863A (en) * | 1985-06-04 | 1987-01-27 | Plus Development Corporation | Modular unitary disk file subsystem |
| US5070475A (en) * | 1985-11-14 | 1991-12-03 | Data General Corporation | Floating point unit interface |
| US4763294A (en) * | 1985-12-19 | 1988-08-09 | Wang Laboratories, Inc. | Method and apparatus for floating point operations |
| JPS62151971A (en) * | 1985-12-25 | 1987-07-06 | Nec Corp | Microprocessor |
| US4777613A (en) * | 1986-04-01 | 1988-10-11 | Motorola Inc. | Floating point numeric data processor |
| US5053941A (en) * | 1986-08-29 | 1991-10-01 | Sun Microsystems, Inc. | Asynchronous micro-machine/interface |
| US4800516A (en) * | 1986-10-31 | 1989-01-24 | Amdahl Corporation | High speed floating-point unit |
| US4926318A (en) * | 1986-11-12 | 1990-05-15 | Nec Corporation | Micro processor capable of being connected with a coprocessor |
| JPS63158657A (en) * | 1986-12-23 | 1988-07-01 | Fanuc Ltd | Coprocessor control system |
| US5001624A (en) * | 1987-02-13 | 1991-03-19 | Harrell Hoffman | Processor controlled DMA controller for transferring instruction and data from memory to coprocessor |
| US5226170A (en) * | 1987-02-24 | 1993-07-06 | Digital Equipment Corporation | Interface between processor and special instruction processor in digital data processing system |
| US5091845A (en) * | 1987-02-24 | 1992-02-25 | Digital Equipment Corporation | System for controlling the storage of information in a cache memory |
| IN171198B (en) * | 1987-02-24 | 1992-08-15 | Digital Equipment Corp | |
| JPS63259727A (en) * | 1987-04-17 | 1988-10-26 | Hitachi Ltd | Interface system for coprocessor |
| DE3855524T2 (en) * | 1987-06-19 | 1997-02-06 | Hitachi Ltd | Parallel arithmetic processing unit and associated compiler |
| JPH0679307B2 (en) * | 1987-10-22 | 1994-10-05 | 日本電気株式会社 | Coprocessor parallel operation control method |
| US4914581A (en) * | 1987-10-26 | 1990-04-03 | Motorola, Inc. | Method and apparatus for explicitly evaluating conditions in a data processor |
| JPH01147656A (en) * | 1987-12-03 | 1989-06-09 | Nec Corp | Microprocessor |
| US5027272A (en) * | 1988-01-28 | 1991-06-25 | Weitek Corporation | Method and apparatus for performing double precision vector operations on a coprocessor |
| JP2741867B2 (en) * | 1988-05-27 | 1998-04-22 | 株式会社日立製作所 | Information processing system and processor |
| US5210834A (en) * | 1988-06-01 | 1993-05-11 | Digital Equipment Corporation | High speed transfer of instructions from a master to a slave processor |
| EP0377970B1 (en) * | 1989-01-13 | 1995-08-16 | International Business Machines Corporation | I/O caching |
| US5287482A (en) * | 1989-01-13 | 1994-02-15 | International Business Machines Corporation | Input/output cache |
| US4961162A (en) * | 1989-01-13 | 1990-10-02 | International Business Machines Corporation | Multiprocessing system for performing floating point arithmetic operations |
| US5161219A (en) * | 1989-01-13 | 1992-11-03 | International Business Machines Corporation | Computer system with input/output cache |
| US5109495A (en) * | 1989-02-03 | 1992-04-28 | Digital Equipment Corp. | Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor |
| US5019965A (en) * | 1989-02-03 | 1991-05-28 | Digital Equipment Corporation | Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width |
| JP2754825B2 (en) * | 1989-02-03 | 1998-05-20 | 日本電気株式会社 | Microprocessor |
| US5067069A (en) * | 1989-02-03 | 1991-11-19 | Digital Equipment Corporation | Control of multiple functional units with parallel operation in a microcoded execution unit |
| DE69130519T2 (en) * | 1990-06-29 | 1999-06-10 | Digital Equipment Corp | High-performance multiprocessor with floating point unit and method for its operation |
| EP0623874A1 (en) * | 1993-05-03 | 1994-11-09 | International Business Machines Corporation | Method for improving the performance of processors executing instructions in a loop |
| US5898877A (en) * | 1996-02-29 | 1999-04-27 | Sanyo Electric Co., Ltd. | Processor using special instruction set to enhance exception handling |
| AU739533B2 (en) * | 1997-04-30 | 2001-10-18 | Canon Kabushiki Kaisha | Graphics processor architecture |
| US6505290B1 (en) * | 1997-09-05 | 2003-01-07 | Motorola, Inc. | Method and apparatus for interfacing a processor to a coprocessor |
| US5983338A (en) * | 1997-09-05 | 1999-11-09 | Motorola, Inc. | Method and apparatus for interfacing a processor to a coprocessor for communicating register write information |
| US5923893A (en) * | 1997-09-05 | 1999-07-13 | Motorola, Inc. | Method and apparatus for interfacing a processor to a coprocessor |
| US6636995B1 (en) | 2000-07-13 | 2003-10-21 | International Business Machines Corporation | Method of automatic latch insertion for testing application specific integrated circuits |
| JP4527571B2 (en) * | 2005-03-14 | 2010-08-18 | 富士通株式会社 | Reconfigurable processing unit |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4179734A (en) * | 1976-07-02 | 1979-12-18 | Floating Point Systems, Inc. | Floating point data processor having fast access memory means |
| JPS5461851A (en) * | 1977-10-27 | 1979-05-18 | Fujitsu Ltd | Data processing system |
| JPS5489455A (en) * | 1977-12-27 | 1979-07-16 | Toshiba Corp | Control system |
| US4208722A (en) * | 1978-01-23 | 1980-06-17 | Data General Corporation | Floating point data processing system |
| US4270167A (en) * | 1978-06-30 | 1981-05-26 | Intel Corporation | Apparatus and method for cooperative and concurrent coprocessing of digital information |
| US4229801A (en) * | 1978-12-11 | 1980-10-21 | Data General Corporation | Floating point processor having concurrent exponent/mantissa operation |
| US4395758A (en) * | 1979-12-10 | 1983-07-26 | Digital Equipment Corporation | Accelerator processor for a data processing system |
| US4338675A (en) * | 1980-02-13 | 1982-07-06 | Intel Corporation | Numeric data processor |
| EP0525831B1 (en) * | 1983-04-18 | 1998-07-01 | Motorola, Inc. | Method and apparatus for enabling a processor to coordinate with a coprocessor in the execution of an instruction which is in the intruction stream of the processor. |
-
1982
- 1982-04-21 US US06/370,390 patent/US4509116A/en not_active Expired - Lifetime
-
1983
- 1983-04-13 AU AU13498/83A patent/AU562479B2/en not_active Ceased
- 1983-04-19 DE DE8383302213T patent/DE3382305D1/en not_active Expired - Fee Related
- 1983-04-19 EP EP83302213A patent/EP0092429B1/en not_active Expired
- 1983-04-20 CA CA000426296A patent/CA1196108A/en not_active Expired
- 1983-04-21 JP JP58070857A patent/JPS5916072A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| DE3382305D1 (en) | 1991-07-11 |
| AU1349883A (en) | 1984-10-25 |
| EP0092429A2 (en) | 1983-10-26 |
| JPS5916072A (en) | 1984-01-27 |
| EP0092429B1 (en) | 1991-06-05 |
| EP0092429A3 (en) | 1987-01-21 |
| AU562479B2 (en) | 1987-06-11 |
| US4509116A (en) | 1985-04-02 |
| JPS6252345B2 (en) | 1987-11-05 |
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