CA1228933A - High density multi-layer circuit arrangement - Google Patents
High density multi-layer circuit arrangementInfo
- Publication number
- CA1228933A CA1228933A CA000479496A CA479496A CA1228933A CA 1228933 A CA1228933 A CA 1228933A CA 000479496 A CA000479496 A CA 000479496A CA 479496 A CA479496 A CA 479496A CA 1228933 A CA1228933 A CA 1228933A
- Authority
- CA
- Canada
- Prior art keywords
- insulative substrate
- conductor
- conductors
- openings
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
- H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
Abstract
A HIGH DENSITY MULTI-LAYER CIRCUIT ARRANGEMENT
ABSTRACT
An arrangement for constructing multi-layered printed circuits characterized by a first layer having top and bottom surfaces with the top surface including a plurality of parallel conductors divided into at least two conductor groups by a transversely oriented break across each conductor. The bottom surface further includes a plurality of parallel conductors arranged perpendicular to the conductors on the top surface and is also divided into at least two conductor groups by a transversly oriented break across each conductor. A plurality of holes extend through the first layer with, each hole adjacent to an intersecting conductor pair. A second layer including top and bottom surfaces and a plurality of plated-through holes has conductor pennants extending from selected holes in a first direction on the top sur-face and a second opposite direction on the bottom surface.
A plurality of first and second layers are sandwiched together, with each hole of each layer in registration with the other and each conductor pennant contacting a respective first layer conductor. Conductor segments printed on the second layer top and bottom surfaces inter-connect selected conductors between respective conductor groups. Additionally, two or more second layers are interconnected by via pins extending through the arrange-ment.
ABSTRACT
An arrangement for constructing multi-layered printed circuits characterized by a first layer having top and bottom surfaces with the top surface including a plurality of parallel conductors divided into at least two conductor groups by a transversely oriented break across each conductor. The bottom surface further includes a plurality of parallel conductors arranged perpendicular to the conductors on the top surface and is also divided into at least two conductor groups by a transversly oriented break across each conductor. A plurality of holes extend through the first layer with, each hole adjacent to an intersecting conductor pair. A second layer including top and bottom surfaces and a plurality of plated-through holes has conductor pennants extending from selected holes in a first direction on the top sur-face and a second opposite direction on the bottom surface.
A plurality of first and second layers are sandwiched together, with each hole of each layer in registration with the other and each conductor pennant contacting a respective first layer conductor. Conductor segments printed on the second layer top and bottom surfaces inter-connect selected conductors between respective conductor groups. Additionally, two or more second layers are interconnected by via pins extending through the arrange-ment.
Description
~2~ 3 A HIG~1 DENSITY MULTI-LAYER CIRCUIT ARRANGEMENT
CROSS-REFERENCE TO RELATED APPLICATION
The present application is related to co-pending Canadian app]ication serial number ~79,497-4, titled, "A High Density Multi-Layer Printed Circuit Arrangement," having the same inventive entity and being assigned the same assignee.
BACKGROUND OF THE INVENTION
This invention relates in general to circuit interconnection devices and more particularly to an arrangement for interconnecting solid state devices and other components that require multi-layer type substrates.
In a number of electronic applications, the interconnection of solid state devices require conductor paths, which if were wires, would cross paths many times. Therefore, to isolate the wire runs, multi-layer type etched or printed circuits are used, whereby specific runs are found on specific layers of the multi-layered circuit isolated from the next.
One present method of accomplishing complex interconnections is by bridging conductive paths with an insulating material and printing a conductor patch on the bridge to series connect the patch with a conductor path, creating in effect, a crossover. This may be repeated many times on a single circuit and with appropriate process steps may be tiered or layered, thus creating the multi-layer circuit.
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Another method is to print conductor ink on a plurality of ceramic substrates. The conductor paths on the ceramic substrates are accessed by via holes.
Once a set of substrates is printed with appropriate conductor paths, the substrates are aligned and stacked in their required order and fired at high temperatures in a furnace, creating an integral interconnection of conductors. The top layer is generally configured with conductor paths for the assembly of components.
The disadvantages of constructing the multi-layer circuits described above is in the excessive processing cost and the low yield. In the case of the crossover type, a great number of screening and furnace firing operations are necessary. The greater the number of firing operations, the lower the yield of the circuit.
Still another method of making multi-layer circuits requires a precise locating of each layer and a fusing of the conductors at via holes. This arrange-- ment also finds disadvantage in its costly operation and yield problem due to the very great number of con-nections that must be made.
Accordingly, it is the object of the present invention to provide a means to interconnect components of a circuit in an efficient and simple process when such interconnections are of such complexity so as to require mult;-layer circuit techniques.
~2~ 33 SUMMARY OF THE INVE TION
In accomplishing the option of the present, there is provided a multi-layered printed circuit arrange-ment having at least a first combination including a first insulative substrate having a top and a bottom surface. The top surface includes a first set of spaced and parallel conductors and the bottom surface includes a second set of spa ed parallel conductors. the first set of conductors is further divided into at least first and second conductor groups by a transversely oriented break across each conductorO Similarly, the second set of conductors is also divided into at least third and fourth conductor groups by a transversely oriented break across each conductor. The second set of spaced and parallel conductors are oriented perpendicular to the first set of conductors. The plurality of openings extend between the top and the bottom surfaces with each opening located adjacent to an intersection of a different one of the first and second set of conductors.
A second insulative substrate having a top and a bottom surface and a plurality of plated through openings is arranged to have its top surface attached to the first insu1ative substrate bottom surface with each of the second lnsulative substrate openings in registration with a respective one of the first insula-tive substrate openings. The second insulative substrate top surface further includes first connecting means extending from at least one of the plated through openings "
K 33~
and contacting one of the first insulatlve substrates second set of conductors. The second insulative sub-strate top surface may further include at least one conductor segment for interconnecting one conductor of the first insulative substrate's third conductor group to at least one conductor of the fourth conductor group. The second insulative substrate Eurther includes second connecting means on the bottom surface which also extend from at least one o the plated through openings.
The first combination is completed by the addition of a third insulative substrate which is identi-cal to the first insulative substrate. The third in-sulative substrate has its top surface attached to the second insulative substrate bottom surface and the second insulative substrate's second connecting means is arranged to contact one of the third insulating substrate's second set of conductors The second insulative substrate bottom surface may further include at least one conductor segment for interconnecting one conductor of the third insulative substrate's irst conductor group to at least one conductor of the second conductor group.
Additionally, the combination described above can be expanded by the addition of at least one addi-tional second combination which includes a fourth in-sulative substrate identical to the second insulative substrate. The fourth insulative substrate's top surface attaches to the third insulative substrate's bottom ~2~
surface with the fourtn insulative substrate's opening in registration with the third insulative substrate openings. The fourth insulative substrate's first connecting means contacts a least one of the third insulative substrate's second set of conductors.
A fifth insulative substrate identical to the first insulative substrate has its top surface attached to the fourth insulative substrate's bottom surface and the fifth insulative substrates openings in registration with a respective one of the fourth insulative substrate's openings. The fourth insulative substrate's second connecting means contacts at least one oE the fith insulative substrate's first set of conductors.
The first circuit combination and the second circuit combination are interconnected by interconnection means extending through the plated through openings of at least the second and fourth insulative substrates, connecting the first and second connecting means of the second insulative substrate to the first and second connecting means of the fourth insulative substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. I is a top plan view of the first insula-tive substrate or A-type layer of the present invention.
Fig. 2 is a top plan view of the second insula-tive substrate or B type layer in accordance with the present invention ~2~3~
Fig. 3 is an elevational view showing the stacking arrangement of the A-type layers to the B-typ~
layers and the interconnection of the layers using via pinsO
Fig. 4 is an elevational view showing the multi-layered printed circuit arrangement of the present inYention packaged on a plastic base and including via pins acting as terminals.
DESCRIPTION OE' THE PREFERRED EMBODIMENT
The proposed arrangement of the present inven-tion utilizes two types of layer elements, an A type layer as shown in Fig. 1 and a B type layer as shown in Fig. 2. By identifying the layers and conductor paths, very simple charts can be generated for the inter-connection of the A type layers with the B type layers.
The A type layer 10 as shown in Fig. 1 is essentially a sheet oE GE ULTEM or DUPONT KAPTON
plastic approximately 5 mils. or greater in thickness, with seymented conductor paths 10 mils. wide spaced 50 mils. apart. The conductor pattern is generaked by etching foil backed sheets or employing an additive process. The conductors 12 run in the horizontal direction or X direction on one side of the sheet and conductors 11 in the vertical direction or Y direction on the opposite side. Conductors 12 are interrupted by breaking conductors 11 along a common ax;s shown as 15 perpendicular to conductors 11 direction.
Conductors 11 are also interrupted by breaking onductors 11 along a common axis shown as 14 perpendicular to conductors 12 direction. The interruption ox sonductor 11 and 12 divides the conductors into six distinct yroups which are electrically isolated from each other. At the center of the squares defined by X and Y conductors 12, 11, a 20 milO diameter hole 13 is made It should be noted that the dimensions stated are merely for purposes of example and the invention is not limited thereto.
The B type layer 20 as shown in Fig. 2 is comprised of approximately 25 mil. or greater thick GE
ULTEM or DUPONT K~PTON plastic sheet with 20 mil.
diameter holes 23 in the same precise pattern as the holes 13 in the A type layer 10. In addition, an element of a conductor 22r 21, hereafter termed a penant, may be generated on either side oE this layer or on both sides at riyht angles to each other and connected by a plated-through hole 23. The penants 22, 21 ring the 20 mil. diameter hole 23 and project outward approxi-mately .030 inches either in the X or Y direction, depend-ing upon its function. Where penants 22, 21 on opposite sides are interconnected by plated-through holes, they are always at right angles to each other. The B type layer 20 Eurther includes conductor segments 35 on side 25 and conductor segments 36 on side 26. The conductor segments are used when a conductive bridge is required between one group and the next. A conductor segment 35 ~2~
would be used to electrically connect a conductor 11 of one group to the next. One or more of the conductor segments 35 and 36 may be used depending on the final circuit layout.
As shown in Fig. 3, the assembled A type layers 10 are placed on the bottom and the top of the B type layers 20. Conductors 11 in the X direction (the bottom 15 of the A type layer 10) become accessible to the top 25 of the B type layer 20. Conductors 11 in the Y direc-tion (the top 16 of the A type layer 10) become accessible to the bottom 26 of the B type layer 20. The bottom side of the B type layer 20 will have required penants 21 pointing in the X direction 90 as to intersect Y
direction conductors and the top 25 of B type layer 20 will have required penants 22 pointing in the Y direction so as to intersect the X direction conductors 12 of the associated A type layer 10. The various layers are interconnected by via pins 30 which are inserted into appropriate holes 13, 23 respectively. The via pins 30 may be hollow (tubes) or tubular on one end for receiv -ing component leads, or the tubes may act as receptacles for the pins of a socket type device, into which compo-nents can be plugged.
The conductors 11, 12 penants 21, 22 and con-ductor segments 35, 36 of the A type 10 and B type 20 layers respectively are solder coated with the A type layer 10 leveled with a hot-air knife/ leaving a solder thickness of 1-2 mils. The assembled A and B type layers and via pins are subjected to heat and some pressure, which reflows the solder joining the penants 21, 22 to the via pins 30 and conductor segments 35 and 36 to their appropriate X and Y conductor runs This results in an integral multi-layer circuit with more efficient use of area for conductor interconnections than present used multi-layer systems.
As shown in Fig 4, the final top layer 50 ]0 of the arrangement may receive component parts with socket terminals acting as via pins or ceramic hybrid thick/thin film circuits with holes for access to via pins. The bottom may be inserted to a plastic base or retainer 40 with longer via pins 35 acting as terminals for the multi-layer package Areas not required to be connected within the multi-layer package could be protected by solder resist.
It will appreciated by those skilled in the art that the A type layer 10 is a standard component part and thus would be quite cost effective since a large quantity can be processed at one time and stored until ready for assembly in a multi-layer package.
The B type layer ~0, although not a standard part, uses a standard tab penant 21, 22 and thus genera-tion of art work for any required pattern becomes relatively simple. The via pins may be interconnected to any level, creating the potential for very complex interconnections. Finally, the scheme gives the circui'c designer great flexibility as he can prototype circuits in a very short time.
although the preEerred embodiment of the inven-tion has been illustrated, in that form described in detail, it will he readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims
CROSS-REFERENCE TO RELATED APPLICATION
The present application is related to co-pending Canadian app]ication serial number ~79,497-4, titled, "A High Density Multi-Layer Printed Circuit Arrangement," having the same inventive entity and being assigned the same assignee.
BACKGROUND OF THE INVENTION
This invention relates in general to circuit interconnection devices and more particularly to an arrangement for interconnecting solid state devices and other components that require multi-layer type substrates.
In a number of electronic applications, the interconnection of solid state devices require conductor paths, which if were wires, would cross paths many times. Therefore, to isolate the wire runs, multi-layer type etched or printed circuits are used, whereby specific runs are found on specific layers of the multi-layered circuit isolated from the next.
One present method of accomplishing complex interconnections is by bridging conductive paths with an insulating material and printing a conductor patch on the bridge to series connect the patch with a conductor path, creating in effect, a crossover. This may be repeated many times on a single circuit and with appropriate process steps may be tiered or layered, thus creating the multi-layer circuit.
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1~28~3~
Another method is to print conductor ink on a plurality of ceramic substrates. The conductor paths on the ceramic substrates are accessed by via holes.
Once a set of substrates is printed with appropriate conductor paths, the substrates are aligned and stacked in their required order and fired at high temperatures in a furnace, creating an integral interconnection of conductors. The top layer is generally configured with conductor paths for the assembly of components.
The disadvantages of constructing the multi-layer circuits described above is in the excessive processing cost and the low yield. In the case of the crossover type, a great number of screening and furnace firing operations are necessary. The greater the number of firing operations, the lower the yield of the circuit.
Still another method of making multi-layer circuits requires a precise locating of each layer and a fusing of the conductors at via holes. This arrange-- ment also finds disadvantage in its costly operation and yield problem due to the very great number of con-nections that must be made.
Accordingly, it is the object of the present invention to provide a means to interconnect components of a circuit in an efficient and simple process when such interconnections are of such complexity so as to require mult;-layer circuit techniques.
~2~ 33 SUMMARY OF THE INVE TION
In accomplishing the option of the present, there is provided a multi-layered printed circuit arrange-ment having at least a first combination including a first insulative substrate having a top and a bottom surface. The top surface includes a first set of spaced and parallel conductors and the bottom surface includes a second set of spa ed parallel conductors. the first set of conductors is further divided into at least first and second conductor groups by a transversely oriented break across each conductorO Similarly, the second set of conductors is also divided into at least third and fourth conductor groups by a transversely oriented break across each conductor. The second set of spaced and parallel conductors are oriented perpendicular to the first set of conductors. The plurality of openings extend between the top and the bottom surfaces with each opening located adjacent to an intersection of a different one of the first and second set of conductors.
A second insulative substrate having a top and a bottom surface and a plurality of plated through openings is arranged to have its top surface attached to the first insu1ative substrate bottom surface with each of the second lnsulative substrate openings in registration with a respective one of the first insula-tive substrate openings. The second insulative substrate top surface further includes first connecting means extending from at least one of the plated through openings "
K 33~
and contacting one of the first insulatlve substrates second set of conductors. The second insulative sub-strate top surface may further include at least one conductor segment for interconnecting one conductor of the first insulative substrate's third conductor group to at least one conductor of the fourth conductor group. The second insulative substrate Eurther includes second connecting means on the bottom surface which also extend from at least one o the plated through openings.
The first combination is completed by the addition of a third insulative substrate which is identi-cal to the first insulative substrate. The third in-sulative substrate has its top surface attached to the second insulative substrate bottom surface and the second insulative substrate's second connecting means is arranged to contact one of the third insulating substrate's second set of conductors The second insulative substrate bottom surface may further include at least one conductor segment for interconnecting one conductor of the third insulative substrate's irst conductor group to at least one conductor of the second conductor group.
Additionally, the combination described above can be expanded by the addition of at least one addi-tional second combination which includes a fourth in-sulative substrate identical to the second insulative substrate. The fourth insulative substrate's top surface attaches to the third insulative substrate's bottom ~2~
surface with the fourtn insulative substrate's opening in registration with the third insulative substrate openings. The fourth insulative substrate's first connecting means contacts a least one of the third insulative substrate's second set of conductors.
A fifth insulative substrate identical to the first insulative substrate has its top surface attached to the fourth insulative substrate's bottom surface and the fifth insulative substrates openings in registration with a respective one of the fourth insulative substrate's openings. The fourth insulative substrate's second connecting means contacts at least one oE the fith insulative substrate's first set of conductors.
The first circuit combination and the second circuit combination are interconnected by interconnection means extending through the plated through openings of at least the second and fourth insulative substrates, connecting the first and second connecting means of the second insulative substrate to the first and second connecting means of the fourth insulative substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. I is a top plan view of the first insula-tive substrate or A-type layer of the present invention.
Fig. 2 is a top plan view of the second insula-tive substrate or B type layer in accordance with the present invention ~2~3~
Fig. 3 is an elevational view showing the stacking arrangement of the A-type layers to the B-typ~
layers and the interconnection of the layers using via pinsO
Fig. 4 is an elevational view showing the multi-layered printed circuit arrangement of the present inYention packaged on a plastic base and including via pins acting as terminals.
DESCRIPTION OE' THE PREFERRED EMBODIMENT
The proposed arrangement of the present inven-tion utilizes two types of layer elements, an A type layer as shown in Fig. 1 and a B type layer as shown in Fig. 2. By identifying the layers and conductor paths, very simple charts can be generated for the inter-connection of the A type layers with the B type layers.
The A type layer 10 as shown in Fig. 1 is essentially a sheet oE GE ULTEM or DUPONT KAPTON
plastic approximately 5 mils. or greater in thickness, with seymented conductor paths 10 mils. wide spaced 50 mils. apart. The conductor pattern is generaked by etching foil backed sheets or employing an additive process. The conductors 12 run in the horizontal direction or X direction on one side of the sheet and conductors 11 in the vertical direction or Y direction on the opposite side. Conductors 12 are interrupted by breaking conductors 11 along a common ax;s shown as 15 perpendicular to conductors 11 direction.
Conductors 11 are also interrupted by breaking onductors 11 along a common axis shown as 14 perpendicular to conductors 12 direction. The interruption ox sonductor 11 and 12 divides the conductors into six distinct yroups which are electrically isolated from each other. At the center of the squares defined by X and Y conductors 12, 11, a 20 milO diameter hole 13 is made It should be noted that the dimensions stated are merely for purposes of example and the invention is not limited thereto.
The B type layer 20 as shown in Fig. 2 is comprised of approximately 25 mil. or greater thick GE
ULTEM or DUPONT K~PTON plastic sheet with 20 mil.
diameter holes 23 in the same precise pattern as the holes 13 in the A type layer 10. In addition, an element of a conductor 22r 21, hereafter termed a penant, may be generated on either side oE this layer or on both sides at riyht angles to each other and connected by a plated-through hole 23. The penants 22, 21 ring the 20 mil. diameter hole 23 and project outward approxi-mately .030 inches either in the X or Y direction, depend-ing upon its function. Where penants 22, 21 on opposite sides are interconnected by plated-through holes, they are always at right angles to each other. The B type layer 20 Eurther includes conductor segments 35 on side 25 and conductor segments 36 on side 26. The conductor segments are used when a conductive bridge is required between one group and the next. A conductor segment 35 ~2~
would be used to electrically connect a conductor 11 of one group to the next. One or more of the conductor segments 35 and 36 may be used depending on the final circuit layout.
As shown in Fig. 3, the assembled A type layers 10 are placed on the bottom and the top of the B type layers 20. Conductors 11 in the X direction (the bottom 15 of the A type layer 10) become accessible to the top 25 of the B type layer 20. Conductors 11 in the Y direc-tion (the top 16 of the A type layer 10) become accessible to the bottom 26 of the B type layer 20. The bottom side of the B type layer 20 will have required penants 21 pointing in the X direction 90 as to intersect Y
direction conductors and the top 25 of B type layer 20 will have required penants 22 pointing in the Y direction so as to intersect the X direction conductors 12 of the associated A type layer 10. The various layers are interconnected by via pins 30 which are inserted into appropriate holes 13, 23 respectively. The via pins 30 may be hollow (tubes) or tubular on one end for receiv -ing component leads, or the tubes may act as receptacles for the pins of a socket type device, into which compo-nents can be plugged.
The conductors 11, 12 penants 21, 22 and con-ductor segments 35, 36 of the A type 10 and B type 20 layers respectively are solder coated with the A type layer 10 leveled with a hot-air knife/ leaving a solder thickness of 1-2 mils. The assembled A and B type layers and via pins are subjected to heat and some pressure, which reflows the solder joining the penants 21, 22 to the via pins 30 and conductor segments 35 and 36 to their appropriate X and Y conductor runs This results in an integral multi-layer circuit with more efficient use of area for conductor interconnections than present used multi-layer systems.
As shown in Fig 4, the final top layer 50 ]0 of the arrangement may receive component parts with socket terminals acting as via pins or ceramic hybrid thick/thin film circuits with holes for access to via pins. The bottom may be inserted to a plastic base or retainer 40 with longer via pins 35 acting as terminals for the multi-layer package Areas not required to be connected within the multi-layer package could be protected by solder resist.
It will appreciated by those skilled in the art that the A type layer 10 is a standard component part and thus would be quite cost effective since a large quantity can be processed at one time and stored until ready for assembly in a multi-layer package.
The B type layer ~0, although not a standard part, uses a standard tab penant 21, 22 and thus genera-tion of art work for any required pattern becomes relatively simple. The via pins may be interconnected to any level, creating the potential for very complex interconnections. Finally, the scheme gives the circui'c designer great flexibility as he can prototype circuits in a very short time.
although the preEerred embodiment of the inven-tion has been illustrated, in that form described in detail, it will he readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims
Claims (8)
1. A multi-layered circuit arrangement having at least a first combination comprising:
a first insulative substrate having a top and a bottom surface, said top surface including a first set of spaced and parallel conductors having at least one transversely oriented break across each conductor isolating said first set of conductors into a first conductor group and a second conductor group, and said bottom surface including a second set of spaced and parallel conductors oriented perpendicular to said first set of conductors said second set of conductors having at least one transversely oriented break across each conductor isolating said second set of conductors into a third conductor group and a fourth conductor group, and a plurality of openings extending between said top and bottom surfaces, each opening located adjacent to an intersection of a different one of said first and second set of conductors;
a second insulative substrate having a top and a bottom surface and a plurality of plated through openings, said second insulative substrate top surface attached to said first insulative substrate bottom surface with each of said second insulative substrate openings in registration with a respective one of said first insulative substrate openings, said second in-sulative substrate top surface further including first connecting means extending from at least one of said plated-through openings and contacting one of said first insulative substrate's second set of conductors, and said second connecting means bottom surface including second connecting means extending from at least one of said plated through openings; and, a third insulative substrate identical to said first insulative substrate having its top surface attached to said second insulative substrate bottom surface and said second insulative substrate second connecting means contacting one of said third insulative substrate's first set of conductors.
a first insulative substrate having a top and a bottom surface, said top surface including a first set of spaced and parallel conductors having at least one transversely oriented break across each conductor isolating said first set of conductors into a first conductor group and a second conductor group, and said bottom surface including a second set of spaced and parallel conductors oriented perpendicular to said first set of conductors said second set of conductors having at least one transversely oriented break across each conductor isolating said second set of conductors into a third conductor group and a fourth conductor group, and a plurality of openings extending between said top and bottom surfaces, each opening located adjacent to an intersection of a different one of said first and second set of conductors;
a second insulative substrate having a top and a bottom surface and a plurality of plated through openings, said second insulative substrate top surface attached to said first insulative substrate bottom surface with each of said second insulative substrate openings in registration with a respective one of said first insulative substrate openings, said second in-sulative substrate top surface further including first connecting means extending from at least one of said plated-through openings and contacting one of said first insulative substrate's second set of conductors, and said second connecting means bottom surface including second connecting means extending from at least one of said plated through openings; and, a third insulative substrate identical to said first insulative substrate having its top surface attached to said second insulative substrate bottom surface and said second insulative substrate second connecting means contacting one of said third insulative substrate's first set of conductors.
2. A multi-layered circuit arrangement as claimed in claim 1, wherein: said second insulative substrate top surface further includes at least one conductor segment connecting at least one conductor of said first insulative substrate third conductor group to at least one conductor of said fourth conductor group.
3. A multi-layered circuit arrangement as claimed in claim 2, wherein: said second insulative substrate bottom surface further includes at least one conductor segment connecting at least one conductor of said third insulative substrate first conductor group to at least one conductor of said fourth conductor group.
4. A multi-layered circuit arrangement as claimed in claim 3, wherein; there is provided a second combination comprising;
a fourth insulative substrate identical to said second insulative substrate, said fourth insulative substrate top surface attached to said third insulative substrate bottom surface and said fourth insulative substrate openings in registration with a different one of said third insulative substrate openings, and said fourth insulative substrate first connecting means contacting one of said third insulative substrate's second set of conductors; and, a fifth insulative substrate identical to said first insulative substrate having its top surface attached to said fourth insulative substrate bottom surface and said fifth insulative substrate openings in registration with a different one of said fourth insulative substrate openings and said fourth insulative substrates second connecting means contacting at least one of said fifth insulative substrate's first set of conductors.
a fourth insulative substrate identical to said second insulative substrate, said fourth insulative substrate top surface attached to said third insulative substrate bottom surface and said fourth insulative substrate openings in registration with a different one of said third insulative substrate openings, and said fourth insulative substrate first connecting means contacting one of said third insulative substrate's second set of conductors; and, a fifth insulative substrate identical to said first insulative substrate having its top surface attached to said fourth insulative substrate bottom surface and said fifth insulative substrate openings in registration with a different one of said fourth insulative substrate openings and said fourth insulative substrates second connecting means contacting at least one of said fifth insulative substrate's first set of conductors.
5. A multi-layered circuit arrangement as claimed in claim 4, wherein; said first circuit combination and said second circuit combination are interconnected by interconnection means extending through said plated through openings of at least said second and fourth insulative substrates, connecting said first and second connecting means of said second insulative substrate to said first and second connecting means of said fourth insulative substrate.
6. A multi-layered printed circuit arrange-ment as claimed in claim 5, wherein: said first insula-tive substrate top surface is arranged to accommodate electrical elements having terminals and said terminals comprising said interconnection means.
7. A multi-layered printed circuit arrange-ment as claimed in claim 6, wherein: said interconnection means are tubular via pins having hollow portions and said hollow portions extend outward of said first in-sulated substrate arranged to accept terminals of said electronic elements therein.
8. A multi-layered printed circuit arrange-ment as claimed in claim 7, wherein: said first and said second combinations are housed in a plastic base, said base including openings and said via pins extend outward of said fifth insulative substrate and said base through said base openings forming terminal pins arranged to be connected to a source of electrical signals.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US638,176 | 1984-08-06 | ||
| US06/638,176 US4598166A (en) | 1984-08-06 | 1984-08-06 | High density multi-layer circuit arrangement |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1228933A true CA1228933A (en) | 1987-11-03 |
Family
ID=24558951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000479496A Expired CA1228933A (en) | 1984-08-06 | 1985-04-18 | High density multi-layer circuit arrangement |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4598166A (en) |
| CA (1) | CA1228933A (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4700016A (en) * | 1986-05-16 | 1987-10-13 | International Business Machines Corporation | Printed circuit board with vias at fixed and selectable locations |
| JPH0648404B2 (en) * | 1986-06-12 | 1994-06-22 | コニカ株式会社 | Development device |
| US4847446A (en) * | 1986-10-21 | 1989-07-11 | Westinghouse Electric Corp. | Printed circuit boards and method for manufacturing printed circuit boards |
| US4888665A (en) * | 1988-02-19 | 1989-12-19 | Microelectronics And Computer Technology Corporation | Customizable circuitry |
| US5081561A (en) * | 1988-02-19 | 1992-01-14 | Microelectronics And Computer Technology Corporation | Customizable circuitry |
| US4927983A (en) * | 1988-12-16 | 1990-05-22 | International Business Machines Corporation | Circuit board |
| US5097593A (en) * | 1988-12-16 | 1992-03-24 | International Business Machines Corporation | Method of forming a hybrid printed circuit board |
| US4899439A (en) * | 1989-06-15 | 1990-02-13 | Microelectronics And Computer Technology Corporation | Method of fabricating a high density electrical interconnect |
| JPH0714024B2 (en) * | 1990-11-29 | 1995-02-15 | 川崎製鉄株式会社 | Multi-chip module |
| US5155302A (en) * | 1991-06-24 | 1992-10-13 | At&T Bell Laboratories | Electronic device interconnection techniques |
| US5623160A (en) * | 1995-09-14 | 1997-04-22 | Liberkowski; Janusz B. | Signal-routing or interconnect substrate, structure and apparatus |
| US6131279A (en) * | 1998-01-08 | 2000-10-17 | International Business Machines Corporation | Integrated manufacturing packaging process |
| US6198635B1 (en) * | 1999-05-18 | 2001-03-06 | Vsli Technology, Inc. | Interconnect layout pattern for integrated circuit packages and the like |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2932772A (en) * | 1956-06-11 | 1960-04-12 | Western Electric Co | Circuitry systems and methods of making the same |
| US2963626A (en) * | 1957-09-10 | 1960-12-06 | Jr Herbert Du Val | Control systems and apparatus |
| US3904934A (en) * | 1973-03-26 | 1975-09-09 | Massachusetts Inst Technology | Interconnection of planar electronic structures |
| GB1501500A (en) * | 1975-06-20 | 1978-02-15 | Int Computers Ltd | Multilayer printed circuit boards |
| JPS53129863A (en) * | 1977-04-19 | 1978-11-13 | Fujitsu Ltd | Multilayer printed board |
| US4434321A (en) * | 1981-02-09 | 1984-02-28 | International Computers Limited | Multilayer printed circuit boards |
-
1984
- 1984-08-06 US US06/638,176 patent/US4598166A/en not_active Expired - Fee Related
-
1985
- 1985-04-18 CA CA000479496A patent/CA1228933A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4598166A (en) | 1986-07-01 |
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