CA1230421A

CA1230421A - Analog storage integrated circuit

Info

Publication number: CA1230421A
Application number: CA000478018A
Authority: CA
Inventors: Soo I. Chae; Dietrich R. Freytag; Stephen L. Shapiro; Raymond S. Larsen; James T. Walker; Martin Breidenbach
Original assignee: Leland Stanford Junior University
Current assignee: Leland Stanford Junior University
Priority date: 1984-04-02
Filing date: 1985-04-01
Publication date: 1987-12-15
Also published as: DE3587082D1; EP0157607A3; AU4058085A; AU579856B2; US4811285A; JPS615499A; EP0157607A2; DE3587082T2; EP0157607B1

Abstract

ABSTRACT OF THE DISCLOSURE:

A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks.

Description

z~
A-40~69 ANAL~G STORAGE INTEGRATED CIRCUIT

The invention is directed generally to an analog storage device and more particularly to a device for very high speed sampling of analog pulse information, the pulse ~idths being in the range of 10's of nanoseconds.

An increasingly important problem in large scale physics detectors is the sampling of and recording of analog pulse information for pulse widths in the range of a few tens of nanoseconds with accuracy of the order of one percent and with a dynamic range o~ the order of eleven bits (one part in two-thousand). The generation of high precision time and amplitude information related to the outputs from various kinds of detectors is of consider-able significance in applications including high energy physics, transient digitizing of signals associated with nuclear impulses, laser fusion, optic communication, and general lab measurement methods. In most known systems, the accuracy degrades significantly as the signal to be sampled approaches the low end of the dynamic range. It is therefore an object of the present invention to provide an analog pulse sampling system and method which can maintain a high level of accuracy over a wide dynamic range.

An objective of the present invention is to provide an improved analog pulse storage integrated circuit.

Analog pulse storage systems frequently find use in instrumenting and recording the data from large scale experiments which may have up to several hundred thou-sand channels of information consisting of time and amplitude measurement of the signal. An objective o~
the present invention is to provide an integrated detector which is of small size, low power, and low cost to be used to detect the signal values carried on each channel.

Because of the very low pulse width, in the range of a few lO's of nanoseconds, an effective sampling rate of 2 x 108 samples per second is desirable, while maintaining accuracy on the order of 11 bits~

Prior art attempts to monitor and record analog pulse information for very small width pulses has frequently utilized threshold detectors which could not provide 2etailed analysis of the pulses heing studied.

An objective of the present invention is to provide analog pulse sampling information comprising a plurality of sample points for a pulse on any given channel, each sample having an aperture of about 1 nanosecond with a sample time position error less ~han or equal to 0.1 nanosecond.

The sample clock interval should be both very regular and at extremely high ~requency to provide a maximum number of samples across the pulse, which may have a pulse width of no more than a few lO's of nanosecondc.

Another objective of the present invention is to provide an integrated circuit solution, in order to reduce the cost and maximize the speed of the sampling chip. It is th~refore highly desirable to provide a chip having a sampling cell design which is highly regular and thus extremely reproducible on a large scale.

Known methods of high speed sampling for a multiple channel environment include cascaded discrete componen sample and holds in each channel. Howe~rer, the use Ol discrete components limits the number of channels which can be instrumented due to drive problems, and componert size and speed limits the number of samples which c~r~ be made per channel.

second known prior art device is the RETICO~ 5501 which is a bucket brigade device of a well known design.
However, this device as with the device described above must be cascaded, so that it suffers from drive problems and size limitation. Also, because of the way the circuit is designed, the sampling rate cannot be con-trolled except by cable delay of the sampling gate which is very cumbersome. The sampling aperture time is relatively limited. The analog storage system described in IEEE Transactions on Nuclear Science, Vol NS30, February 1983 at page 339-341 suffers from the same limitations, due to the use of a delay line.

Another method in some general use is to place a high speed or flash ADC analog to digital converter on each channel. Such devices work at rates of 100 x 106 samples per second (100 mhz) but yield accuracies no better than 5 to 6 bits, unless extended by elaborate additional circuitry. The cost of a single converter and the power consumption for each converter are both undesirably high for large systems, and probably imprac-tical for systems for greater than 100,000 channels.

The limitations of the prior art are overcome in the presently disclosed analog storage integrated circuit, in which each storage cell is defined to include two input gates between the pulse input at which the analog pulse information is received, and a storage capacitor for storing the analog signal level for the defined i~)Y ~ ~cJ ~ Q r k aperture. ~he cells are arrayed in rGl,7s and colu;-.s, and the input gates are controlled by separate ro~J and column clocks. One of the clocks operates at a rela-tively low rate; the other clock operates at the rate of sampling. Data is read and stored by each cell only or coincidence of the two clocks. Therefore, if the lo~"
speed clock is the column clock, and the high speed clock is the row clock, then the column clock need shift from column to column only after every row cell in that column has been activated by the row clock.

Utilizing this arrangement, one clock may be continuous-ly running, the other clock being initiated by de-tection of the pulse to be sampled, or by receipt of a known time marker or trigger synchronously with the arrival of the data pulse to be sampled.

Use of a chip design having such a regular array of cells lends itself to cascading to extend the number of samples per channel before any stored cell data is read out.

In a further advantage, if a sufficient number of cells are provided to separately store all the analog pulse sample information appearing on a channel, then the storage time can be extended to any length compatible with the ultimate data storage device.

In the data storage array of the present invention, a separate reference cell is provided of identical design to all of the storage cells on the chip, but not receiv-ing any of the analog pulse information. By reading out the analog storage cell in parallel with the output of the storage transistor on each cell through matched transistors incorporated in each cell, any degradation of the analog information on the cell with storage time can be taken into account. Further, reading out the - 5 - 1051-125~
information through matched transistor pairs for the reference cell output and the storage capacitor cell output on a differential basis maintains -the absolute accuracy of the magnitude of the analog data stored in each cell.
In a further advantageous feature of the present invention, the columns are divided vertically into two halves.
Therefore, the column pulse which activates the controls for the cells in the bottom half of the column can overlap in real time with the pulse being used to activate the control gates for the other half of the column. By interleaving the numerical sequence of row activation, the speed of the actual pulse writing (storage) is optimized, while minimizing the complexity of the input clock timing circuitry.
According to a broad aspect of the invention there is provided a high speed data acquisition system for storing a succession of analog signal sample values comprising analog signal input means and analog signal output means, a first analog bus connected to said input means and a second analog bus connected to said output means, a storage array comprising a plurality of cells arranged in rows and columns, row clock means coupled to said array for selectively activating each row of said array, column clock means coupled to said array for selectively activating each column of said array, said input means being directly connected to said array for supplying said analog signal to the cells of the array, and means responsive to the row and column clock means for successively activating each of said cells for storing said succession of analog pulse sample values, each of said cells ,.1, - 5a - 1051-1~53 comprising a pair of gates connected between said input and means in said cell for storing said analog signal sample value, said gates being responsive to said row and column clock activating means, each of said cells comprising a voltage follower coupled to said capacitor and a multiplex output device connected between said voltage follower and said output bus for transferring a proportional representation of said stored voltage increment to said output bus.
According to another broad aspect of the invention there is provided a method of very high frequency analog pulse sampling utilizing an array of cells arranged in n rows and m columns, comprising selectively activating each row of said array while each of said columns is activated selectively, activating each column of said array, supplying said signal to the cells of the array, said rows being activated for a time interval defining the minimum pulse sampling interval, said row activating step comprising activating alternate ones of the n rows in said pulse sampling cycle, the rows 1 through n/2 being interleaved with the rows (n/2~ ~ 1 to n to reduce the sample spacing time limit caused by propagation delay n in the column clock path.
The foregoing and other advantages of the present invention will become more apparent from a study of the following figures wherein:

- 5b - 1051-1853 FIGURE l comprises a block diagram of the analog storage integrated circuit system of the present invention.
FIGU~E 2 is a more detailed block diagram of the on-chip input shift register of the present invention.
FIGURE 3 is a schematic diagram of the structure of each of ~he cells incorporated in the 16 x 16 memory cell array shown in Figure 1.
FIGURE 4 is a more detailed schematic of the reference cell of the present invention.
FIGURE 5 illustrates the relative timing of two column clock pulses to the split line of cells in each column, as well as the relative timing of the row and column timing pulses.

The basic elements of the analog storage inteara-ea circuit are shown in figure 1. All These elemen's illustrated are on chip except the row gate puk-,e generator 12 which comprises the row clock trigger. A
differential buffer Inot shown) is also provided Cor reading out the stored data to a remote memory. The input signal which is an analog pulse typically of a few 10's of nanoseconds is applied simultaneousl~ to all of the inputs of all of the cells via inputs SIGl and SIG2.
Typically there are two~hundred-fifty-six cells on each sampler chip arrayed 'n a 16 x 16 matrix as shown in figure 1. Each cell is designed in accordance with the schematic shown in figure 3. As shown therein, each of the cells includes a storage capacitor 20 which is capable of storing charge only during the time period that both of the input gate transistors Ql, Q2 are turned on. The other details of the cell of Figure 3 are explained below.

Returning to Figure 1, the row gate clock pulse genera-tor 12 runs continuously at the analog pulse sampling rate. The arrival of the analog data pulse on input lines SI~l, SIG2 is signaled by either a threshold detector which detects the actual pulse, or a pulse detector which receives a trigger pulse which is trans-mitted in timed relation to receipt of the analog pulse.Turning on the column counter 28 will now transmit column clock input signals to each of the memory cells in turn. This signal to each cell is shown as 0c at gate Q2 in Figure 3. Coincidence of the row and column clock signals at any gate allows storage of a brief analog sample (aperture about 1 nanosecond) of the data pulse on the storage capacitor. Signal storage occurs when 0f makes a high to low transition, turning OFF Q1.
The stored value cannot be altered by 0f being at a high state if 0c is low so that Q2 is off. The gate transis-tors are separately acti~ated by a row clock generator 12 and a column gate pulse generator 28 which includes a unit driver 29 and shift register 30. Two points are significant with respect to ~rrangement of the merory cells. It can be seen that the 16 fast clock pulses are provided to rows which are interleaved; that is, the numbers on the l~ inputs represent the order in whicr.
the rows are triggered. This is to allow for the propagation time of the column clock signals up the columns, since the row clock signals are transferre~
horiz~ntally on metal lines which carry signals at very fast speeds, but the clock signals run vertically up polysilicon lines which have longer propagation delays.
Because of the high speed at which the column gates are triggered, with only 80 nanoseconds allocated per column, each column is actually divided in two sections.
That is, in each vertical column of 16 cells, 8 of the cells are triggered by one output of the shift register and driver 28. The other 8 cells, are triggered off a second output. Thus for example alternate groups of cells in the trigger sequence (1-8,9-16) are triggered ~y alternate column clock outputs (0c1,0c2). Thus the input shift register 28 which provides column clock signals to the columns has 32 outputs (0c1,...0c32).
Note that the input shift register 28 (shown in figure

2) comprises a set of half-shift registers 30 and accompanying drivers, both of standard design. The major control signals which are used to implement this timed storage operation are shown both in figure 2 and figure l;

INHS: runs to column access drivers; if low, turns off the column clocks so no cells can be turned on, preventing an attempt to store data into a cell which has not yet been read of previously stored data.

01s, ~2s: the two phase column clocks for driving the two sets of half shift registers; this is necessary because of the overlapping output of the cclumn c ock pulses shown in Figure 5.

RFSET: initializes all registers to starting state.

START: puts bit in first register to be advanced throu~h registers by 01s, 02s.

INHRI: if low, clears all column clocks to 0; if high, then recirculation occurs, so that the first two half shift registers are high, (see Figure 2) and the rest are zero.

END: if cells are cascaded, then this signal output occurs at the proper t;me to start data storage in the next chip.

The Recirculation logic, 35, shown in detail in Figure 2, responds to and generates these last three signals.
Generation of the other identified signals is accomplished by techniques well known in this art.

The x and y coordinate output shift registers 32, 34 are of similar design to those shown in Figure 2f The clock logic is used to simplify chip layout, as these shift registers run at the same rate-typically significantly slower than the input rate.

Returning to the design of the memory cell itself, as shown in Figure 3 each cell includes in addition to the input section a highly linear output stage. Speci~lcal-ly, each memory cell includes a nonloading readoutamplifier section ~0, and multiplex readout portion 42 for conveying a linear representation of the charge stored on the capacitor 20 through the multiple~ readout portions 42 and 44 to the chip outputs OUT and OUT.

E?.ch of the output sections including the non-lGac~lrg amplifier 40 and the buffer amplifier 42 cor,-~rise matched pairs of identical transistors. The inpu~ to the transistor Q5 of amplifier 40 is connected to the capacitor Cs. Thus upon coincidence of the readout signa~s ~x~ 0y from the output shift drivers 32, 34 the voltage at point A linearly tracks the voltage stored or Cs .
By providing a transistor Q7 to function as a current mirror, and a transistor Q9 which has the voltage at point A applied to its gate and functions as a ~ource follower, a linear representation of the magnitude of the voltage stored on the capacitor 20 can be applied to the output bus through the multiplexor 44.

In order to provide for temperature compensation and leakage from the capacitor, a reference cell 60 shown in detail in figure 4 is provided on each chip. As can be seen from figure 4, the design of the reference cell 60 is identical to the design of each of the memory cells in the array. The cell is pulsed by IN~S after all data cells have received the data which they are to store;
thus the voltage V ref which is applied to the transis-tor Q6 provides a differential reference level which is coupled through transistors Q8, Q10, Q12, and Q14 to the output bus so that a reference level is always available which accounts for the temperature changes and capacitor leakageO Thus the output being read as a differential output will accurately represent the analog pulse sample. The use of differential signal readout for Vsig, together with careful use of matched transistor pairs 40 and 42 from Cs and V ref through the multiplexer 44 to the output prevents signal level errors due to process and temperature variations.

A-40~9 10 Two further transistors Q3 and Q4 are provided ir he cell input stage to further enhance the accuracy of the stored analog value. A signal 0reset is provided to gate a transistor Q4 connected across the storage capacitor 20 incorporated in each memory cell. This is provided to allow for draining the storage capacitor 2G
to ground after the data has been read out to remote storage. A second signal 0INH is provided to gate a transistor Q3 connected to a node in between the two gate transistors Q1, Q2. This is used to grouna the intermediate node, so that any leakage current, gate or signal feed-through from the first gate, which is the gate receiving the continuously running fast row clock pulses, does not affect the readout of the storage capacitor 20.

It will be apparent to one of skill in the art who has reviewed the subject invention disclosed, that the integrated circuit design of the present invention provides a number of significant advantages in the field of physics data recording. The use of NMOS IC technolo-gy, for the analog storage cell, allows an order of magnitude improvement in density and makes practical systems of a very large scale because of the ease of reproduction of the integrated circuit and the low power consumption. The accuracy of the analog samples record-ed will be significantly improved because of the identi-ty of every cell in the memory cell array. The power consumption will be significantly reduced over known prior art methods such as Flash A/D converters. Any high power circuitry required for drive purposes can be shared by many channels. The dynamic range, the sampling aperture, and the accuracy are much improved over known methods. An accuracy of 11 bits (one ir two-thousand) compared with six bits (one in six-ty-four), is achieved. The cost per channel in large scale systems will be significantly reduced. The figure of merit (speed x dynamic range divided by coct) r,Jill yield an improvement ratio of at least 100 to 1 compared with current alternatives, Persons skilled in this field on reviewing this invention disclosure may ma'v.e modifications to the present design. Therefore, the scope of the present invention is to be l~mited only by the following claims,

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A high speed data acquisition system for storing a succession of analog signal sample values comprising analog signal input means and analog signal output means, a first analog bus connected to said input means and a second analog bus connected to said output means, a storage array comprising a plurality of cells arranged in rows and columns, row clock means coupled to said array for selectively activating each row of said array, column clock means coupled to said array for selectively activating each column of said array, said input means being directly connected to said array for supplying said analog signal to the cells of the array, and means responsive to the row and column clock means for successively activating each of said cells for storing said succession of analog pulse sample values, each of said cells comprising a pair of gates connected between said input and means in said cell for storing said analog signal sample value, said gates being responsive to said row and column clock activating means, each of said cells comprising a voltage follower coupled to said capacitor and a multiplex output device connected between said voltage follower and said output bus for transferring a proportional representation of said stored voltage increment to said output bus.

2. A system as claimed in Claim 1 wherein said row and column activating means comprise clock driven devices operating at first and second rates of repetition.

3. A system as claimed in Claim 1 wherein said storage means in said cell comprise a capacitor which cooperates with the internal resistance of said gate to form an RC circuit having a short time constant defining the time aperture of said analog sample.

4. A system as claimed in Claim 3 wherein each of said gates comprises an N-channel device.

5. A system as in Claim 2 wherein said row and column activating means comprise first and second clock drivers , one of said clock drivers running continuously, the second of said clock drivers being periodically activated upon receipt of said input signal.

6. A system as claimed in Claim 2 further comprising a reference cell comprising two input gates and a storage capacitor and having an output connected in parallel with the output of each cell of the array, the decaying voltage on the capacitor representing the nominal decay of cell storage voltage with time occurring in each cell of the array.

7. A system as claimed in Claim 5 wherein each of said columns in the array is divided into first and second portions, the second of said clock drivers having separate outputs running to said first and second portions of said column, alternate ones of the output clock pulses from said outputs being overlapping in time.

8. A system as claimed in Claim 7 wherein said row activating means comprises said continuously running clock, successive row activating pulses being connected to alternate rows of said array.

9. A system as claimed in Claim 8 comprising a conse-cutively numbered rows wherein rows numbered from 1 thru n/2 are interleaved with rows numbered from (n/2)+1 to n.

10. A system as claimed in Claim 3 wherein the time constant of said RC circuit is less than 1 nanosecond.

11. A system as claimed in Claim 4 further including a switch coupled between the output of said input gates and said capacitor and responsive to a reset signal for grounding the capacitor whereby rapid resetting of a sequence of said signals is developed.

12. A system as claimed in Claim 3 further comprising means for grounding at least one of said gates outputs during a reading cycle whereby the signal leakage of said input gates does not affect the output voltage from a cell of said system.

13. A system as in Claim 1 further comprising means coupled via said output means to said output bus coupled to said cells for reading out the data stored in the array comprising a first row shift register means for generating row activating readout signals and a second column shift register means for generating column readout signals, said column readout shift register advancing by one column each time every row has been pulsed by said row shift register.

14. A system as claimed in Claim 13 further comprising means coupling said row and clock shift register means for causing completion of a cycle by said row shift register means to advance said column shift register.

15. A method of very high frequency analog pulse sampling utilizing an array of cells arranged in n rows and m columns, comprising selectively activating each row of said array while each of said columns is activated selectively, activating each column of said array, supplying said signal to the cells of the array, said rows being activated for a time interval defining the minimum pulse sampling interval, said row activating step comprising activating alternate ones of the n rows in said pulse sampling cycle, the rows 1 through n/2 being interleaved with the rows (n/2) + 1 to n to reduce the sample spacing time limit caused by propagation delay n the column clock path.

16. A method as claimed in Claim 15 wherein said rows are being continuously cyclically activated, said columns being activated only during receipt of said pulse to be sampled.

17. A method as claimed in Claim 16 wherein said rows are activated at a multiple of the rate at which columns are activated.

18. A method as claimed in Claim 17 further comprising the step of providing a reference cell identical in construction to the cells in said array but not receiving said signal input, the method including the step of reading the output of each cell as a differential output compared to output of the reference cell whereby leakage and offset are taken into account.

19. A method as defined in Claim 17 wherein each column is divided into two sections having an equal number of cells, the method including the step of providing actuating pulses to the cells of said sections overlapping in real time to maximize the speed of writing to each cell.

20. A method as claimed in Claim 19 including the step of activating alternate ones of the n rows in said pulse sampling cycle, the rows 1 through n/2 being interleaved with the rows (n/2) + 1 to n to reduce the sample spacing time limit caused by propagation delay in the column clock path.