CA1258718A - Metallized semiconductor device including an interface layer - Google Patents
Metallized semiconductor device including an interface layerInfo
- Publication number
- CA1258718A CA1258718A CA000534348A CA534348A CA1258718A CA 1258718 A CA1258718 A CA 1258718A CA 000534348 A CA000534348 A CA 000534348A CA 534348 A CA534348 A CA 534348A CA 1258718 A CA1258718 A CA 1258718A
- Authority
- CA
- Canada
- Prior art keywords
- essentially
- layers
- titanium
- semiconductor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 46
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 20
- 239000010936 titanium Substances 0.000 claims abstract description 20
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 6
- 150000001875 compounds Chemical group 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- 239000012212 insulator Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000000637 aluminium metallisation Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 238000001465 metallisation Methods 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- -1 e.g. Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 229910052762 osmium Inorganic materials 0.000 description 2
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000004321 preservation Methods 0.000 description 2
- 229910052703 rhodium Inorganic materials 0.000 description 2
- 239000010948 rhodium Substances 0.000 description 2
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 244000187656 Eucalyptus cornuta Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000005001 rutherford backscattering spectroscopy Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12528—Semiconductor component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12771—Transition metal-base component
- Y10T428/12806—Refractory [Group IVB, VB, or VIB] metal-base component
Abstract
METALLIZED SEMICONDUCTOR DEVICE
INCLUDING AN INTERFACE LAYER
Abstract Structures of alternating amorphous layers of titanium and a semiconductor material serve as effective interface layers between an insulator or semiconductor material and an aluminum metallization material in semiconductor devices. Such structures effectively serve to minimize interdiffusion during device manufacture without undue increase in electrical contact resistance during device operation.
INCLUDING AN INTERFACE LAYER
Abstract Structures of alternating amorphous layers of titanium and a semiconductor material serve as effective interface layers between an insulator or semiconductor material and an aluminum metallization material in semiconductor devices. Such structures effectively serve to minimize interdiffusion during device manufacture without undue increase in electrical contact resistance during device operation.
Description
~S~7~
MErl'ALLIZED S~MICONDUC'l~P~ ~EVICE
IllCL[]DI~IG A~ ERE~CL L~YER
Technical Eield rrhe invention is concerned with devices comprising an electricalLy conducting interface or contact layer ~etween metal and semiconductor materials.
Background of t_ Inventio Integrated device technology depends heavily on the use of metallization layers and the patterning of such layers on semiconductor and insulator materials;
typically, such materials are doped or undoped silicon, gallium arsenide, other binary, ternary, or ~uaternary III-V or II-VI semiconductor materials, or insulator materials such as, e.g., silica, alumina, and polymeric layers. Familiar metallization materials may be selected, e.g., from the group of noble metals; see, e.g., U. S. patent 3,881,~8~ which discLoses the manufacture of a composite conductive layer comprisiny
MErl'ALLIZED S~MICONDUC'l~P~ ~EVICE
IllCL[]DI~IG A~ ERE~CL L~YER
Technical Eield rrhe invention is concerned with devices comprising an electricalLy conducting interface or contact layer ~etween metal and semiconductor materials.
Background of t_ Inventio Integrated device technology depends heavily on the use of metallization layers and the patterning of such layers on semiconductor and insulator materials;
typically, such materials are doped or undoped silicon, gallium arsenide, other binary, ternary, or ~uaternary III-V or II-VI semiconductor materials, or insulator materials such as, e.g., silica, alumina, and polymeric layers. Familiar metallization materials may be selected, e.g., from the group of noble metals; see, e.g., U. S. patent 3,881,~8~ which discLoses the manufacture of a composite conductive layer comprisiny
2~ an exposed layer of goJd, platinum, palladium, iridium, rhodium, ruthenium, or osmium, underlying non-noble conductor material being separated from an insulating substrate by means of a titanium anti-diffusion layer.
U. S. patent 3,657,029 discloses a method for patterning a multi-layer metallization of platinum, palladium, rhodium, ruthenium, osmium, or iridium there, a layer of titanium or chromium is used as a mask material.
Popular also is the use of aluminum and aluminum alloys as relatively inexpensive alternatives to noble metals; for example, U. S. patent 4,017,890 discloses aluminum and aluminum-copper conductor stripe metallizations.
Typically, ~hen aluminum or aluminum alloys are used for silicon device metallization, a contact material is placed between doped silicon source reyions, ~2S8~7~
doped silicon drain regions, and silicon oxide gate regions on the one hand, and the aluminum-containing interconnect metallization. Moreover, it has been Eound desirable to interpose an interface material between contact and interconnect metallizations; such interface material has desirably low resistivity and acts as a barrier against interdiffusion during device manufacture.
While, in this respect, the use of tungsten has been advocated as an interface material, there remains a need for interdiffusion barriers which retain their efficacy at elevated temperatures. In particular, such barriers are desired to remain effective at temperatures significantly greater than approximately 450 degrees C.
~ummary of the Invention It has been discovered that structures consisting of alternating amorphous layers of titanium and a semiconductor material are suitable as contact and interface layers in device manufacture where aluminum or aluminum alloy metallizations are being used.
In accordance with one aspect of the invention there is provided a device comprising a body of semiconductor; material and an electrical conductor element which consists of a material which comprises aluminum in an amount of at least 90 weight percent, characterized in ~hat, between said body and said conductor element, there is a structure of alternating, essentially amorphous, first and second interface layers of first material which consists essentially of tltanium, and second material which consists essentially of semiconductor material.
In accordance with another aspect of the invention there is provided a method for making a device comprising a body of semiconductor material and an electrical conductor element which consists o~ a material which comprises aluminum in an amount of at least 90 ~S~71~3 - 2a -weight percent, characterized in that, between said body and said conductor element, a structure of alternating, essentially amorphous interface layers is depositefl consisting of a first makerial which consis~s essentially of titanium, and a second material which consists essentially of a semiconductor ma~erial, and said method comprises processing at a temperature which is greater than 200 degrees C.
Brief Description o~ the Drawing The Figure shows, enlarged and in schematic cross section, an integrated semiconductor device comprising three interface layers in accordance with the invention.
~etailed Description -The Figure schematically shows a cross section of an n-channel metal-oxide semiconductor device (MOS) comprising a body of silicon 1 which is doped p plus except for a source region 2 and a drain region 3 which are doped n-plus. A channel region 4 is covered with a gate oxide layer 5, and field oxide regions 6 adjoin the source region 2 and the drain region 3. A source contact layer 7 is on the source region 2, a drain contact layer 8 is on the drain region 3, and a gate contact layer 9 i5 on the gate oxide layer 5. Interface 1~25871~
layers 10 and 11 are on tne contact layers ~ and ~, respectively; a first insulating oxide layer 12 insulates thc field oxi~e rcyions 6 as wre~ 5 thr~ yate contac-t layer ~; and a first int~rconnect metallization 13 is sho~"n in contact with layers '~, 10 and 11. A second insulating oxide layer 14 is on the interconnect metallization layer 13, and a second interconnect rnetallization layer 15 on the second insulating oxide layer l~ is in contact ~Ji th the first interconnect metallization layer 13 through etched windows in the second insulating oxide layer 14.
In accordance with the invention a contact or interface layer such as, e.y., gate contact layer 9, interface layer 10, and interface layer 11 is made as a structure of alternating amorphous layers of titanium and a semiconductor material. ~It is understood that, especially under conditions of processing at elevated temperatures, there will be a certain amount of alloy formation at layer interfaces. Such partial alloying does not significantly reduce the anti-interdiffusion efficacy of a layered structure and may contribute to desired low contact resistance.) Titanium layers preferably cc)mprise at least 99 weight percent titanium, the remaining at most l percent being made up of impurities such as, e.g., iron or nickel. In the interest of essentially amorphous structure, titanium layer thickness does not exceed approximately ~ nanometers and preferably 5 nanometers. For the sake of ease of deposition of a continuous layer, preferred thiclcness is at least 0.1 micrometer.
Semiconducting layers may consist of undoped, p-doped, or n-doped semiconductor material, and such material may be elemental, compound, or mixed. Silicon is considered particularly suitable in combination with titanium for interface structures between silicon substrates and aluminum metallizations. Thickness of ~'~58'7~8 silicon layers is less critic;il thiln titanium layer thic~ness; however, tt~ickncsses ~reatf-r t}1an lO nanometers are consi~ered a_ une1(onomical witt1 respect to the purpose of the invention. Also, for the sake of continuity of a depositec3 layer, preEerred thickness is at least O.l micrometer.
The number of periods of alternating layers mcay oe from l or, preferably, 2 to 500, greater numbers giving increased protection against in~erdiffusion and also greater contact resistance.
Structures in accordance with the invention are intended primarily for tlle protection against interdiffusion between aluminum metallizations and semiconductor or insulator materials during device manufacture involving processing at elevated - temperatures. In this respect, semiconductor device processing may involve heating to temperatures above 20Q degrees C. Aluminum metallizations typically are made of aluminum which has been alloyed with a small amount of copper, preferred aluminum content being at least 90 weight percent. Especially important among insulator and semiconductor materials are oxidized silicon and n- or p-doped silicon.
For the sake of minimized contact resistance during su~sequent device operation, localized short-term heating can be used as part of device processing to raise the temperature of a layered structure so as to allow for at least partial interdifEusion of the semiconductor and titanium layers and, po~sibLy, for stoichiometric compound formation. Such localized heating may be effected, e.g., by infrared laser irradiation.
Example _ Alternating layers of titanium and silicon 3S were deposited by electron-beam evaporation on a p-type, {OOl} silicon substrate which hacl been spin-dried after cleaning in a l:lO0-solution of hydrofluoric acid in ~Z587~8 water. Duriny deposition the substrat~ temperature ,was approximately 5 degrees C, and deposition was in vacuum having a residual atmosE~hc-re consisting esserltially of hydrogen at a partial pressure of approximately 667xlO-9 (approximately 5xlO9 torr). ~rhe electrorl guns were held to a potential of approximately 9 kV, and deposition rate was approximately 0.08 nanometer/sec. Individua layers of titanium and silicon had approximate respective thicknesses oE 1 nanometer and 2 nanom2ters, and a structure havinc; 5 periods of alternating titanium and silicon layers was deposited. The structure was then metallized with a layer of aluminum-copper having a thickness of approximately 120 nanometers.
The deposited structure was annealed at a temperature of approximately 450 degrees C, and the annealed structure was examined by means of Rutherford backscat-tering and X-ray analysis. Excellent preservation of the layered structure was observed. The structure was then annealed at a temperature of approximately 550 degrees C, and, ayain, preservation of the structure was observed.
For the sake of comparison, a prior-art tungsten interdiffusion barrier layer was similarly annealed. While such tungsten barrier layer retained its integrity after annealing at a temperature of 450 degrees C, annealing at 550 de~rees C resulted in its interdiffusion and reaction with silicon of the subs-trate and aluminum of the metalli~ation.
Example 2.
~ZS~7~L8 ~ i~he procedure described above ir ].~xample 1 ~,/as followed excep-t that drepositer~ layer.s had a thicknri~s of 2 nanometers for titanium as ~e7].l as for silicor" and that the deposited structure nad 10 periods of alternating layers of titanium and silicon. ~esistance to interdiffusion ~as as describerl in Example 1.
U. S. patent 3,657,029 discloses a method for patterning a multi-layer metallization of platinum, palladium, rhodium, ruthenium, osmium, or iridium there, a layer of titanium or chromium is used as a mask material.
Popular also is the use of aluminum and aluminum alloys as relatively inexpensive alternatives to noble metals; for example, U. S. patent 4,017,890 discloses aluminum and aluminum-copper conductor stripe metallizations.
Typically, ~hen aluminum or aluminum alloys are used for silicon device metallization, a contact material is placed between doped silicon source reyions, ~2S8~7~
doped silicon drain regions, and silicon oxide gate regions on the one hand, and the aluminum-containing interconnect metallization. Moreover, it has been Eound desirable to interpose an interface material between contact and interconnect metallizations; such interface material has desirably low resistivity and acts as a barrier against interdiffusion during device manufacture.
While, in this respect, the use of tungsten has been advocated as an interface material, there remains a need for interdiffusion barriers which retain their efficacy at elevated temperatures. In particular, such barriers are desired to remain effective at temperatures significantly greater than approximately 450 degrees C.
~ummary of the Invention It has been discovered that structures consisting of alternating amorphous layers of titanium and a semiconductor material are suitable as contact and interface layers in device manufacture where aluminum or aluminum alloy metallizations are being used.
In accordance with one aspect of the invention there is provided a device comprising a body of semiconductor; material and an electrical conductor element which consists of a material which comprises aluminum in an amount of at least 90 weight percent, characterized in ~hat, between said body and said conductor element, there is a structure of alternating, essentially amorphous, first and second interface layers of first material which consists essentially of tltanium, and second material which consists essentially of semiconductor material.
In accordance with another aspect of the invention there is provided a method for making a device comprising a body of semiconductor material and an electrical conductor element which consists o~ a material which comprises aluminum in an amount of at least 90 ~S~71~3 - 2a -weight percent, characterized in that, between said body and said conductor element, a structure of alternating, essentially amorphous interface layers is depositefl consisting of a first makerial which consis~s essentially of titanium, and a second material which consists essentially of a semiconductor ma~erial, and said method comprises processing at a temperature which is greater than 200 degrees C.
Brief Description o~ the Drawing The Figure shows, enlarged and in schematic cross section, an integrated semiconductor device comprising three interface layers in accordance with the invention.
~etailed Description -The Figure schematically shows a cross section of an n-channel metal-oxide semiconductor device (MOS) comprising a body of silicon 1 which is doped p plus except for a source region 2 and a drain region 3 which are doped n-plus. A channel region 4 is covered with a gate oxide layer 5, and field oxide regions 6 adjoin the source region 2 and the drain region 3. A source contact layer 7 is on the source region 2, a drain contact layer 8 is on the drain region 3, and a gate contact layer 9 i5 on the gate oxide layer 5. Interface 1~25871~
layers 10 and 11 are on tne contact layers ~ and ~, respectively; a first insulating oxide layer 12 insulates thc field oxi~e rcyions 6 as wre~ 5 thr~ yate contac-t layer ~; and a first int~rconnect metallization 13 is sho~"n in contact with layers '~, 10 and 11. A second insulating oxide layer 14 is on the interconnect metallization layer 13, and a second interconnect rnetallization layer 15 on the second insulating oxide layer l~ is in contact ~Ji th the first interconnect metallization layer 13 through etched windows in the second insulating oxide layer 14.
In accordance with the invention a contact or interface layer such as, e.y., gate contact layer 9, interface layer 10, and interface layer 11 is made as a structure of alternating amorphous layers of titanium and a semiconductor material. ~It is understood that, especially under conditions of processing at elevated temperatures, there will be a certain amount of alloy formation at layer interfaces. Such partial alloying does not significantly reduce the anti-interdiffusion efficacy of a layered structure and may contribute to desired low contact resistance.) Titanium layers preferably cc)mprise at least 99 weight percent titanium, the remaining at most l percent being made up of impurities such as, e.g., iron or nickel. In the interest of essentially amorphous structure, titanium layer thickness does not exceed approximately ~ nanometers and preferably 5 nanometers. For the sake of ease of deposition of a continuous layer, preferred thiclcness is at least 0.1 micrometer.
Semiconducting layers may consist of undoped, p-doped, or n-doped semiconductor material, and such material may be elemental, compound, or mixed. Silicon is considered particularly suitable in combination with titanium for interface structures between silicon substrates and aluminum metallizations. Thickness of ~'~58'7~8 silicon layers is less critic;il thiln titanium layer thic~ness; however, tt~ickncsses ~reatf-r t}1an lO nanometers are consi~ered a_ une1(onomical witt1 respect to the purpose of the invention. Also, for the sake of continuity of a depositec3 layer, preEerred thickness is at least O.l micrometer.
The number of periods of alternating layers mcay oe from l or, preferably, 2 to 500, greater numbers giving increased protection against in~erdiffusion and also greater contact resistance.
Structures in accordance with the invention are intended primarily for tlle protection against interdiffusion between aluminum metallizations and semiconductor or insulator materials during device manufacture involving processing at elevated - temperatures. In this respect, semiconductor device processing may involve heating to temperatures above 20Q degrees C. Aluminum metallizations typically are made of aluminum which has been alloyed with a small amount of copper, preferred aluminum content being at least 90 weight percent. Especially important among insulator and semiconductor materials are oxidized silicon and n- or p-doped silicon.
For the sake of minimized contact resistance during su~sequent device operation, localized short-term heating can be used as part of device processing to raise the temperature of a layered structure so as to allow for at least partial interdifEusion of the semiconductor and titanium layers and, po~sibLy, for stoichiometric compound formation. Such localized heating may be effected, e.g., by infrared laser irradiation.
Example _ Alternating layers of titanium and silicon 3S were deposited by electron-beam evaporation on a p-type, {OOl} silicon substrate which hacl been spin-dried after cleaning in a l:lO0-solution of hydrofluoric acid in ~Z587~8 water. Duriny deposition the substrat~ temperature ,was approximately 5 degrees C, and deposition was in vacuum having a residual atmosE~hc-re consisting esserltially of hydrogen at a partial pressure of approximately 667xlO-9 (approximately 5xlO9 torr). ~rhe electrorl guns were held to a potential of approximately 9 kV, and deposition rate was approximately 0.08 nanometer/sec. Individua layers of titanium and silicon had approximate respective thicknesses oE 1 nanometer and 2 nanom2ters, and a structure havinc; 5 periods of alternating titanium and silicon layers was deposited. The structure was then metallized with a layer of aluminum-copper having a thickness of approximately 120 nanometers.
The deposited structure was annealed at a temperature of approximately 450 degrees C, and the annealed structure was examined by means of Rutherford backscat-tering and X-ray analysis. Excellent preservation of the layered structure was observed. The structure was then annealed at a temperature of approximately 550 degrees C, and, ayain, preservation of the structure was observed.
For the sake of comparison, a prior-art tungsten interdiffusion barrier layer was similarly annealed. While such tungsten barrier layer retained its integrity after annealing at a temperature of 450 degrees C, annealing at 550 de~rees C resulted in its interdiffusion and reaction with silicon of the subs-trate and aluminum of the metalli~ation.
Example 2.
~ZS~7~L8 ~ i~he procedure described above ir ].~xample 1 ~,/as followed excep-t that drepositer~ layer.s had a thicknri~s of 2 nanometers for titanium as ~e7].l as for silicor" and that the deposited structure nad 10 periods of alternating layers of titanium and silicon. ~esistance to interdiffusion ~as as describerl in Example 1.
Claims (14)
1. Device comprising a body of semiconductor material and an electrical conductor element which consists of a material which comprises aluminum in an amount of at least 90 weight percent, CHARACTERIZED IN
THAT, between said body and said conductor element, there is a structure of alternating, essentially amorphous, first and second interface layers of first material which consists essentially of titanium, and second material which consists essentially of semiconductor material.
THAT, between said body and said conductor element, there is a structure of alternating, essentially amorphous, first and second interface layers of first material which consists essentially of titanium, and second material which consists essentially of semiconductor material.
2. Device of claim 1 in which said first material comprises titanium in an amount greater than or equal to 99 weight percent.
3. Device of claim 1 in which said second material is essentially the same in all of said second interface layers.
4. Device of claim 1 in which the thickness of said first layers is less than 8 nanometers.
S. Device of claim 1 in which said body consists essentially of silicon.
6. Device of claim 1 in which said second material consists essentially of silicon.
7. Device of claim 1 in which the material of said conductor element comprises copper.
8. Device of claim 1 in which said second material is essentially in elemental form.
9. Device of claim 1 in which said second material is essentially in compound form.
10. Device of claim 1 in which said second material is a mixture.
11. Device of claim 1 in which said structure is on a source region.
12. Device of claim 1 in which said structure is on a drain region.
13. Device of claim 1 in which said structure is on a gate insulating layer.
14. Method for making a device comprising a body of semiconductor material and an electrical conductor element which consists of a material which comprises aluminum in an amount of at least 90 weight percent, characterized in that, between said body and said conductor element, a structure of alternating, essentially amorphous interface layers is deposited consisting of a first material which consists essentially of titanium, and a second material which consists essentially of a semiconductor material, and said method comprises processing at a temperature which is greater than 200 degrees C.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US850,978 | 1986-04-11 | ||
| US06/850,978 US4725877A (en) | 1986-04-11 | 1986-04-11 | Metallized semiconductor device including an interface layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1258718A true CA1258718A (en) | 1989-08-22 |
Family
ID=25309619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000534348A Expired CA1258718A (en) | 1986-04-11 | 1987-04-09 | Metallized semiconductor device including an interface layer |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4725877A (en) |
| EP (1) | EP0243024B1 (en) |
| JP (1) | JP2608283B2 (en) |
| KR (1) | KR950007351B1 (en) |
| CA (1) | CA1258718A (en) |
| DE (1) | DE3784757T2 (en) |
| ES (1) | ES2038987T3 (en) |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2552159B2 (en) * | 1987-02-02 | 1996-11-06 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof |
| US4963510A (en) * | 1987-11-02 | 1990-10-16 | Texas Instruments Incorporated | Method and apparatus for providing interconnection between metallization layers on semiconductors devices |
| US4873565A (en) * | 1987-11-02 | 1989-10-10 | Texas Instruments Incorporated | Method and apparatus for providing interconnection between metallization layers on semiconductor devices |
| KR920008886B1 (en) * | 1989-05-10 | 1992-10-10 | 삼성전자 주식회사 | Method of producing for dram cell |
| US5252382A (en) * | 1991-09-03 | 1993-10-12 | Cornell Research Foundation, Inc. | Interconnect structures having patterned interfaces to minimize stress migration and related electromigration damages |
| US6081034A (en) * | 1992-06-12 | 2000-06-27 | Micron Technology, Inc. | Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer |
| JP3159561B2 (en) * | 1993-03-29 | 2001-04-23 | ローム株式会社 | Electrodes for crystalline thin films |
| US5439731A (en) * | 1994-03-11 | 1995-08-08 | Cornell Research Goundation, Inc. | Interconnect structures containing blocked segments to minimize stress migration and electromigration damage |
| US5935462A (en) * | 1994-10-24 | 1999-08-10 | Matsushita Electric Industrial Co., Ltd. | Repair of metal lines by electrostatically assisted laser ablative deposition |
| US5683601A (en) * | 1994-10-24 | 1997-11-04 | Panasonic Technologies, Inc. | Laser ablation forward metal deposition with electrostatic assisted bonding |
| US6060127A (en) * | 1998-03-31 | 2000-05-09 | Matsushita Electric Industrial Co., Ltd. | Mechanically restricted laser deposition |
| US6180912B1 (en) | 1998-03-31 | 2001-01-30 | Matsushita Electric Industrial Co., Ltd. | Fan-out beams for repairing an open defect |
| US7554829B2 (en) | 1999-07-30 | 2009-06-30 | Micron Technology, Inc. | Transmission lines for CMOS integrated circuits |
| JP2002026134A (en) * | 2000-07-12 | 2002-01-25 | Seiko Epson Corp | Manufacturing method for semiconductor integrated circuit, and semiconductor integrated circuit manufactured by the same |
| US7082838B2 (en) * | 2000-08-31 | 2006-08-01 | Tdk Corporation | Extraordinary piezoconductance in inhomogeneous semiconductors |
| US8026161B2 (en) * | 2001-08-30 | 2011-09-27 | Micron Technology, Inc. | Highly reliable amorphous high-K gate oxide ZrO2 |
| US6767795B2 (en) * | 2002-01-17 | 2004-07-27 | Micron Technology, Inc. | Highly reliable amorphous high-k gate dielectric ZrOXNY |
| US6893984B2 (en) * | 2002-02-20 | 2005-05-17 | Micron Technology Inc. | Evaporated LaA1O3 films for gate dielectrics |
| US7589029B2 (en) * | 2002-05-02 | 2009-09-15 | Micron Technology, Inc. | Atomic layer deposition and conversion |
| US7045430B2 (en) * | 2002-05-02 | 2006-05-16 | Micron Technology Inc. | Atomic layer-deposited LaAlO3 films for gate dielectrics |
| US7205218B2 (en) | 2002-06-05 | 2007-04-17 | Micron Technology, Inc. | Method including forming gate dielectrics having multiple lanthanide oxide layers |
| US7221586B2 (en) | 2002-07-08 | 2007-05-22 | Micron Technology, Inc. | Memory utilizing oxide nanolaminates |
| US7101813B2 (en) * | 2002-12-04 | 2006-09-05 | Micron Technology Inc. | Atomic layer deposited Zr-Sn-Ti-O films |
| US7192892B2 (en) | 2003-03-04 | 2007-03-20 | Micron Technology, Inc. | Atomic layer deposited dielectric layers |
| DE602005009793D1 (en) * | 2005-01-21 | 2008-10-30 | St Microelectronics Srl | Phase change memory device and method for its production |
| US7662729B2 (en) * | 2005-04-28 | 2010-02-16 | Micron Technology, Inc. | Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer |
| US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3657029A (en) * | 1968-12-31 | 1972-04-18 | Texas Instruments Inc | Platinum thin-film metallization method |
| US3881884A (en) * | 1973-10-12 | 1975-05-06 | Ibm | Method for the formation of corrosion resistant electronic interconnections |
| US4017890A (en) * | 1975-10-24 | 1977-04-12 | International Business Machines Corporation | Intermetallic compound layer in thin films for improved electromigration resistance |
| US4135292A (en) * | 1976-07-06 | 1979-01-23 | Intersil, Inc. | Integrated circuit contact and method for fabricating the same |
| JPS5679450A (en) * | 1979-11-30 | 1981-06-30 | Mitsubishi Electric Corp | Electrode and wiring of semiconductor device |
| JPS56165354A (en) * | 1980-05-23 | 1981-12-18 | Nec Corp | Semiconductor device |
| JPS5745228A (en) * | 1980-08-29 | 1982-03-15 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5771175A (en) * | 1980-10-22 | 1982-05-01 | Nec Corp | Semiconductor device |
| JPS584924A (en) * | 1981-07-01 | 1983-01-12 | Hitachi Ltd | Forming method for semiconductor device electrode |
| JPS58132962A (en) * | 1982-02-01 | 1983-08-08 | Toshiba Corp | Semiconductor device |
| JPH0691257B2 (en) * | 1984-04-20 | 1994-11-14 | 富士通株式会社 | Amorphous silicon thin film transistor |
-
1986
- 1986-04-11 US US06/850,978 patent/US4725877A/en not_active Expired - Lifetime
-
1987
- 1987-04-03 ES ES198787302913T patent/ES2038987T3/en not_active Expired - Lifetime
- 1987-04-03 EP EP87302913A patent/EP0243024B1/en not_active Expired - Lifetime
- 1987-04-03 DE DE87302913T patent/DE3784757T2/en not_active Expired - Fee Related
- 1987-04-08 KR KR1019870003318A patent/KR950007351B1/en not_active IP Right Cessation
- 1987-04-09 CA CA000534348A patent/CA1258718A/en not_active Expired
- 1987-04-10 JP JP62087235A patent/JP2608283B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR870010625A (en) | 1987-11-30 |
| EP0243024A3 (en) | 1988-04-20 |
| US4725877A (en) | 1988-02-16 |
| DE3784757D1 (en) | 1993-04-22 |
| KR950007351B1 (en) | 1995-07-10 |
| DE3784757T2 (en) | 1993-09-30 |
| JP2608283B2 (en) | 1997-05-07 |
| JPS62295453A (en) | 1987-12-22 |
| ES2038987T3 (en) | 1993-08-16 |
| EP0243024A2 (en) | 1987-10-28 |
| EP0243024B1 (en) | 1993-03-17 |
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