CA1273063A - Adjustable impedance driver network - Google Patents
Adjustable impedance driver networkInfo
- Publication number
- CA1273063A CA1273063A CA000540566A CA540566A CA1273063A CA 1273063 A CA1273063 A CA 1273063A CA 000540566 A CA000540566 A CA 000540566A CA 540566 A CA540566 A CA 540566A CA 1273063 A CA1273063 A CA 1273063A
- Authority
- CA
- Canada
- Prior art keywords
- impedance
- gates
- voltage source
- transmission
- transmission gates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0005—Modifications of input or output impedance
Abstract
ADJUSTABLE IMPEDANCE DRIVER NETWORK
ABSTRACT
A variable impedance driver network comprises a plurality of transmission gates connected in parallel between a voltage source and an output. Each trans-mission gate has a predetermined nominal impedance and by turning on selective gates the overall impedance of the network may be adjusted to match that required at the output.
ABSTRACT
A variable impedance driver network comprises a plurality of transmission gates connected in parallel between a voltage source and an output. Each trans-mission gate has a predetermined nominal impedance and by turning on selective gates the overall impedance of the network may be adjusted to match that required at the output.
Description
~7~i3 ADJUSTABLE IMPEDANCE DRIVER NETWORK
B~CKGROUND OF THE INVENTION
The following invention relates to a variable impedance driver circuit for providing test signals from automatic test e~uipment in order to stimulate a device under test.
In driver circuits of the type used with automatic test e~uipment, it is often advantageous to use CMOS
integrated chip technology to build the drivers needed to provide the test signal pulses used to stimulate a device under test because of the relative inexpensiveness and compact size of CMOS IC's. The device under test is usually connectP.d to the driver output by a fixed impedance transmission line.
Thus, in order to ma.intain the desired shape of the test pulses, it is necessary to match the output impedance of the driver circuit to the impedance of the transmission line.
one problem wikh such drivers, however, is that due to performance variations in the CMOS chips, the impedance of such drivers may vary considerably. It is not uncommon for the impedance of similar CMOS devices made by the same manufacturing process to vary as much as 100%. What is
B~CKGROUND OF THE INVENTION
The following invention relates to a variable impedance driver circuit for providing test signals from automatic test e~uipment in order to stimulate a device under test.
In driver circuits of the type used with automatic test e~uipment, it is often advantageous to use CMOS
integrated chip technology to build the drivers needed to provide the test signal pulses used to stimulate a device under test because of the relative inexpensiveness and compact size of CMOS IC's. The device under test is usually connectP.d to the driver output by a fixed impedance transmission line.
Thus, in order to ma.intain the desired shape of the test pulses, it is necessary to match the output impedance of the driver circuit to the impedance of the transmission line.
one problem wikh such drivers, however, is that due to performance variations in the CMOS chips, the impedance of such drivers may vary considerably. It is not uncommon for the impedance of similar CMOS devices made by the same manufacturing process to vary as much as 100%. What is
2~ needed, therefore, in a test instrument using CMOS
transmission gates as output drivers, is a way to match the impedance of each driver to the transmission line which is to be connected to the device under test.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention there is provided a driver circuit having a high voltage output state and a low voltage output state and having a variable output impedance comprising: (a) a first plurality of transmission gates connected in parallel between a high
transmission gates as output drivers, is a way to match the impedance of each driver to the transmission line which is to be connected to the device under test.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention there is provided a driver circuit having a high voltage output state and a low voltage output state and having a variable output impedance comprising: (a) a first plurality of transmission gates connected in parallel between a high
3~) voltage source and a transmission line; (b) a second plurality of transmission gates connected between a low voltage source and said transmission line; and (c) logic circuit means for simultaneously selectively enabling various ones of said gates 3~
when either a high level or low level actuating signal is provided to one of said respective pluralities of tra~smission gates, thereby adjusting the impedance between said high or low voltage source, respectively, and said transmission line.
The gates may be transmission gates utilizing a CMOS
FET pair comprising an N channel device and a P channel device connected in parallel. Each gate has a predetermined nominal impedance, and the gates may be related in a ~inary sense such that for any given plurality of gates connected in parallel, the impedances may be R, 2R, ...2~R, respectively. Each transmission gate may be controlled by a control line connected to a logic circuit which selectively actuates one or more of the gates in parallel. By turning on various ones of the gates and turning off others, the impedance of the network connecting a voltage source to the transmission line may be controlled.
It is a principal object of this invention to provide a compact, low cost variable impedance driver.
The foregoing and other objectives, features and 2~ advantages of the present invention will be more readily understood upon consideration of the following detailed description of the invention taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block schematic diagram of a variable impedance driver network constructed according to the present invention.
FIG. 2 is a schematic diagram of one of the transmission gates shown in FIG. 1.
DETAILED DESCRIPTION OF THE INVENTION
A driver network 10 comprises a plurality of CMOS
transmission gates 12, 1~, 16, 1~, 20 and 22. Referring to FIG. 2, which illustrates transmission gate 12, it can be seen that each of the gates 12, 1~, " ;
.
, :
, 3C~
16, 18, 20 and 22 compr~seY a P channel tran~lstor con-nec~ed in parallel with an N channel tran~istorq Both transi~ors accordingly have a co~mon ~ource 24 and a common drain 26. The gate of the P channel tran~istor 28 is connected to control line 30 through invertlng amplifier 320 Ea~h of the tran~miQsion gates 12, 14, 16, 18, 20 and 22, re~pectively, are controlled by control lines 30, 34, 36, 3B, 40 and 42, respecti~ely.
The state of each of the control line3 30, 34, 36, 38, 40 and 42 are controlled by coded input line Cl~ C2, C3, C4, C5 and C6 in conjunction with lines Al and A2 which control the state of the driver 10, that is whether it is to be in a high or low level logic ~tate.
The output of the driver 10 i8 connected to a transmis~ion line 44 which in turn may be connected to a device under test 46. By controlling variou~ ones of the tran~misQion gates 12, 14 and 16 in, for example, a high level logic ~tate, one may choo~e the output impedance of the driver circuit 10. This is because each of the tran~mis~ion gates 12, 14 and 16 ha~ a pre~
determined nominal impedance when turned on and has a nearly infinite impedance when turned off. Thus, by selectively turning on and off variou~ ones of the transmission gate3, the overall impedance, which i8 calculated according to Ohm's Law, may be adjusted.
A finer degree of ad~ustment may be provided if the individual impedances of the transmis~ion gates in their ~on" 3tatea are binarily related. That is, if gate 12 h~ a resistance R, gate 14 would have a re~istance 2R and gate 16 would have a re~istance 4R.
There may be more than three gates ~or the high and low logic level~ re~pectively, and in 3uch a ca~e the values of the re3i~tances would be Rt 2R, ...2nR, respectively. Thus, the high control line Al or the low control line A2 controls whether the driver i~ in a high or a low logic ~tate~, and combination~ of the control line~ Cl through C3 for the high voltage level :~'73~
when either a high level or low level actuating signal is provided to one of said respective pluralities of tra~smission gates, thereby adjusting the impedance between said high or low voltage source, respectively, and said transmission line.
The gates may be transmission gates utilizing a CMOS
FET pair comprising an N channel device and a P channel device connected in parallel. Each gate has a predetermined nominal impedance, and the gates may be related in a ~inary sense such that for any given plurality of gates connected in parallel, the impedances may be R, 2R, ...2~R, respectively. Each transmission gate may be controlled by a control line connected to a logic circuit which selectively actuates one or more of the gates in parallel. By turning on various ones of the gates and turning off others, the impedance of the network connecting a voltage source to the transmission line may be controlled.
It is a principal object of this invention to provide a compact, low cost variable impedance driver.
The foregoing and other objectives, features and 2~ advantages of the present invention will be more readily understood upon consideration of the following detailed description of the invention taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block schematic diagram of a variable impedance driver network constructed according to the present invention.
FIG. 2 is a schematic diagram of one of the transmission gates shown in FIG. 1.
DETAILED DESCRIPTION OF THE INVENTION
A driver network 10 comprises a plurality of CMOS
transmission gates 12, 1~, 16, 1~, 20 and 22. Referring to FIG. 2, which illustrates transmission gate 12, it can be seen that each of the gates 12, 1~, " ;
.
, :
, 3C~
16, 18, 20 and 22 compr~seY a P channel tran~lstor con-nec~ed in parallel with an N channel tran~istorq Both transi~ors accordingly have a co~mon ~ource 24 and a common drain 26. The gate of the P channel tran~istor 28 is connected to control line 30 through invertlng amplifier 320 Ea~h of the tran~miQsion gates 12, 14, 16, 18, 20 and 22, re~pectively, are controlled by control lines 30, 34, 36, 3B, 40 and 42, respecti~ely.
The state of each of the control line3 30, 34, 36, 38, 40 and 42 are controlled by coded input line Cl~ C2, C3, C4, C5 and C6 in conjunction with lines Al and A2 which control the state of the driver 10, that is whether it is to be in a high or low level logic ~tate.
The output of the driver 10 i8 connected to a transmis~ion line 44 which in turn may be connected to a device under test 46. By controlling variou~ ones of the tran~misQion gates 12, 14 and 16 in, for example, a high level logic ~tate, one may choo~e the output impedance of the driver circuit 10. This is because each of the tran~mis~ion gates 12, 14 and 16 ha~ a pre~
determined nominal impedance when turned on and has a nearly infinite impedance when turned off. Thus, by selectively turning on and off variou~ ones of the transmission gate3, the overall impedance, which i8 calculated according to Ohm's Law, may be adjusted.
A finer degree of ad~ustment may be provided if the individual impedances of the transmis~ion gates in their ~on" 3tatea are binarily related. That is, if gate 12 h~ a resistance R, gate 14 would have a re~istance 2R and gate 16 would have a re~istance 4R.
There may be more than three gates ~or the high and low logic level~ re~pectively, and in 3uch a ca~e the values of the re3i~tances would be Rt 2R, ...2nR, respectively. Thus, the high control line Al or the low control line A2 controls whether the driver i~ in a high or a low logic ~tate~, and combination~ of the control line~ Cl through C3 for the high voltage level :~'73~
-4-and C4 through C6 for the low voltage level control the output impedance of the driver 10 according to a digi~
tal code which ~electively enables various ones of the transmission gates 12, 14, 16, 18, 20 and 22.
The terms and expres3ions which have been employed in the foregoing ~pecification are used therein as terms of de~cription and not of limitation, and there i9 no intention~ in the use of such terms and expressionY, of excluding equivalent~ of the features ~hown and de~cribed or portionA thereof~ it being recognized that the scope of the invention is defined and limited only by the cl~ims which follow.
tal code which ~electively enables various ones of the transmission gates 12, 14, 16, 18, 20 and 22.
The terms and expres3ions which have been employed in the foregoing ~pecification are used therein as terms of de~cription and not of limitation, and there i9 no intention~ in the use of such terms and expressionY, of excluding equivalent~ of the features ~hown and de~cribed or portionA thereof~ it being recognized that the scope of the invention is defined and limited only by the cl~ims which follow.
Claims (7)
1. A driver circuit having a high voltage output state and a low voltage output state and having a variable output impedance comprising:
(a) a first plurality of transmission gates connected in parallel between a high voltage source and a transmission line;
(b) a second plurality of transmission gates connected between a low voltage source and said transmission line; and (c) logic circuit means for simultaneously selectively enabling various ones of said gates when either a high level or low level actuating signal is provided to one of said respective pluralities of transmission gates, thereby adjusting the impedance between said high or low voltage source, respectively, and said transmission line.
(a) a first plurality of transmission gates connected in parallel between a high voltage source and a transmission line;
(b) a second plurality of transmission gates connected between a low voltage source and said transmission line; and (c) logic circuit means for simultaneously selectively enabling various ones of said gates when either a high level or low level actuating signal is provided to one of said respective pluralities of transmission gates, thereby adjusting the impedance between said high or low voltage source, respectively, and said transmission line.
2. The driver circuit of claim 1 wherein each transmission gate in each of said pluralities has a predetermined nominal impedance.
3. The driver circuit of claim 2 wherein in each of said pluralities of transmission gates, the individual transmission gates have nominal impedances of R, 2R, ...2?R, respectively.
4. The driver circuit of claim 3 wherein the transmission gates are CMOS field effect transistors.
5. An adjustable impedance driver network for coupling a voltage source to an output, comprising:
(a) a plurality of CMOS transmission gates, each gate in said plurality having a predetermined nominal impedance when turned on, and a substantially infinite impedance when turned off, connected in parallel between said voltage source and said output;
(b) a voltage source coupled to each of said CMOS
transmission gates; and (c) logic circuit means coupled to a control electrode of each of said transmission gates and responsive to both an actuating signal and a predetermined digital code, for selectively turning on various ones of said gates simultaneously to provide a variable impedance for said voltage source.
(a) a plurality of CMOS transmission gates, each gate in said plurality having a predetermined nominal impedance when turned on, and a substantially infinite impedance when turned off, connected in parallel between said voltage source and said output;
(b) a voltage source coupled to each of said CMOS
transmission gates; and (c) logic circuit means coupled to a control electrode of each of said transmission gates and responsive to both an actuating signal and a predetermined digital code, for selectively turning on various ones of said gates simultaneously to provide a variable impedance for said voltage source.
6. The adjustable impedance driver of claim 5 wherein said logic circuit means comprises an AND gate array, each AND gate in said array having an output connected to each respective control electrode and having respective inputs comprising said actuating signal and one bit of said digital code.
7. The adjustable impedance driver network of claim 6 wherein the nominal impedances of said gates are R, 2R,...2?R, respectively.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/887,314 US4707620A (en) | 1986-07-22 | 1986-07-22 | Adjustable impedance driver network |
| US887,314 | 1992-05-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1273063A true CA1273063A (en) | 1990-08-21 |
Family
ID=25390896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000540566A Expired - Fee Related CA1273063A (en) | 1986-07-22 | 1987-06-25 | Adjustable impedance driver network |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4707620A (en) |
| EP (1) | EP0254011B1 (en) |
| JP (1) | JPS6331311A (en) |
| CA (1) | CA1273063A (en) |
| DE (1) | DE3783963T2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7307863B2 (en) | 2005-08-02 | 2007-12-11 | Inphi Corporation | Programmable strength output buffer for RDIMM address register |
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| JPS62200804A (en) * | 1986-02-27 | 1987-09-04 | Ricoh Co Ltd | Semiconductor integrated circuit device having programmable analog element |
| US4761565A (en) * | 1987-06-29 | 1988-08-02 | Eastman Kodak Company | CCD clock driver circuit |
| JP2656537B2 (en) * | 1988-04-13 | 1997-09-24 | 株式会社日立製作所 | Power semiconductor device |
| US5182479A (en) * | 1988-06-24 | 1993-01-26 | U.S. Philips Corp. | Gate circuit having increased voltage handling capability |
| ATE98077T1 (en) * | 1988-08-08 | 1993-12-15 | Siemens Ag | BROADBAND SIGNAL COUPLER. |
| US4918333A (en) * | 1988-10-31 | 1990-04-17 | Anderson Floyd E | Microprocessor having high current drive |
| GB8830282D0 (en) * | 1988-12-28 | 1989-02-22 | Astec Int Ltd | The setting of electronic circuits |
| DE4007978A1 (en) * | 1989-03-17 | 1990-09-20 | Tektronix Inc | Output driver circuitry with min. transition impedance variations - has two pulse expanders, first one in high pass signal release, and second one in low pass signal release |
| US5165046A (en) * | 1989-11-06 | 1992-11-17 | Micron Technology, Inc. | High speed CMOS driver circuit |
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| US5276912A (en) * | 1990-02-06 | 1994-01-04 | Motorola, Inc. | Radio frequency power amplifier having variable output power |
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| US5243229A (en) * | 1991-06-28 | 1993-09-07 | At&T Bell Laboratories | Digitally controlled element sizing |
| US5585741B1 (en) * | 1994-04-22 | 2000-05-02 | Unitrode Corp | Impedance emulator |
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| US5592394A (en) * | 1995-01-31 | 1997-01-07 | Dell U.S.A., L.P. | FET current sensor for active balancing or regulating circuits |
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| US5982191A (en) * | 1997-06-25 | 1999-11-09 | Sun Microsystems, Inc. | Broadly distributed termination for buses using switched terminator logic |
| US5990701A (en) * | 1997-06-25 | 1999-11-23 | Sun Microsystems, Inc. | Method of broadly distributing termination for buses using switched terminators |
| US5955894A (en) * | 1997-06-25 | 1999-09-21 | Sun Microsystems, Inc. | Method for controlling the impedance of a driver circuit |
| US6411131B1 (en) | 1997-06-25 | 2002-06-25 | Sun Microsystems, Inc. | Method for differentiating a differential voltage signal using current based differentiation |
| US6870419B1 (en) * | 1997-08-29 | 2005-03-22 | Rambus Inc. | Memory system including a memory device having a controlled output driver characteristic |
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| US6316957B1 (en) | 1999-09-20 | 2001-11-13 | Sun Microsystems, Inc. | Method for a dynamic termination logic driver with improved impedance control |
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| DE10246741B4 (en) | 2002-10-07 | 2007-04-19 | Infineon Technologies Ag | Method and semiconductor device for matching interface devices |
| US7119549B2 (en) * | 2003-02-25 | 2006-10-10 | Rambus Inc. | Output calibrator with dynamic precision |
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| KR100542695B1 (en) * | 2003-11-13 | 2006-01-11 | 주식회사 하이닉스반도체 | Test mode circuit in a semiconductor device |
| US6980020B2 (en) * | 2003-12-19 | 2005-12-27 | Rambus Inc. | Calibration methods and circuits for optimized on-die termination |
| US7152012B2 (en) * | 2004-09-28 | 2006-12-19 | Lsi Logic Corporation | Four point measurement technique for programmable impedance drivers RapidChip and ASIC devices |
| US7389194B2 (en) * | 2005-07-06 | 2008-06-17 | Rambus Inc. | Driver calibration methods and circuits |
| US7479799B2 (en) * | 2006-03-14 | 2009-01-20 | Inphi Corporation | Output buffer with switchable output impedance |
| WO2008126603A1 (en) * | 2007-03-13 | 2008-10-23 | Advantest Corporation | Driver circuit and semiconductor testing apparatus |
| US7999530B2 (en) * | 2008-03-21 | 2011-08-16 | Intersil Americas Inc. | Device under test power supply |
| DE102009006332B4 (en) | 2009-01-27 | 2014-08-21 | Oliver Bartels | Line driver or amplifier with frequency-dependent variable apparent impedance |
| JP2013130427A (en) * | 2011-12-20 | 2013-07-04 | Tokyo Electron Ltd | Inspection device for semiconductor device |
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| US4329600A (en) * | 1979-10-15 | 1982-05-11 | Rca Corporation | Overload protection circuit for output driver |
| JPS59101931A (en) * | 1982-12-01 | 1984-06-12 | Nec Ic Microcomput Syst Ltd | Electronic circuit |
| DE3244843C2 (en) * | 1982-12-03 | 1984-11-29 | Siemens AG, 1000 Berlin und 8000 München | DUT loading device |
-
1986
- 1986-07-22 US US06/887,314 patent/US4707620A/en not_active Expired - Lifetime
-
1987
- 1987-06-11 DE DE8787108416T patent/DE3783963T2/en not_active Expired - Fee Related
- 1987-06-11 EP EP87108416A patent/EP0254011B1/en not_active Expired - Lifetime
- 1987-06-25 CA CA000540566A patent/CA1273063A/en not_active Expired - Fee Related
- 1987-07-16 JP JP62178149A patent/JPS6331311A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7307863B2 (en) | 2005-08-02 | 2007-12-11 | Inphi Corporation | Programmable strength output buffer for RDIMM address register |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3783963T2 (en) | 1993-05-27 |
| JPH0573290B2 (en) | 1993-10-14 |
| EP0254011B1 (en) | 1993-02-03 |
| JPS6331311A (en) | 1988-02-10 |
| US4707620A (en) | 1987-11-17 |
| EP0254011A2 (en) | 1988-01-27 |
| EP0254011A3 (en) | 1989-07-19 |
| DE3783963D1 (en) | 1993-03-18 |
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