CA1284370C - Programmable controller with parallel processors - Google Patents

Abstract

Abstract A programmable controller suitable for operating a machine to carry out programmed functions includes a plural-ity of program processors. Each of the program processors being operable to execute simultaneously a different user control program that directs the operation of the machine to perform specific functions. Each of the processor means is contained within a separate module which also includes a memory for storing the user control programs that are to be executed by that processor means. A mechanism is also provided to control the sequence in which the user control programs are executed and which of the processor means executes a given control program. At least one input/output interface circuit controls the gathering of data from various external sensors and in response to output data received from the processor means, controls the operation of actuator devices on the machine. The input/output data regarding state of the sensors and actuator devices are stored in a memory within the interface circuit. A system controller supervises the interaction and intercommunication of the plurality of processor means and the input/output interface circuits.

Description

PROGRAMMABLE CONTROLLER WITH PARALLEL PROCESSORS

The field of the invention is programmable controllers such as those described in U.S. Patent Nos. 3,810,118;
3,942,158; 4,165,534; and 4,442,504.
:BACKGROUND OF THE INVENTION
Programmable controllers are typically connected to industrial equipment such as assembly lines and machine tools to sequentially operate the equipment in accordance with a stored program. In programmable controllers such as those disclosed in the above cited patents, for example, the control program is stored in a memory and includes instruc-tions which are read out in rapid sequence and executed to examine the condition of selected sensing devices on the controlled equipment, or to energize or de-ener~ize selected operating devices on the controlled equipment contingent upon the status of one or more of the examined sensing de-vices.
The processor for these controllers i5 designed to rapidly execute programmable controller type instructions which in medium to large sized controllers include not only instructions that manipulated single-bit input and output data, but also arithmetic instructions, file handling in-structions! timers and counters, sequencers and other, more complex instructions. Such instructions have become quite standardized in the industry and they may be directly asso-ciated with elements of a ladder diagram which is easily understood by control engineers. Program panels such as those disclosed in U.S. Patent. Nos. 3,798,612 and 3,813,649 and in U.S. Patent. No. 4,070,702 have been developed to assist the user in developing and editing ladder diagram L~

type control programs comprised of such programmable controller instructions.
To insure that the programmable controller can respond quickly to change in the status of sensing devices on the controlled S system, it is imperative that the controller execute the control program repeatedly at a very high rate. The rate at which a programmable controller can execute the instructions in its instruction set, as well as the size of the control program, are the primary factors which determine the rate at which the programmable controller can repeatedly execute, or "scan", the control program.
While ladder diagram control programs are particularly ~asy to create and edit for relatively small to medium scale control tasks, they become cumbersome and inefficient to use in large control lS tasks. Large ladder diagram control programs are difficult to understand, difficult to trouble shoot, and require a long time to execute.
U.S. Patent 4,742,443 issued May 3, 1988 entitled "Programmable Controller with Eunction Chart Interpreter" addresses this problem.
~0 The controller described therein includes a processor which stores a plurality of separate ladder control programs that are logically related to each other by a stored function chart program, and the processor is operable to execute the stored function chart program which directs which ones of the stored ladder programs are to be repeatedly executed by the processor at any point in time~ It has been discovered that large control tasks can usually be broken down into separate control steps which are executed in a sequential order as the controlled machine or process advances through its states. Each control step is defined by a separately J ~
executable ladder program which is easy to understand and which may be executed at a very high scan rate. The sequence in which the separate control steps are executed is defined by the function chart program which i5 a general expression of how the controlled machine or process is to operate. The user may thus define the general manner in which the machine or process is to operate using function chart cons~ructs, and then define the detailed operation of the machine or process in separate, easily managed ladder programs.
A difficulty that remained with the improved system of function charts and ladder diagrams occurred when the func-tion chart contained two or more parallel branches which ran simultaneously. For example, at a point in a given process sevèral operations involving different pieces of equipment or functions may have to be carried out in unison, with each piece of equipment or function being controlled by a differ-ent ladder prvgram. The only way that a prior controller system could simultaneously handle multiple ladder programs was to concatenate them into one large executable ladder diagram or otherwise sequentially execute each separate lad-der program. The controller would then repeatedly execute the concatenated ladder program which could significantly increase the execution time of any of the original ladder program segments. If the process controlled by one of these segments involved time-critical steps which required fre-quent monitoring and immediate responsive action, the lengthy execution time of the concatenated program might not provide these rapid monitoring and response times.

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SUMMARY OF THE INVENTION
A programmable controller executes a single machine operation program enabling a machine to carry out a plurality of programmed functions. Each step of the machine operation is defined as a separate user control program.
The programmable controller includes a plurality of indi-vidual processor modules each of which is capable of simul-taneously executing a user control program. A storage means is provided to store the control programs and data indicat-ing the sequence in which the control programs are to beexecuted. The programmable controller also includes one or more input/output (I/O) modules for interfacing it to sensors and actuators on the controlled machine. These I/O
modules may interface the controller to the sensors and actuators directly or indirectly through remote I/O
adapters.
Typically, the operation of the controller is defined by a user provided function chart and a series of control programs, such as ladder programs. The function chart sets out the overall process to be performed in a sequence of steps. The function chart is broken down into a series of descriptors each of which contains data specifying a proces-sing step to be performed, a transition condition that oc-curs when the step is completed, and a pointer to the next descriptor in the series. The descriptors of the function chart guide the overall flow of program execution. ~ach processing step is assigned to one of the processor modules for execution. The step is further defined by a process control program which is either a conventional ladder di-agram program or a high level language program. In the pre-ferred embodiment, the control program is compiled and stor-" ~

ed in a local memory of the respective processor module thathas been assigned to execute the program. Once a processor module begins executing a specific control program, it repeatedly carries out the execution until the associate~
transition condition occurs. At that time the next description pointer is read for information as to the next step to perform.
The present invention provides a programmable controller with a plurality of control program processors so ~0 that as required by the function chart program, a number of user control programs may be executed simultaneously without having to concatenate them. As each control program is being executed by an independent processor, its speed o~ operation is not compromised and the frequency at which the process is 1~ monitored and at whi.ch the responsive actions are taken, are substantially the same as though it was the only control program being executed at this time.
In accordance with an embodiment of the invention, a programmable controller for operating a machine to carry out a ~0 plurality of programmed functions is comprised of a plurality of processors each capable! of being simultaneously operable to execute a separate user control program that ~irects the programmable controller to operate the machine to perform a specific function, each of the processors capable of receiving communications from the other processors to control the execution of its user control program, apparatus ~or storing a plurali~y of user control programs, each user program designated ~or execution on one of the processors, and apparatus for interconnecting the plurality of processors S storing apparatus.
In accordance with another embodiment, a programmable controller for operating a machine to carry out a plurality of programmed functions, is comprised of a backplane having leads for conducting data signals, leads for conducting address signals and leads for condu~ting control signals, a plurality of processors connected to the backplane, each processor being operable to simultaneously execute different programs, apparatus coupled to the backplane for storing a plurality of programs for the processors, and I/O interface apparatus connected to the backplane for coupliny the programmable controller to external I/O devices, the interface apparatus having a first memory for storing data regarding the state of the I/O devices, a system controller for supervising the access to the backplane by the plurality of processors, ~0 including apparatus for arbitrating among different ones of the plurality of processors which are seeking access to the backplane.
In accordance with another embodiment, a programmable controller for operating a machine is comprised ~5 of a plurality of processors each capable of simultaneously executing a separate program, a plurality of apparatus for storing a plurality of programs, each of the apparatus for storing being coupled to a different one of the processor, apparatus for interfacing the programmable controller to sensor and actuator devices on the machine, the interfacing apparatus having a first memory for storing the state of the sensor and actuator devices, the state of the actuator devices being set in response to at least one of the processors, and apparatus for responding to requests from the plurality of processors to interconnect one of the processors to the inter~ace apparatus.
BRIEF DESCRIPrrION OF THE DRAWINGS
In the drawings which illustrate khe embodiments of the present invention:
Figure 1 is a perspective view of a programmable controller whi.ch employs the present invention;
Figure 2 is a schematic block diagram of the programmable controller system shown in Figure 1;
Figure 3 is a schematic block diagram of the System ~0 Controller for the programmable controller of Figure 2;
Figure 4 is a schematic block diagram of a Program Execution Processor of the programmable controller shown in Figure 2;

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~igure 5 is a schematic block diagram of the r2ndom - access memory of the Program Execution Processor of Figure : 4;
Figure 6 is a schematic block diagram of the Remote Input/Output Scanner of the Figure 2 programmable control-ler;
Figure 7 is a diagram of the System Controller memory data structure;
Figure 8 is a diagram of the I/0 Scanner memory data structure;
Figure 9 is a diagram of the Program Execution Proces-sor memory data structure;
Figure 10 is an exemplary function chart diagram;
` Figures 11 A, ~ and C are illustrations of the descriptor file data structures generated from the function chart program of Figure 10;
Figures 12A and B show the entries in the mailboxes of : Figure 14 for different types of messages, Figure 13 is a flow chart of the programmable control-ler initialization routine;
" Figure 14 is a schematic representation of a portion of the system of Figure 1 used to described the communication of messages between modules of the programmable controller;
~igure 15 depicts a flow chart of the program steps to initiate the sending of a message from one module to anotherin the programmable controller;
` Figures 16, 17, 18 and 19 are flow charts of portions of the software for interpreting function chart data and ' executing user control programs;
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01 Figure 20 is a schematic block diagram of the 02 baekplane arbitration circuit of Figure 3;
03 Figures 21 - 2B are schematie diagrams for each of 04 the slot priority cireuits shown in Figure 20; and 05 Figure 29 .is a table illustrating the order of 06 baekplane aeeess priority.

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~ ' , DETAILED DESCRIPTION OF TME INVENTION
With initial reference to Figure 1, a programmable controller 10 of the present invention is housed in a rack 12 which includes a series of slots that receive a plurality o~ printed circuit ~oard modules. These functional modules connect to a mother board whi~h extends along the back surface of the rack 12 to provide a backplane 11. The backplane 11 has a plurality of module connectors which are interconnected by a conductive pattern on the backplane. The backplane 11 provides a series of signal buses to which the modules connect. The rack 12 contains a power supply module 14, a system controller 16, a number of program execution processor modules 18 and a plurality of remote input/output (I/O) scanner modules 20, although only one scanner module is required.
The remaining locations in rack 12 are empty and the slots are l~ covered by blank plates until additional functional modules are to be inserted in these slots. The physical construction of the rack 12 is disclosed in U.S. Patent 4,716,495 issued December 29, 1987 and assigned to the same assignee as the present invention.
Up to four remote I/O scanner modules 20 interface the ~0 controller 10 to external remote I/O racks 17 via serial I/O data links, such as link 15. Each remote I/O rack 17 has a plurality of local I/O modules l9 which are coupled to individual sensors and actuators on the controlled equipment. The local I/O modulPs 19 may take many forms and may include, for example, D.C. inputs or outputs, A.C. inputs or outputs, analog inputs or outputs, and open or closed loop positionin~ modules. The I/O racks 17 and networks 15 employ conventional interface and communication technology.

, The remote I/0 rack 17 also contains an adapter module l9';
such as the one described in U.S. Patent No. 4,413,319, which controls the transmission of data via the I/0 network 15 between the I/0 modules 19 and the scanner modules 20.
The system controller 16 is connected through cable 25 to a programming terminal 24, which is used to load the user programs into the programmable controller and configure its operation, as well as monitor its performance. The terminal 24 is a personal computer programmed to enable the u~er to develop the control programs on the terminal. For example, these programs can be enhanced versions of conventional function chart programs that specify the sequence in which ladder diagram programs are executed. The different pro-grams are then downloaded into the programmable control-ler. Once the programs have been loaded into the program-mable controller 10 and its operation debugged, the terminal 24 may be disconnected from the system controller 16 if further monitoring is not required. The system controller 16 may be also connected via a cable 26 to a local area network 28 over which it may receive data and programming instructions, as well as issue status information and report data to a host computer. This enables a central host computer or central terminal to program and control the operation of a plurality of programmable controllers on a factory floor.
Different steps of a function chart program are as-signed to various ones of the program execution modules 18. The user control program for each step is stored in the local memory of the corresponding program execution module 18. For example the user control program may be a conven-tional ladder program. Several user control programs may be ;

executed simultaneously on different ones of the program execution modules. At other times a "background task" may be executed on one program execution module 18 while another module 18 executes a user control program.
During the course of carrying out a user control pro-gram, the program execution module 18 reads input status data from the input image tables in one or more of the I/0 scanner modules 20. As called for by the program instruc-tions, the program execution module also writes output state data to the output image table in the I/0 scanning module 20 that services the respective output device. Access to the I/0 tables is obtained via the rack backplane 11.
When a program execution module completes a function chart step, it sends a command to the program execution module 18 containing the next step to be executed. The command identifies the next step and instructs that program execution module 18 to begin executing it.
Hardware In order for the data and commands to be transferred among the modules of the programmable controller, the modules are interconnected as shown in ~igure 2.
Each of the blocks in Figure 2 contains a reference to other Figures of the drawings that contain the details of the component represented by the block. Each of the modules is connected to the rack backplane 11 which consists of separate control, data and address buses, 21-23 respective-ly. The control bus 21 consists of a number of separate lines to which a module may connect to depending upon the control signals required for that type of module. The data bus 22 is thirty-two bits wide and the address bus is twenty-seven bits wide.

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In the preferred embodiment, each of the system con-troller 16, program execution processor modules 18 and re-mote I/O scanner modules 20 includes a removable daughte,r board containing a local memory for data and operating in-structions for that module. The daughter board contains abattery to sustain the memory when power is removed from the controller, The memory 134 in each remote I/O scanner mod-ule contains an I/O image table that indicates the state of each of the sensor devices and the desired state of each of the controlled actuators connected to the scanner module 20. The system controller's memory 69 contains various ; segments that store data regarding the system status and configuration as well as information relating to specific system operations. Each of the processor modules 18 have a random access memory 106 which stores the function chart data, user control programs and their operating variables.
Each of the functional modules of the programmable controller 10 will be described in detail in the following sections.
~0 System Controller As noted previously, the system controller module 16 provides a communication interface for the programmable con-troller to external terminals and local area networks. The system controller 16 also performs system housekeeping func-tions, such as providing an indication of the system status and supervising access to the backplane 11.
During normal operation of the programmable controller, the system controller takes care of communication with the external devices that are connected to it, such as network 28 and programming terminal 24. One of the significant :

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tasks is communicating with the terminal 24 to provide information allowing the operator to monitor the system performance and to detect faulty sensors or actuators.
Another task supervised by the system controller is the exchange of data with a host computer or a peer prograrnmable controller via the local area network 28. This enables the host computer to collect statistics from one or a number of programmable controllers regarding their operation. In addition to these functions another function the system con-troller 16 receives all programming changes and sees to itthat the program in the corresponding program execution module 18 is updated. For example, this includes adding, deleting and changing various r,ungs of the ladder program.
The system controller as shown schematically in Figure 3 connects to the backplane buses 21-23 and is divided into three sections (delineated by dashed lines) for backplane interface, processing and communication operations. The backplane interface section supervises the backplane access for all the rack modules and interfaces the controller module 16 to the backplane 11. The processor section exe-cutes a supervisory program for the controller 10. The communication section is primarily responsible for communi-cating with external terminal 24 and local area networks, such as LAN 28. Each of the processor and communication sections includes a set of internal buses, cornmunication buses 31-33 and processor buses 61-63 respectively.
Various circuits connected to the communication buses control the interfacing of the system controller 16 to the programming terminal 24 and the local area network 28. The communication buses consist of control bus 31 having a num-ber of individual control lines running between various . .

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components in the communication section, an eight bit ~7ide data bus 32 and a sixteen bit wide address bus 33. The communication section is built around a microprocessor 30, such as the model Z80 manufactured by Zilog, Incorporated.
The microprocessor 30 executes machine language instructions which are stored in a read-only memory (ROM) 34. The in-structions are fetched from the ROM, decoded and then exe-cuted by the microprocessor 30 to carry out the communi-cation functions. The program controlling these functions is similar to that employed in previous programmable con-trollers.
A conventional address decoding circuit 36 receives each address issued by the microprocessor 30 and decodes it to produce the proper set of signals on control lines 31.
For example, if the microprocessor 30 is accessing the ROM
34, the address decode circuit 36 will recognize that the address sent by the microprocessor 30 on bus 33 is within the range of addresses at which the ROM is located. Once it has recognized which device in the communications section is to be accessed, the address decode circuit 36 produces con-trol signals for the device to carry out the access.
Two serial input/output devices, UART 46 and serial input/output controller (SIO) 48, are also connected to the three communication buses 31-33. The UART 46 may be any of - 25 several commercially available universal asynchronous re-ceiver/transmitter integrated circuits.- The UART 46 con-verts the parallel data which is present on he communica-tion data bus 32 into a properly formatted serial signal which is fed to an input/output line driver/receiver 50.
The line driver 50 provides output signals corresponding to any one of several serial signal standards, such as RS232, -12~

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v RS423 or ~S422. The serial I/O communication controller 48 may be any of several commercially available integrated circuits which service two synchronous serial communication channels. The SIO ~8 interfaces the communication section of the system controller 16 to local area networks connected to the line drivers 52 and 54, such as network 23 of Figure 1. The programming terminal 24, shown in Figure 1, is con-nected to one of these line driver 52 or 54.
Also located within the communication section is a ran-dom access memory (RAM) 38 for temporary storage of data received from or to be sent to the various external devices connected to the system controller. The RAM 38 may be ac-cessed via address bus 33 so that data may be written into or read from the memory via bus 32 depending upon enablinq siqnals from control bus 31. RAM 38 incorporates a parity circuit which analyzes each digital byte being stored in the RAM and produces a parity bit using conventional techniques.
This parity bit is employed to check the integrity of the data read from the random access memory 38. A direct memory access (DMA) circuit 42 is provided to enable rapid data ex-change between the SIO 48 and the RAM 38 during the communi-cation process. The DMA circuit 42 allows the SIO 48 to access RAM 38 to store or obtain data which have been re-ceived or will be transmitted over their respective external communication channels.
` Access to the communication buses 31-33 is controlled ~` by an arbitration circuit 40 which resolves conflicts when several devices request access to these buses at the same time. The arbitration circuit 40 determines which component of the communication section will have access to the shared buses 31-33. A device seeking the buses sends a request -13~

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signal to the arbitration circuit 40 via a line of the con-trol bus 31 and the arbitration circuit grants the request to one device at a time by producing an access signal on another control line for that device.
A counter/timer circuit (CTC) 44 connects to the commu-- nication buses 31-33 and to an interrupt terminal on micro-processor 30 in order to process interrupt requests from the other components within the communications section. The CTC
44 is also configured as a timer to produce an interrupt request to the microprocessor 30 at a given periodic inter-val, such as every 10 milliseconds, so that various routines may be periodically executed regardless of the task then being performed by microprocessor 30. In response to an interrupt request from the CTC 44, the microprocessor 30 reads a vector from the CTC 44 directing the microprocessor to the appropriate interrupt service routine stored in ROM
34, such as performing a data I/O request from either UART
46 or SIO 48.
Referring still to Figure 3, the processor section is linked together by a set of buses that comprise control lines 61, a sixteen bit data bus 62 and a twenty-three bit address bus 63. Access to these buses is controlled by an arbitration circuit 64 similar to circuit 40 on the communi-cation buses. Two sets of data yates 56 and 5~ extend be-2S tween the communciation buses 32 and 33 and processor buses 62 and 63 of the system controller module 16. Specifically, ; the first set of gates 56 provides an eight bit bidirection-al connection of the communication section data bus 32 to the data bus 62 of the processor section; and the second set of gates 58 connects the two address buses 33 and 63. The data gate 56 consists of two sets of eight individual .
--lg--tristate data gates, each set controlling data flow in one direction between the two buses 32 and 62. Only the lower eight lines of the processor data bus 62 are coupled to the eight bit communication section data bus 32. As addressing will only occur from the processor section to the communica-tion section, address gates 58 consist of one set of sixteen tri-state signal gates coupling the sixteen communication address bus lines 33 to the lower sixteen address lines in the processor section. An interbus control circuit 60 is connected to control lines 61 and 31 from the processor and the communication sections, respectively, and in response to access request signals from arbitration circuits 40 and 64, the control circuit 60 enables the data and address ~uffers 56 and 58.
The processor section is built around a sixteen-bit microprocessor 66, such as a model 68010 manufactured by Motorola Inc., which executes program code stored in read only memory 68. The 68010 microprocessor is essentially a memory mapped device and does not have any input/output lines directly connected to it. Therefore, its access to other components on the processor bus must be accomplished through issuing addresses on bus 63. The address sent from the microprocessor 66 is decoded in an address decode cir-cuit 70 to produce the proper control signals for the acces-sed component. The processor address decoder 70 functionsin much the same manner as the communication section address decoder circuit 36. The processor section also contains an interrupt processor 72 which controls interrupts to the microprocessor 66 and provides the proper instruction ad-dress vectors.

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A data transfer acknowledge and bus error (DTACK/3ERR) circuit 74 is also connected to the processor control bus 61. Circuit 74 responds to signals from the various compo-nents in the processor section to acknowledge the completion of a data transfer and issue bus error signals in the event of improper addressing or failure of data transfer. These signals are acted on by the microprocessor 66 which takes corrective action. The processor section also includes clock circuit 89 that contains the main system clock and a real time clock. A system status circuit 88 receives input signals related to the status of the entire system 10 and provides an indication of that status.
The main random access memory (RAM) 69 for the system controller 16 is also connected to the processor buses 61-63. The RAM 69 is a static memory containing 393,216 (384K) memory locations each of which is 16 bits wide and serves as the system memory for the entire controller lOo The system memory 69 can be directly accessed via the back-plane 11 by other modules in the system without the inter-vention of the central processing unit 66 within the system controller.
Figure 7 illustrates the data structures within the main system memory 69 included in the system controller module 16. The system memory 69 stores separate data files, which contain data for performing specific functions during ` the operation of the programmable controller. The data structures include various forms of data such as integers, floating point numbers, ASCII characters, and various control structures. The first file 200 is a directory of the other files stored in the system controller memory 69.
The remaining memory is divided into a system status file ~ . , .;. , 201, system data table 202 and a set of system support ~iles 203.
The system status file 201 contains data relating to the configuration of the entire programmable controller 10. Included in this file is information identifying the various user selectable features of the programmable con-troller that have been enabled by the system operator. The real time clock data regarding the time of day, month, day and year are also included in this portion of the system memory. Digital words indicating the occurrence and type of various system faults and errors, as well as pointers indi-cating the program instruction being executed when the ault occurs are stored within another sub-file of this section.
A section of the system status file 201 also lists the lS number and type of all the active modules on the system as well as the relative module number and address pointers necessary to access each module. For example, if more than one program processor module 18 or remote I/O scanner module 20 is present in rack 12, the user must assign a unique number via a thumb wheel on the module to distinguish the various modules of that type. The thumb wheel setting is read by the system controller during initial start-up of the system and stored in this portion of the system status file 201.
The system data table 202 contains data that is shared by more than one module. For example, results of various computations from one program processor module 18 may be stored in this portion of the system memory so that other program processor modules may readily access the data. Mem-ory space is allocated within the system data table 202 to store the data that was received or that will be transmitted .
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, via the various external communication Iinks of the system controller's communication section. Other modules in the system 10 are directly able to access these storage loca~
tions.
The system data table 202 also contains the value of various system counters and variables which are either used by the system controller 16 or which are commonly used by a number of other modules such as program processor modules 18 or the I/O scanner modules 20. The final sub-file within the system data table 201 is a space allocated for the user defined data for various programs that the user has loaded into the programmable controller.
The final section 203 of the system controller main memory 69 is dedicated to the system support files. These files include the source program information for the func-tion chart program. The programmable controller 10 does not directly execute the function chart program. However, as will be described later, the function chart is employed dur-,ng the programming step to generate data which is used to direct the operation of the program execution modules 18.
In order to permit the subsequent editing of these programs, a source version of the function chart must be available for display on the programming terminal. As also will be de-scribed hereinafter, the support files 203 contain simul-taneous counters for execution of various branches of the function chart. Although the local memory in each module contains data regarding its status, in some instances these memories do not have a battery to sustain them. In order to retain such volatile information after a power shut-down, the status information for these modules is replicated in a sub~file of section 203 of the system memory 69.

Communication parameters are also stored in this sec-tion 203 for configuring the UART 46 and the serial I/O
module 48 within the communication section of the system controller 16. Among other things these parameters include baud rate, word size and control bits for the serial data signal format. For example, parameters for communicating with the operator terminal 24 are stored in this portion of the system memory. In addition, as noted previously, a number of programmable controllers may be connected via the local area network 28, in which case, parameters must be provided in each controller instructing them how to communi-cate over the network.
; Referring again to Figure 3, the processor section of the system controller 16 interfaces with the backplane buses of rack 12 via a plurality of components that are coupled to both sets of buses. Specifically, the backplane data bus 22 is connected to the processor data bus 62 by a set of bidi-rectional data transmission gates 78 and the backplane ad-dress bus 23 is connected to the processor address bus 63 by another set of bidirectional gates 76. When the system controller 16 seeks to exercise control over the backplane 11 of the programmable controller 10, a master mode control circuit Bl responds to signals on the control lines of the processor bus 61 and issues the proper control signals over the backplane control bus 2I to access other modules within the rack 12.
When another module within the rack 12 seeks access to the system controller 16, in order to read the contents of ain RAM 69, for example, the system controller becomes subordinate to the control of the backplane 11 by this other module. In this circumstance, a slave mode control circuit ~ 3'~ 3 82 within the system controller 16 responds to the addressof the system controller that appears on the backplane address bus 23 and to control signals on the control lines of the backplane bus 21 which lead from the other module. In response the slave mode control 82 issues signals to trans-mission gates 76 and 78 enabling the other backplane module to access the system controller 16. In this latter in-stance, the master mode control circuit 81 is in a dormant state. The two bus gates 7~ and 78 receive enabling control signals from the master or slave mode control circuits 81 and 82 via the lines of control bus 61 depending upon the mode of backplane communication.
A backplane arbitration circuit 84 supervises access to the backplane 11 and resolves conflicting requests for ac-.-ess from the modules in the system. In previous program-mable controllers the priority for access to the backplane buses was determined based upon the slot within the rack 12 that the requesting module occupied. For example, if two or more modules requested access to the backplane at the same time, the module in the leftmost slot was awarded access.
Because the present programmable controller includes several processor modules 18, the amount of backplane acti~ity has increased. ~herefore, determining priority for access to the backplane 11 on a purely slot order basis could deprive modules located in the rightmost slots from obtaining access within a reasonable amount of time. As a result, the pres-ent backplane arbitration circuit 84 employs a rotating priority system for determining which of several modules simultaneously seeking access to the backplane will be granted such access. With the rotating priority system, ~`

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each time that a module relinquishes control cf the back-plane 11, the order o~ priority shifts.
A schematic diagram of the arbitration circuit 84 is shown in Figure 20~ One of eight backplane request lines BR0-3R7 originates at each of the eight slots of the rack 12. The request lines BR0-BR7 are part of the backplanecontrol bus 21. The eight backplane request lines are coupled to the inputs of an eight bit request latch 170 and to an eight input NAND gate 171. When a module in the rack requests access to the backplane 11 it applies a low logic level to its backplane request line, BR0-BR7. This low level. produces a high output from NAND gate 171. A
backplane grant acknowledge llne, BGACK, is part of the backplane control lines 21 and is connected to each module 16-20 and the arbitration circuit 84. WHen the backplane 11 is available a high logic level will be present on the back-plane grant acknowledge line BGACK.
The two high level signals from NAND gate 171 and the : BGACK line produce a low output from NAND gate 172. The output of NAND gate 172 is coupled to an enable terminal for the request latch 170 which causes the latch to store the : signals on each of the eight backplane request lines BR0-BR7. The latched backplane request signals REQ0-REQ7 are coupled to eight slot priority circuits 181-188.- Each priority circuit corresponds to one of the eight rack slots and determines whether its slot should have access to the ` backplane. This determination is based upon which module slots are requesting backplane access and the order of priority then in effect.
The eight orders of priority are illustrated by the . matrix of Figure 29. Each column of the matrix represents .
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L~ 13 one order of priority with the relative priority level of each slot shown in descending order down each column. For example, in the first priority order (column 0) the module in the slot 0 has top priority for accessing the back-plane. The priority then decreases in slot number orderwith the last module in slot 7 having the lowest priority.
In the next priority order (column 1) each module has moved up in priority with slot 1 having top priority. The module in slot 0 now has the lowest priority. The priority of each module increases with each subsequent order set until in the rightmost column, the module in slot 7 has the highest pri-ority. By sequentially placing each priority order into effect one at a time, each module in the rack periodically will have the highests priority level assigned to it.
Which of the priority orders is in effect is determined by the output of a three bit priority counter 173. The counter 173 is incremented by each rising edge of the signal on the BGACK line. When the output of the priority counter is seven, the next rising edge of the BGACK signal resets the counter to zero. The three output bit lines from the priority counter 173 are connected to each of the slot pri-ority circuits 181-188 via the backplane control bus 21.
The details of each of the slot priority circuits 181-188 is shown in Eigures 21-28 respectively. Each priority circuit 181-188 includes a chain of six AND gates to which seven of the output lines REQ0-REQ7 from the request latch 170 are coupled. The outputs of the six AND gates are con-nected to different inputs of an 8 to 1 multiplexor (MUX).
Which seven of the request latch output lines REQ0-REQ7 are connected to the AND gates and how the AND gate outputs are .

- .

coupled to the multiplexor determines the priority order sequence for each priority count.
In order to better understand how each priority circuit 181-188 operates the circuit 181 for slot 0 will be describ-ed in detail. With reference to Figure 21, the output line REQ7 from the request latch 170 is coupled to an input I7 of ; an 8 to l multiplexor (MUX) 197. Output line REQ7 is also coupled to the A input of a first AND gate 191 whose B input is coupled to output line REQ6 from the request latch 170.
The output from the first AND gate l91 is coupled to input I6 of multiplexor 197 and to the A input of a second AND
gate 192. The B inpu~ of the second AND gate 192 is coupled to request latch output line REQ5. The output from the second AND gate 192 is coupled to multiplexor input I5 and to the A input of a third AND gate 193. The ~ input of the third AND gate 193 is coupled to output line REQ4 from the request latch 170. Input I4 of multiplexor 197 is coupled to the output of the third AND gate 193 which output is also coupled to the A input of the fourth AND gate 194. The B
input to the fourth AND gate 194 is coupled to the request latch output line REQ3. The output from the fourth AND gate : 194 is coupled to multiplexor input I3 and to the A input of a fifth AND gate 195. The output line REQ2 from the request latch 170 is coupled to the B input of the fifth AND gate 195. The output from the fifth AND gate 195 i5 coupled to the A input of a sixth AND gate 196 and to input I2 of the `. multiplexor 197. The B input of the sixth AND gate 196 is coupled to the request latch output line REQl. The output from the slxth AND gate 196 is coupled to multiplexor input Il and input I0 is clamped to a high logic level potential Vdd.

~' - .
:

~ 3 The three output lines from priority counter 173 (Fig-ure 20) are coupled to the select inputs of multiplexor 197. The signals levels on the select.inputs determine which of the eight multiplexor signal inputs I0-I7 is con-nected to this output. With each incrementation of thepriority counter lg3, the multiplexor output is coupled to a different point on the AND gate chain thereby changing the relative priority of the corresponding rack slot. Thè same changing of relative priority occurs simultaneously in the other priority circuits.
With continued reference to Figures 20 and 21, assuming that the counter's output is initially zero, the multiplexor 197 in the slot 0 priority circuit 181 will connect the `
first input I0 to its output. Because this input is con-lS nected to Vdd, the output of the multiplexor 197 will behigh. This output is coupled to a three input NAND gate 199. If the module in slot 0 is requesting access to the backplane 11, the low bus request signal (BR0) on line REQ0 will be converted to a high level by inverter 198 and ap-plied to another input of NAND gate 199.
The NAND gate 199 also receives a high level outputenable signal from node 180 on Figure 20. The output enable signal is generated by delay circuit 177, inverters 189 and 179, and NAND gate 178 from a low output of AND gate 172 and a high level signal on the BGACK line~ The output from AND
gate 172 i5 delayed 70 nanoseconds to allow the output from the multiplexors in the priority circuits 181~188 to be valid. If the output of the delay circuit 177 is low and the signal on the BGACK line is high, a high level priority output enable signal will be applied to the NAND gate, such as gate 199, in each of the slot priority circuits.

~ 3 With reference to the particular priority circuit for slot 0 in Figure 21, all three inputs to NAND gate 199 will be high when it is the highest priority module requesting access to the backplane and the backplane is available. When this occurs N.~ND gate 199 produces a low level baclcplane grant siynal BG0. The BG0 signal is coupled over a backplane control line 21 to the module in slot 0 to indicate that it has control of the backplane 11. At this time the modules in the other slots will receive high level signals on their backplane grant lines BGl-BG7 from their respective priority circuits 182-187.
Upon receiving the low BG0 signal, the module in slot 0 will produce a low signal on the backplane grant acknow-ledge line BGACK. This signal will be coupled to NAND gate 178 producing a low level at node 180, thereby removing the low level BG0 signal.
When the module in slot 0 ceases its use of the back-plane 11, it removes the low level signal from the BGACK
line. The resulting rising edge of the signal on line BGACK
increments the counter 173 to a value of one. This results in the priority order depicted in the second column of Fi-gure 29 being implemented. The portion of the arbitration circuit shown on Figure 20 still functions as described above when one or more modules now request access to the backplane 11. Specifically, the new backplane requests are latched in the request latch 170 and the active low back-plane grant, output from one of the slot priority circuits 181-188 is enabled 70 nanoseconds thereafter.
The operation of the priority circuits 181-188, how-ever, is different. The output from the priority counter173, a digital one, causes the multiplexor MUX in each pri-, .

; : , ority circuit to couple its second input Il to its output.This results in a different point of the chain of AND gates being coupled to the output NAND gate 199 of each circuit.
With respect to the priority circuit 181 for the first slot, the modules in slots one through seven now have a higher priority. A backplane request from any of these modules on lines BRl-BR7 will produce a low signal on the corresponding output line REQl-REQ7 from the request latch 170. A low level on any one of these lines will be coupled through the chain of AND gates 191-196 and produce a low level at the second input Il of MUX 197. This low level is coupled to one input of the output NAND gate 199 producing a high level BGO signal regardless of the level of line REQ0. Therefore, any request from one of the other modules will take priority over a request from the module in slot 0. However, if none of the other modules is requesting access to the backplane 11, the output of MUX 197 will be high. Thus if the module in slot 0 now seeks access to the backplane 11, its low level signal on line REQO will produce an active low level BG0 signal from the output NAND gate 199 .
With each subsequent incrementation of the counter 173, the MUX 197 will select a higher numbered input line IO-I7. This couples a different point on the chain of AN~
gates 191-196 to the output NAND gate 199 and decreases the number of request signals on lines REQl-REQ7 that can in-hibit a backplane request on line REQ0 from the first module in slot 0. The connections to the AND gate chains in the other priority circuits 182~188 are similarly changed by the different counter values. Therefore each time the backplane 11 becomes available, the arbitration current 84 in the ,: ' .

?L~ ~5~ 3 system controller module 16 changes the order of access priority.
As noted above the system controller module 16 executes programs which control ~he initialization of the system and communication with external computers. It does not execute the user control programs.
Program Execution Processor The program execution processor modules 18 store and execute specific user control programs, such as ladder pro-grams. One of these modules is shown schematically inFigure 4. During this execution the modules 18 read the state of the sensing devices from input image table in the ; memory 134 of the various I/O scanner modules 20, and write output data from its memory to the output image tables in the I/O scanner modules. Data is also obtained from the system memory 69 in the system controller 16.
In order to perform these tasks, each processor module 18 has a set of internal buses 91-93 which are coupled to the backplane 11. Specifically the processor module 18 has a thirty-two bit internal data bus 92, a set of control lines 91 and a sixteen bit address bus 93. These are coupled to the data and address buses of the backplane 11 by respective set of tri-state, bidirectional transmission ~ates 94 and 96. The operation of these gates 94 and 96 is governed by an interbus control circuit 95 coupled to back-plane control lines 21 and the module control lines 91. It should be noted that both the internal data bus 92 and the backplane data bus 22 are thirty-two bits wide. Therefore, thirty-two bit data from the processor module 18 can be sent over the backplane as one thirty-two bit word if the recipi-ent module has a thirty-two bit wide data bus. In some pro-cessing functions the module 18 operates on si~teen bit data, and in such case sixteen-bit words are applied to the backplane 11.
The remaining components of the processor module 18 are connected to the internal buses 31-93. These internal buses are driven by a microprocessor 98, which is a thirty-two bit microprocessor sold commercially by Motorola, Inc. as the 68020 microprocessor. The microprocessor 98 has an inter-rupt port which is coupled to an interrupt interface circuit 99. This interface circuit receives signals from four exter-nal interrupt lines connected to terminals on the front of the processor module 18. These external interrupt lines permit devices which sense high priority events, to be interfaced directly to the processor module for fast re-sponse. Three other interrupt lines on the interface cir-cuit 99 connect to circuits within the processor module 18. A signal on any of these external or internal interrupt lines causes the microprocessor 9~ to immediately interrupt normal program execution and execute a routine that cor-responds to that interrupt line. The user may program the routines for the external interrupts, but the internal in-terrupts are serviced by dedicated interrupt service rou-tines.
The processing capability o~ the processor module 18 is also supported by a floating point co-processor 100, and by a bit co-processor 102. The floating point co-processor 100 is commercially available from Motorola, Inc. as the 68881, and it is specifically designed to work with the 68020 microprocessor 98. The bit co-processor 102 is a custom ~ 30 integrated circuit for carrying out Boolean logic operations ; on individual bits of the data words. Bit co-processors .` . . ' have been used in programmable controllers in the past to execute a set of ladder diagram ins~ructions using hardwired logic as described in the aforenoted U.S. Patent 4,742,443.
The three processors 98, 100 and 102 operate in S tandem to execute specific types of instructions included in the control program. The microprocessor 98 may begin execution of the con~rol program and when it encounters a floating point arithmetic function, the floating point co-processor 100 is enabled and the microprocessor relinquishes lo the internal buses 91-93 to it. The floating point co-processor 100 takes over the processing function until the arithmetic operation is complete at which time the microprocessor 98 resumes program execution. If the control program calls for bit processing (i.e. contains an instructions in the set for the bit co-processor 102), the microprocessor immediately relinquishes control to the bit co-processor 102 by writing the address of the control program instruction into a program counter in the bit co-processor 102. The bit co-processor 102 then removes the microprocessor ~0 98 from the internal buses 91-93 and executes the subsequent control program instructions until a stop instruction is encountered. At this point the bit co-processor 102 signals the microprocessor 98 via the control bus 91 to resume control of the buses and execution of the control program.
Approximately 85-90 percent of a typical control program of the "ladder" type may be executed by the bit co-processor 102.
The operation of the custom Boolean logic bit co-processor 102 in conjunction with a microprocessor is fully described in the .

.

above~cited U.S. Patent 4,742,443.
The processor module 18 includes a data size acknowledge (DASACK) circuit 108. This circuit provides a two-bit code on two of the control bus lines which indicates S the "width" of the data on the data bus 92. As will be - described in more detail below, this data may be a long word consisting of thirty-two bits, a regular sixteen bit word, or a single eight bit byte. This data size in~ormation is used by the various module components in this data processing.
The final component of the processor module 18 is a control and status circuit 100 which monitors the status of - the processor module and provides proper control signals on various lines o~ the control bus 91 to enable various components in a conventional manner.
IS Both a read only memory (ROM) 104 and a read-write random access memory (RAM) 106 are connected to all three internal buses 91-93 within the processor module 18. The ROM
104 contains 16 bit storage locations for instructions and constants for the three processors 98, 100, and 102. The RAM
~0 106 provides storage for the operands and the results of the various computations performed by the processor module 18.
The control programs to be axecuted by the module 18 are also contained in its RAM 106.
The details of the RAM memory 106 are shown in ~5 Figure 5. The random access memory 106 is divided into lower and upper banks 112 and 114. Each bank contains a number of storage locations, for example 196,608 (192K) memory addresses. The memory location in each bank is sixteen bits wide and both banks can be enabled simultaneously to provide `'~ , storage for thirty-two bit data wor~s. As noted above the width of the data processed by the execution ~odule 18 may be sixteen or thirty-two bits wide. In order to optimize the storage capacity when sixteen bit words are processed, a transmission gate multiplexer is incorporated into the ran-dom access memory 106 to allow separate sixteen bit words to be stored in both the upper and lower memory banks. Spe-cifically, the multiplexer consists of three sets of tri-state bidirectional transmission gates 116-118, each of ; 10 which provides bidirectional control of sixteen data lines. The first set of transmission gates 116 couples the sixteen least significant bits (bits 0-15) of the data bus 92 to the data terminals of the lower memory bank 112.
Similarly, the third set of transmission gates 118 couples the sixteen most significant bits (bits 16-31) of the data bus 92 to the data terminals of the upper memory bank 114.
The second set of transmission gates 117 cross couples the sixteen least significant bits of the data bus to the data terminals of the upper memory bank 114. The three sets of transmission gates receive control signals from the DASACK
108 via control bus 91 which enables the various transmis-sion gate sets depending upon the width and address of the word being sent on data bus 92. All of the address bus lines 93 go to each memory bank 112 and 114.
I~ thirty-two bits of data are being sent on the data bus 92, the DASACK 108 enables the first and third sets of transmission gates 116 and 118. This stores the sixteen least significant bits in the lower memory bank 112 and the sixteen most significant bits of the data in the upper mem-ory bank 114. When a sixteen bit word is being sent on the data bus 92 it may be stored in either of the memory banks :
.~

~ 3~
112 or 114. If it is to be stored in the lo~7er me~ory bank 112, the DASACK 108 enables only the first set of transmis-sion gates 116 to pass the data to that memory bank. To maximize the storage capability for sixteen bit words, the separate data may also be stored at the same address in the upper memory bank 114, in which case DASACK 108 enables only the second set of transmission gates 117 which couples the sixteen least significant bits of data to the upper memory bank. When sixteen bits of data are being processed, the third set of transmission gates 118 is never enabled.
Figure 9 represents the data structure of the RAM mem-ory 106 for each program execution processor module 18. The memory 106 includes a section 310 which contains status information regarding the module's operation. Each program execution processor module 18 also contains its own data table 312 which is stored in the RAM 106. The data table 312 includes memory locations for various counters, timers and intermediate computation values.
The largest share of the RAM memory 106 is devoted to storing the control programs. The actual program contents, as will be described in detail later, comprise compiled control programs, independent background tasks and various interrupt routines to be processed by the processor modules 18. In order to properly carry out the control programs, support files containing the function chart data, called "descriptors," are also contained within the program area 313.
In one mode of operation of the program execution pro-cessor module 18, referred to herein as the "synchronous mode" r the processor module 18 periodically copies the en-tire input image table from the I/O scanner module 20 into : , its own memory 106. Space for this copy of the I/O image table is provided in memory section 314.

Remote I/O Scanner Module As noted above, the I/O scanner modules gather input sensor data for use by the program e~ecution processor mod-ules 18. Referring to Figure 1, 2 and 6, a remote I/O scan-ner module 20 couples the programmable controller 10 to one or more remote input/output racks 17 containing individual I/O modules 19 which interface the sensors, or input de-vices, and accuators, or output devices, to the programmable controller 10. Each scanner module 20 periodically requests input data pertaining to the status of the input devices connected to the remote I/O racks 17 and s~ores it in the module's input image table for reading by other controller modules, such as the processor modules 18. The scanner module 20 also contains an image table of output data that it receives from other controller modules, such as the processor modules 18. At regular intervals the updated output data in the scanner module's output image table is transferred to the respective remote input/output racks 17 to control the various actuators connected to these racks.
Referring specifically to Figure 6, each remote I/O
scanner module 20 connects to the three backplane buses 21-23. The I/O scanner 20 contains three sets of internal buses: memory access buses 121-123, microprocessor buses 131-133 and I/O buses 141-143. The three memory buses 121-123 are connected to the backplane 11 by a set of ad-dress bus gates 124 and a set of data bus gates 126. Both of these transmission gates are controlled by an inter-bus ` control circuit 128 which sends signals to the gates 124 and : -33-, :

~L~ 3 ~
126 via the memory control bus 121. A local random access memory, referred to as main RAM 134, is coupled to the three memory buses 121-123. It stores the input image table for the sensor information being input to the I/O scanner 20 from the remote I/O racks 17 and it also stores the output image table for the output data being output to the remote I/O racks 17.
Figure 8 shows in detail the data structures stored in the main RAM 134 of each I/O scanner module 20. These data structures include an I/O image table for the remote sensors and actuators serviced by that module 20. The input image table 210 represents the sensor data and consists of three separate sections 212-214. The first section 212 is the image of the actual state of the various sensing devices.
The information relating to the inputs that are forced on is contained in the second section 213 within the input image table 210. As with previous programmable controllers, the user may force the status of a given sensor to appear to be either on or off regardless of its actual state. This en-; 20 ables the bypassing of faulty sensors, for example. Forced on sensors are designated by a binary one in an address for i each such input.
The sensors that are forced off are indicated in the third section 214 of the input image table 210 by a logical zero stored for those sensors. Although by definition the user may write into the forced data tables 213 and 214, the user is prohibited from writing into the actual input image table 212. During the operation of the programmable con-troller, the user programs can read either the actual input image data from section 212 or the forced image of the sen-~ -3~-.' , ~L~
sor. If the forced image is read, the scanner module 20 logically OR's the actual sensor input state ~7ith the forced on data from section 213, then that result is ANDed with the forced off data for that sensor from section 214.
S The output image table 211, also stored in the main RAM
134, includes the output image data table 215 which repre-sents the status for the output devices connected to the remote I/O racks 17 serviced by the I/O scanner module 20.
Typically, this output data is determined by the execution of the user control program in the processor module 18. A
second section 216 representing the forced on output data and a third section 217 representing the forced off output data are also included in the output table 211. This allows the user to define a given actuator as always being on or off regardless of the results from the execution of the user control program. For example, this is useful where a por-tion of the controlled equipment may have to be shut down for maintenance and should not be turned on by the user control program. The control program may read each of the output tables 215-217 individually. If the forcing of the output states is disabled the data sent to the remote I/O
racks 17 for activating or deactivating the various controlled devices is from the output image table 215. If output state forcing is enabled then the data sent to the remote I/O racks 17 is a logical combination of the three output tables 215-217 using Boolean logic that is identical to the combination of the three input tables 212-214 described above.
Referring still to Figure 8, the data structure in the main RAM 134 of the I/O scanner module 20 also includes a .
.

block 218 that contains data regarding the status of the communication adapter in each of the remote I/O racks 17 serviced by the module 20. This data is used during the transfer of information over the I/O links lS with those S remote I/O racks.
~lthough the state of most of the sensor and operating devices may be represented by a single binary bit, certain devices, such as position sensors and analog devices, pro-duce or require information that comprises a plurality of digital words. These data may be transmitted to or from the remote I/O rack 17 into the I/O scanner module 20 as a large block of data. Memory section 219 in the main RAM 134 con-tains information necessary to control such transfers of blocks of data and a companion section 220 provides a memory area for the storage of the actual blocks of data. For a detailed description of this block transfer reference is made to U.S. Patent No. 4,413,319 entitled "Programmable Controller for Executing Block Transfer with Remote I/O
Interface Racks".
Reerring again to Figure 6, the inter-bus control circuit 128 also sends control signals to an I/O data arbi-tration circuit 130 which resolves conflicting requests for access to the memory buses 121-123 from the backplane 11 and the microprocessor buses 131-133. Two sets of transmission gates, address gates 136 and bi-directional data gates 138, interconnect the memory buses 121-123 to the microprocessor buses 131-133 and receive control signals from the I/O data arbitration circuit 130 via the memory control bus 121. The operation of the remote I/O scanner 20 is controlled by an eight-bit microprocessor 140 which is connected to three .
`'~`' . ' ' ., 3~
microprocessor buses 131-133. Microprocessor 140 is com-mercially available from Zilog, Inc. as the Z80 and it is the only device which is directly connected to the micro-processor buses 131-133, other than the sets of transmission gates 136, 138, 144 and 146 and the I/O data arbitration circuit 130.
A set of address gates 144 interconnects the micropro-cessor address bus 133 to the I/O address bus 143 and a set of bi-directional gates 146 interconnect ~he data buses 132 and 142. Both sets of tri-state gates 144 and 146 receive control si~nals from the I/O data arbitration circuit 130 via the microprocessor control bus 131. The microprocessor control bus 131 is directly coupled to the I/O control bus 141.
The I/O control buses 141-143 interconnect the devices . which interface the I/O scanner module 20 to the remote I/O
racks 17. These include a serial I/O interface circuit 148 which provides two synchronous serial input/output channels 150 and 151, each of which has its own cable driver/receiver circuit 152 and 153 respectively. A counter/timer circuit (CTC) 154 and a direct memory access IDMA) controller 156 are also connected to the I/O buses 141-143. The I/O bus section of the scanner 20 also includes a random access memory, indicated as I/O RAM 158 for temporary storage of ; 25 input and output data communicated over I/O serial links 15. A read-only memory (ROM) 160 is also connected to the . I/O buses 141-143 and it contains the programs which are executed by the microprocessor 140 to carry out the func-tions of the scanner module 20. An address decode circuit 162 is also connected to the address and control buses in the I/O section of the scanner module 20 to interpret the .:
.. . .
,~ .

~ 3 addresses generated by the microprocessor 140 and produce the proper enabling and control signals on the lines of control buses 131 and 141.
The operation of the remote I/O scanner modules 20 is described in a subsequent section on data acquisition and transfer.
Controller Operation The novel architecture of the present programmable controller 10 dictates that it functions in a unique man-ner. The areas in which the present system operates differ-ently than previous programmable controllers include system initialization, I/O data acquisition and transfer, and in-termodule communication. However, the most significant difference with respect to this controller lies in the form-ulation and execution of the user control programs. Each ofthese unique functions will be described in detail.

System Initialization During system power-up, the system controller 16 super-vises the configuration of the system and various othertasks as shown in the flowchart of Figure 13. The first phase 450 of power-up occurs immediately after the system reset signal terminates. During this interval no module is allowed on the backplane 11 and the various modules perform local tests of their own memory and other subsystems. When each module is finished, it releases a common ready line of the backplane control bus 21. When the last module has completed its internal tests the signal on the ready line is ; true. This signals the system controller 16 to make a tran-sition into the next power-up phase.

, -;8-During the second phase 451, the system controller 16 goes on to the backplane 11 and requests the module in each slot of the rack 12 to identify itself and provide the sys-tem controller 16 with various information regarding the module, such as the module type, and addresses for various interrupts and data pointers which are stored in the system memory 69. Based on the information received from each module, the system controller 16 verifies that the system is properly configured. For example, if there is more than one program execution~processor module 18 on the system, the system controller 16 verifies that each one has a unique module thumb wheel designation and that two of them do not have the same designation.
In the next phase 452, the system controller module 16 stores the backplane communication parameters in preassigned memory locations in each module. These parameters instruct the modules how to communicate over the backplane. Once a module knows how to communicate via the backplane 11 it - loads its memory address pointers into memory locations in the system memory 69 of the system controller 16. These address pointers are used by other modules to access the data in the module or issue instruction to it. For example each module loads the addresses of its interrupts into the system status section 201 of the System Memory (Fig. 7). In ~5 the course of this phase, the various functional modules may communicate only with the system controller 16, not with any other type of module. Referring again to ~igure 13, the next phase 453 of the intialization allows the modules to talk with each other and exchange any necessary data. At the completion of this phase, the programmable controller 10 .
.~ , .
; , -, , .

r~'~3 at step 454 makes a normal transition into the user defined start-up mode, typically either "PROGRAM" or ~RUNo 1~
The system has three primary modes of operation: pro-gramming, program run and fault mode, as determined by the system controller module 16. Each of these modes is subdi-vided into a number of internal modes. For example, the run mode has an initial input prescan internal mode which prior to program execution causes each of the remote I/O scanner modules 20 to gather data from their respective I/O racks 17 ; 10 and create an initial input image table 210. Following the input prescan, a program prescan is carried out during which one or more user control programs are scanned once to create an initial output image table 211. Once both of these prescan modes have been completed and the input and output lS image tables 210 and 211 have been created, the various outputs are enabled and the run mode commences formal execution of the user control program.
In order to explain the formulation and execution of the user control program, one must understand how data and commands are transferred within the programmable controller 10 .

Data Acquisition and Transfer .Referring to Figures 1, 2 and 6, periodically each I/O
module 20 gathers input data from sensors connected to each of the controller's remote racks 17. This acquisition of data is similar to the I/O scans performed by previous pro-grammable controllers such as the one described in U.S.
Patent No. 4,442,504. While the system is in the run mode, each I/O scanner module 20 sequentially requests each remote .

rack 17 to send input data regarding the status of sensing devices connected to the remote rack.
With reference to Figure 6, the gathering of data from the remote I/O racks 17 is carried out by microprocessor 140 instructing the I/O data arbitration circuit 130 to enable transmission gates 144 and 146. This couples the micropro-cessor buses 131-133 to the I/O buses 141-143. After the connection of the buses is completed, the microprocessor 140 sequentially sends commands to the remote I/O racks via SIO
148 and line drivers 152 and 153. In response to these commands the remote racks 17 transmit their sensor input data to the I/O scanner module 20. The received input data is temporarily stored in I/O RAM 158. The communication protocol used to gather data from the remote I/O racks 17 is similar to that used by previous programmable controllers.
At regular intervals the gathered input data is trans-ferred from the I/O RAM 158 to the input image table con-tained within the module's main RAM 134. This transfer is accomplished by the microprocessor 140 requesting that the I/O data arbitration circuit 130 couple the memory access buses 121-123, microprocessor buses 131-133 and I/O buses 141-143 together. If the backplane 11 is not coupled to the memory access buses 121-123, the I/O data arbitration circuit 130 will issue control signals via control buses 121 and 131 to transmission gates 136,-138, 144 and 146. In response to the control siqnals, the transmission gates interconnect the three sets of internal buses. The I/O data arbitration circuit 130 then sends an acknowledge signal to the microprocessor 140 indicatinq that the connection has been made. Upon receiving the acknowledge signal, the microprocessor 140 transers the data between the I/O RAM

, .

, ' 158 and the main RAM 134. The input data is stored in the input imase table 212 (Figure 8) of main RAM 134. When the transfer is complete the microprocessor 140 signals the I/O
data arbitration circuit 130 to disconnect the interconnec-tion of the internal buses.
; At other periodic intervals, the remote I/O scanner module 20 sends output state data to the remote I/O racks 17. This process is similar to that described immediately above with respect to the input status data. The micropro-cessor 140 requests the interconnection of the internal module buses 121-123, 131-133 and 141-143. Once the inter-connection is made the output image table data in main RAM
134 is transferred to the I/O RAM 1~8. The bus intercon-nection is then disconnected. The output data in I/O RAM
158 is systematically sent to the remote I/O racks 17 over serial links 15 to activate or deactivate the operating ; devices on the controlled equipment.
As noted above, the I/O RAM 158 is used to store the data that is sent and received over the serial links 15.
During the communication process the microprocessor 140 does not have to access the main I/O image table stored in main RAM 134. This freeing of the main RAM 134 from communica-tion tasks as well as the I/O module's separate internal bus configuration permits other modules on the backplane 11, such as the system controller 16 and processor modules 18l to directly access the I/O image table data in the main R~M
134. This direct access from the backplane does not involve the microprocessor 140 which may be simultaneously control-ling the communication with the remote I/O racks 17.
When the system controller 16 or one of the processor modules 18 desires to read the status of a given input de-.. . ............ .
~,. . . .
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vice, it requests access to the backplane buses 21-23 in order to interrogate the I/O scanner module 20 that receives the input data from that particular sensor. Upon being granted access to the backplane 11, the processor module 18 S or system controller 16 addresses the appropriate I/O scan-ner module 20. In response to this addressing, the interbus ` access controller 128 within the respective I/O scanner module 20 receives an access request signal over a line of the control bus 21 of the backplane 11. The interbus access - 10 controller then signals the I/O data arbitration circuit 130 that a request to access main RAM 134 has been received from another module. At the appropriate time when the internal memory buses 121-123 are available to be connected to the backplane buses 21-23, the I/O data arbitration circuit 130 lS signals the interbus access controller 128 that it may con-nect the backplane and memory buses together via transmis-sion gates 124 and 126. The completion of this connection is then acknowledged by the inter-bus control circuit 128 to the requesting module via a line of the backplane control bus 21. The other module then reads from or writes data into the I/O data image table in the main RAM 134. The data transmission may be a single data word or a block of words. The requesting module holds control of the back-plane 11 until all of the requested data has been transmit-ted to it from the I/O scanner 20. When the access is fin-`~ ished the inter-bus control circuit 128 is signaled via the backplane control bus 21 and the connection to the backplane 11 is disconnected.
As is seen, the configuration of the I/O scanner module 20 permits other modules connected to the backplane to have direct access to the I/O scanner's main RAM 134 without the .

intervention of the scanner's microprocessor 140. This allows the microprocessor to devote its attention to con trolling the gathering of sensor data and transmitting out-put commands to the equipment actuators.
The access to the I/O image table data by each program execution processor 18 may be on an "as needed" basis or periodically an image of the entire I/O data table may be read by the processors from the scanner modules 20. In the "as needed" mode, whenever the user controller program being executed by the processor module 18 requires the evaluation of a sensor status, the processor module 18 gains access to the backplane buses 21-23 and requests data from that sensor via the appropriate I/O scanner 20. This mode is referred to as "asynchronous" in that the access to the I/O scanner module 20 is on an "as needed" basis and not a periodic basis which is synchronized to the execution of the user program.
An alternative method of accessing the sensor input data from the I/O scanner modules 20 is in a synchronous, or periodic, fashion. At a given point within the execution of the user control program by one of the program execution processors 18, the input image table 210 from each I/O
scanner 20 is read and copied into the local memory 106 within the processor module 18. For ex~mple, just prior to the commencement of each pass through the user control program, the processor module 18 gains access to the back-plane 11 and interrogates each of the I/O scanner modules 20 copying each scanner's input image table 210 into the processor module memory 106. This ensures that the input data being used during the subsequent pass through the user ~ program will remain constant and that each rung will be :~.

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~ 3 evaluated using the same sensor status. The choice of which mode of operation to use is left to the operator/programmer and depends upon the characteristics of the particular function chart and user control programs being executed.
Unless otherwise specified by the operator, the system defaults into the asynchronous mode.
Referring particularly to Figures 2 and 8, the output image table 211 in each I/O scanner module 20 is updated immediately upon a change of the status of an actuator con-ted to one of the remote I/O racks for that module. Speci-fically, when the user's program calls for a change in status of a controlled actuator, the program execution pro-cessor 18 gains access to the I/O scanner module 20, as described above, and reads from the I/O scanner RAM 134 the output image table word that contains the bit or bits to be changed. Once the processor module 18 receives a copy of that output image table word, it changes the corresponding portion and writes the altered word back into the output image table 211 of the same scanner module 20. During this reading and writing of the I/O scanner module's RAM 134, the program execution processor module 18 retains control of the backplane buses 21-23 so that no other module may read or alter the output image table 211 of that scanner module 20 while the processor module 18 is performing its output func-tion. This ensures that the output image table 211 is notchanged or that another execution module uses stale data.
` It is, however, up to the user, through the control pro-`~ grams, to ensure that a given controlled device is only being activated or deactivated by one processor module 18 at a time.
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~ t Once a module has relinquished its control of the back-plane 11 another module in the system may access the back-plane. If more than one module seeks such access at the same time, the backplane arbitration circuit 84 in the sys-S tem controller 16 resolves the conflict. The arbitrationcircuit ~4 implements the rotating priority scheme described above whereby the highest priority level for backplane access passes from one module to the next in rack slot number order. Initially, the module in the leftmost rack slot has the highest priority and the priority level de-creases with each slot to the right. At this time, if a conflict exists between the modules in the second, fourth and sixth slots, the module in the second slot gains access. When a module is granted access, the priority lS levels shift one module slot to the right. Now the second module has the highest priority and the module in the first slot has the lowest priority. Then, if the modules in the first, third and eighth slots simultaneously seek access to the backplane 11, the third module gets access as it has the highest priority among the three. Then the eighth module has access and finally the first module is granted access the backplane 11. The priority keeps shifting whenever any one of the modules accesses the backplane 11. After the module in the last slot has had the highest priority level, the highest level rotates back to the module in the first, or leftmost, slot.
The system controller memory 69 may also be directly - addressed by other modules on the backplane 11 so that they may gain access to system data. During the execution of the user control program, the main functions performed by the ~ L~ 3 system controller 16 relate to the handling and execution of communications on the local area network 2~ and the pro-gramming terminal 24.
A module requiring data from the system controller S module 16 or an I/O scanner module 20 is able to access the main RAM's in these modules directly via the backplane 11.
However, when a module desires to send a block of data or a command to another module in the rack 12, a different tech-nique for communication between the two modules must be employed.

Inter-module Communication As indicated above, I/O data may be transferred direct-ly from one module on the backplane 11 to another module.
This direct transfer is possible when data is being read from or written to very specific memory data structures in the other module, such as an I/O image tables. However, in ; the present multiprocessor system, other forms of messages which do not reside in predefined data structures are often - conveyed between the modules. A more general purpose inter-module communication process is required for such mes-sages. This process is referred to herein as "sending mail".
Within each module that is capable of receiving mail is a set of mailboxes as illustrated in Figure 14. The set comprises sections for "priority" and "regular" mail. Each section has sixteen mailboxes, each consisting of a two word storage location. These sixteen mailboxes allow the ex-change of messages with modules in the eight slots of the main programmable controller rack 12 and with eight modules in an auxlliary rack (not shownl. Each of the mailboxes in .

_it~'J~ J ~ 3 each section corresponds to one of the slots in the two racks. During the configuration process, each module writes the address of the top of its mailbox set into the area of the system status file 201 (Fig. 7) which contains data for that module. The address of each module's mailbox interrupt is also stored in the system status portion 201 of the main system memory 69.
A "priority mail" message forms an urgent command which the recipient module is to immediately carry out. The com-mand is either executed within the mail handling task whichdetects the receipt of the command, or it is passed to a destination task for processing. The priority ~ail message consists of two sixteen bit words as shown in Figure 12a.
The first bit of the first word is a zero designating the message as priority mail. The next seven bit field (CMD) of the first word contains the coded form of the command to be executed which is selected from the following list:

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Command Code Command Description lH Mailbox Command Acknowledgment 2H Begin Function Chart Step Execution 3H Begin Interrupt Routine Execution 4H Change System Mode 5H Change Power Up Phase ~5 6H End Power Up 7H Halt Active System Operation The remaining bits of the first word are not be used by every command. The second word contains a pointer to a location within the recipient module local memory containing data for executing the command. For example, a priority mail message is sent by one program execution processor module 18 to inform another such module to commence the i ' , execution of a specific user program ~or a given function chart step. In this instance the command (CMD) in the first word is "2H" telling the recipient module to begin a new function chart step. The second word is an offset pointer for the table containing the address in the recipient's memory that contains information about the step and its control program. This information is passed to the function chart interpreter program in the recipient module.
Referring to Figures 12A and 14, in order to send mail the source module 230 first formula~es the two word message in its memory. Transfer of the message is controlled by a mail handling task within the module~ The priority mail transfer process is initiated by the source module 230 ac-cessing the system controller main RAM 69 via the backplane ll to obtain the addresses of the mail interrupt and the top of the mailbox set 233 in the recipient module 232. These addresses are stored in the system s~atus section 201 of the system controller's main ~AM 69 (Figure 7). The source module 230 knows the index from the top of the mailbox set 233 in order to access its mailbox slot in the recipient module. The mail handling task in the source module 230 ; then again seeks access to the backplane 11. When i~
receives access to the backplane ll, the source module 230 checks the first word of its priority mailbox in the recipient module memory 234. If the first word of the mailbox is non-zero indicating a previous message is still in the mailbox, the source module waits a period of time and tries again. When the first mailbox word is found to con-tain all zeroes, the source module 230 writes the two word message containing the command and address offset pointer ` -49-.
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. '. ~ ' ' J~tS'~3 into its slot in the recipient mailbox list and sends an interrupt word to the recipient module's mailbox interrupt address.
The mail handling task in the recipient module 232 in response to the interrupt reads the priority mail entry. If the entry is a command to start a new function chart step, an entry is made in the queue for the function chart inter-preter program. An acknowledgment is then returned to the source module 230 via an entry in its mailbox list and an interrupt. At this time ~he recipient module loads the source module's mailbox slot with zeroes preparing it to receive another message.
"Regular mail" typically is used for transferring more than two words of data, although command messages described above also may be sent to these mailbox slots. For example, regular mail is used during system start-up to send configu-ration data to each module. It is also used during normal operations to send messages that do not require immediate response or action. Still referring to Figure 14, when a source module 230 has several words of data to transfer, it assembles the data into a block 236 in its local memory 238. It then stores, in another block of memory 240, all the parameters necessary for the destination module to access the data in the source module's memory and acknowledge access to the source module 230. These parame-ters have a predefined format similar to that used in previous programmable controllers and include the address of the data message, its length, the destination module's task . , , ' .

., ~ . , .: . -~, .

which will use the data, and other information necessary totransfer the data.
The two word message is formulated in the source module's memory 238. The format of the message is shown in Figure 12B. The first bit of the first word is a one desig-nating this as a regular message. The next three bits are all zeroes indicating a data block type message as opposed to a command. The remaining twelve bits of the first word and all sixteen bits of the second word contain the beginning address of the transfer parameters within the ` source module.
The source module 230 then notifies its mail handling task to send the regular mail message. As with priority mail, the mail handling task accesses the backplane 11 and tests its regular mailbox slot in the recipient module's memory to make sure that it is empty. When the first word of the mailbox slot in the destination module ls all zeroes, the two word regular message is written into the slot. Once the mailbox slot in the recipient module is loaded, the interrupt word is sent to the recipient module's mail inter-rupt addesss.
The recipient module 232 upon being interrupted scans its mailboxes for the message. Unlike priority mail, the recipient module 23Z does not immediately process the re~u-lar mail, but places the mail entry in a queue for handlingwhen time permits. The handling of regular mail is a lower priority task as compared to the execution of the user ; control program. When the recipient module 232 has time available, it accesses the source module's memory 238 via the backplane 11 and reads the information in the parameter ~ L~ d'~
block 240. The recipient module then uses these parameters to copy the message data block 236 into its local memory 234 via the data acquisition process described above. After copying the data the recipient module 232 sends an acknow-ledgment via regular mail to the source module 230 andzeroes out the regular mailbox slot. The data then may be processed by the recipient module 232.
With an understanding as to how data and commands are sent between modules, the execution of the different types of programs can be described.

Program Formulation and Execution The present programmable controller may execute several general types of programs, such as machine operation pro-grams, independent background programs, interrupt subrou-tines and fault subroutines. The machine operation programsare developed by the user of the programmable controller to apply it to his particular machine or process. For very complex processes, the machine operation program is defined by a sequential function chart showing each major step of the process. A separate user control program is developed to perform the functions of each step. These user control `programs may be written in a ladder diagram language, as well as other high level languages supported by the pro-gramming terminal. Because the preferred embodiment exe-cutes compiled versions of the user control programs,assembly language and high level languages, such as BASIC, may be employed to generate the source code for the user control programO The user control programs are assigned for execution to the different processor modules 18. However, the present programmable controller provides the coordina-; -52-.
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tion of this parallel processing in accordance with the single machine operation program.
The independent background tasks are user programs that are subordinate in execution to control programs and may be used for lengthy non-time critical operations such as data acquisition from other computers and report generation.
Interrupt routines allow high priority operations to be executed upon the occurrence of a given event, while fault routines permit a graceful recovery from a detected error condition in either the programmable controller 10 or the equipment being controlled.
Each processor module 18 has its own operating system which runs completely independent of the other modules 18 in the system and which is unaffected by the processing of those other modules. Routines on the same processor module 18 share the resources of that module with the operating system deciding how much processing time is allocated to each one of the simultaneously running routines.
In order to provide orderly execution of the various types of programs by a processor module, a priority system is established. The highest priority level consists of various interrupt routines that are so time critical that their execution may never be interrupted. The next level includes all other interrupts which are normally run to ; 25 completion except when a top priority interrupt or fault occurs.
Interrupt routines comprise processor input interrupts and-selectable timed interrupts. Processor input interrupts ` are started by an externally generated input and are used for high priority routines which are intended to be executed .

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~ 3 only upon the occurrence of a specific input condition. To accommodate the processor input interrupts, each processor module 18 has an interrupt interface 99 (Figure 4) which receives and handles interrupt signals from external devices. Selectable timed interrupt routines are started at regular specified intervals by the system's real time clock. A priority is associated with each interrupt and if more than one interrupt is pending, the one with the higher priority will be executed first.
~he execution of the various other program types is carried out by grouping the programs and allocating a por-tion of the processing time to each group. A given amount of the execution time may be designated by the operator during system configuration for the execution of non-time critical operations; such as background tasks, handling of regular inter-module messages, communicating with other computers and miscellaneous tasks. These low priority oper-ations will be collectively referred to as "background tasks," although it is understood that background tasks are but one type of these operations. Typically, the operator may select 20, 30, 40 or 50 percent of the processing time of each processor module 18 for handling these tasks. The operating system will time-slice between the various opera-tions of this type during the time allocated for them. When the allocated time expires the processing of these tasks is suspended until the occurrence of another interval for their operation. In addition, if the processor module is not currently executing a control program, the entire processing time wiil be devoted-to the background tasks as necessary.

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The remaining processing time is allotted to the execu-tion of the machine operation program. As this task is usually time critical, the amount of time designated for background task processing generally is a function of how much time mus~ remain for the machine operation program.
The machine operation program continues running until a timed interrupt signals the start of a background task interval.
The present programmable controller provides an im-proved system for executing a machine operation controlprogram, therefore, this execution will be described in detail. A function chart program defines the overall control process as a sequence of steps and provides the mechanism for coordinating the simultaneous execution of lS different parts of a single machine operation program in parallel by multiple program execution processor modules.
As per convention each step is followed by a transition condition which specifies when the step is completed. A
separate user control program, such as a ladder program, is written for each step and transition of the function chart.
The machine operation program is written on the intelligent terminal 2~ or on a personal computer or host computer connected via the local area network 28. These devices contain the necessary software so that the programmer can author the function chart and the user control programs. The terminal or programming computer also compiles each user control program into machine language instructions for direct execution by one of the processor modules 18. If a ladder program is used as the control program, the technique for authoring it is the same as for _L~
conventional programmable controllers. The only difference is the compilation of the completed program.
The authoring of the function chart is different for the present programmable controller than for previous ones. The function chart is still graphically constructed on the screen of the programming terminal 24 or computer.
The software and techniques for doing this are similar to that practiced with conventional programmable controllers.
However, unlike previous controllers, the ~unction chart does not produce executable code but rather generates a set of files which may be thought of as directives that instruct the programmable controller which user control program to execute, when to do so and which processor module to use.
An example of a function chart is shown in Figure 10.
Each processing step of the function chart is designated by a rectangle such as box 403 and each transition from one step to another is designated by a horizontal line, such as line 402. The double rectangular box 400 designates the initial step of the function chart. As with function charts for previous programmable controllers, step 400 includes the name of a file in memory (e.g. FILE 1) that contains the user control program to be executed for that step. Unlike previous function charts, the box 400 also contains an indication (Pl, P2, etc.) of the processor module 18, that will execute the user control program for that particular function chart step. The present programmable controller 10 has two processor modules 18, which are designated Pl and P2, although additional processor modules may be inserted in the rack 12. The user control program for step 400 for example is executed by the first processor module Pl which repeatedly executes the control program until a programmed condition is met. That condition is represented by a trans-ition (such as at 402) immediately below the ~ox (400) in the function chart. Typically the transition 402 is defined by a single rung ladder program which i5 executed on the same processor module, e.g. Pl as the associated step. If this rung is found to be true, the execution of the user control program for step 400 ceases and the program execution advances to the next function chart step 403. The portion of the function chart in Fiyure 10 containing step 400, transition 402 and step 403 is typically referred to as a "sequence" construct in that each step sequentially fol-lows the other.
Following step 403 are three separate program branches, only one of which wlll be selected for execution depending upon the corresponding transition condition. This choice of one of many branches is referred to as a "selection" con-struct. The first branch includes an initial transition 404 that is defined by the user control program contalned in file 12 and processing step 407 defined by the user control program contained in file 3. Step 407 is followed by a ter-mination transition condition 410 that is contained in file 15. Similarly, the middle branch contains an initial tran-sition 405, a processing step 408 followed by a termination' transition 411. The third and final branch of the selection construct consists of initial transition 406, main process-ing step 409 and a termination transition 412. Following transition 412 is a GOTO statement which when executed causes the program to jump to the point where the designated label appears. In this case the program jumps to the label "BRAD" before step 419 at the bottom of the function chart.
All of the initial branch transition files 12, 13 and 14 are .

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' , stored on and are executed by the same processor module (Pl) as the previous ~unction chart step (403). It should be noted that since only one of the three branches Oe the sel-ection construct is executed, they all may be processed by a single processor module 18, in this case the first processor module Pl. Although, different branches could be designated for execution by different processor modules 18.
Upon the completion of the previous function chart step 403, which preceeds a selection construct, the conditions of the initial transitions 404-406 in each branch are sequenti-ally examined. The first initial transition which is found to be true determines which of the branches will then be executed. For example, if the condition defined by the user control program in file 13, transition 405, becomes true first then only the middle branch havlng step 408 will be executed. The completion of the control program for step 408 is indicated by the termination transition 411 contained in file 16. When that transition becomes true, the program transfers to step 413 contained in file 6 which is executed on the second processor P2.
Once step 413 is completed as indicated by transition 414 the function chart enters what is referred to herein as ; a "simultaneous" construct. A simultaneous construct com-prises a plurality of function chart branches each contain-ing at least one step. As the name implies the branches are executed simultaneously. In this case three processor steps ` 415-417 are to be executed in unison. The first step 415 comprises the user control program stored in file 7 which is to be executed on the first processor module Pl. The program for the second branch step 416 is contained in file 8 and is to be executed on the first execution module Pl, ` '. '. ' . ~
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while the third branch step 417 which is represented by the control programs in file 9 is assigned to the second processor P2. Because files 7 and ~ are both assigned for execution by the first processor module Pl, the user control program contained in each of the files will be concatenated (i.e. strung together to run sequentially). This con-catenation is similar to that practiced in present program-mable controllers. However, whereas previous programmable controllers would have to concatenate all of the simultane-ous construct files, including file 9, the present systemhas assigned file g for execution by the second processor module P2 and the remaining two files 7 and 8 for execution by the first processor Pl. If the programmable controller 10 contained three separate processor modules 18, the func-lS tion chart step for each branch could be assigned for execu-tion by a separate one of the modules.
; As an example, the simultaneous construct portion of the function diagram in Figure 10 could control a manufac-turing process where the user control program in file 7 controls the manufacturing process by reading various sen-sors and in response thereto activates or deactivates vari-ous pieces of production equipment. File 8 may consist of a control program that displays on the terminal 24 the status of the process beinq controlled by the program in File 7.
In this case, the user control program in File 9 may monitor other sensors and activate alarms should any o~ these , sensors indicate that given manufacturing errors have occurred.
` The transition out of the simultaneous construct sec-~` 30 tion is indicated by what is referred to herein as a "con-verge" construct. This construct contains a single transi-, tion step 418 in which the user control program in file 19 is executed on the second processor module P2 following each scan of the user control program in file 9. When the transition 418 is true, the execution of each branch of the simultaneous construct ceases at the end of their current program scan. As noted above with respect to the data structure of the system controller 16 in Figure 7, the system support file 203 contains a memory area for the step counters of the simultaneous portions of the function diagram. One of these counters is loaded upon entry into the simultaneous section with the number of simultaneous processin~ steps in the construct. After the transition condition 418 is satisfied, this counter is decremented as each step 415-417 completes its program scan and comes to a halt. When the counter reaches zero, all of the simul-taneous steps are completed and the transition to the next step 419 following the converge construct can occur.
In prior art systems, the three function chart steps 415-417 ~Figure 10), which were simultaneously executed, had to be concatenated for execution by a single processor and the execution of a given user control program occurred only once per pass throu~h all three programs. Therefore, with respect to the above example if the control program in File 9 was an alarm function, it would only be scanned at the completion of the scan of the user control programs in Files 7 and 8. Whereas in the present multiple processor system which utilizes parallel processing, the `user control program for the alarm function is repeatedly processed by its own processor module P2 without the intervention of other user control programs being concatenated with it. This provides .

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more frequent monitoring of time-critical conditions than is possible in a single processor system.
The graphical representation of the function chart per se is not executed by the programmable controller. It is used, however, by the programming terminal software to as-semble a set of data files for each of the processor modules 18. Specifically, the function chart is reduced to a series of descriptor files that describe the operations of a por-tion of the function chart. Each descriptor contains data which identifies the user control program for a step in the function chart, data which identifies the termination trans-ition, and data which identifies the descriptor (and its processor module) that is to execute the next section of the function chart. These descriptor files are stored in the processor module 18 designated in the function chart. The function chart interpfeter software in each processor module 18 uses the respective descriptor files to control the exe-cution of each user program.
By way of example with reference to the exemplary func-tion chart of Figure 10, a master descriptor file table isgenerated by the programming terminal 24 as shown in Figure llA. The descriptors fall into four distinct catagorie~
which correspond to the function chart construct (i.e. se-quence, selection, simultaneous, and converge) that gener-ated the descriptor. Referring to Figures 10 and llA thefirst descriptor 430 represent~ the sequence portion of the function chart, and its contents are displayed on the right side of Figure llA. The first word of the descriptor con-tains several bits, T, which indicate the type of the des-criptor file, in this case a sequence type. The remainingportion of the first word identifies the number of the file :

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that contains the user control program to be executed for the corresponding function chart step. In this e:~ample, function chart step 400 contains the user control program in file 1 for the first processor module Pl. The first S descriptor 430 also contains the number of the transition file which specifies the condition that is to occur before the execution of the user control program should terminate. File 11 is the transition file number in the first descriptor 430 as specified at point 402 in the function chartO The descriptor 430 also identifies the next descriptor file to be used upon the completion of the current descriptor file and the processor module 18 in which it is stored. In this example the first descriptor 430 designates "Descriptor 2" as the next descriptor file which is assigned for execution by the first processor module Pl.
The second descriptor file 432 on Figure llA is gener-ated from the selection construct of the function chart in Figure 10. The first word in the second descriptor 432 indicates that it is a selection type and that file number 2 contains the user control program for this step. The remainder of the descriptor 2 contains an array of tran-sitions and their corresponding next decriptor file number and processor. For example, as shown in the function chart of Figure lO, the first element of the array indicates tran-sition file 12 and its next descriptor is de~criptor 3; thesecond element of the array indicates transition file 13 and descriptor 4; and the final entry in the array indicates transition file 14 followed by the next descriptor 5.
The descriptors for the three selection branches (descriptors 3, 4, and 5) are of the sequence type and have the same format as the first descriptor 430. The sixth descriptor is designated as the next descriptor file number in both descriptors 3 and 4. ~o~ever, the next descriptor file number in the descriptor 5 for the third selection branch is the tenth descriptor for step 419 because of the GOTO statement in the function chart.
The next type of descriptor is represented by the sixth descriptor 434 in Figure llA, which is produced from the simultaneous construct of the Figure 10 function chart. The sixth descriptor 434 contains information regarding its type, the control program file number and a single transition condition file to be executed. This descriptor 434 also contains an array of the next descriptor files which indicate the descriptors for each of the simultaneous construct branches, in this example branch steps 415-417.
Each of these next descriptors is executed by its designated processor module 18 when the transition condition occurs.
The final type of descriptor file is a converge des-criptor which controls the execution of each simultaneously executing branch, for example, steps 415-417 of the func-tion chart in Figure 10. A converge descriptor is generatedfor each branch. The branch steps 415, 416 and 417 are represented by descriptors 7, 8 and 9 in Figure llA. All of the converge descriptor files, as shown by descriptors ~35 and 436, contain a word having several bits (T) designating ~S its type and the number of the file containing the user control program for the function chart step. Bach converge descriptor file also contains a pointer to the simultaneous counter address in the system support file 203 within the memory of the system controller module 16. As will become apparent in the course of the description of the function -~3-'' chart interpreter software relating to the converge portion, the simultaneous counter is used to determine when all o~
the simultaneous branches have completed their execution.
All of the converge branch descriptor files also contain the number of the next descriptor file to be executed and the processor module containing it. The converge descriptor file for the rightmost branch, in this case the ninth converge descriptor 436, also identifies the file containing the transition condition upon the o~currence of which the simultaneous execution terminates.
Once all of the individual descriptors are assembled by the programming terminal 24, they are sorted into groups ac-cording to the particular processor module Pl or P2 that has been assigned to interpret them. The various user control programs which are specified in the descriptors are similar-ly sorted by processor module. The descriptor data and user control program files are then transferred by the program-ming terminal 24 into the proper processor module 18 in the programmable controller 10. For example, the function chart descriptors 1-5, 7 and 10 and the user control programs in files 1-5, 7, 10-17 and 20 are assembled into a single data ` structure, as shown in Figure llB. This data structure is downloaded into the program memory area 313 of the first - program execution processor module Pl~ The descriptors and user control program files for the remaining steps and transitions are assembled into another data structure as shown in Figure llC for the second processor module P2.
Once the sorted files have been downloaded into the respective processor modules 18, the programmable controller 10 is placed in the "run" mode. Each processor module 18 contains a function chart interpreter program which inter-, .
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prets the descriptors stored in its R~M 106 and executes the user control programs called for by the descriptors. ~hen the execution of a machine operation step terminates, such as when the transition condition is satisfied, the inter-preter program may commence interpretation of the next des-criptor file or notify another processor module 18 that contains the next descriptor to begin interpreting it. As required by the descriptors, one or more processor modules can execute different portions of the machine operation program simultaneously.
Figures 16-19 illustrate flow charts of the program which enables each processor module 18 (Figure 4) to inter-pret and process the various types of descriptors. The processing begins at step 590 at the top of Figure 16 with the microprocessor 98 inspecting a list of active descriptor file numbers stored in RAM 106. This active list contains a designation of each descrptor file that is currently being interpreted by the processor module 18. If there are no descriptors listed, the processor module enters a dormant state at step 609 where it remains until it receives a processing command. If the list contains an entry, the top descriptor is gotten off the active list at step 592 and the remaining entries, if any, are moved up in the list. The microprocessor 98 then evaluates the bits which indicate the type of the descriptor. Based ~pon the type of descriptor, the program at step 600 branches to one of four sections depending upon whether the descriptor is a select, simul-taneous, sequence or converge type descriptor. As will be elaborated upon, there are several types of converge descriptors which are evaluated at branch step 607 before ~ 3 branching further to the specific routine for that converge type.
The remaining portion of Figure 16 is a flow chart for the execution of a sequence type descriptor file ~hich will be described with reference to the first descriptor file 430 in Figure llA. This branch routine commences with the pro-cessor module Pl at step 601 making one execution pass through the user control program specified by the step file number within the descriptor. At the completion of one pass through the user control program the file containing the transition condition indicated in the descriptor file is executed at decision block 602. If the condition has not happened, the descriptor is returned to the bottom of the active list in the processor RAM 106 at step 606. The lS program then returns to step 590 to get the next descriptor from the active list. If only one descrip~or is on the active list, the same user control pro~ram will be immedi-ately executed again. This loop continues until the transi-tion condition has occurred. At this point, step 603, the microprocessor 98 interprets the information within the first descriptor 430 relating to the next descriptor file to determine which program execution processor 18 contains the next descriptor to be interpreted. If the same processor module (Pl) is to execute the next descriptor, that descrip-` 25 tor file is obtained from RAM 106 at program step 604 and placed in the active list at step 605. The program returns to step 590 for the microprocessor to check the active list to obtain the next descriptor for processing.
If the next descriptor file is contained in the memory of another pxocessor module 18, a command is sent at step 608 to that processor module via priority mail as descrlbed .

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above. The command instructs the other processor module to begin interpreting the next descriptor. Once the informa-tion regarding the next descriptor has been transmitted to and acknowledged by the other processor module 18, the pre-viously active processor module 18 goes into a dormant stateat point 609 unless other descriptors remain on the active list. In this dormant state a processor module 18 may exe-cute background and other low priority tasks as will be described.
In the exemplary function chart of Figure 10, the sel-ection construct is processed next by the first processor module Pl. As the second descriptor 432 is a selection type the program branches to the routine show in Figure 17. With reference also to the schematic of the processor module in Figure 4, the microprocessor 98 at the first step 610 of the routine determines the number of elements in the array of transition condition files. An array pointer address in RAM
106 is set at step 611 to the first element in the transition condition array. The user control program designated by the step file number in the descriptor 432 is then executed by the processor module P2 at point 612.
At the completion of one scan through the user control program, the transition condition contained within the file specified by the first element of the array is evaluated by the microprocessor 98 at step 613 to determine if the con-dition is met. If the transition has not occurred, the address contained in the array pointer is checked at de-cision block 614 to determine whether it is pointing to the address in RAM 106 containing the last element of the ar-ray. Since it is not the last element, the array pointer is incremented at step 615 and the program returns to decision ' _L~ 3 block 613. The transition condition designated by the next array element is checked at decision block 613. Assuming that none of the transition conditions specified in the array has occurred, this loop continues until the last transition condition in the array has been tested. At this point the execution of decision block 614 indicates that the array pointer is at the address of the last array element and the program advances to step 621 where the descriptor is returned to the bottom of the active list. The processor module program execution then returns to step 590 (Figure 16) to process the descriptor at the top of the active list.
! The user control program for the select descriptor ` continues to be executed until such time a~ one of the tran-sition conditions in the descriptor array has occurred. At lS which point in time, this transition condition is found to have been met at step 613 and the program branches to step 616. The microprocessor 98 at step 616 reads the array field pointed to by the array pointer which specifies the file number and location of the next descriptor to be pro-cessed. At step 617 the next descriptor specification is evaluated. If the next descriptor is stored on the same processor module 18 as the current descriptor, the micropro-cessor 98 will read the descriptor file from its RAM 106 at process block 618. The program adds the new descriptor to ~` 25 the active list at step 620 and returns to step 590 in Figure 16 to process the next descriptor file.
` If the next descriptor is stored in the RAM of another processor module 18 for execution, the program will ~ranch from decision block 617 to step 619 where the current pro-cessor module Pl sends a command message by priority mail to the other processor module 18 specifying that it is to "wake up" and begin processing the next descriptor. This rnessage specifies the file number containing the next descriptor.
Upon receiving acknowledgment of the command message, if the active list is empty, the current processor module Pl enters a dormant state at step 609 until it is notified by another - module 18 that it is to resume processing another descrip-tor.
Referring to the exemplary function chart of Figure 10, each of the selection branches is represented by a separate sequential type descriptor, the third, fourth and fifth descriptors in Figure llA. The transition from whichever one of the selection branches was chosen to the next step 413 is a standard sequential type transition. Specifically, if step 408 was selected for execution, the user control program contained in file 4 will be repeatedly executed until the transition condition 411 contained in file 16 occurs. At this point the program execution transfers to function chart step 413. This transfer will be accomplished by the first processor module Pl sending a priority mail message to the second processor module P2 indicating that it is to commence execution of the sixth descriptor 434 (Figure llA).
The second processor module P2 contains a copy of the function chart interpreter program in its local RAM 106.
Upon receiving the command message from the first processor module Pl, the second processor P2 adds the sixth descriptor 434 to its active list. If the second processor module P2 was in the dormant state, it wakes up entering its interpreter program at step 590 (Figure 16). When the second processor module P2 begins execution of the sixth descriptor 434, its function chart interpreter program will :
`` -69 , , v determine at step 600 (Fig. 16) that this descriptor is a simultaneous construct type and the program will transfer to the routine indicated by the 1OW chart of Figure 18. The first program step 630 in the interpretation of the simultaneous descriptor is the determination of the number of elements in the array of next descriptors which indicates - the number of simultaneous function chart steps to be performed. The contents of array pointer address in RAM 106 is then set to the address of the first element at process block 631. The user control program contained in file 6, is then executed by the second processor module P2 at step 632. At the completion of one scan of the user control program, the occurrence of the transition condition 414 con-tained in file 18 is tested at decision block 633. If the condition has not occurred, the descriptor is returned to the bottom of the active list so that the user control program will be executed again.
When thè transition condition 414 has occurred, the processing transfers to commence the execution of the vari-ous function chart branches. The first element in the array of next descriptors, descriptor 434, is read from RAM 106 by the microprocessor 98 at block 634 and the processor module 18 for that next descriptor is then determined at block 635. If the module is the same as the current one, the next descriptor file is read from RAM 106 at point 636 and in step 637 i9 added to the processor module's active descrip-tor list with any other user control programs to be simul-taneously executed on this processor module.
If one of the next descriptors is to be executed on another processor module (e.g. Pl), the descriptor interpre-tor program~branches from dec~ision block 635 to step 639 'L~
where the current processor module P2 transmits a co~nand via a priority mail message to that to that other module.
The command instructs the other processor module to begin interpreting the descriptor file stored in it. The program then returns to decision block 641 where the microprocessor 98 in the first processor module Pl determines whether the last array element has been processed. If additional elements remain, the contents of the array pointer address are incremented by the microprocessor 98 at step 642 and the next descriptor file number is read from the array at step 634.
This process of evaluating each of the next descriptors continues for each element in the array. Once the last element has been processed by the currently operative pro-cessor module P2 at block 641, the program returns to step 590 to check the active descriptor list for more work.
In the exemplary function chart depicted in Figure 10, the three simultaneous branches, steps 415-417, terminate in a converge construct. The converge construct contains a single transition condition 418 upon the occurrence of which the execution of all the branches ceases. Each branch is represented by a separate descriptor (Descriptors 7-9) stored in the RAM 106 of the processor module Pl or P2 which is designated by the user to perform respective step of the function chart. Descriptors 7 and 8 are stored in processor Pl for execution and the ninth descriptor is assigned to the second processor P2. One of the descriptors, in this - example the ninth one 436 (Fig. llA) contains the transition condition and the next descriptor file number~
The operation of the second processor module P2 will be initially described before discussing the simultaneous oper-.

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ation of the first processor module Pl. The ninth descript-or 435 is stored in the second processor module P2. The interpretation of the ninth descriptor 436 begins on at itep 600 Fiqure 16 -~ith the processor module's microprocessor 9 reading the descriptor from the active list and evaluating its type. For a converge type descriptor the program advances to step 607 where a branching occurs depending upon the particular type of converge descriptor as determined by the microprocessor 98. In this case the converge descriptor contains the transition condition file number and the pro-gram advances to node D of the routine shown in Figure l9.
This converge descriptor interpreter routine begins at block 660 by the microprocessor 98 setting a pointer to the address of the simultaneous counter contained within the system support file 203 of the system controller's main RA~
69 (Figure 7). The first time through the converge routine for a given descriptor the microprocessor 98 at step 661 loads the simultaneous counter address with the number of simultaneous branches being executed, in this case three.
The second processor module P2 then begins execution of the user control program from file 9 at process block 662. At the completion of one pass through the user control program, the microprocessor 98 executes the program in the transition condition file specified in the ninth descriptor file 436.
If this transition condition has not occurred, the program returns the descriptor to the active list and then goes to step 590 (Figure 16).
However, if the transition condition has occurred, the second processor module P2 at step 664 sets a flag in the system controller RAM 69 indicating the end of the simul-taneous execution. While the second module P2 has access to .. ~ .

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the system controller RAM 69, it decrements the simultaneous counter at step 665 indicating that the processing of its simultaneous branch has been completed. Next at step 666, an evaluation of the counter is made by the second processor module P2 to determine if the counter has reached zero. If the count is not zero the program returns to step 590 ; (Figure 16) to see if other descriptors remain to process.
As none are left for the second processor module P2, it enters the dormant state in step 609.
10If all of the simultaneous execution is completed, the second processor module P2 at step 667 examines which processor module is to execute the next descriptor. If the second processor module P2 is to begin executing the next ; descriptor file, its microprocessor 98 at process block 668 lS reads the next descriptor and adds it to the active list at step 670. Then the program returns to step 590 at the beginning of the routine in Figure 16 ~here it processes the new descriptor. If the next descriptor is to be handled by another processor module (e.g. Pl), the routine branches to step 669. The second~module P2 sends a priority mail mes-sage to that other module Pl informing it to begin executing J
the next descriptor. Then the second processor module P2 enters the dormant state at step 609.
As previously stated, there are several types of con-verge descriptors. The descriptors for the branch con-taining function chart steps 415 and 416 (Figure 10) do not contain any information regarding the transition condition (see the eighth descriptor 435 of Figure llA). These descriptors are stored and interpreted on the first processor module Pl. When these descriptors are evaluated by the microprocessor 98 at step 607 of Figure 16, the _L~
interpreter pro~ram in the respective processor module 18 branches to node E of the routine illustrated in Figure 1~. In this routine an address pointer is set at block 680 to the simultaneous counter address in the system controller main RAM 69. The user control program is then executed by the microprocessor 98 at step 681. After each the control program scan, the end flag address in the system controller main RAM 69 is checked to determine whether or not it has been set, thereby indicating that the user control program processing is to terminate. If the flag is not set, the descriptor is returned to that processor's active list at step 683. If the flag is set, the simultaneous counter is decremented twice at step 665 to indicate that the execution of files 7 and 8 by this processor module Pl is ceasing.
;` 15 The first module Pl then at step 666 checks the simultaneous counter and proceeds as previously described with respect to steps 666-670.
As noted above, in addition to the function chart and `~ user control programs the user also may define "background tasks" for a specific processor module 18 to process. These programs are used to perform lengthy non-time critical tasks without an adverse delay in the operation of the function chart control program. User defined background tasks in-clude report generation and certain subordinate control tasks. Report data regarding the performance of controlled ; equipment may be prepared for transmlssion via LAN 28 to a host computer. Such reports are not so urgent that the control of the equipment must be suspended while they are prepared and sent. The background control tasks also are used for lengthy calculations which are similar to those , ~``

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found in the main function chart program, but which are not required for real time control.
; A background task program may be invoked from a user control program, an interrupt routine such as a selectable timed interrupt, or from another background program. A
percentage of the processing time for each processor module 18 has been allocated to performing these background tasks. This percentage is set by the user so that the execution of background tasks do not significantly affect the execution of the machine operation program. Periodi-cally the processing of the user control program is interrupted by the real time clock and the background tasks are performed for a given interval of time. If the end of the background task execution period occurs before the completion of the background program, the execution of the background task will be suspended and resumed during the next background task interval. When a user control program is not being run on the processor module 18, the background task may run almost continuously. In normal operation the background tasks will run intermittently to co~pletion, however, their execution may be aborted by the user control program or upon the occurrence of an error condition.
Because the present programmable controller system has multiple processor modules 18, no single processor is con-stantly devoted to running the user control programs. Thisresults in time being available for the processor modules to perform background tasks, without such tasks adversely af-fecting the control of the manufacturing equipment. This is i yet another benefit of the present parallel processing con-` 30 cept as applied to programmable controllers.

The present programmable controller 10 also provides a two mode power loss recovery mechanism. This recovery mechanism is activated whenever power is lost during the execution of the machine operation program, such as due to an electric power outage. The operator may select during system configurations whether, when power is restored after such a loss, the program restarts at the beginning ~i.e. the initial function chart step~ or resumes execution at the start of the user control program that was being executed when the power failed. The operator's selection of the recovery mode is stored in the system status file 201 in the system controller's main R~M 69.
With reference to Figure 3, the system status circuit 88 detects the power beginning to fail and interrupts the processor section's microprocessor 66. This causes the ; microprocessor to execute on interrupt subroutine which stores the state of each processor module's execution in a non-volatile memory. This state data includes the file numbers of the descriptors currently being executed and the descriptors on each processor module's active descriptor list. Information regarding any background tasks being executed is also saved.
When power is restored, if the resume mode is selected, the system controller notifies each processor module to begin execution with the descriptor file number that was stored when the power failed. As noted above, the major modules in the system have internal batteries to keep their respective memories alive when the power is shut off.
Therefore, the programs and I~0 tables remain stored in the modules' memories during the power outage.

,: .

Claims (21)

1. A programmable controller for operating a machine to carry out a plurality of programmed functions, which comprises:
a plurality of processor means each capable of being simultaneously operable to execute a separate user control program that directs the programmable controller to operate the machine to perform a specific function, each of said processor means capable of receiving communications from the other processor means to control the execution of its user control program;
a means for storing a plurality of user control programs, each user program designated for execution on one of the processor means; and means for interconnecting said plurality of processor means and said storing means.

2. The programmable controller as recited in claim 1 further comprising a system controller for supervising the interaction of said plurality of processing means and said means for storing.

3. The programmable controller as recited in claim 2 wherein said system controller comprises means for interfacing the programmable controller with other computer systems.

4. The programmable controller as recited in claim 2 wherein said system controller comprises a memory for stor-ing system configuration data.

5. The programmable controller as in claim 2 wherein said system controller comprises an arbitation means for resolving conflicts when two or more processing means seek access to said interconnecting means at the same time, said arbitration means assigning a priority level to each said processing means and periodically changing the priority assignments.

6. The programmable controller as in claim 1 further comprising an arbitration means for resolving conflicts when two or more processing means seek access to said intercon-necting means at the same time, said arbitration means as-signing a priority level to each said processing means and periodically changing the priority assignments.

7. The programmable controller as recited in claim 1 wherein each of said processor means includes:
a microprocessor;
a floating point arithmetic co-processor; and a Boulean logic co-processor for executing a set of instuctions of the user control programs.

8. The programmable controller is recited in claim 1 further comprising an I/O circuit for interfacing the programmable controller with external I/O devices.

9. The programmable controller as recited in claim 8 wherein said I/O circuit includes a memory for storing data regarding the state of the I/O devices, which memory being accessible by said plurality of processor means.

10. A programmable controller for operating a machine to carry out a plurality of programmed functions, which comprises:
a backplane having leads for conducting data signals, leads for conducting address signals and leads for conducting control signals;
a plurality of processing means connected to said backplane, each processor means being operable to simultaneously execute different programs;
means coupled to said backplane for storing a plurality of programs for said processor means;
an I/O interface means connected to said backplane for coupling the programmable controller to external I/O
devices, said interface means having a first memory for storing data regarding the state of the I/O devices;
a system controller for supervising the access to said backplane by said plurality of processing means, including means for arbitrating among different ones of said plurality of processor means which are seeking access to the backplane.

11. The programmable controller as recited in claim 10 wherein each of said processing means is contained in a separate module; and said means for storing is divided into a plurality of segments with one of said segments being contained within each of the modules, each memory segment storing the programs that are to be executed by the proces-sing means contained within the same module.

12. The programmable controller as recited in claim 10 wherein said means for storing comprises a program memory divided into a plurality of segments, one of said segments being associated with a different one of said processing means for storing the programs that are to be executed by that processing means.

13. The programmable controller as recited in claim 10 further comprising means for each processing means to directly access the first memory of said I/O interface means to obtain data related to the state of the external I/O
devices as such data is needed by the execution of a program.

14. The programmable controller as recited in claim 10 wherein each of said processing means further comprises means for directly accessing said I/O interface means first memory at regular intervals to obtain data related to the state of the external I/O devices.

15. The programmable controller as recited in claim 10 wherein said interfacing means includes a means for said processing means to access said interfacing means first memory without affecting the interfacing means gathering data from the external I/O devices.

16. The programmable controller as recited in claim 10 wherein said I/O interface means further includes means for enabling each of said processor means to directly address the I/O interface means first memory in order to access the data stored therein.

17. The programmable controller as recited in claim 10 wherein said I/O interface means further includes:
means for coupling the I/O interface means first memory to said backplane;
a communication section for controlling the exchange of data with said I/O devices; and means for coupling said communication section to the first memory of the I/O interface means.

18. The programmable controller as recited in claim 10 wherein each of said processor means includes a plurality of processors each for executing a separate set of program instructions.

19. The programmable controller as in claim 10 wherein said interfacing means comprises:
a section for controlling communication with said sens-ing devices and actuators, this section including a second memory for storing the communicated data;
means for exchanging data between said first and second memories; and mean for interfacing said processing means to said first memory for the storage and retrieval of data.

20. A programmable controller for operating a machine comprising:
a plurality of processor means each capable of simul-taneously executing a separate program;
a plurality of means for storing a plurality of pro-grams, each of said means for storing coupled to a different one of said processor means;
means for interfacing the programmable controller to sensor and actuator devices on the machine, said interfacing means having a first memory for storing the state of the sensor and actuator devices, the state of the actuator devices being set in response to at least one of said processor means; and means for responsing to requests from said plurality of processor means to interconnect one of said processor means to said interfacing means.

21. The programmable controller as recited in claim 20 wherein said means for interfacing includes:
a communication section for receiving data from to the sensor devices and data to the actuator devices, said com-munication section having a second memory for storing the data received from or to be sent to the sensor and actuator devices;
means for connecting the first and second memories together to enable the exchange of data between the two memories; and means for coupling the first memory to the means for interconnecting so that data may be exchanged with said pro-cessor means.