CA1305759C

CA1305759C - Rapid signal validity checking apparatus

Info

Publication number: CA1305759C
Application number: CA000586882A
Authority: CA
Inventors: Alfred R. Koelle; Donald F. Speirs; Peter L. Hendrick
Original assignee: Amtech Tech Corp
Current assignee: TC License Ltd
Priority date: 1988-01-28
Filing date: 1988-12-22
Publication date: 1992-07-28
Anticipated expiration: 2009-07-28
Also published as: NO890362L; NO174442B; ES2059536T3; EP0325837A3; KR890012236A; JP2740230B2; NO174442C; KR0133293B1; HK143496A; US4864158A; AU2633488A; AU605077B2; JPH01224685A; NO890362D0; DE3850090D1; EP0325837A2; EP0325837B1; IL88623A0; IL88623A

Abstract

RAPID SIGNAL VALIDITY CHECKING APPARATUS

ABSTRACT
This invention relates to an improved signal reader for reading signals from transponders placed on moveable objects such as ship containars, automobiles or railroad cars.
The reader sends out a continuous signal, which is modified by The information contained in the transponder attached to the moveable object. Multiple antennas, each of which receive separate signals, may be multiplexed at the reader. The improved circuit of the invention provides quick recognition of the receipt of a valid signal from a transponder or, in the alternative, the absence of such a valid signal. The circuit of the invention first provides a detection pulse stream. Each pulse of the detection pulse stream coincides in time with an expected edge of the predetermined pulse stream reflected back to the reader from the transponder. A detection circuit is connected to receive the detection pulse stream at the same time it receives signals lo be evaluated. The detection circuit detects the presence of pulse edges which are coincident with the pulses from the detection pulse stream, and provides a detection output signal in the event of such coincidence. A counter counts the number of detection output signals from the detection circuit and provides a validity signal depending upon the number of detection output signals received for a given number of detection pulses. A preferred embodiment of the invention also detects the number of background noise pulses when there are no pulses from the detection pulse stream. These coincidences indicate the receipt of invalid data, and are subtracted in the counter as an invalidity signal. The apparatus of the invention is thus capable of rapidly separating valid pulse streams from invalid ones and providing a validity or invalidity signal which may be used to control the multiplexing of a reader from one antenna to another.

Description

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BACRGROUWD OF THE INVENTION

This invention relates to systems for identifying objects on a remote basis~ The system includes a reader for providing a simple and reliable identification of an objec~
which is a considerable distance away by de~ecting a unique sequence o signal cycles identifying the object.
As commerce becomes increasingly complex, the volume of moving articles and vehicles reguiring individual identification increases. For example, containers holding goods are stacked on merchant ships. When the merchant ships .
reach a destination port~ only a portion of the containers need : :

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1 to be unloaded, the remaining ones staying on the ship for subsequent destination ports. It i5 thus desirable to identify the containers remotely, as they are being loaded or unloaded.
Systems of this nature have been developed. Such systems include a reader, displaced from the ohjec~, for transmitting a signal which interrogates an electronic transponder tag on the object. The tag has an identifying code which is unique to the object being interrogated. This code is represented by a sequence of binary l's and O's. Each binary 1 and 0 in this sequence is converted to a plurality of signal cycles having a predetermined periodicity which are transmitted to the reader. The signal cycles in each plurality are made up of portions having two different frequencies in a particular pattern, one pattern to identify a binary "1" and another pattern to identify a binary "0". The antenna at the reader picks up a signal reflected from the transponder at the ob}ect which contains the unique signals from the object.
In some applications, systems of this type employ a single reader to read multiplexed signals from several 20 antennas. For example, it is sometimes desirable to read data from electronic tags on passing railroad cars. These cars often have transponder tags only on one side of the car.
However, since railroad cars commonly get turned around, one never knows on which side of the track the tag will be.
Therefore on~ m~st have an antenna on both sides of the track.

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l ~ne simple solution, of course, would be to have two antennas and two readers, one on each side of the track.
Alternatively, of course, one can put tags on both sides of the railroad car. ~oth of these are obviously wasteful solutions.
A better solution is to have a single tag on each car with .
antennas on opposite sides of the track, both multiplexed to a single reader.
The difficul~y with this solution is that the multiplexing of the two antenna inputs to a single reader must lo be extremely fast. The reader must be able to determine quickly that there is no signal from one antenna, and still have time to check the antenna on the other side of the rapidly passing railroad car for a signal from a tag on the opposite side. ..
With the readers which were available prior to this invention, the only way the presence or absence Qf a tag signal could be ascertained was to completely read all of the information containe~ in the tag and make computations to see if it was valid information. If invalid, the reader became free to be switched to another antenna. If this technique were employed with fast-moving railroad cars, it is likely that by the time the computer ascertained that here was no taq present on one side, and switched to receive signals from the ante~na o~ the opposite side of the car, the tag, if any, on the second side would have passed beyond the antenna's range.

1 These same systems are also used to ide~tify automobiles in ~oll booth lanes for automa~ic toll collection.
Where a single reader is to be multiplexed to several antennas in several lanes approaching ~he toll booth, if the absence of a car cannot be detected quickly, more readers must be used for fewer lanes, perhaps even one reader for each lane, BRIEF DESCRIPTION OF THE INVENTION

lo The system of the invention provides a means for quickly detecting the presence or absence of a predetermined transmitted signal without the necessity of reading and validating the entire signal, as has been required in the past. The signals transmitted to the readers of the type employed in this invention are described in United states Patent No. 4,739,328, filed July 14, 1986, en~itled System for Identifying Particular Objects and assigned to the same assignee as this invention. They have a predetermined periodicity. The circuit of this invention takes advantage of 2 that predetermined periodicity to provide early validation of signal receipt based upon the receipt of only a limited number of s~gnal pulses, normally far fewer than the entire signal.
Briefly, th~ circuit of the invention first provides a detection pulse stream. Each pulse of the detection pulse stream coincides with or overlaps an expected or possible puise ~ 5~

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1 edge of the predetermined transmitted pulse stream received at an antenna. The predetermined pulse stream is fed into a detector designed to detect the presence of the expected pulse edge coincident with the duration of a pulse from the detection pulse stream. The detector provides an output signal in the event that such coincidence is detected, and~ in a preferred embodiment, will also provide an output signal if a pulse edge from the transmitted pulse stream is detected during the period between pulses of the detection pulse stream when it should not lo be there.
Finally, a counter is incremented for each valid signal detected during a given number o detection pulses, the count reaching a predetermined number to indicate acknowledgment of the receipt of a valid signal. In a preferred embodimenti the counter also will be decremented for each invalid pulse received, providing a validity signal indicative of the net of valid less invalid pulses.
The absence of a validity signal can be used to trigger or validate the switching or multiplexing of a reader from one antenna to the next. Typicall~, the reader is multiplexed to the next antenna when no valid signal is received from the first antenna. This provides the ability to have 4ewer readers for more antennas.
In a preferred embodiment of the invention, two 25 detectors are provided, one out of phase with the other. The .

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1 reason for this is that the predetermined pulse stream has pulses with a given periodicity, with the pulses midway in between the regular pulses appearing only in if the signal is a transition from a 1 to a 0 or vice versa, for the coding format employed. Accordingly, the in-between pulses are data-related and do not necessarily appear at every in-between cycle. For the most rapid detection, therefore, two detectors are used, one out-of-phase with the other. One of the two (you do not need to know which one) will pic~ up the regular pulse stream; the other one, out-of-phase with the first, will pick up the data pulse stream. Normally the one pic~ing up the regular pulse stream will count faster since it detects pulses every cycle compared with the other which only detects pulses in the event of certain data patterns.
lS The outputs from these two detection circuits are counted and can be compared, with the higher one being used as the validity signal. This allows validity to be ascertained in the fastest manner~
Accordingly, in one of its aspects the invention provides for a circuit for early detection of a predetermined pulse stream having a given periodicity, comprising means for providing a detection pulse stream wherein the width of the pulses include the expected edges of said predetermined pulse stream; first and second detecting means connected to receive said predetermined ~ , 7-''f.~

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1 pulse stream for detecting ~he presence of the expected pulse edges during the duration of every other pulse of said detected pulse stream, and for providing a first ou~put signal in the event of such detection, said second detecting means being out of phase with said first detecting means, said first and second detecting means also detecting the presence of a pulse edge in said predetermined pulse stream i.n the absence of coincidence with a pulse of said detection pulse stream, and providing a second output signal in the event of such detection; and means for counting the number of said first output signals and said second output signals from each of said first and second detecting means and for providing a validity signal depending on a predetermined net number of said first output signals received from the one of lS the first and second detection means having the higher count for a given number of detection pulses.

BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be better understood from the more detailed description which follows, making reference to the drawings in which:
FIG 1 is a schematic circuit diagram of the pulse detection circuit of the invention; and -7a-:~"

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l FIG 2 is a graph showing the various pulse streams of the invention at the indicated points A-E in FIG l, DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to the schematic of FIG l and the graph of the various pulse streams of FIG 2, it shouldl be apparent that ~e pulse streams identified as A, B, C, D, and E in FIG 2 are t~e streams appearing at the points A-E shown in FIG l. Pulse stream A is a sample of 8 bits of cod~ which may result from the signal from an antenna after amplification, demodulation, and filtering. The format of this code is called "Manchester". In this format, a 1 is indicated, as shown for '~BIT .l", as a transition from a high d.c. level to a low level, as shown in pulse sequence A. BIT 2, a binary 0, is the opposite, a:transition from a low d.c. level ~o a high level.
~ Pulse sequence A represents the binary pulse sequence lOOlOOlO.
: Pulse sequence A shown in FI~ 2 is received, as shown in FIG l, at point A at the input lO to the edge detection and pulse-forming circui~ ll. The output o~ circuit 11 appears at point B in FIG 1 and is ~hown as pulse sequence B in FIG 2. In the example shown, the pulses may appear a minimum of every 50 microseconds. In pulse sequence B in FIG 2, for example, there is a 50 microsecond time between pulse edge 32 and pulse edge 2C 33, However, ~here are IOO microseconds between pulse edge 31 ,, , - :

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5~ ' 1 and pulse edge 32. Every 100 microseconds after pulse edge 31, there is another pulse edge in pulse sequence B, as shown.
However, if the first pulse edge received by the reader happened to be pulse edge 33, there is only one other pulse in pulse sequence B in synchronism at 100 microsecond in~ervals with pulse edge 33, and that is pulse edge 34 in pulse sequence B between BIT 5 and BIT 6. However, pulse edge 31 is the start of a series of eight regular pulse edges, one every lOo microseconds, for each of the B binary bits in pulse stream B, irrespective of whether they are l's or O's.
Pulse sequence ~, representing the raw data, is fed into the synchronizer and detection pulse stream generator 12.
Generator 12 serves to synchronize the detection pulse stream C
with the first~received pulse edge in pulse s~ream B. The detection pulse stream supplied by generator 12 is shown in FIG
2 as pulse sequence C and it appears at point C in FIG 1. Note that pulse sequence C has pulses every 50 microseconds, including pulses 35, 36 and 37 shown. Detection pulse stream generator 12 emits regular pulses at the minim~m possible interval at whi~h pulses may be received from edge detector 11 in FIG 1 when a valid signal is being received.
Although pulse stream C is synchronized in edge detector ll with the first received edge, it is not possible to ascertain from that edge whether that pulse represents one of the pulses appearing every 100 microseconds starting with pulse . .

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l 31 in pulse sequence B, or whether it is the first of a stream starting with pulse 33, which only randomly appears every 109 microseconds in accordance with the data. Because of this a~biguity, pulse sequence C is fed to the input of flip-flop 18 as shown in FIG 1. Remembering that detection pulse stream C
has a regular pulse every 50 microseconds, flip-flop 18 flips back and orth with every detection pulse. The output of flip-lop 18 provides pulse sequences D and E. Pulse seq~lence D contains pulses 42, 44 and others every lO0 microseconds which are out o phase with pulses 51, 53 and the rest of pulse stream E which also occur every lO0 microseconds.
The pulses emitted by detection pulse stream gen~rator 12 should be wide enough to bracket the window of the possible detection times of the pulse edges from the pulse stream B. As an example, assuming the minimum time between pulses is 50 microseconds in a valid pulse stream, detection pulse stream C
emitted from pulse stream generator 12 could be designed to open a window at a time of about 37.5 microseconds from the receipt of the first pulse edge passed through edge detec~or ll, and to close it at 62.5 microseconds. This provides 12.5 microseconds on either side of each of the expected 50 microsecond-spaced pulses to insure detection. Detection puls~
stream C thus remains high for 25 microseconds for each e~pected pulse.

... .. . ........ .... . .

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1 Thus out-of-phase pulses D and E emitted from flip-flop 1~ are used as enabling pulses to AND-gates 13 and 15, as shown in FIG 1. AND-gate 15 is enabled by the pulses in pulse sequence D and AND~gate 13 by the pulses in pulse sequence E, which are out-of-phase with the pulses in pulse sequence ~. Thus AND-gates 15 and 13 are enabled at different times, out-of-phase with each other.
The input pulse stream A, after being passed through edye detector 11 to provide pulse sequence 8 s~own in FI~ 2, is also fed as an input to ~ND-gates 13 and lS. Since AND-gates 13 and 15 are ou~of-phase with each other, one of them is going to detect one set of pulse edges in pulse sequence B
coincident with pulse edges 31 and 32 which appear every 100 microseconds. The other of the two AND-gates is going to detect pulse edges in phase with pulse edges 33 and 34 in pulse sequence B, which appear ran~omly. The circuitry of FIG 1 is designPd so that it doesn't matter which is which. ~or the purposes of illustration, we will assume that AND-gate 13 detects the pulses synchronized in 100 microsecond intervals with pulse 31 and 32 in pulse sequence B, and AND~gate 15 detects the pulses synchronized at 100 microsecond intervals with pulses 33 and 34 and those in phase at 100 microsecond inter~al~ with them. In the example shown, therefore, AND-gate 13 will have more output pulses in a giv~n time than AND-gate 15 because AND-gate 13 will emit an output pulse every 100 5~

1 microseconds upon receipt of a valid signal at input 10, whzreas AND-gate 15 will only emit signals randomly in accordance with ~he data.
The output pulse streams from AND-gates 13 and 15, respectively, pass through OR-gates 16 and 17 to counters 21 ~nd 22, respectively. In the example chosen, counter 21 will count faster.
Counters 21 and 22 initially are reset by detection pulse stream generator 12 before the first edge is detected.
lo The counters then may be reset to zero, but for reasons that will be explained later, it is preferred to reset the counters to 1. Reset is accomplished by a pulse sent from sa~ple pulse generator 25. The count required to provide a validity output signal may also be set at any level, depending on the number of pulses in an average signal and the number of "hits" which ~he user r~quires to reach a reasonable confidence that a valid signal is being received. As an example, this maximum may be 7. When the maximum is reached, a signal appears at the "}imit out" t~rminal of counters 21 or 22, which is passed through OR-gate 23 to latch 24.
~ t the end of eight bit periods, the sample pulse generator 25 sends a sample pulse to the reset inputs of counters 21 and 22 and to latch 24. At that time, if OR-gate 23 is high as a result of one of counters 21 and 22 having ~5 reached a count of seven, which indicates receipt of a valid ~ 3 ~

1 signal, latch 24 will be set by the sample pulse generator 25 to indicate validity. If neither counter has reached the limit, there will be no high signal through OR-gate 23 and latch 2~ will not be set, indicating no valicl signal has been S received In the example where AND-gate 13 rec2ives the regular, 100 microsecond pulses, counter 21 will reach the predetermined limit of seven first. Thus it will emit a limit or validity signal through OR-gate 23 to latch 24 indicating a valid pulse lo stream is being received. Alternatively, if the first edge detec~ed happened to be edge 33 in pulse sequence B, and that pulse was passed ~hrough flip-flop 18 to AND-gate 1~, the other AND-gate 15 would be the one to receive the regular 100 microsecond pulses, such as pulses, 31 and 32 in pulse sequence B. Therefore counter 22 and not 21 would reach a count of . seven faster and thus be the first to emit an output signal through OR-gate 23 to latch 24. Obviously, a valid signal is a valid signal at the latch output 24 -- irrespective of which of : counters 21 and 2~ sent it.
~ Another feature of a preferred embodiment of the invent~ion is the ability to decrement the count in counters 21 a~d 22 if invalid pulses are received. Invalid pulses are defin~d as pulses which appear outside the windows set by detection pul5e stream C in FIG 2. In other words, they are pulses which appear when the siqnal in pulse sequence C is ~3~5~5~

1 low. ~ulse Sequence C is emitted from detection pulse strea~
generator 12 and passed, as shown in FIG 1, to an inverter input 19 of AND-gate 14, thus enabling AND-gate 14 during the low portion of pulse sequence C, bu~ not dur:ing the high S por~ion. Since all the pulse edges of pulse sequence B are sent to the other input of AND-gate 14, AND-gate 14 will emit an output signal at anytime it detects a pulse edge ou~side of the proper expected windows defined ~y the pulses of pulse sequence C. Pulse sequence C also operates the up~down controls of counters 21 and 22. During the receipt of one of the pulses, such as 35, 36 or 37, of pulse sequence C, the up/down controls of counters ~1 and 22 are set to count up (increment). In the absence of one of these pulses, when pulse sequence C is low, the up~down controls of counters 21 and 22 are changed so that the counters will count down (decreased).
Since AND-gate 14 is also enabled out-of-phase with de~ection pulses 35, 36 and 37, its output signal passes through both OR-gate~ 16 and 17 to both counters 21 and 22 when AND-gate 14 receives an edge input (which must be invalid) while pulse sequence C is low. The counters are both then set to decrement, so they will reduce their count by 1.
What this means is for every good pulse received, either counter 21 or 22 will increment; for every bad pulse received, bo~h coun~ers 21 and 22 wi11 decrement. The output of each of ~hese coun~er~, therefore, in this preferred ~3575~

1 embodimen~, which passes through OR~gate 23 to latch 24, represents the net of good pulses less bad ones. The counters only provide a valid signal output when this net reaches seven in the example given. This puts an extra rec~irement on the validation of the signal.
Because of the possibil~ty of an initial down count if noise is being received at the start, it has been ound preferable to reset counters 21 and 22 ~o an initial 1 rather than a 0. The counters are reset every eight bit periods by a sampl~ pulse from sample pulse senerator 25. This permits the possibility of at least one initial decrement registering before the counter reaches O (the lowest possible count).
Obviously, if the counters had been reset to 0, an initial down count would have had no e~fect.
The reader of this invention has multiple inputs for various antennas. It regularly and continuously must switch from one antenna to the next. Before each switch, its ~witching circuit (not shown) interrogates latch 24 to see if ~here has been an output signal from either counter, indicating that the an~enna present}y emitting signals is receiving a valid signal. If not, indicated by the absence of an output signal at latch 24, the reader switches to the next antenna in ~equence. If there is a valid ou~put signal at latch 2i, no switching takes place until the complete signal has been received, at which time latch 24 wiil be reset to the opposite .

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1 st~te unless another valid signal is then being received.
The circuitry of this invention is capable of picking out valid signals from transponders carried on moving objects such as railroad cars, automobiles or shipping containers, for example, from the amplified background noise, such as from fluorescent lights, random microwave transmission or the like which is picked up in the absence of other signals. Because the presence of a valid signal may be quickly ascertained before it has been completely received, or its absence noted equally guickly, multiple antennas which receive signals from di~ferent sets of transponders may be serviced by the same reader with reduced risk of loss of valid signals.
Obviously modifications may be made to the ~referred embodiments described above without deviating from the spirit and scope of the invention, which is defined in the claims which follow.

Claims

1. A circuit for early detection of a predetermined pulse stream having a given periodicity, comprising:
means for providing a detection pulse stream wherein the width of the pulses include the expected edges of said predetermined pulse stream;
first and second detecting means connected to receive said predetermined pulse stream for detecting the presence of the expected pulse edges during the duration of every other pulse of said detected pulse stream, and for providing a first output signal in the event of such detection, said second detecting means being out of phase with said first detecting means, said first and second detecting means also detecting the presence of a pulse edge in said predetermined pulse stream in the absence of coincidence with a pulse of said detection pulse stream, and providing a second output signal in the event of such detection; and means for counting the number of said first output signals and said second output signals from each of said first and second detecting means and for providing a validity signal depending on a predetermined net number of said first output signals received from the one of the first and second detection means having the higher count for a given number of detection pulses.

2, The circuit of claim 7 wherein said means for counting is incremented once for the receipt of each first output signal and decremented once for the receipt of each second output signal, and said means for counting provides said validity signal when its net count reaches said predetermined net number.