CA1319199C - Bus data path control scheme - Google Patents
Bus data path control schemeInfo
- Publication number
- CA1319199C CA1319199C CA000580560A CA580560A CA1319199C CA 1319199 C CA1319199 C CA 1319199C CA 000580560 A CA000580560 A CA 000580560A CA 580560 A CA580560 A CA 580560A CA 1319199 C CA1319199 C CA 1319199C
- Authority
- CA
- Canada
- Prior art keywords
- data
- buses
- subsystem
- width
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
Abstract
ABSTRACT OF THE DISCLOSURE
A bus data path control scheme facilitates communications in a data processing system between subsystem elements that have different data widths. A
plurality of buses is provided whereby each subsystem or element is connected to one of the plurality of buses.
A control logic array detects requests to transfer data between subsystems. Each of the plurality of buses are connected to one another through a bidirectional transceiver. Once the control logic array detects the request for transferring data between subsystems, the array and the transceiver operate in concert to permit subsystem devices having different data widths to communicate with one another. In particular, the array and transceiver act to redirect data so that as it is shifted from a first bus to which the sending subsystem is connected to a second bus to which the receiving subsystem is connected, the data is moved into the proper bit location on the second bus so as to be received properly by the receiving subsystem.
A bus data path control scheme facilitates communications in a data processing system between subsystem elements that have different data widths. A
plurality of buses is provided whereby each subsystem or element is connected to one of the plurality of buses.
A control logic array detects requests to transfer data between subsystems. Each of the plurality of buses are connected to one another through a bidirectional transceiver. Once the control logic array detects the request for transferring data between subsystems, the array and the transceiver operate in concert to permit subsystem devices having different data widths to communicate with one another. In particular, the array and transceiver act to redirect data so that as it is shifted from a first bus to which the sending subsystem is connected to a second bus to which the receiving subsystem is connected, the data is moved into the proper bit location on the second bus so as to be received properly by the receiving subsystem.
Description
BUS DATA PATH CONTROL SCHEME
BACKGROUND OF THE INVENTION
Field of the Invention -The present invention relates to a bus data path control scheme. In particular, the present invention relates to a scheme in a data processing system by which subsystems of the data processing system, having dif~erent data widths, are capable of co~municating with each other in a fast manner where a minimum amount of hardware is required for interfacing the subsystems.
Description of the Related Art Known data processing systems may consist of a central processing unit and a plurality of subsystems.
In particular, data processing systems may include a plurality of memory subsyskems such as dynami.c random access memories (dRAMs), video dynamic random access memories (video dRAMs) and other read only memories (ROMs). The data processing system may also include such subsystems as a disk controller, a cursor controller, a serial line controller a.-~/or a pluralit~
of other subsystem elements.
It is possible that not all of the subsystem elements of the data processing system will have the same data widths. For example, a disk controller in the system may be a 32 bit disk controller, that is it may have a data width of 32 bits. In contrast, a serial line controller in the system may be a 16 bit device.
Similarly, memory devices in the system may be 16 or 32 bit devices.
It is sometimes necessary to transfer data from a device or subsystem having a first data width to a device or subsystem having a second data width where the - two data widths are different.
Prior data processing systems have accommodated such transfers by using registers and multiplexers on the inputs and outputs of each of the subsystems. The multiplexers and registers permit a conversion of the data width of a device so as to make communications between devices having different data widths more uniform. Unfortunately, registers and multiplexers for the inputs and outputs of each of the subsystems constitute a considerable amount of hardware. In addition, signal processing through these multiplexers and registers introduces an undesirable amount of delay into the operation of the system.
Sum ary of the Invention The present invention obviates the disadvantages associated with known systems for establishing communications between subsystems having different data widths.
1 3 1 9 1 9~ 72896-7 According to a broad aspect of the invention there is provided a data path controller in a data processing system that includes a central processor unit and a plurality of sub-systems, the controller providing for a transfer of data between subsystems having different data path widths, comprising: a plurality of buses intercoupling the central processing unit and the plurality of subsystems, each bus having a data path width equal to or greater than a data path width of a subsystem having the greatest data path width, wherein at least two subsystems having differing data path widths are coupled to the same one of said plurality of buses; and means for controlling a flow of data between subsystems over said plurality of buses, said means for controlling being coupled to said plurality of buses and compris-ing, means for producing a control signal in response to a request to transfer data from a sending subsystem, ~rhich is caupled to one of the plurality of buses, to a receiving subsystem, which is coupled to one of the plurality of buse;s, and means for control-ling the data width of a flow o~ data between any two of said plurality of buses, said means for controlling the data width being responsive to said control signal so that data from said sending subsystem is transferred to said receiving subsystem, wherein said means for controlling the data width is coupled between any two of said plurality of buses and receiving the con-trol signal from said means for producing a control signal.
According to another broad aspect of the invention there is provided a data path controller in a data processing .~
_ 1 31 91 qq 72896-7 system that includes a central processor unit and a plurality of subsystems, the controller providing for a transfer of data between subsystems ha~ing di~ferent data path widths, comprising:
a plurality of buses i.~tercoupling the central processing unit and the plurality of subsystems, each bus having a aata path width equal to or greater than a clata path width of a subsystem having the greatest data path width, wherein at least two sub-systems having differing data path widths are coupled to the same one of said plurality of buses; and means for controlling a flow of data between subsystems over said plurality of buses, said means for controlling being coupled to said plurality of buses and comprisin.g, means for producing a control signal in response to a request to trans~er data from a sending subsystem, which is coupled to one of the plurality of buses, to a receiving subsystem, wherein said means for producing the control signal comprises a control logic circuit, and means for controlling the data width of a flow of data between any two of said plurality of buses, said means for controlling the data width being responsive to said control signal so that data from said sending subsystem is transferred to said receiving subsystem, wherein said means for controlling the data width of a flow of data comprises means for converting the data width of the data from said sending subsystem to the data width associated with said receiving subsystem, said means for controlling the data width is coupled between any two of said plurality of buses and receiving the control signal from said means for producing a control signal.
- 3a -72896~7 131ql99 According to another broad aspect of the invention there is provided a data path controller in a processing system including a plurality of subsystems and a central processing unit, the system providing data paths between subsystems which ha~e different data widths and comprisi:ng: a plurality of data buses, wherein eacy subsystem is coupled to a data bus; means for coupling each of said plurality of data buses to the others of said plurality of data buses; and means for controlling said means for coupling in response to a data transfer request, so as to transfer data from a sending subsystem having a data width to a receiving subsystem ha~ing with its own data width~
- 3b -13191q9 r~
Brief Description of the Drawinqs The present invention will be understood from the detailed description set forth below in connection with the drawing of the present application in which Figure l illustrates an embodiment of a bus data controller in accordance with the present invention.
Detalled Descri ~
The present invention may be implemented in a data processing system in which there are a plurality of subsystems. Each subsystem may have its own data width.
As described above, it is flesirable that data transfers occur between subsystems even if those subsystems have non-matching data widths.
Figure 1 illustrates an embodiment of a bus data control scheme which enables the transfer of data between subsystem elements that have different data widths.
In Figure l three main buses are illustrated.
There is a primary bus 12, secondary bus lO and tertiary bus 14. Primary bus 12 is associated with the CPU 11.
Secondary bus lO is associated with a subset of the subsystems of the data processing system. Connected to bus 10 in Figure 1 are a 32 bit controller 13 and a 16 bit controller 15. Connected to tertiary bus 14 are memory subsystems of the data processing syste~. These memory subsystems include a dRAM 17 and a video dRAM 19.
Additional subsystem elements may be disposed so as to be connected to either the secondary bus 10 or the 1 3 1 9 1 9q , tertiary bus 14. Primary bus 12 is associated strictly with the CPU or the host of the data processing system.
The primary bus 12, the secondary bus 10 and the tertiary bus 14 are 32 bit buses.
In the present invention known transceiver elements are used to connect the primary, secondary and tertiary buses. As can be seen in Figure 1, a transceiver 16a is disposed between primary bus 12 and secondary bus 10.
Connectors 20 connect transceiver 16a to these two buses. Transceiver element 16b provides coupling between secondary bus 10 and tertiary bus 14.
Connectors 20 are utilized for coupling the transceiverS
16b directly to the two buses 10 and 14.
It should be noted that the present invention is not limited to the use of three buses. Nor is it limited to the use cf 2 transceivers. The present invention contemplates that transceiver elements which provide a gating effect for a flow o~ data are utilized to provide connections between each of the buses in the data processing syste~ when a plurality of buses to which subsystems are attached are utilized. Logic array element 18 is considered to be part of the host in this embodiment although the logic array element may be provided separatelyO The logic array element 18 is connected through the CPU 11 to primary bus 12. It is also connected to transceivers 16a and 16b. The array includes a memory 21.
The operation of this system will now he described in greater detail by means o an example. When it is desired that a data transfer occur, a transfer request signal is produced indicati~g that a first device desires a transfer of information between itself and a second device or subsystem. This data request signal is 1 3 1 9 1 q~
, -6-detected by control logic in the logic array 18 of Figure 1. For example, should a 16 bit device such as a l~ bit controller 15 connected to the secondary bus 10 desire to write data to a 32 bit memory location in dRAM
17 connected to tertiary bus 14, a signal is produced which is detected by the control logic of the logic array 18 connected to the CP'U 11. In response to this data request signal, the logic array 18 produces a control signal which is transmitted to the transceiver 16b that couples the secondary bus 10 and tertiary bus 14. The control signal sets forth an operation cycle that gates the flow of data from the secondary bus 10 into the tertiary bus 14.
The logic array 18 controls an operation by which data is shifted on the secondary bus 10. Data is shifted to direct the data into the proper bit position on the secondary bus for transfer to the tertiary bus and on to the 32 bit dRAM 17.
First the controller produces an address which equates to a 16 bit word location in the dRAM 17. The logic array 18 has a memory 21 associated with it that latches this address. The array 18 then produces the appropriate memory address in a Row Address/Column Address ~RAS/CAS) multiplexed format. The 16 bit controller 15 then places the data which it desires to send to the dRAM 17 onto the secondary bus lO. It is placed onto the low end of the secondary bus lO, locations 00 to 15 of the bus. The logic array 18 signals the transceiver 16b to allow the data from location 00 to 15 of the secondary bus 10 to flow to location 00 to 15, the low end of the tertiary bus 14.
The logic array also causes a 16 bit write cycle to the 32 bit dRAM 17.
131919q The 16 bit controll~- then produces an address which corresponds to the .~ext 16 bit memory location.
The array 18 latches the 16 bit word and again produces the correct RAS~CAS address for the memory. This second 16 bit word is placed on the low end of the secondary bus 10, location 00 to 15. The logic array directs that the 16 bit word to be transferred to the high end of secondary bus 10, locations 16 to 31. The logic array 18 then directs the transceiver 16b to allow the data to flow from the high end of the secondary bus 10 to the high end of the tertiary bus 14, loca~ions 16 to 31.
Finally the second and last 16 bit write to the dynamic random access memory 17 is initiated by the logic array 18. The write operation of ~ 16 bit words from the 16 bit controller to a 32 bit memory location is complete.
The logic array 18 in concert with transceiver l~b is responsible for directing data over the secondary and tertiary buses so as to complete a data transfer from the 16 bit controller 15 to the 32 bit memory 17.
Due to the flexibility of the logic array 18 and the bidirectional nature of transceiver~ 16a, and 16b it is also possible to transfer data from a 32 bit device to a 16 bit device. For example, if the 16 bit controller desires to read information from the 32 bit memory 17 then similar activity to that described above would occur but in reverse order.
The controller produces an address for a 16 bit location in the 32 bit dRAM 17. Data is then moved from the word in the low end nemory location, location 00 to 15 of the memory onto the low end of the tertiary bus 14. The transceiver receives a control signal from the logic array which enables the transceiver to pass the word appearing on the low end of the tertiary bus 14 to 131qlqq the lo~ end of the secc-~ary bus, 10. The data word i5 transferred to the disk controller along lines 00 to 15 of the secondary bus 10. The word in the high end of the memory location, 16 to 31 is transferred onto the tertiary bus 14. The data word is then directed to the low word area 00 to 15 of tertiary bus 14. The logic array 18 transmits a control signal to the transceiver 16b which enables the transceiver to pass the word on the low end of the tertiary bus 14 to the low end of the secondary bus 10. Therefore the original high word passes to the controller lS.
The logic array, in connection with the transceiver acts to control the flo~ of data between subsystems in the data processing system illustrated in Figure 1. The logic array senses data transfer requests and sends appropriate control signals to the transceiver which couples the buses to which the subsyste~s that wish to communicate are attached. The logic array acts to shift data to appropriate locations on th~ bus to which the sending station is connected. The array then signals the transceiver to pass the data from the bus to which the sendiny subsystem is connected to the bus to which the receiving subsystem is connected.
As described above, the array and transceiver may provide connections bet~een subsystems having data widths of 16 bits and 32 bits. It is also possible to have subsystem elements having an 8 bit data width. The array and transceiver can be easily adapted to control the flow of data so as to enable an 8 bit width subsystem to communicate with a 16 bit width device or a 32 bit width device. The logic array acts to latch portions of the data that is to be transmitted and to shift it into an appropriate position for receipt by the 1 ~ 1 9 1 99 subsystem which is intended to receive the data communication. The logic array in operation with the transceiver acts as a traffic cop that directs data traffic between subsyste~s of the data processing system ~~
over a plurality of buses in that processing system.
The present invention reduces the amount of hardware necessary to enable communication between subsystems that have different data path widths. In addition, it reduces the amount of time necessary for communication between such elements. The invention allows the reduction of cost and complexity in data path management systems and also increases the reliability of those systems. The present invention allows high performance data path management through a sequence of latching and producing memory addresses in the RAS/CAS
multiplexed for~at as described above and therefore removes the need for using registers and multiplexers on the inputs and outputs of the various subsystems.
BACKGROUND OF THE INVENTION
Field of the Invention -The present invention relates to a bus data path control scheme. In particular, the present invention relates to a scheme in a data processing system by which subsystems of the data processing system, having dif~erent data widths, are capable of co~municating with each other in a fast manner where a minimum amount of hardware is required for interfacing the subsystems.
Description of the Related Art Known data processing systems may consist of a central processing unit and a plurality of subsystems.
In particular, data processing systems may include a plurality of memory subsyskems such as dynami.c random access memories (dRAMs), video dynamic random access memories (video dRAMs) and other read only memories (ROMs). The data processing system may also include such subsystems as a disk controller, a cursor controller, a serial line controller a.-~/or a pluralit~
of other subsystem elements.
It is possible that not all of the subsystem elements of the data processing system will have the same data widths. For example, a disk controller in the system may be a 32 bit disk controller, that is it may have a data width of 32 bits. In contrast, a serial line controller in the system may be a 16 bit device.
Similarly, memory devices in the system may be 16 or 32 bit devices.
It is sometimes necessary to transfer data from a device or subsystem having a first data width to a device or subsystem having a second data width where the - two data widths are different.
Prior data processing systems have accommodated such transfers by using registers and multiplexers on the inputs and outputs of each of the subsystems. The multiplexers and registers permit a conversion of the data width of a device so as to make communications between devices having different data widths more uniform. Unfortunately, registers and multiplexers for the inputs and outputs of each of the subsystems constitute a considerable amount of hardware. In addition, signal processing through these multiplexers and registers introduces an undesirable amount of delay into the operation of the system.
Sum ary of the Invention The present invention obviates the disadvantages associated with known systems for establishing communications between subsystems having different data widths.
1 3 1 9 1 9~ 72896-7 According to a broad aspect of the invention there is provided a data path controller in a data processing system that includes a central processor unit and a plurality of sub-systems, the controller providing for a transfer of data between subsystems having different data path widths, comprising: a plurality of buses intercoupling the central processing unit and the plurality of subsystems, each bus having a data path width equal to or greater than a data path width of a subsystem having the greatest data path width, wherein at least two subsystems having differing data path widths are coupled to the same one of said plurality of buses; and means for controlling a flow of data between subsystems over said plurality of buses, said means for controlling being coupled to said plurality of buses and compris-ing, means for producing a control signal in response to a request to transfer data from a sending subsystem, ~rhich is caupled to one of the plurality of buses, to a receiving subsystem, which is coupled to one of the plurality of buse;s, and means for control-ling the data width of a flow o~ data between any two of said plurality of buses, said means for controlling the data width being responsive to said control signal so that data from said sending subsystem is transferred to said receiving subsystem, wherein said means for controlling the data width is coupled between any two of said plurality of buses and receiving the con-trol signal from said means for producing a control signal.
According to another broad aspect of the invention there is provided a data path controller in a data processing .~
_ 1 31 91 qq 72896-7 system that includes a central processor unit and a plurality of subsystems, the controller providing for a transfer of data between subsystems ha~ing di~ferent data path widths, comprising:
a plurality of buses i.~tercoupling the central processing unit and the plurality of subsystems, each bus having a aata path width equal to or greater than a clata path width of a subsystem having the greatest data path width, wherein at least two sub-systems having differing data path widths are coupled to the same one of said plurality of buses; and means for controlling a flow of data between subsystems over said plurality of buses, said means for controlling being coupled to said plurality of buses and comprisin.g, means for producing a control signal in response to a request to trans~er data from a sending subsystem, which is coupled to one of the plurality of buses, to a receiving subsystem, wherein said means for producing the control signal comprises a control logic circuit, and means for controlling the data width of a flow of data between any two of said plurality of buses, said means for controlling the data width being responsive to said control signal so that data from said sending subsystem is transferred to said receiving subsystem, wherein said means for controlling the data width of a flow of data comprises means for converting the data width of the data from said sending subsystem to the data width associated with said receiving subsystem, said means for controlling the data width is coupled between any two of said plurality of buses and receiving the control signal from said means for producing a control signal.
- 3a -72896~7 131ql99 According to another broad aspect of the invention there is provided a data path controller in a processing system including a plurality of subsystems and a central processing unit, the system providing data paths between subsystems which ha~e different data widths and comprisi:ng: a plurality of data buses, wherein eacy subsystem is coupled to a data bus; means for coupling each of said plurality of data buses to the others of said plurality of data buses; and means for controlling said means for coupling in response to a data transfer request, so as to transfer data from a sending subsystem having a data width to a receiving subsystem ha~ing with its own data width~
- 3b -13191q9 r~
Brief Description of the Drawinqs The present invention will be understood from the detailed description set forth below in connection with the drawing of the present application in which Figure l illustrates an embodiment of a bus data controller in accordance with the present invention.
Detalled Descri ~
The present invention may be implemented in a data processing system in which there are a plurality of subsystems. Each subsystem may have its own data width.
As described above, it is flesirable that data transfers occur between subsystems even if those subsystems have non-matching data widths.
Figure 1 illustrates an embodiment of a bus data control scheme which enables the transfer of data between subsystem elements that have different data widths.
In Figure l three main buses are illustrated.
There is a primary bus 12, secondary bus lO and tertiary bus 14. Primary bus 12 is associated with the CPU 11.
Secondary bus lO is associated with a subset of the subsystems of the data processing system. Connected to bus 10 in Figure 1 are a 32 bit controller 13 and a 16 bit controller 15. Connected to tertiary bus 14 are memory subsystems of the data processing syste~. These memory subsystems include a dRAM 17 and a video dRAM 19.
Additional subsystem elements may be disposed so as to be connected to either the secondary bus 10 or the 1 3 1 9 1 9q , tertiary bus 14. Primary bus 12 is associated strictly with the CPU or the host of the data processing system.
The primary bus 12, the secondary bus 10 and the tertiary bus 14 are 32 bit buses.
In the present invention known transceiver elements are used to connect the primary, secondary and tertiary buses. As can be seen in Figure 1, a transceiver 16a is disposed between primary bus 12 and secondary bus 10.
Connectors 20 connect transceiver 16a to these two buses. Transceiver element 16b provides coupling between secondary bus 10 and tertiary bus 14.
Connectors 20 are utilized for coupling the transceiverS
16b directly to the two buses 10 and 14.
It should be noted that the present invention is not limited to the use of three buses. Nor is it limited to the use cf 2 transceivers. The present invention contemplates that transceiver elements which provide a gating effect for a flow o~ data are utilized to provide connections between each of the buses in the data processing syste~ when a plurality of buses to which subsystems are attached are utilized. Logic array element 18 is considered to be part of the host in this embodiment although the logic array element may be provided separatelyO The logic array element 18 is connected through the CPU 11 to primary bus 12. It is also connected to transceivers 16a and 16b. The array includes a memory 21.
The operation of this system will now he described in greater detail by means o an example. When it is desired that a data transfer occur, a transfer request signal is produced indicati~g that a first device desires a transfer of information between itself and a second device or subsystem. This data request signal is 1 3 1 9 1 q~
, -6-detected by control logic in the logic array 18 of Figure 1. For example, should a 16 bit device such as a l~ bit controller 15 connected to the secondary bus 10 desire to write data to a 32 bit memory location in dRAM
17 connected to tertiary bus 14, a signal is produced which is detected by the control logic of the logic array 18 connected to the CP'U 11. In response to this data request signal, the logic array 18 produces a control signal which is transmitted to the transceiver 16b that couples the secondary bus 10 and tertiary bus 14. The control signal sets forth an operation cycle that gates the flow of data from the secondary bus 10 into the tertiary bus 14.
The logic array 18 controls an operation by which data is shifted on the secondary bus 10. Data is shifted to direct the data into the proper bit position on the secondary bus for transfer to the tertiary bus and on to the 32 bit dRAM 17.
First the controller produces an address which equates to a 16 bit word location in the dRAM 17. The logic array 18 has a memory 21 associated with it that latches this address. The array 18 then produces the appropriate memory address in a Row Address/Column Address ~RAS/CAS) multiplexed format. The 16 bit controller 15 then places the data which it desires to send to the dRAM 17 onto the secondary bus lO. It is placed onto the low end of the secondary bus lO, locations 00 to 15 of the bus. The logic array 18 signals the transceiver 16b to allow the data from location 00 to 15 of the secondary bus 10 to flow to location 00 to 15, the low end of the tertiary bus 14.
The logic array also causes a 16 bit write cycle to the 32 bit dRAM 17.
131919q The 16 bit controll~- then produces an address which corresponds to the .~ext 16 bit memory location.
The array 18 latches the 16 bit word and again produces the correct RAS~CAS address for the memory. This second 16 bit word is placed on the low end of the secondary bus 10, location 00 to 15. The logic array directs that the 16 bit word to be transferred to the high end of secondary bus 10, locations 16 to 31. The logic array 18 then directs the transceiver 16b to allow the data to flow from the high end of the secondary bus 10 to the high end of the tertiary bus 14, loca~ions 16 to 31.
Finally the second and last 16 bit write to the dynamic random access memory 17 is initiated by the logic array 18. The write operation of ~ 16 bit words from the 16 bit controller to a 32 bit memory location is complete.
The logic array 18 in concert with transceiver l~b is responsible for directing data over the secondary and tertiary buses so as to complete a data transfer from the 16 bit controller 15 to the 32 bit memory 17.
Due to the flexibility of the logic array 18 and the bidirectional nature of transceiver~ 16a, and 16b it is also possible to transfer data from a 32 bit device to a 16 bit device. For example, if the 16 bit controller desires to read information from the 32 bit memory 17 then similar activity to that described above would occur but in reverse order.
The controller produces an address for a 16 bit location in the 32 bit dRAM 17. Data is then moved from the word in the low end nemory location, location 00 to 15 of the memory onto the low end of the tertiary bus 14. The transceiver receives a control signal from the logic array which enables the transceiver to pass the word appearing on the low end of the tertiary bus 14 to 131qlqq the lo~ end of the secc-~ary bus, 10. The data word i5 transferred to the disk controller along lines 00 to 15 of the secondary bus 10. The word in the high end of the memory location, 16 to 31 is transferred onto the tertiary bus 14. The data word is then directed to the low word area 00 to 15 of tertiary bus 14. The logic array 18 transmits a control signal to the transceiver 16b which enables the transceiver to pass the word on the low end of the tertiary bus 14 to the low end of the secondary bus 10. Therefore the original high word passes to the controller lS.
The logic array, in connection with the transceiver acts to control the flo~ of data between subsystems in the data processing system illustrated in Figure 1. The logic array senses data transfer requests and sends appropriate control signals to the transceiver which couples the buses to which the subsyste~s that wish to communicate are attached. The logic array acts to shift data to appropriate locations on th~ bus to which the sending station is connected. The array then signals the transceiver to pass the data from the bus to which the sendiny subsystem is connected to the bus to which the receiving subsystem is connected.
As described above, the array and transceiver may provide connections bet~een subsystems having data widths of 16 bits and 32 bits. It is also possible to have subsystem elements having an 8 bit data width. The array and transceiver can be easily adapted to control the flow of data so as to enable an 8 bit width subsystem to communicate with a 16 bit width device or a 32 bit width device. The logic array acts to latch portions of the data that is to be transmitted and to shift it into an appropriate position for receipt by the 1 ~ 1 9 1 99 subsystem which is intended to receive the data communication. The logic array in operation with the transceiver acts as a traffic cop that directs data traffic between subsyste~s of the data processing system ~~
over a plurality of buses in that processing system.
The present invention reduces the amount of hardware necessary to enable communication between subsystems that have different data path widths. In addition, it reduces the amount of time necessary for communication between such elements. The invention allows the reduction of cost and complexity in data path management systems and also increases the reliability of those systems. The present invention allows high performance data path management through a sequence of latching and producing memory addresses in the RAS/CAS
multiplexed for~at as described above and therefore removes the need for using registers and multiplexers on the inputs and outputs of the various subsystems.
Claims (10)
1. A data path controller in a data processing system that includes a central processor unit and a plurality of sub-systems, the controller providing for a transfer of data between subsystems having different data path widths, comprising:
a plurality of buses intercoupling the central processing unit and the plurality of subsystems, each bus having a data path width equal to or greater than a data path width of a subsystem having the greatest data path width, wherein at least two subsystems having differing data path widths are coupled to the same one of said plurality of buses; and means for controlling a flow of data between sub-systems over said plurality of buses, said means for controlling being coupled to said plurality of buses and comprising, means for producing a control signal in response to a request to transfer data from a sending subsystem, which is coupled to one of the plurality of buses, to a receiving subsystem, which is coupled to one of the plurality of buses, and means for controlling the data width of a flow of data between any two of said plurality of buses, said means for controlling the data width being responsive to said control signal so that data from said sending subsystem is transferred to said receiving subsystem, wherein said means for controlling the data width is coupled between any two of said plurality of buses and receiving the control signal from said means for producing a control signal.
a plurality of buses intercoupling the central processing unit and the plurality of subsystems, each bus having a data path width equal to or greater than a data path width of a subsystem having the greatest data path width, wherein at least two subsystems having differing data path widths are coupled to the same one of said plurality of buses; and means for controlling a flow of data between sub-systems over said plurality of buses, said means for controlling being coupled to said plurality of buses and comprising, means for producing a control signal in response to a request to transfer data from a sending subsystem, which is coupled to one of the plurality of buses, to a receiving subsystem, which is coupled to one of the plurality of buses, and means for controlling the data width of a flow of data between any two of said plurality of buses, said means for controlling the data width being responsive to said control signal so that data from said sending subsystem is transferred to said receiving subsystem, wherein said means for controlling the data width is coupled between any two of said plurality of buses and receiving the control signal from said means for producing a control signal.
2. The data path controller of claim 1 wherein said means for controlling the data width of a flow of data comprises means for converting the data width of the data from said sending subsystem to the data width associated with said receiving subsystem.
3. The data path controller of claim 2 wherein said means for controlling the data width further comprises a bi-directional transceiver coupled between any two of said plurality of buses, said transceiver being responsive to said control signal and gating a flow of data between the buses to which it is coupled.
4. The data path controller of claim 2 wherein said means for producing a control signal comprises a control logic circuit disposed on a single chip.
5. A data path controller in a data processing system that includes a central processor unit and a plurality of sub-systems, the controller providing for a transfer of data between subsystems having different data path widths, comprising:
a plurality of buses intercoupling the central pro-cessing unit and the plurality of subsystems, each bus having a data path width equal to or greater than a data path width of a subsystem having the greatest data path width, wherein at least two subsystems having differing data path widths are coupled to the same one of said plurality of buses; and means for controlling a flow of data between sub-systems over said plurality of buses, said means for controlling being coupled to said plurality of buses and comprising, means for producing a control signal in response to a request to transfer data from a sending subsystem, which is coupled to one of the plurality of buses, to a receiving subsystem, wherein said means for producing the control signal comprises a control logic circuit, and means for controlling the data width of a flow of data between any two of said plurality of buses, said means for controlling the data width being responsive to said control signal so that data from said sending subsystem is transferred to said receiving subsystem, wherein said means for controlling the data width of a flow of data comprises means for converting the data width of the data from said sending subsystem to the data width associated with said receiving subsystem, said means for control-ling the data width is coupled between any two of said plurality of buses and receiving the control signal from said means for producing a control signal.
a plurality of buses intercoupling the central pro-cessing unit and the plurality of subsystems, each bus having a data path width equal to or greater than a data path width of a subsystem having the greatest data path width, wherein at least two subsystems having differing data path widths are coupled to the same one of said plurality of buses; and means for controlling a flow of data between sub-systems over said plurality of buses, said means for controlling being coupled to said plurality of buses and comprising, means for producing a control signal in response to a request to transfer data from a sending subsystem, which is coupled to one of the plurality of buses, to a receiving subsystem, wherein said means for producing the control signal comprises a control logic circuit, and means for controlling the data width of a flow of data between any two of said plurality of buses, said means for controlling the data width being responsive to said control signal so that data from said sending subsystem is transferred to said receiving subsystem, wherein said means for controlling the data width of a flow of data comprises means for converting the data width of the data from said sending subsystem to the data width associated with said receiving subsystem, said means for control-ling the data width is coupled between any two of said plurality of buses and receiving the control signal from said means for producing a control signal.
6. A data path controller in a processing system includ-ing a plurality of subsystems and a central processing unit, the system providing data paths between subsystems which have different data widths and comprising:
a plurality of data buses, wherein each subsystem is coupled to a data bus, means for coupling each of said plurality of data buses to the others of said plurality of data buses; and means for controlling said means for coupling in response to a data transfer request, so as to transfer data from a sending subsystem having a data width to a receiving subsystem having its own data width.
a plurality of data buses, wherein each subsystem is coupled to a data bus, means for coupling each of said plurality of data buses to the others of said plurality of data buses; and means for controlling said means for coupling in response to a data transfer request, so as to transfer data from a sending subsystem having a data width to a receiving subsystem having its own data width.
7. The data path controller of claim 6 wherein said means for coupling comprises a transceiver for each coupling of two of said plurality of buses.
8. The data path controller of claim 6 wherein said means for controlling said means for coupling comprises:
means for receiving said data transfer request;
means for directing data movement on the data bus to which said sending subsystem is coupled in response to said data transfer request; and means for producing a control signal as an output in response to said data transfer request, said control signal defines an operation cycle of said means for coupling which will enable the data transfer between data buses to which said sending and said receiving subsystems are coupled.
means for receiving said data transfer request;
means for directing data movement on the data bus to which said sending subsystem is coupled in response to said data transfer request; and means for producing a control signal as an output in response to said data transfer request, said control signal defines an operation cycle of said means for coupling which will enable the data transfer between data buses to which said sending and said receiving subsystems are coupled.
9. The system of claim 8 wherein said means for coupling comprises a bidirectional transceiver providing coupling between the data bus coupled to said sending subsystem and the data bus coupled to said receiving subsystem.
10. The system of claim 8 wherein said means for 13a controlling said means for coupling comprises a control logic circuit disposed on a single chip.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/111,642 US4965723A (en) | 1987-10-23 | 1987-10-23 | Bus data path control scheme |
| US111,642 | 1987-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1319199C true CA1319199C (en) | 1993-06-15 |
Family
ID=22339641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000580560A Expired - Fee Related CA1319199C (en) | 1987-10-23 | 1988-10-19 | Bus data path control scheme |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4965723A (en) |
| EP (1) | EP0313064A3 (en) |
| JP (1) | JPH01129344A (en) |
| CA (1) | CA1319199C (en) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2211326B (en) * | 1987-10-16 | 1991-12-11 | Hitachi Ltd | Address bus control apparatus |
| US5168562A (en) * | 1989-02-21 | 1992-12-01 | Compaq Computer Corporation | Method and apparatus for determining the allowable data path width of a device in a computer system to avoid interference with other devices |
| JPH0398145A (en) * | 1989-09-11 | 1991-04-23 | Hitachi Ltd | Microprocessor |
| JP3118266B2 (en) * | 1990-03-06 | 2000-12-18 | ゼロックス コーポレイション | Synchronous segment bus and bus communication method |
| US5511229A (en) * | 1991-09-13 | 1996-04-23 | Matsushita Electric Industrial Co., Ltd. | Data processing system having a switching network connecting multiple peripheral devices using data paths capable of different data bus widths |
| US5848297A (en) * | 1991-12-30 | 1998-12-08 | Apple Computer, Inc. | Control apparatus for maintaining order and accomplishing priority promotion in a computer interconnect |
| US5410677A (en) * | 1991-12-30 | 1995-04-25 | Apple Computer, Inc. | Apparatus for translating data formats starting at an arbitrary byte position |
| US5887196A (en) * | 1991-12-30 | 1999-03-23 | Apple Computer, Inc. | System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer |
| JPH05257851A (en) * | 1991-12-30 | 1993-10-08 | Apple Computer Inc | Device for controlling order of transfer of data |
| US5640599A (en) * | 1991-12-30 | 1997-06-17 | Apple Computer, Inc. | Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed |
| KR100295074B1 (en) * | 1992-12-22 | 2001-09-17 | 리패치 | Application Custom Integrated Circuits Error Correction Code Memory Controller |
| CA2109043A1 (en) * | 1993-01-29 | 1994-07-30 | Charles R. Moore | System and method for transferring data between multiple buses |
| US5450543A (en) * | 1994-10-11 | 1995-09-12 | Ati Technologies Inc. | Flag-based high-speed I/O data transfer |
| JPH096498A (en) * | 1995-05-02 | 1997-01-10 | Symbios Logic Inc | Automatic termination of plurality of multiconnectors |
| US5937174A (en) * | 1996-06-28 | 1999-08-10 | Lsi Logic Corporation | Scalable hierarchial memory structure for high data bandwidth raid applications |
| US5881254A (en) * | 1996-06-28 | 1999-03-09 | Lsi Logic Corporation | Inter-bus bridge circuit with integrated memory port |
| US6070206A (en) * | 1997-03-31 | 2000-05-30 | Lsi Logic Corporation | Method and apparatus for terminating a bus |
| US6061806A (en) * | 1997-05-12 | 2000-05-09 | Lsi Logic Corporation | Method and apparatus for maintaining automatic termination of a bus in the event of a host failure |
| US6029216A (en) * | 1997-06-27 | 2000-02-22 | Lsi Logic Corporation | Auto-termination method and apparatus for use with either active high or active low terminators |
| US6092131A (en) * | 1997-07-28 | 2000-07-18 | Lsi Logic Corporation | Method and apparatus for terminating a bus at a device interface |
| WO2003040903A1 (en) * | 2001-11-07 | 2003-05-15 | Vitesse Semiconductor Corporation | A system and method for communicating between a number of elements and a method for configuring and testing the system |
| US7461364B2 (en) * | 2006-04-10 | 2008-12-02 | International Business Machines Corporation | Methods and readable media for using relative positioning in structures with dynamic ranges |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4296464A (en) * | 1977-03-03 | 1981-10-20 | Honeywell Inc. | Process control system with local microprocessor control means |
| US4144562A (en) * | 1977-06-23 | 1979-03-13 | Ncr Corporation | System and method for increasing microprocessor output data rate |
| US4296469A (en) * | 1978-11-17 | 1981-10-20 | Motorola, Inc. | Execution unit for data processor using segmented bus structure |
| US4321665A (en) * | 1979-01-31 | 1982-03-23 | Honeywell Information Systems Inc. | Data processing system having centralized data alignment for I/O controllers |
| US4286321A (en) * | 1979-06-18 | 1981-08-25 | International Business Machines Corporation | Common bus communication system in which the width of the address field is greater than the number of lines on the bus |
| IT1121031B (en) * | 1979-09-19 | 1986-03-26 | Olivetti & Co Spa | MULTIPROCESSOR DATA PROCESSING SYSTEM |
| JPS5652454A (en) * | 1979-10-05 | 1981-05-11 | Hitachi Ltd | Input/output control method of variable word length memory |
| US4388697A (en) * | 1980-09-08 | 1983-06-14 | Bell Telephone Laboratories, Incorporated | Voiceband data set circuitry with dual bus architecture |
| DE3265361D1 (en) * | 1981-07-10 | 1985-09-19 | Siemens Ag Albis | Bus system |
| JPS5892025A (en) * | 1981-11-26 | 1983-06-01 | Hitachi Ltd | Data processing system |
| JPS58114119A (en) * | 1981-12-26 | 1983-07-07 | Fujitsu Ltd | Data transfer controlling system |
| US4635192A (en) * | 1983-12-06 | 1987-01-06 | Tri Sigma Corporation | Self configuring bus structure for computer network |
| BG39765A1 (en) * | 1985-02-14 | 1986-08-15 | Turlakov | Device for connecting 8- degree and 16- degree modules to 16- degree microprocessor system |
| BG44841A1 (en) * | 1985-04-30 | 1989-02-15 | Khristo A Turlakov | |
| US4683534A (en) * | 1985-06-17 | 1987-07-28 | Motorola, Inc. | Method and apparatus for interfacing buses of different sizes |
-
1987
- 1987-10-23 US US07/111,642 patent/US4965723A/en not_active Expired - Lifetime
-
1988
- 1988-10-19 CA CA000580560A patent/CA1319199C/en not_active Expired - Fee Related
- 1988-10-20 JP JP63265210A patent/JPH01129344A/en active Pending
- 1988-10-21 EP EP19880117559 patent/EP0313064A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP0313064A3 (en) | 1990-09-26 |
| JPH01129344A (en) | 1989-05-22 |
| EP0313064A2 (en) | 1989-04-26 |
| US4965723A (en) | 1990-10-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1319199C (en) | Bus data path control scheme | |
| CA1183272A (en) | Synchronous data bus with automatically variable data rate | |
| US4016541A (en) | Memory unit for connection to central processor unit and interconnecting bus | |
| US5430849A (en) | Data path apparatus for IO adapter | |
| US4845609A (en) | Computer communications subsystem using an embedded token-passing network | |
| US4755937A (en) | Method and apparatus for high bandwidth shared memory | |
| US7269088B2 (en) | Identical chips with different operations in a system | |
| JPH0326865B2 (en) | ||
| US4918598A (en) | Method for selectively activating and deactivating devices having same first address and different extended addresses | |
| EP0518488A1 (en) | Bus interface and processing system | |
| US5263139A (en) | Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsystems | |
| NZ245346A (en) | Bus interface logic for computer with dual bus architecture | |
| KR850007129A (en) | Microcomputer system with bus control | |
| US4488232A (en) | Self-adjusting, distributed control, access method for a multiplexed single-signal data bus | |
| US4912627A (en) | Method for storing a second number as a command address of a first peripheral device and a third number as a command address of a second peripheral device | |
| US4593350A (en) | Distributed processor with periodic data transfer from each memory to like addresses of all other memories | |
| US5694557A (en) | Time multiplexing address and data on an existing PC parallel port | |
| US5218683A (en) | Method and apparatus for concealing the enablement of a device by modifying a status word | |
| CA1252573A (en) | Dual bus system | |
| US5961627A (en) | High speed switch for high speed connection between computers and peripheral devices | |
| CA2025511C (en) | Method and apparatus for concealing the enablement of a device by modifying a status word | |
| KR100298234B1 (en) | Communication method between multiple subsystems and apparatus | |
| US6216194B1 (en) | Information processing unit for separately controlling a plurality of shared buses | |
| KR950010948B1 (en) | Apparatus and method for relaying data in vesa local system | |
| KR100703387B1 (en) | Td-bus and p-bus interface device by used main processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |