CA1324221C - Method and apparatus for filtering invalidate requests - Google Patents
Method and apparatus for filtering invalidate requestsInfo
- Publication number
- CA1324221C CA1324221C CA000603895A CA603895A CA1324221C CA 1324221 C CA1324221 C CA 1324221C CA 000603895 A CA000603895 A CA 000603895A CA 603895 A CA603895 A CA 603895A CA 1324221 C CA1324221 C CA 1324221C
- Authority
- CA
- Canada
- Prior art keywords
- memory
- cache
- tag store
- bus
- processors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
Abstract
METHOD AND APPARATUS FOR FILTERING
INVALIDATE REQUESTS
ABSTRACT
A method and apparatus which filter the number of invalidates to be propagated onto a private processor bus are provided. This is desirable so that the processor bus is not overloaded with invalidate requests. The present invention describes a method of filtering the number of invalidates to be propagated to each processor. A memory interface filters the invalidates by using a second private bus, the invalidate bus, which communicates with the cache controller. The cache controller can tell the memory interface whether data corresponding to the address on the invalidate bus is resident in the private cache memory of that processor. In this way, the memory interface only has to request the private processor bus when necessary, in order to perform the invalidate.
INVALIDATE REQUESTS
ABSTRACT
A method and apparatus which filter the number of invalidates to be propagated onto a private processor bus are provided. This is desirable so that the processor bus is not overloaded with invalidate requests. The present invention describes a method of filtering the number of invalidates to be propagated to each processor. A memory interface filters the invalidates by using a second private bus, the invalidate bus, which communicates with the cache controller. The cache controller can tell the memory interface whether data corresponding to the address on the invalidate bus is resident in the private cache memory of that processor. In this way, the memory interface only has to request the private processor bus when necessary, in order to perform the invalidate.
Description
` ~ ~ 3242~
~ 66382-54 ;:;.' . `
.`;
,;~
~ . ~
METHOD AND APPARATUS FOR FI LTERING
, INVALIDATE REQUESTS
. '~
"~
~i This invention relates generally to computer systems , which utilize cache memory, and more specifically relates ¦ to multi-processor computer systems having multiple copies of shared data residing in any or all of the local cache ~ memories.
i~, The architecture of a typical, single-processor computing system can be viewed as some variation of the von Neumann model of computation. According to this model, instructions and data are stored in the same memory, and the processor fetches instructions one by one from the memory, executing operations on data as specified ~i .
.. .
, ., .
.
;` ` 1 324221 in the instructions. As the speed of processors has increased, there has been a need to find ways to more suitably match the access time of the main computer memory `~ to the computational speed of the processor. One known way of accomplishing this i9 through the use of cache memory which typically has a much faster access time than main memory, but can also be many times more expensive ~i~i than main memory. Accordingly, as a practical consideration, it is usually much smaller than main memory.
A cache memory contains some subset of the information stored in main memory, and resides between the processing unit and the system bus, which provides the data path between a processor and main memory. When a - processor attempts to access a main memory location that is copied in its cache ~a cache 'hit'), no access to main memory is required to provide the requested value to the CPU, and the processor can resume operation more quickly.
On the other hand, when the processor attempts to access a main memory location that is not copied in the cache (a cache 'miss'), a main memory access must occur. In this event the read data is sent to both the processor and to the cache, so that some subsequent attempts to access the memory location will result in cache hits. In this way, the effective memory access time for the processor is reduced to a value somewhere between the fast access time of the cache memory and the slower access time of main memory. Since the cache memory is usually smaller than main memory by an order of magnitude or more, the computer subsystem which controls the cache memory must employ ~; methods of determining which memory location is to ; correspond to which cache location (the mapping function), and which cache location should be overwritten in the case that a new memory location is to be written into an , already full cache (the cache replacement algorithm).
- .
.: . ~ ...... .
,:
` 1 3242~1 Judicious selection of these configuration options can result in a cache 'hit ratio' (the percentage of memory access requests that result in cache hits) of 90 to 99 percent.
; Another critical aspect of cache performance i5 the ~` procedure that mu5t be followed in order for a processing : unit to determine whether a desired memory location is also resident in that processing unit's cache memory.
Many techniques in the art exist for allowing these cache memory look-ups to be as fast and efficient as possible.
r~ The exact technique employed depends upon the particular implementation of the cache itself, especially the mapping function. Typically, however, a structure called a 'tag directory' or 'tag store' is provided to enable swift cache look-ups. A tag store i9 a table of multiple ~ entries, each entry corresponding to a block of a cache r~ memory. Traditionally, a cache block contains several main memory words, and all access to the cache is performed in units of this basic cache block size. Each tag store entry contains enough bits to specify any one of the cache blocks in the cache. When a block of data from main memory is mapped into a cache block, the tag store entry corresponding to that cache block is loaded with the higher order bits of the address of the data block in main memory. In fully associative cache designs, when the processor wants to search the cache looking for a desired main memory location, it compares the desired address to the entries in the tag store. If a match is found, the corresponding word is selected from within the multiple word cache block. In a direct mapped cache design, the least significant bits of the address of interest are used as an index into the tag store. The remaining higher order bits of the address are then compared with the tag store entries to determine a cache hit. In a set associative cache design, the least significant bits of `; I 32422 1 the address of interest are used as an index into a small number ~e.g. 2 or 4) of locations within the tag store, the indexed entries from each of these locations is .~
extracted and a comparison is performed on each of this limited number of entries in parallel to determine a cache ~` hit.
~. ., -I; A further enhancement that is useful for decreasing the average memory access time for a CPU module is to organize the cache memory in a multi-level hierarchical structure, with the smallest and fastest primary cache S memory close t to the CPU, and increasingly slower and larger secondary cache memories along the data path between a processor and main memory. Such a configuration 15 represents a compromise between the high cost of very fast memory devices and the slower access times of relatively lower cost memory devices. A cache miss in the fastest and smallest primary cache memory causes the CPU to access the next lower cache memory in the hierarchy, where the 20 larger size suggests an even greater probability of a cache hit. A cache miss here causes the CPU to access a secondary cache memory even lower in the hierarchy, and so on, until such time as a cache hit occurs in some level of s the cache structure, or a main memory access is initiated.
Along with the increase in system efficiency resulting from the use of cache memory, however, comes the problem of data coherence. That is, there must be assurance that a cache location holds the same value as 30 the main memory location to which it corresponds. One way to maintain data coherence is to write modified values of data contained in the cache memory both to the cache memory (if it is resident in the cache) and to the corresponding main memory location, each time memory write 35 access to that locàtion is requested. This method is called a "no write-allocate" write-through policy. A
.~
~, ~; - -!i ~., ~. .
-~ 5 write-through policy may alternatively allocate a memory ` location for write transactions for which the memory location is not already resident in its cache, in which ~ case the write-through policy uses a write-allocate - 5 capability. Another cache coherence technique involves a write-back policy, in which a modified data value is not written to the slower main memory until the corresponding cache location must be overwritten. The tradeoff between these policies involves the re~uirement of gre~ter 10 bandwidth at the memory subsystem level in updating main memory for each write access in a write-through policy versus the increased complexity in cache coherence in a write-back policy. In systems with sufficient bandwidth, a write-through policy is often preferred due to its 15 simplicity.
:
Recent decreases in the cost of processing units have facilitated the advent of a more radical departure from the von Neumann machine organization, in which a plurality ~ 20 of processors operate concurrently with each other, while `~ still accessing a common main memory space via a common system bus. Each processor can have its own private cache 5~ which resides between the processor and the system bus.
For such multi-processor systems, the use of cache s 25 memories is more crucial to system performance than in single processor systems, since each of the processors is in contention with the others for use of the common system bus in order to access the shared memory. The problem of data coherence is likewise more pronounced, since the 30 value stored in a single memory location might at one time be replicated in the private cache memory of any or all of the processors. If the local cache memories each employs a write-back policy, the system must somehow ensure that when one processor modifies the value of a memory location 35 and writea that modi~ication only to its cache memory, the .
,. ~
copies of that memory location in any of the other local caches reflects the change made by that one processor.
The ?resent invention is directed to a multi-S processor computer system comprising a plurality of CPU
modules which share a common memory space via a time-^` shared system bus. The common memory space can be realized as a plurality of memory modules each containing part of the shared system memory. A CPU module includes a 10 processor on which instructions are executed, a private cache memory unit and possibly additional supporting hardware for efficient control of the CPU module and coordination of ~he CPU module with other components of the system.
As is common in the art of multi-processor systems, any of the modules interfaced to the system bus can initiate one of four kinds of transactions on the bus:
v null, read, write and read data transactions. The time 20 during which one of these transactions is taking place on y the bus i9 called a bus cycle. A null transaction occurs when no module requires the bus, and is ignored by all i modules. A read transaction is one in which a CPU sends a request to a memory module to return memory data. A write 25 transaction is one in which a CPU sends a request to a memory module to write new memory data. A read data transaction is one in which a memory module returns data to a CPU module in response to a previous read transaction. Contention for use of system bus among the 30 various modules is arbitrated in some manner specific to the system bus implementation and known in the art of arbitration protocols.
As part of the support hardware associated with a CPU
35 module, known techniques in the art suggest that a structure called a Read Data Queue may be introduced , ,.
~.
: between the system bus and the CPU module. This structure holds data values that have been returned from memory in response to read transactions. The queuing of read data enhances the performance of the system by allowing a processor to accomplish other tasks while main memory i access is made, instead of waiting idly for the data to be - returned. The Read Data Queue is a first-in-first-out ^~ (FIFO) queue containing multiple entries, each of which i3~ includes a data field and a valid bit. When the CPu module receives data from main memory via a read data transaction, that data is placed on one end of the Read Data Queue, and the valid bit is set for that entry. When the CPU i9 ready to accept incoming data to put in its cache memory, the first valid entry is removed from the ~; 15 other end of the queue and the valid bit is cleared.
.~
Another FIFO structure called an Invalidate Queue may also be introduced between the system bus and the CPU
module. The Invalidate Queue also contains multiple 20 entries called 'invalidates', each including at least an address field and a valid bi~. The CPU monitors the system bus for coherence transactions. In a system employing a write-through policy, the CPU module monitors for write transactions on the system bus. When any data 25 write transaction i8 detected on the system bus, the address of that transaction is placed on one end of the CPU module's Invalidate Queue and the valid bit is set.
When the CPU is able to process an invalidate, the first valid entry is removed from the other end of the 30 Invalidate Queue and its valid bit is cleared. The ~; address of the write transaction is checked against the contents of the cache structure, and if present, the entry corresponding to that address is marked as invalid. In ~j this way, the CPU can be prevented from using data values * 35 which are outdated.
t ., .
7, ~?
' ,.
. .
The requirements for cache coherency in multi-processor systems are complex. One component of cache coherency in multi-processor systems is maintained when each cache memory processes transactions in the same order as they occurred on the system bu9. The order of ~ invalidates as they appeared on the system bus can be ;~ preserved by the FIFO queue that holds them. Similarly, the order of read data transactions can be preserved in `J. their FIFO queue. Unfortunately, however, the order of i~ 10 invalidates in relation to read data transactions, or equivalently, the order of read data transactions relative to invalidates, as they appeared on the system bus, is normally not preserved by the use of separate Read Data and Invalidate Queues.
Alternative methods of maintaining cache coherence, which do not involve the use of the queues described above, also exist in the art. For example, the system could include additional hardware providing the means for i 20 direct communication between individual processor modules;
h or, the CPU's instruction set could include commands dedicated to preserving data coherency; or, means of direct communication could be established between main memory and each individual private cache memory. Another 25 alternative would be to implement a global directory such that the system keeps track of what data is in each of the cache memories, allowing the system to invalidate data in a cache memory as required to maintain data coherence.
In implementing any of the above techniques, however, some expense is likely to be incurred, either in system ! cost or system performance. In the case of establishing paths of communication between processors or between cache memories and main memory, as well as in the case of including a global cache directory, this penalty would be primarily economic, while a modified instruction set would _9_ probably preserve data coherence at the expense of system performance.
Other systems which process every write transaction - 5 detected in order t~ preserve data coherence may suffer CPU (processor) bus saturation; that i9~ the ervicing of invalidates by each CPU for every write transaction on the system bus would occupy a large amount of the multi-~ processor system's total computational time.
',~ 10 It would therefore be advantageous to implement an j efficient means by which the number of invalidates i propagated onto a private processor bus be "filtered", such that the processor bus not be overloaded. That is, it would be advantageous to propagate onto the private ~! processor bus only those invalidates corresponding to ~ memory addresses resident in that processor's cache.
; The present invention provides a method and apparatus which enables a CPU module in a multi-processor system to "filter out" write transactions that would otherwise have no effect on the data in that CPU module's cache memory.
In this way, the system efficiency would not be as significantly decreased due to the heavy invalidate traffic generated in a multi-processor system.
A multi-processor computer system designed in accordance with this invention includes a plurality of CPU
modules interfaced to a common systems bus. These modules share access to a plurality of memory modules which define the main memory of the computer and which are also interfaced to the time-sharing system bus. The CPU
modules each include, in addition to a central processor, a local cache memory used to store some subset of the information in main memory, along with the necessary hardware to control the functioning of the cache memory.
a , . .
.
' In one embodiment of this invention, the local cache memories have a hierarchical structure consisting of a primary cache and a lar~er secondary or backup cache.
Data contained in the primary cache memory could be a ` 5 subset of the data contained in the backup cache memory, i or the sets of data in each of the cache memories could be mutually exclusive of one another. In the former case, ;~ the problem of data coherence i5 Eurther complicated by the necessity of keeping data coherent among the copies in the primary and backup cache memories of each processor module.
A processor bus in each CPU module provides the data , pa~h from the CPU to the memory interface for reading data -~ 15 from and writing data to either the main memory or to cache memory. The processor bus is also used to perform cache invalidates if they are required. A memory interface in each CPU module is responsible for connecting the local processor bus to the common time-shared system ~' 20 bus. The memory interface participates in the arbitration protocol used to manage contention for the bus among the plurality of CPU modules in the system. In addition to the processor bus, the present invention specifies that a dedicated data path be provided for direct communication between the memory interface and the cache controller logic. This dedicated data path is referred to hereinafter as the invalidate bus (I-bus) and this bus, along with the processor bus, may logically be considered as part of the memory interface.
~- 30 The filtering of potential invalidates is accomplished in the memory interface of each CPU module.
. The memory interface monitors the common system bus for memory writes from other CPU modules. When a write transaction is detected, the memory interface communicates with the cache controller via the I-bus in order to ,~ .
. .
.
1 321l~22 1 determine whether the write transaction involves a memory location copied in the cache memory hierarchy of the CPU
module. If the written location is not present anywhere in the cache memory of the cPu, the write transaction is ignored and no invalidate is forwarded to the cache controller or CPU, and the procesqor bu~ remains available for use by the CPU. If the written location is copied in ` the cache memory of the CPU module, the memory interface broadcasts the write transaction information over the processor bus, where it is received by the cache controller and the CPU to be processed as an invalidate.
In this way, invalidate traffic on the processor bus is significantly reduced.
The above-noted and other aspects of the present invention will become more apparent from a description of a preferred embodiment when read in conjunction with the accompanying drawings.
.~
The drawings illustrate a preferred embodiment of the ~: invention, wherein like members bear like reference numerals and wherein:
.~
FIG. 1 is a block diagram of a multi-processor computer system, including a plurality of memory modules comprising the shared main memory and a plurality of CPU
; modules, all interfaced to a common system bus.
FIG. 2 is a block diagram of a similar multi-- 30 processor computer system, showing two CPU modules each ~ having a two-level hierarchical cache memory, and each - interfaced to a common system bus.
FIG. 3 is a block diagram of one of the CPU modules ? 35 of FIG. 1, organized in accordance with the present invention.
.
`` 1 32422 1 ;, The general configuration of a multi-processor based ~;computer system 8 in accordance with the present invention is shown in FIG. l. A number, N, of memory modules lO
comprising the shared main memory of the system are repre9ented, being interfaced to a common system bus 12 by means dependent upon the implementation of the bus, well known in the art. In practice, the number N of memory modules lO can be any number greater than or equal to one, depending on the desired implementation of main memory.
Although the present invention is directed to computer systems utilizing two or more processor modules 14, for clarity only two are shown.
.~
FIG. 2 shows a similar multi-processor system 8 having two CPU modules 14. Each CPU module 14 employs a two-level hierarchical cache memory structure consisting of a tightly coupled primary cache and CPU unit 20, and a backup cache/cache controller unit 22. Each CPU module 14 also includes a memory interface unit 24 which is responsible for participating in an arbitration protocol for access to the system bus 12. A processor bus 30 provides the data path for communication between the CPU
20 and the backup cache/cache controller unit 22, as well as between the CPU 20 and the memory interface unit 24 of each CPU module 14. A shared main memory for the system is implemented in the form of a plurality of memory modules 10 which also are interfaced to the system bus 12.
Such an implementation and interfacing scheme for main memory is well known in the art. Furthermore, the CPU
modules 14 are typical examples of CPUs which employ a two-level cache memory heirarchy.
Cache memory invalidation in the multi-processor system 8 shown in FIG. 2 proceeds as follows: The memory interface units 24 monitor the system bus 12 and detect every write transaction that appears there. For each , . .
,~,1 !..
, ~ .
~, ';
.'.
write transaction, the memory interface units 24 send appropriate invalidation information (including the address of the write access) to both the CPU 20 and the backup cache~cache controller unit 22 via the processor bus 30 in each respective CPU module 14, The present invention describes a different configuration within its CPU modules. In particular, FIG.
; 3 shows one of the CPU modules 14 of FIG. l, designed in accordance with the present invention. The CPU modules 14 are comprised of a CPU/primary cache unit 20, a cache ` controller/backup cache unit 22, a memory interface unit ; 24, and a processor bus 30 connecting the three units together, as in the typical multi-processor system shown in FIG. 2. Included within the CPU/primary cache unit 20 is a primary cache tag store 44, providing a table of multiple entries, each entry corresponding to a block of data in the primary cache memory. An aspect of the present invention, however, is the inclusion in the cache controller unit 22 of a copy 40 of the primary cache tag store 44. Another feature depicted in FIG. 3 is an additional data path 46 between the memory interface 24 and the cache controller/backup cache unit 22. This additional data path 46 is a dedicated bus referred to as the Invalidate Bus (I-bus).
Cache memory invalidation in the system of the present invention is carried out as follows: The memory interface 24 monitors the system bus 12 in the conventional manner, monitoring write transactions. When a write transaction is detected, the memory interface forwards the address of the write access to the cache controller/backup cache unit 22 via the Invalidate Bus 46.
. The cache controller/backup cache unit 22 queries both the backup cache tag store 42 and the copy of the primary cache tag store 40 to see if the location involved in the ~ .
.
.. . . .
~'' , .
~ 1 324~2 1 write transaction i9 resident in either the primary cache tag store 44 or the backup cache tag store 42. If the ~; location of the write access is resident in either cache tag store, the memory interface unit 24 issues an invalidate on the processor bus 30, to be processed by either the CPU/primary cache unit 20 or the cache controller/backup cache unit 22 or both, in the customary manner. If the memory location involved in the write transaction is found not to be resident in either cache ;' 10 memory, no other actions need to be taken, and the -~ processor bus 30 is left free.
~j In another embodiment (not shown) the cache controller is associated directly with the CPU and no backup or secondary cache is employed. The dedicated I-BU9 46 is this embodiment is coupled directly to the CPU
and functions as herein described to filter invalidate ~, requests to the processor bus 30.
.,s The principles, preferred embodiments and modes of operation of the present invention have been described in ~;~ the foregoing specification. The invention is not to be construed as limited to the particular forms disclosed, since these are regarded as illustrative rather than restrictive. Moreover, variations and changes may be made by those skilled in that art without departing from the spirit of the invention.
~, !~
i .:
~,''.~
,,
~ 66382-54 ;:;.' . `
.`;
,;~
~ . ~
METHOD AND APPARATUS FOR FI LTERING
, INVALIDATE REQUESTS
. '~
"~
~i This invention relates generally to computer systems , which utilize cache memory, and more specifically relates ¦ to multi-processor computer systems having multiple copies of shared data residing in any or all of the local cache ~ memories.
i~, The architecture of a typical, single-processor computing system can be viewed as some variation of the von Neumann model of computation. According to this model, instructions and data are stored in the same memory, and the processor fetches instructions one by one from the memory, executing operations on data as specified ~i .
.. .
, ., .
.
;` ` 1 324221 in the instructions. As the speed of processors has increased, there has been a need to find ways to more suitably match the access time of the main computer memory `~ to the computational speed of the processor. One known way of accomplishing this i9 through the use of cache memory which typically has a much faster access time than main memory, but can also be many times more expensive ~i~i than main memory. Accordingly, as a practical consideration, it is usually much smaller than main memory.
A cache memory contains some subset of the information stored in main memory, and resides between the processing unit and the system bus, which provides the data path between a processor and main memory. When a - processor attempts to access a main memory location that is copied in its cache ~a cache 'hit'), no access to main memory is required to provide the requested value to the CPU, and the processor can resume operation more quickly.
On the other hand, when the processor attempts to access a main memory location that is not copied in the cache (a cache 'miss'), a main memory access must occur. In this event the read data is sent to both the processor and to the cache, so that some subsequent attempts to access the memory location will result in cache hits. In this way, the effective memory access time for the processor is reduced to a value somewhere between the fast access time of the cache memory and the slower access time of main memory. Since the cache memory is usually smaller than main memory by an order of magnitude or more, the computer subsystem which controls the cache memory must employ ~; methods of determining which memory location is to ; correspond to which cache location (the mapping function), and which cache location should be overwritten in the case that a new memory location is to be written into an , already full cache (the cache replacement algorithm).
- .
.: . ~ ...... .
,:
` 1 3242~1 Judicious selection of these configuration options can result in a cache 'hit ratio' (the percentage of memory access requests that result in cache hits) of 90 to 99 percent.
; Another critical aspect of cache performance i5 the ~` procedure that mu5t be followed in order for a processing : unit to determine whether a desired memory location is also resident in that processing unit's cache memory.
Many techniques in the art exist for allowing these cache memory look-ups to be as fast and efficient as possible.
r~ The exact technique employed depends upon the particular implementation of the cache itself, especially the mapping function. Typically, however, a structure called a 'tag directory' or 'tag store' is provided to enable swift cache look-ups. A tag store i9 a table of multiple ~ entries, each entry corresponding to a block of a cache r~ memory. Traditionally, a cache block contains several main memory words, and all access to the cache is performed in units of this basic cache block size. Each tag store entry contains enough bits to specify any one of the cache blocks in the cache. When a block of data from main memory is mapped into a cache block, the tag store entry corresponding to that cache block is loaded with the higher order bits of the address of the data block in main memory. In fully associative cache designs, when the processor wants to search the cache looking for a desired main memory location, it compares the desired address to the entries in the tag store. If a match is found, the corresponding word is selected from within the multiple word cache block. In a direct mapped cache design, the least significant bits of the address of interest are used as an index into the tag store. The remaining higher order bits of the address are then compared with the tag store entries to determine a cache hit. In a set associative cache design, the least significant bits of `; I 32422 1 the address of interest are used as an index into a small number ~e.g. 2 or 4) of locations within the tag store, the indexed entries from each of these locations is .~
extracted and a comparison is performed on each of this limited number of entries in parallel to determine a cache ~` hit.
~. ., -I; A further enhancement that is useful for decreasing the average memory access time for a CPU module is to organize the cache memory in a multi-level hierarchical structure, with the smallest and fastest primary cache S memory close t to the CPU, and increasingly slower and larger secondary cache memories along the data path between a processor and main memory. Such a configuration 15 represents a compromise between the high cost of very fast memory devices and the slower access times of relatively lower cost memory devices. A cache miss in the fastest and smallest primary cache memory causes the CPU to access the next lower cache memory in the hierarchy, where the 20 larger size suggests an even greater probability of a cache hit. A cache miss here causes the CPU to access a secondary cache memory even lower in the hierarchy, and so on, until such time as a cache hit occurs in some level of s the cache structure, or a main memory access is initiated.
Along with the increase in system efficiency resulting from the use of cache memory, however, comes the problem of data coherence. That is, there must be assurance that a cache location holds the same value as 30 the main memory location to which it corresponds. One way to maintain data coherence is to write modified values of data contained in the cache memory both to the cache memory (if it is resident in the cache) and to the corresponding main memory location, each time memory write 35 access to that locàtion is requested. This method is called a "no write-allocate" write-through policy. A
.~
~, ~; - -!i ~., ~. .
-~ 5 write-through policy may alternatively allocate a memory ` location for write transactions for which the memory location is not already resident in its cache, in which ~ case the write-through policy uses a write-allocate - 5 capability. Another cache coherence technique involves a write-back policy, in which a modified data value is not written to the slower main memory until the corresponding cache location must be overwritten. The tradeoff between these policies involves the re~uirement of gre~ter 10 bandwidth at the memory subsystem level in updating main memory for each write access in a write-through policy versus the increased complexity in cache coherence in a write-back policy. In systems with sufficient bandwidth, a write-through policy is often preferred due to its 15 simplicity.
:
Recent decreases in the cost of processing units have facilitated the advent of a more radical departure from the von Neumann machine organization, in which a plurality ~ 20 of processors operate concurrently with each other, while `~ still accessing a common main memory space via a common system bus. Each processor can have its own private cache 5~ which resides between the processor and the system bus.
For such multi-processor systems, the use of cache s 25 memories is more crucial to system performance than in single processor systems, since each of the processors is in contention with the others for use of the common system bus in order to access the shared memory. The problem of data coherence is likewise more pronounced, since the 30 value stored in a single memory location might at one time be replicated in the private cache memory of any or all of the processors. If the local cache memories each employs a write-back policy, the system must somehow ensure that when one processor modifies the value of a memory location 35 and writea that modi~ication only to its cache memory, the .
,. ~
copies of that memory location in any of the other local caches reflects the change made by that one processor.
The ?resent invention is directed to a multi-S processor computer system comprising a plurality of CPU
modules which share a common memory space via a time-^` shared system bus. The common memory space can be realized as a plurality of memory modules each containing part of the shared system memory. A CPU module includes a 10 processor on which instructions are executed, a private cache memory unit and possibly additional supporting hardware for efficient control of the CPU module and coordination of ~he CPU module with other components of the system.
As is common in the art of multi-processor systems, any of the modules interfaced to the system bus can initiate one of four kinds of transactions on the bus:
v null, read, write and read data transactions. The time 20 during which one of these transactions is taking place on y the bus i9 called a bus cycle. A null transaction occurs when no module requires the bus, and is ignored by all i modules. A read transaction is one in which a CPU sends a request to a memory module to return memory data. A write 25 transaction is one in which a CPU sends a request to a memory module to write new memory data. A read data transaction is one in which a memory module returns data to a CPU module in response to a previous read transaction. Contention for use of system bus among the 30 various modules is arbitrated in some manner specific to the system bus implementation and known in the art of arbitration protocols.
As part of the support hardware associated with a CPU
35 module, known techniques in the art suggest that a structure called a Read Data Queue may be introduced , ,.
~.
: between the system bus and the CPU module. This structure holds data values that have been returned from memory in response to read transactions. The queuing of read data enhances the performance of the system by allowing a processor to accomplish other tasks while main memory i access is made, instead of waiting idly for the data to be - returned. The Read Data Queue is a first-in-first-out ^~ (FIFO) queue containing multiple entries, each of which i3~ includes a data field and a valid bit. When the CPu module receives data from main memory via a read data transaction, that data is placed on one end of the Read Data Queue, and the valid bit is set for that entry. When the CPU i9 ready to accept incoming data to put in its cache memory, the first valid entry is removed from the ~; 15 other end of the queue and the valid bit is cleared.
.~
Another FIFO structure called an Invalidate Queue may also be introduced between the system bus and the CPU
module. The Invalidate Queue also contains multiple 20 entries called 'invalidates', each including at least an address field and a valid bi~. The CPU monitors the system bus for coherence transactions. In a system employing a write-through policy, the CPU module monitors for write transactions on the system bus. When any data 25 write transaction i8 detected on the system bus, the address of that transaction is placed on one end of the CPU module's Invalidate Queue and the valid bit is set.
When the CPU is able to process an invalidate, the first valid entry is removed from the other end of the 30 Invalidate Queue and its valid bit is cleared. The ~; address of the write transaction is checked against the contents of the cache structure, and if present, the entry corresponding to that address is marked as invalid. In ~j this way, the CPU can be prevented from using data values * 35 which are outdated.
t ., .
7, ~?
' ,.
. .
The requirements for cache coherency in multi-processor systems are complex. One component of cache coherency in multi-processor systems is maintained when each cache memory processes transactions in the same order as they occurred on the system bu9. The order of ~ invalidates as they appeared on the system bus can be ;~ preserved by the FIFO queue that holds them. Similarly, the order of read data transactions can be preserved in `J. their FIFO queue. Unfortunately, however, the order of i~ 10 invalidates in relation to read data transactions, or equivalently, the order of read data transactions relative to invalidates, as they appeared on the system bus, is normally not preserved by the use of separate Read Data and Invalidate Queues.
Alternative methods of maintaining cache coherence, which do not involve the use of the queues described above, also exist in the art. For example, the system could include additional hardware providing the means for i 20 direct communication between individual processor modules;
h or, the CPU's instruction set could include commands dedicated to preserving data coherency; or, means of direct communication could be established between main memory and each individual private cache memory. Another 25 alternative would be to implement a global directory such that the system keeps track of what data is in each of the cache memories, allowing the system to invalidate data in a cache memory as required to maintain data coherence.
In implementing any of the above techniques, however, some expense is likely to be incurred, either in system ! cost or system performance. In the case of establishing paths of communication between processors or between cache memories and main memory, as well as in the case of including a global cache directory, this penalty would be primarily economic, while a modified instruction set would _9_ probably preserve data coherence at the expense of system performance.
Other systems which process every write transaction - 5 detected in order t~ preserve data coherence may suffer CPU (processor) bus saturation; that i9~ the ervicing of invalidates by each CPU for every write transaction on the system bus would occupy a large amount of the multi-~ processor system's total computational time.
',~ 10 It would therefore be advantageous to implement an j efficient means by which the number of invalidates i propagated onto a private processor bus be "filtered", such that the processor bus not be overloaded. That is, it would be advantageous to propagate onto the private ~! processor bus only those invalidates corresponding to ~ memory addresses resident in that processor's cache.
; The present invention provides a method and apparatus which enables a CPU module in a multi-processor system to "filter out" write transactions that would otherwise have no effect on the data in that CPU module's cache memory.
In this way, the system efficiency would not be as significantly decreased due to the heavy invalidate traffic generated in a multi-processor system.
A multi-processor computer system designed in accordance with this invention includes a plurality of CPU
modules interfaced to a common systems bus. These modules share access to a plurality of memory modules which define the main memory of the computer and which are also interfaced to the time-sharing system bus. The CPU
modules each include, in addition to a central processor, a local cache memory used to store some subset of the information in main memory, along with the necessary hardware to control the functioning of the cache memory.
a , . .
.
' In one embodiment of this invention, the local cache memories have a hierarchical structure consisting of a primary cache and a lar~er secondary or backup cache.
Data contained in the primary cache memory could be a ` 5 subset of the data contained in the backup cache memory, i or the sets of data in each of the cache memories could be mutually exclusive of one another. In the former case, ;~ the problem of data coherence i5 Eurther complicated by the necessity of keeping data coherent among the copies in the primary and backup cache memories of each processor module.
A processor bus in each CPU module provides the data , pa~h from the CPU to the memory interface for reading data -~ 15 from and writing data to either the main memory or to cache memory. The processor bus is also used to perform cache invalidates if they are required. A memory interface in each CPU module is responsible for connecting the local processor bus to the common time-shared system ~' 20 bus. The memory interface participates in the arbitration protocol used to manage contention for the bus among the plurality of CPU modules in the system. In addition to the processor bus, the present invention specifies that a dedicated data path be provided for direct communication between the memory interface and the cache controller logic. This dedicated data path is referred to hereinafter as the invalidate bus (I-bus) and this bus, along with the processor bus, may logically be considered as part of the memory interface.
~- 30 The filtering of potential invalidates is accomplished in the memory interface of each CPU module.
. The memory interface monitors the common system bus for memory writes from other CPU modules. When a write transaction is detected, the memory interface communicates with the cache controller via the I-bus in order to ,~ .
. .
.
1 321l~22 1 determine whether the write transaction involves a memory location copied in the cache memory hierarchy of the CPU
module. If the written location is not present anywhere in the cache memory of the cPu, the write transaction is ignored and no invalidate is forwarded to the cache controller or CPU, and the procesqor bu~ remains available for use by the CPU. If the written location is copied in ` the cache memory of the CPU module, the memory interface broadcasts the write transaction information over the processor bus, where it is received by the cache controller and the CPU to be processed as an invalidate.
In this way, invalidate traffic on the processor bus is significantly reduced.
The above-noted and other aspects of the present invention will become more apparent from a description of a preferred embodiment when read in conjunction with the accompanying drawings.
.~
The drawings illustrate a preferred embodiment of the ~: invention, wherein like members bear like reference numerals and wherein:
.~
FIG. 1 is a block diagram of a multi-processor computer system, including a plurality of memory modules comprising the shared main memory and a plurality of CPU
; modules, all interfaced to a common system bus.
FIG. 2 is a block diagram of a similar multi-- 30 processor computer system, showing two CPU modules each ~ having a two-level hierarchical cache memory, and each - interfaced to a common system bus.
FIG. 3 is a block diagram of one of the CPU modules ? 35 of FIG. 1, organized in accordance with the present invention.
.
`` 1 32422 1 ;, The general configuration of a multi-processor based ~;computer system 8 in accordance with the present invention is shown in FIG. l. A number, N, of memory modules lO
comprising the shared main memory of the system are repre9ented, being interfaced to a common system bus 12 by means dependent upon the implementation of the bus, well known in the art. In practice, the number N of memory modules lO can be any number greater than or equal to one, depending on the desired implementation of main memory.
Although the present invention is directed to computer systems utilizing two or more processor modules 14, for clarity only two are shown.
.~
FIG. 2 shows a similar multi-processor system 8 having two CPU modules 14. Each CPU module 14 employs a two-level hierarchical cache memory structure consisting of a tightly coupled primary cache and CPU unit 20, and a backup cache/cache controller unit 22. Each CPU module 14 also includes a memory interface unit 24 which is responsible for participating in an arbitration protocol for access to the system bus 12. A processor bus 30 provides the data path for communication between the CPU
20 and the backup cache/cache controller unit 22, as well as between the CPU 20 and the memory interface unit 24 of each CPU module 14. A shared main memory for the system is implemented in the form of a plurality of memory modules 10 which also are interfaced to the system bus 12.
Such an implementation and interfacing scheme for main memory is well known in the art. Furthermore, the CPU
modules 14 are typical examples of CPUs which employ a two-level cache memory heirarchy.
Cache memory invalidation in the multi-processor system 8 shown in FIG. 2 proceeds as follows: The memory interface units 24 monitor the system bus 12 and detect every write transaction that appears there. For each , . .
,~,1 !..
, ~ .
~, ';
.'.
write transaction, the memory interface units 24 send appropriate invalidation information (including the address of the write access) to both the CPU 20 and the backup cache~cache controller unit 22 via the processor bus 30 in each respective CPU module 14, The present invention describes a different configuration within its CPU modules. In particular, FIG.
; 3 shows one of the CPU modules 14 of FIG. l, designed in accordance with the present invention. The CPU modules 14 are comprised of a CPU/primary cache unit 20, a cache ` controller/backup cache unit 22, a memory interface unit ; 24, and a processor bus 30 connecting the three units together, as in the typical multi-processor system shown in FIG. 2. Included within the CPU/primary cache unit 20 is a primary cache tag store 44, providing a table of multiple entries, each entry corresponding to a block of data in the primary cache memory. An aspect of the present invention, however, is the inclusion in the cache controller unit 22 of a copy 40 of the primary cache tag store 44. Another feature depicted in FIG. 3 is an additional data path 46 between the memory interface 24 and the cache controller/backup cache unit 22. This additional data path 46 is a dedicated bus referred to as the Invalidate Bus (I-bus).
Cache memory invalidation in the system of the present invention is carried out as follows: The memory interface 24 monitors the system bus 12 in the conventional manner, monitoring write transactions. When a write transaction is detected, the memory interface forwards the address of the write access to the cache controller/backup cache unit 22 via the Invalidate Bus 46.
. The cache controller/backup cache unit 22 queries both the backup cache tag store 42 and the copy of the primary cache tag store 40 to see if the location involved in the ~ .
.
.. . . .
~'' , .
~ 1 324~2 1 write transaction i9 resident in either the primary cache tag store 44 or the backup cache tag store 42. If the ~; location of the write access is resident in either cache tag store, the memory interface unit 24 issues an invalidate on the processor bus 30, to be processed by either the CPU/primary cache unit 20 or the cache controller/backup cache unit 22 or both, in the customary manner. If the memory location involved in the write transaction is found not to be resident in either cache ;' 10 memory, no other actions need to be taken, and the -~ processor bus 30 is left free.
~j In another embodiment (not shown) the cache controller is associated directly with the CPU and no backup or secondary cache is employed. The dedicated I-BU9 46 is this embodiment is coupled directly to the CPU
and functions as herein described to filter invalidate ~, requests to the processor bus 30.
.,s The principles, preferred embodiments and modes of operation of the present invention have been described in ~;~ the foregoing specification. The invention is not to be construed as limited to the particular forms disclosed, since these are regarded as illustrative rather than restrictive. Moreover, variations and changes may be made by those skilled in that art without departing from the spirit of the invention.
~, !~
i .:
~,''.~
,,
Claims (8)
1. A method of operating a computer system, the computer system having a main memory for storing blocks of data, said computer system further having a plurality of processors capable of issuing write transactions defining invalidate requests, said computer system further having a system bus for intercoupling said main memory and said processors, each of said processors having an associated primary cache memory for storing a subset of the data stored in said main memory and a primary cache tag store for indentifying blocks of memory addresses resident in said primary cache memory, each of said processors further having a memory interface for detecting write transactions on said system bus, each of said processors further having a cache controller coupled to said memory interface by an invalidate bus, said cache controller including a secondary cache memory for storing a subset of the data stored in said main memory and a secondary cache tag store for identifying blocks of memory addresses resident in said secondary cache memory, said cache controller further including a copy of the primary cache tag store, said method of operating including filtering invalidate requests by the steps of:
a. detecting a write transaction on the system bus, said write transaction defining a memory location in said main memory;
b. forwarding the memory address so defined to the cache controller by way of said invalidate bus;
c. comparing said memory address to memory addresses indicated in said secondary cache tag store and in said copy of the primary cache tag store; and d. if said memory address is indicated in said secondary cache tag store or in said copy of the primary cache tag store, issuing an invalidate request, otherwise ignoring said write transaction.
a. detecting a write transaction on the system bus, said write transaction defining a memory location in said main memory;
b. forwarding the memory address so defined to the cache controller by way of said invalidate bus;
c. comparing said memory address to memory addresses indicated in said secondary cache tag store and in said copy of the primary cache tag store; and d. if said memory address is indicated in said secondary cache tag store or in said copy of the primary cache tag store, issuing an invalidate request, otherwise ignoring said write transaction.
2. A computer system comprising:
a. a main memory means including a plurality of addressable storage locations for storing data and for generating memory control signals;
b. a plurality of processors for processing data, each of said processors including:
i. a central processing unit for processing data in response to instructions and for initiating transactions that access addressable storage locations in said main memory means, said central processing unit including a primary cache memory for storing a subset of the data stored in said main memory and a primary cache tag store for indicating memory addresses of the data stored in said primary cache memory; and ii. a cache controller including a secondary cache memory for storing a subset of the data stored in said main memory, a secondary cache tag store for indicating memory addresses of the data stored in said secondary cache memory and a primary cache tag store copy means for storing a copy of said primary cache tag store;
d. a system bus for intercoupling said main memory and said processors and for intercoupling each of said processors to any other processor;
e. each of said processors further including a memory interface, said memory interface including i. coupling means coupling said memory interface to said system bus for monitoring write transactions on said system bus;
ii. receiving means for receiving write transactions detected on said system bus;
iii. invalidate bus means for transmitting memory addresses associated with detected write transactions to said cache controller; and iv. processors bus means for coupling said receiving means with said cache controller and with said central processing unit wherein, if a memory address transmitted by said receiving means to said cache controller is resident in either the primary cache tag store or in said secondary cache tag store, the memory address is transmitted on said processor bus as an invalidate, otherwise, said write transaction is ignored by said processor.
a. a main memory means including a plurality of addressable storage locations for storing data and for generating memory control signals;
b. a plurality of processors for processing data, each of said processors including:
i. a central processing unit for processing data in response to instructions and for initiating transactions that access addressable storage locations in said main memory means, said central processing unit including a primary cache memory for storing a subset of the data stored in said main memory and a primary cache tag store for indicating memory addresses of the data stored in said primary cache memory; and ii. a cache controller including a secondary cache memory for storing a subset of the data stored in said main memory, a secondary cache tag store for indicating memory addresses of the data stored in said secondary cache memory and a primary cache tag store copy means for storing a copy of said primary cache tag store;
d. a system bus for intercoupling said main memory and said processors and for intercoupling each of said processors to any other processor;
e. each of said processors further including a memory interface, said memory interface including i. coupling means coupling said memory interface to said system bus for monitoring write transactions on said system bus;
ii. receiving means for receiving write transactions detected on said system bus;
iii. invalidate bus means for transmitting memory addresses associated with detected write transactions to said cache controller; and iv. processors bus means for coupling said receiving means with said cache controller and with said central processing unit wherein, if a memory address transmitted by said receiving means to said cache controller is resident in either the primary cache tag store or in said secondary cache tag store, the memory address is transmitted on said processor bus as an invalidate, otherwise, said write transaction is ignored by said processor.
3. A method of operating a computer system, the computer system having a main memory for storing blocks of data, said computer system further having a plurality of processors each of said processors capable of issuing write transactions defining invalidate requests, said computer system further having a system bus for intercoupling said main memory and said processors, each of said processors having an associated primary cache memory for storing a subset of the data stored in said main memory and a primary cache tag store for identifying blocks of memory addresses resident in said primary cache memory, each of said processors further having a memory interface for detecting write transactions on said system bus, each of said processors further having a cache controller coupled to said memory interface by an invalidate bus, said cache controller including a copy of the primary cache tag store, said method of operating including filtering invalidate requests by the steps of:
a. detecting a write transaction on the system bus, said write transaction defining a memory location in said main memory;
b. forwarding the memory address so defined to the cache controller by way of said invalidate bus;
c. comparing said memory address to memory addresses identified in said copy of the primary cache tag store; and d. if said memory address is indicated in said copy of the primary cache tag store, issuing an invalidate request, otherwise ignoring said write transaction.
a. detecting a write transaction on the system bus, said write transaction defining a memory location in said main memory;
b. forwarding the memory address so defined to the cache controller by way of said invalidate bus;
c. comparing said memory address to memory addresses identified in said copy of the primary cache tag store; and d. if said memory address is indicated in said copy of the primary cache tag store, issuing an invalidate request, otherwise ignoring said write transaction.
4. A method according to claim 3 wherein said cache controller includes a secondary cache memory for storing a subset of the data stored in said main memory and a secondary cache tag store for identifying blocks of memory addresses resident in said secondary cache memory.
5. A method according to claim 4 including the steps of comparing said memory address to memory addresses identified in said secondary cache tag store, and if said memory address is indicated in said secondary cache tag store issuing said invalidate request.
6. A computer system comprising:
a. a main memory means including a plurality of addressable storage locations for storing data and for generating memory control signals;
b. a plurality of processors for processing data, each of said processors including:
i. a central processing unit for processing data in response to instructions and for initiating transactions that access addressable storage locations in said main memory means, said central processing unit including a cache memory for storing a subset of the data stored in said main memory and a cache tag store for indicating memory addresses of the data stored in said primary cache memory; and ii. a cache controller including a cache tag store copy means for storing a copy of said cache tag store;
c. a system bus for intercoupling said main memory and said processors and for intercoupling each of said processors to any other processor;
d. each of said processors further including a memory interface coupled to said system bus, said memory interface including i. receiving means for receiving write transactions detected on said system bus;
ii. invalidate bus means for transmitting memory addresses associated with detected write transactions to said cache controller; and iii. processor bus means for coupling said memory interface with said central processing unit; wherein, if a memory address transmitted by said receiving means to said cache controller is resident in either the primary cache tag store or in said copy of said cache tag store, the memory address is transmitted on said processor bus as an invalidate, otherwise, said write transaction is ignored by said processor.
a. a main memory means including a plurality of addressable storage locations for storing data and for generating memory control signals;
b. a plurality of processors for processing data, each of said processors including:
i. a central processing unit for processing data in response to instructions and for initiating transactions that access addressable storage locations in said main memory means, said central processing unit including a cache memory for storing a subset of the data stored in said main memory and a cache tag store for indicating memory addresses of the data stored in said primary cache memory; and ii. a cache controller including a cache tag store copy means for storing a copy of said cache tag store;
c. a system bus for intercoupling said main memory and said processors and for intercoupling each of said processors to any other processor;
d. each of said processors further including a memory interface coupled to said system bus, said memory interface including i. receiving means for receiving write transactions detected on said system bus;
ii. invalidate bus means for transmitting memory addresses associated with detected write transactions to said cache controller; and iii. processor bus means for coupling said memory interface with said central processing unit; wherein, if a memory address transmitted by said receiving means to said cache controller is resident in either the primary cache tag store or in said copy of said cache tag store, the memory address is transmitted on said processor bus as an invalidate, otherwise, said write transaction is ignored by said processor.
7. A computer system according to claim 6 wherein said cache controller includes a secondary cache memory for storing a subset of the data stored in said main memory and a secondary cache tag store for identifying blocks of memory addresses resident in said secondary cache memory.
8. A computer system according to claim 7 wherein, if a memory address transmitted by said receiving means to said cache controller is resident in either said copy of said cache tag store or in said secondary cache tag store, the memory address is transmitted on said processor bus as an invalidate, otherwise, said write transaction is ignored by said processor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/212,416 US5058006A (en) | 1988-06-27 | 1988-06-27 | Method and apparatus for filtering invalidate requests |
| US212,416 | 1988-06-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1324221C true CA1324221C (en) | 1993-11-09 |
Family
ID=22790922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000603895A Expired - Fee Related CA1324221C (en) | 1988-06-27 | 1989-06-26 | Method and apparatus for filtering invalidate requests |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5058006A (en) |
| EP (1) | EP0349122B1 (en) |
| JP (1) | JP2662603B2 (en) |
| CA (1) | CA1324221C (en) |
| DE (1) | DE68924206T2 (en) |
Families Citing this family (76)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5226146A (en) * | 1988-10-28 | 1993-07-06 | Hewlett-Packard Company | Duplicate tag store purge queue |
| CA2011807C (en) * | 1989-03-20 | 1999-02-23 | Katsumi Hayashi | Data base processing system using multiprocessor system |
| US5287484A (en) * | 1989-06-21 | 1994-02-15 | Hitachi, Ltd. | Multi-processor system for invalidating hierarchical cache |
| JPH0348951A (en) * | 1989-07-18 | 1991-03-01 | Fujitsu Ltd | Address monitor device |
| US5283886A (en) * | 1989-08-11 | 1994-02-01 | Hitachi, Ltd. | Multiprocessor cache system having three states for generating invalidating signals upon write accesses |
| JP2509344B2 (en) * | 1989-09-19 | 1996-06-19 | 富士通株式会社 | Data processing device |
| US5307477A (en) * | 1989-12-01 | 1994-04-26 | Mips Computer Systems, Inc. | Two-level cache memory system |
| US5212781A (en) * | 1990-03-21 | 1993-05-18 | Chips And Technologies, Inc. | Secondary cache control for a computer system |
| US5289585A (en) * | 1990-03-26 | 1994-02-22 | Siemens Nixdorf Informationssysteme Ag | Multiprocessor system having a system bus for the coupling of several processing units with appertaining private cache memories and a common main memory |
| JP2986176B2 (en) * | 1990-05-11 | 1999-12-06 | 株式会社日立製作所 | Bus right control system and bus system |
| US5325510A (en) * | 1990-05-25 | 1994-06-28 | Texas Instruments Incorporated | Multiprocessor system and architecture with a computation system for minimizing duplicate read requests |
| EP0468831B1 (en) * | 1990-06-29 | 1997-10-15 | Digital Equipment Corporation | Bus protocol for write-back cache processor |
| CA2045756C (en) * | 1990-06-29 | 1996-08-20 | Gregg Bouchard | Combined queue for invalidates and return data in multiprocessor system |
| US5287512A (en) * | 1990-08-06 | 1994-02-15 | Ncr Corporation | Computer memory system and method for cleaning data elements |
| US5276852A (en) * | 1990-10-01 | 1994-01-04 | Digital Equipment Corporation | Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions |
| IE860318L (en) * | 1990-10-01 | 1986-08-05 | Digital Equipment Corp | System bus for a multi-cache data processing system |
| US5673394A (en) * | 1990-10-31 | 1997-09-30 | Microsoft Corporation | Method of sharing memory between an operating system and an application program |
| US5249282A (en) * | 1990-11-21 | 1993-09-28 | Benchmarq Microelectronics, Inc. | Integrated cache memory system with primary and secondary cache memories |
| US5249283A (en) * | 1990-12-24 | 1993-09-28 | Ncr Corporation | Cache coherency method and apparatus for a multiple path interconnection network |
| JPH04328657A (en) * | 1991-04-30 | 1992-11-17 | Toshiba Corp | Cache memory |
| US5293603A (en) * | 1991-06-04 | 1994-03-08 | Intel Corporation | Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path |
| US5530835A (en) * | 1991-09-18 | 1996-06-25 | Ncr Corporation | Computer memory data merging technique for computers with write-back caches |
| EP0541319B1 (en) * | 1991-11-04 | 1997-05-02 | Sun Microsystems, Inc. | Write through virtual cache memory, alias addressing, and cache flushes |
| US5649154A (en) * | 1992-02-27 | 1997-07-15 | Hewlett-Packard Company | Cache memory system having secondary cache integrated with primary cache for use with VLSI circuits |
| US5528755A (en) * | 1992-12-22 | 1996-06-18 | International Business Machines Corporation | Invalid data detection, recording and nullification |
| JP2819982B2 (en) * | 1993-03-18 | 1998-11-05 | 株式会社日立製作所 | Multiprocessor system with cache match guarantee function that can specify range |
| US5506967A (en) * | 1993-06-15 | 1996-04-09 | Unisys Corporation | Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures |
| US5640531A (en) * | 1993-06-22 | 1997-06-17 | Unisys Corporation | Enhanced computer operational system using auxiliary mini-cache for enhancement to general cache |
| US5598551A (en) * | 1993-07-16 | 1997-01-28 | Unisys Corporation | Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles |
| US5604882A (en) * | 1993-08-27 | 1997-02-18 | International Business Machines Corporation | System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data processing system |
| US5636365A (en) * | 1993-10-05 | 1997-06-03 | Nec Corporation | Hierarchical buffer memories for selectively controlling data coherence including coherence control request means |
| JP3200757B2 (en) * | 1993-10-22 | 2001-08-20 | 株式会社日立製作所 | Storage control method for parallel computer and parallel computer |
| US5572704A (en) * | 1993-12-15 | 1996-11-05 | Silicon Graphics, Inc. | System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes |
| US5832534A (en) * | 1994-01-04 | 1998-11-03 | Intel Corporation | Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories |
| US5671391A (en) * | 1994-01-10 | 1997-09-23 | Ncr Corporation | Coherent copyback protocol for multi-level cache memory systems |
| JP2634141B2 (en) * | 1994-01-19 | 1997-07-23 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Multiprocessor system |
| US5603004A (en) * | 1994-02-14 | 1997-02-11 | Hewlett-Packard Company | Method for decreasing time penalty resulting from a cache miss in a multi-level cache system |
| JPH07334450A (en) * | 1994-06-10 | 1995-12-22 | Mitsubishi Denki Semiconductor Software Kk | Interface device |
| JPH08185359A (en) * | 1994-10-31 | 1996-07-16 | Toshiba Corp | Memory subsystem |
| US5603005A (en) * | 1994-12-27 | 1997-02-11 | Unisys Corporation | Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed |
| US5717942A (en) * | 1994-12-27 | 1998-02-10 | Unisys Corporation | Reset for independent partitions within a computer system |
| US5701313A (en) * | 1995-02-24 | 1997-12-23 | Unisys Corporation | Method and apparatus for removing soft errors from a memory |
| US5511164A (en) * | 1995-03-01 | 1996-04-23 | Unisys Corporation | Method and apparatus for determining the source and nature of an error within a computer system |
| US5581729A (en) * | 1995-03-31 | 1996-12-03 | Sun Microsystems, Inc. | Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system |
| DE69628079T2 (en) * | 1995-03-31 | 2004-02-26 | Sun Microsystems, Inc., Santa Clara | System level mechanism to devalue data stored in the external cache of a processor in a computer system |
| US5657472A (en) * | 1995-03-31 | 1997-08-12 | Sun Microsystems, Inc. | Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor |
| US5696937A (en) * | 1995-04-28 | 1997-12-09 | Unisys Corporation | Cache controller utilizing a state machine for controlling invalidations in a network with dual system busses |
| US5737756A (en) * | 1995-04-28 | 1998-04-07 | Unisys Corporation | Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue |
| US5612865A (en) * | 1995-06-01 | 1997-03-18 | Ncr Corporation | Dynamic hashing method for optimal distribution of locks within a clustered system |
| US5699500A (en) * | 1995-06-01 | 1997-12-16 | Ncr Corporation | Reliable datagram service provider for fast messaging in a clustered environment |
| US5822611A (en) * | 1995-06-05 | 1998-10-13 | Donley; Greggory D. | Method for cycle request with quick termination without waiting for the cycle to reach the destination by storing information in queue |
| US5740400A (en) * | 1995-06-05 | 1998-04-14 | Advanced Micro Devices Inc. | Reducing cache snooping overhead in a multilevel cache system with multiple bus masters and a shared level two cache by using an inclusion field |
| US5778437A (en) * | 1995-09-25 | 1998-07-07 | International Business Machines Corporation | Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory |
| US5745728A (en) * | 1995-12-13 | 1998-04-28 | International Business Machines Corporation | Process or renders repeat operation instructions non-cacheable |
| US6070233A (en) * | 1996-01-26 | 2000-05-30 | Unisys Corporation | Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache |
| US5687348A (en) * | 1996-01-29 | 1997-11-11 | Unisys Corporation | Variable-depth, self-regulating cache queue flushing system |
| US5835946A (en) * | 1996-04-18 | 1998-11-10 | International Business Machines Corporation | High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations |
| US5822763A (en) * | 1996-04-19 | 1998-10-13 | Ibm Corporation | Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors |
| US5920892A (en) * | 1996-08-26 | 1999-07-06 | Unisys Corporation | Method and system for inhibiting transfer of duplicate write addresses in multi-domain processor systems with cross-bus architecture to reduce cross-invalidation requests |
| US6065097A (en) * | 1996-08-29 | 2000-05-16 | Sun Microsystems, Inc. | Apparatus and method for sharing a unified memory bus between external cache memory and primary memory |
| US6202125B1 (en) | 1996-11-25 | 2001-03-13 | Intel Corporation | Processor-cache protocol using simple commands to implement a range of cache configurations |
| US6279098B1 (en) | 1996-12-16 | 2001-08-21 | Unisys Corporation | Method of and apparatus for serial dynamic system partitioning |
| US5875201A (en) * | 1996-12-30 | 1999-02-23 | Unisys Corporation | Second level cache having instruction cache parity error control |
| US5960455A (en) * | 1996-12-30 | 1999-09-28 | Unisys Corporation | Scalable cross bar type storage controller |
| US5970253A (en) * | 1997-01-09 | 1999-10-19 | Unisys Corporation | Priority logic for selecting and stacking data |
| US5822766A (en) * | 1997-01-09 | 1998-10-13 | Unisys Corporation | Main memory interface for high speed data transfer |
| US5860093A (en) * | 1997-01-21 | 1999-01-12 | Unisys Corporation | Reduced instruction processor/storage controller interface |
| US6209072B1 (en) | 1997-05-06 | 2001-03-27 | Intel Corporation | Source synchronous interface between master and slave using a deskew latch |
| US6000015A (en) * | 1997-09-16 | 1999-12-07 | Unisys Corporation | Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cache |
| US6295598B1 (en) * | 1998-06-30 | 2001-09-25 | Src Computers, Inc. | Split directory-based cache coherency technique for a multi-processor computer system |
| US7174401B2 (en) * | 2002-02-28 | 2007-02-06 | Lsi Logic Corporation | Look ahead split release for a data bus |
| US7706302B2 (en) * | 2004-09-14 | 2010-04-27 | Alcatel Lucent | Optimization of routing forwarding database in a network processor |
| US8683128B2 (en) * | 2010-05-07 | 2014-03-25 | International Business Machines Corporation | Memory bus write prioritization |
| US8838901B2 (en) | 2010-05-07 | 2014-09-16 | International Business Machines Corporation | Coordinated writeback of dirty cachelines |
| GB2521227B (en) * | 2013-12-16 | 2020-11-25 | Advanced Risc Mach Ltd | Invalidation of index items for a temporary data store |
| US10402337B2 (en) | 2017-08-03 | 2019-09-03 | Micron Technology, Inc. | Cache filter |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4142234A (en) * | 1977-11-28 | 1979-02-27 | International Business Machines Corporation | Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system |
| JPS5849945B2 (en) * | 1977-12-29 | 1983-11-08 | 富士通株式会社 | Buffer combination method |
| US4410944A (en) * | 1981-03-24 | 1983-10-18 | Burroughs Corporation | Apparatus and method for maintaining cache memory integrity in a shared memory environment |
| US4445174A (en) * | 1981-03-31 | 1984-04-24 | International Business Machines Corporation | Multiprocessing system including a shared cache |
| US4493026A (en) * | 1982-05-26 | 1985-01-08 | International Business Machines Corporation | Set associative sector cache |
| US4562536A (en) * | 1983-06-30 | 1985-12-31 | Honeywell Information Systems Inc. | Directory test error mode control apparatus |
| US4736293A (en) * | 1984-04-11 | 1988-04-05 | American Telephone And Telegraph Company, At&T Bell Laboratories | Interleaved set-associative memory |
| JPS6162150A (en) * | 1984-09-03 | 1986-03-31 | Mitsubishi Electric Corp | Data processor |
| US4755930A (en) * | 1985-06-27 | 1988-07-05 | Encore Computer Corporation | Hierarchical cache memory system and method |
| US4785398A (en) * | 1985-12-19 | 1988-11-15 | Honeywell Bull Inc. | Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page |
| US4814981A (en) * | 1986-09-18 | 1989-03-21 | Digital Equipment Corporation | Cache invalidate protocol for digital data processing system |
| US4959777A (en) * | 1987-07-27 | 1990-09-25 | Motorola Computer X | Write-shared cache circuit for multiprocessor system |
| JPH0212543A (en) * | 1988-06-30 | 1990-01-17 | Nec Corp | Information processing system |
-
1988
- 1988-06-27 US US07/212,416 patent/US5058006A/en not_active Expired - Lifetime
-
1989
- 1989-05-30 DE DE68924206T patent/DE68924206T2/en not_active Expired - Fee Related
- 1989-05-30 EP EP89305427A patent/EP0349122B1/en not_active Expired - Lifetime
- 1989-06-14 JP JP1152049A patent/JP2662603B2/en not_active Expired - Lifetime
- 1989-06-26 CA CA000603895A patent/CA1324221C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0272452A (en) | 1990-03-12 |
| EP0349122B1 (en) | 1995-09-13 |
| DE68924206D1 (en) | 1995-10-19 |
| JP2662603B2 (en) | 1997-10-15 |
| EP0349122A2 (en) | 1990-01-03 |
| EP0349122A3 (en) | 1991-04-24 |
| US5058006A (en) | 1991-10-15 |
| DE68924206T2 (en) | 1996-05-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1324221C (en) | Method and apparatus for filtering invalidate requests | |
| KR100194253B1 (en) | How to Use Mesh Data Coherency Protocol and Multiprocessor System | |
| EP0349123B1 (en) | Multi-processor computer systems having shared memory and private cache memories | |
| US7047322B1 (en) | System and method for performing conflict resolution and flow control in a multiprocessor system | |
| JP2540517B2 (en) | Hierarchical cache memory device and method | |
| Censier et al. | A new solution to coherence problems in multicache systems | |
| US5822763A (en) | Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors | |
| US7017011B2 (en) | Coherence controller for a multiprocessor system, module, and multiprocessor system with a multimodule architecture incorporating such a controller | |
| US5230070A (en) | Access authorization table for multi-processor caches | |
| US6640289B2 (en) | Software controlled cache line ownership affinity enhancements in a multiprocessor environment | |
| US20050021913A1 (en) | Multiprocessor computer system having multiple coherency regions and software process migration between coherency regions without cache purges | |
| EP0062165A2 (en) | Multiprocessors including private and shared caches | |
| US20020174305A1 (en) | Method and apparatus for controlling memory storage locks based on cache line ownership | |
| JPH05127995A (en) | Method for securing consistency between pages which are in common with local cache | |
| EP0139407B1 (en) | Data select match | |
| US6920532B2 (en) | Cache coherence directory eviction mechanisms for modified copies of memory lines in multiprocessor systems | |
| JPH1031625A (en) | Write back buffer for improved copy back performance in multiprocessor system | |
| US6925536B2 (en) | Cache coherence directory eviction mechanisms for unmodified copies of memory lines in multiprocessor systems | |
| US7117312B1 (en) | Mechanism and method employing a plurality of hash functions for cache snoop filtering | |
| US7325102B1 (en) | Mechanism and method for cache snoop filtering | |
| US7159079B2 (en) | Multiprocessor system | |
| US20080307169A1 (en) | Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory | |
| JP2746530B2 (en) | Shared memory multiprocessor | |
| JPH04230549A (en) | Multilevel cache | |
| JPH0551937B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |