CA2004725A1 - Acoustic display generator - Google Patents

Abstract

ACOUSTIC DISPLAY GENERATOR

ABSTRACT OF THE DISCLOSURE

A display generator (23) which converts acoustic sensor data stored in a bulk memory (19) into data which is displayed on a raster-type monitor. The display generator (23) provides for pixel processing and manipulation capabilities supported by a pixel formatter (65), a pixel mover (69), and an acoustic controller (57) with local memory (55). The display generator (23) converts acoustic data from a predetermined sensor format into a variety of display formats compatible with the raster-type monitor. The acoustic controller is a pixel build algorithmprocessor used to initialize and monitor the display generator (23) in real time. It provides for pixel address generation to construct the images in the bit mapped memory (25). The formatter (65) is an independent processor having its own controller and control algorithm processor which provides for parallel processing of the data in parallel with the independent from the operations of the pixel mover(69) and controller (57). Consequently, the display generator (23) provides for parallel pipelining of data from the bulk memory (19) to the bit mapped memory (25). The display generator (23) also permits rapid updates of the displayed image without reconstructing the entire image utilizing the pixel mover (69). The pixel mover (69) updates selected areas of the image stored in the bit mapped memory (25) by operating on multiple pixels at a time, in particular multiple blocks of pixels comprising sixteen pixels each.

Description

2~ 47ZS

ACOUSTI~ DlSPL~Y Gll:NERATOR

I~ACKGROUI~D OF THE INVENTI~N
Tlle present invention generally relates to video display generators and more particularly to a display generator which may be employed as a graphics proccssor in a sonar display syslem, or the like, that constructs, updates and manipulates son;lr im-ages in a bit Illapped memory which are displayed on a raster-type display monilor.
Acoustic display systems for use with sonar systems convert sonar data re-ceived from a sensor array into a f~rm which is displayed Oll a cathode ray tube, for example. Many applications for such display systems require fast image display times and iMage refresh or update rates. Conventional systems whicll provide forrapid image display include "stroker" monitors which draw images directly on a dis-play screen. Images which can be composed by a series of simple geoMetric fonns are well-suited for sucll stroker display systems. However, the disadvantages of sys-tems employing stroker monitors include lack of flexibility and high cost. Thz stro-ker monitor systems are also not effective when displaying complex video and graph-ic images. Thus, if the system requires the display of both graphic and sonar data, a second graphics display system is often needed. Furthermore, stroker monitors are baud limited, in that only so many vectors can be drawn during eacll refresh cycle.
Accordingly, this limits the speed of convenlional stroker monitors.
Raster scan displays are an inexpensive alternative to stroker displays. Raster scan displays pemlit an image to be built line by line, and picture element by yicture element within each line. Thlls, raster scan displays are capable of displayillg a wi~le valiely of ilnage types. Furlhelmole, with appropriale programmillg~ mulliple hll,lg-Z0047'~

es can be displayed on a single raster monitor by using viewporting, or windowing, techniques. In viewporting, different areas of a single screen are dedicated to differ-ent images. Therefore, different image types can be displayed together, or a detail of a scene may be presented with its context displayed on a smaller scale.
However, one disadvalltage of conventional systems employing raster moni-tors is tne amount of information which must be generated and formatted to char;lc-terize and build the raster in1age. For example, a lK by lK raster monitor has a mil-lion pixels. In the case of a red-green-blue (RGB) monitor of sueh dimensiolls, color and intensity informatioll must be determined for each of these million pixels at a very fast rate to construct or update the display during each video display cycle.
In most systems using raster-type monitors, the video or acoustic infor~ tion is serially written into and stored in a bit map memory, so-called because eacll ad-dress in the memory is mappe(l to a predeterrnined pixel on the display. Each display cycle generally involves a complete readout of the bit map memory. While the bitmap memory readout can be performed rapidly, updating the bit map memory to keep pace with rapidly changing inputs from the acoustic sensor array is a problem h conventional systems due to the huge amount of information which must be generat-ed during each display cycle. Thus, prior processors have had dif~lculty in updating the bit mapped memory at a rate sufficient to permit rapid readout thereof.
SUM~l~R~r OF THE lNVENTION
The present invention overcomes the deficiencies in previous acoustic image display systems, and in particular their inability to construct bit mapped memory im-ages fast enough to keep pace with the display data rate. The present invenlion pro-vides for a display generator th;lt comprises a parallel, pipelined, multipixel acoustic graphics processor. The acoustic graphics processor comprises an acoustic control-ler, a pixel formatter and an optional pixel mover, all of which are parallel, multipixel pipelined processors which, once they are configured, operate independently to con-struct and update the images in the bit mapped memory. In particular, the pixel for-matter and pixel mover operate on multipixel groups of signals, generally comprising raster lines and matrices of pixels, respectively. The pixel formatter, acoustic con-troller and pixel mover are each microprogrammable, thereby enabling them to be optimized for differing application environments.
The present invention is generally employed in conjunction with a system thal processes acoustic sensor sigllals, for example, although other types of dat.l sign;lls may be processed ihereby. l;or example, real time simulators or aniMation systems 2~047Z5 m;ly employ lhe prillciples of the present invention. The present invention r.lpidly constructs alld updates acoustic images in the bit n~apped memory prior to thcir~rallsfer ~o a displ.ly, alld al a rate fast enough to keep pace with the dat.l ratc of the incolllillg data. The display generator formats acoustic signals thal are storcd in a predetermilled sensor form.lts in a bulk memory, for example, hlto a plurali~y Or prc-determined display form.lts comp;ltible Witll the bit mapped memory.
The acoustic controller is a pixel build algorithm processor that perfonns ini-tializing and monitorillg functions in real time. It includes hardware that gener;ltcs pixel addresses required to construct the images in the bit mapped memory. l'hc acoustic controller is coupled by way of a direct memory access controller to the bul~;
memory. The direct memory access controller is employed to couple data from thc bulk memory to the pixel fonnatler. l he bulk memory stores acoustic sensor signals, including data an(l display format information, prior to their use by the present invell-tion. The acoustic con~roller is ad;lpled to manipulate line buffer addresses utilize(J in IS the pixel formatter and reglll,lle the data flow through tlle direct memory access con-troller and pixel formatter.
A local melllory is also coupled to an acoustic processor that operales as a commalld interpreter used ~o configure the components of the present inventioll. ll~c acoustic processor trallsfers trallslated command and control signals all(l par;ltlleters 2() to the local memory for storage therein. The local memory provides a conlmalld 4ueue which allows many conmlan(ls to be buffered in a circular buffer. The com-mall(l and con~rol signals an(l parameters indicate the manner in whicll the acoustic signals stored in the bulk memory are to be forrnatted ~nd displayed.
The pixel forlnatter processes acoustic signals from the bulk memory alld for-mats the signals into selected ones of a plurality of display formats. A plurality of raster lines and mul~ipixel sets of data signals are processed wilhill the pixel forn-.lt-ter. The pixel formatter then transfers the formatted signals to the bit mapped memo-ry by way of a memory interface. The pixel formatter is an independent pipelinedprocessor having its own controller section and control algorithm processor that pro-3~) vides for processing of the data signals in parallel with and independent from the op-erations of the pixel mover and acoustic controller. Accordingly, the present inven-tion provides for p.uallel, multipixel pipelining of data from the bulk memory ~o the bit mapped memory.
The op~ional pixel mover is coupled to the bit mapped memory all~l comprises circuitry whicll upd;ltes selected are.ls of the image stored in the memory withollt rc-building tlle iln,lge l~om thc bulk meMory The pixel mover operates on mulliplc ZOQ47'~5 pixels at a thne, n.llllely a m.ltrix array or multiple blocks of pixels comprising six-teen pixels eacll, for exalmple. The multipixel manipul;ltion capabilities of ~he pixcl mover, including waterf.lllillg of rasters and reorientahon of raster pings, an(l moving ~nd rot.atillg grollps of pixels, for example, provides for increased processing speed.
I-lowever, if higll speed processing is not an important aspect of a particul.lr applic;l-tion, the pixel mover need not be employed.

BRIEI; DESCRll'TION OF TIIE DRAWING
The v3rious fentures and advantages of tl-e present invention may be more rea~ily understood with reference ~o the following detailed description taken in COII-junctioll will- the accompallyil-g drawing, wherein like reference numerals design.lte like structural elements, and in which:
FlG.lis a block diagram of a portion of an acoustic display sys~m which in-corporates a display generator in accordance with the principles of the present inven-1 5 tion;
FlG.2isa block diagram of a display generator in accordance wilh the prin-ciples of the present invention;
FlG.3is a diagram showillg process flow in the display generator of FlG. 2;
FlG.4showstlleconlroller of the display generator of FIG.2;
FIG.5 shows a detaile~ illustration of tl-e controller of of FIG. 4;
FlG. 6 sl-ows the pixel fomlatter of the display generator of FlG.2;
FlG. 7 shows the algorithm processor of the pixel formatter of FIG. 6;
FlG.8sllows a flow diagram illustrating the p-rimary process loop for the pixel formaLter of FIG.6;
FlG.9 shows a flow diagram illustrating the process flow for expatlsioll sc-4uences implemented in tl-e pixel formatter of FlG.6;
FlG.lOshows a flow diagram illustrating the process flow for con pression se(luences implemented in Ihe pixel fomlatter of FIG.6;
FIG. 11 shows a flow diagram illustrating the process flow for multipixel modes for DU < 3 implemented in the pixel formatter of FIG.6;
FlG.12showsa now diagram illustrating the process flow for multipixcl modes for DU > 2 implementcd in tlle pixel formatter of FIG.6;
FlG.13showstlle pixel mover of the display generator of FIG.2;
FIG.14 shows a detailed illustration of the pixel mover of FIG. 13;
FIG.lSisa bubhlecll;lrtillllstr.ltingtlle operatiollalsequencesperfollllcdi the pixel mover of Fla. 13;and zon4725 FIG . 1 6a sl-ows tlle concept Or moving the data within memory, an(l FIG . 1 6bshows rotation allcl maskillg of pixel data, performed in the pixel mover of FIG. 13.

l)l~l'AILEI) DESCRIPTION
S Rererring to FlG. 1, and for the purpose of example, a porlion of an acoustic sensor display system 18 utilize(l in a sonar display system is illustrated. The acous-tic display system 18 includes a bulk memory 19 and an acoustic processor 21 lh;lt are coupled ~o an extcmal computer (not shown) in a convention;ll Mallner. An ;ICOUSliC display gellerator 23 in accordance with the present invention is couple~l to the acoustic processor 21, tlle bulk memory 19 and to a bit n~ap memory 25. The bit mapped memory 25 is in turn coupled by way of a conventional raster-type displaycontroller 29 ~o a raster-type display monitor 31 The external computer supplies data signals and control parametcrs ~h.lt arc indicative of the rmanner in which the data signals are to be fomlatted for presentatio on the monitor 31. These control and data signals are loaded and stored in the bulk memory 19. Tllis infonnation comprises display lists and data blocks which are uti-lized by the display generator 23 in constructillg and updating the images stored in the bit mapped memory 25.
The acoustic processor 21 is a generic microprocessor based compu~er which may employ all In~el model 80386 microprocessor, for example. The acousti~ pro-cessor 21 is configured to read the command files from the bulk memory 19 an~J
translate the files into messages usable by the display generator 23. The display gell-erator 23 utilizes the transferred commands to configure the various functiolls for thc required task, SllCh as to construct and update the images in the memory 25, ns will be more fully described below.
The display controller 29 is a conventional raster-type display controller, and it processes images s~ored in the bit map memory 25 and converts the data by way of a color palette look-up table, for example, into analog color and intensity. The dis-play controller 29 also generates monitor and bit map memory timing signals such a!i vertical and horizontal syncllrotlization signals in a conventional manner The display generator 23 in accordance with the present invention is detaile~
in FlG 2. The display generator 23 comprises an acoustic controller 57 having a local meMory 55, a direct mcmory access (DMA) controller 63, a pixel formatler 65, and an optional pixel mover 69. A memory interface unit 67 is provided to allow the display generator 23 to intel race with the bit mapped memory 25. The acouslic con-troller 57 is coupled lo Ille local memory 55 which is employed to store lrallsl;lted comlllallds trallsferred from lhe the bulk memory 19 by the acoustic processor 21.
The acouslic conlloller 57 is coupled to the pixel forrnatter 65, and to the bulk memo-ry 19 by way of the direct memory access controller 63. The direct memory acccsscontroller 63 is coupled to the bulk n]emory 19 in a conventional manner to permit S readout of the pixel dala and control signals stored therein.
The acoustic controller 57 is coupled to ~he rnemory interface ullit 67 wllicl is employed to couple pixel addresses to the bit mapped memory 25. The pixel for-ma~ler 65 is also couple(l to the memory interface unit 67, whicll is employed to cou-ple pixel values to the bit mapped memory 25. The pixel mover 69 is coupled to tlle bit m,lpped melnory 25 alld operates on the pixels stored ~hereill indepelldelltly of thc pixel formatter 65. Tlle direct memory access controller 63, pixel formatter 65,acoustic controller 57, memory interface unit 67 and pixel mover 69 are interconllect-ed by way of a host processor interface (HPI) bus 81, which perlllits transfer of higl level commands from thc acoustic controller 57 or acoustic processor 21 dircctly to these elements of the display generator 23 when required.
FIG. 2 depicts two operational embodiments of the present invention. Tllesc include an embodiment comprising the acoustic controller 57, loc~l memory 55, pi ccl fonnatter 65, direct memory access controller 63 and memory interface Ullit 67. A
second embodiment of the present invention comprises the aforementionetl COlllpO-nellts and also includes the pixel mover 69. The capabilities of these two embodi-ments will be described in more detail below.
ID general, the operation of the display generator 23 is as follows. Th~ dis-play generator 23 operates on data signals stored in the bulk memory 1~, and con-structs acoustic imuges in the bit m.lp memory 25 and rapidly updates and mallipl~-lates these images. The display generator 23 is initially given instructions by the acoustic processor 21, whicll translates standard acoustic commands and parameters stored in the bulk memory 19 and deposits them into the local memory 55. The local memory 55 operates as a command queue for the acoustic controller 57. The com-mand queue is read by the acoustic controller 57 and is translated into hardware com-mand messages used to configure the display generator 23.
The acoustic controller 57 con~lgures, synchronizes and supplies addresses for the pixel formatter 65 which is employed to build display formats. It also syll-chronizes the other elements of the display generator 23. The acoustic controller 57 interprets control messages stored in the local memory 55, and generates data coordi-nates for the data stored in the bulk memory 19, and downloads the data in segmellts to the rormatter 65 using tl~-~ direct memory access controller 63. ~ he pixel formatte ~0472S

65 also generates data and address coordinates for horizontal and vertical rasters.
The direct memory access controller 63 provides direct memory access to the bulkmemory 19 in a conventional manner.
The pixel formatter ~5 processes data words transferred from the bulk memo-S ry 19 in blocks comprising a full raster of lines at a time and forwards the processed blocks to the bit map memory 25 by way of the memory interface 67. The acoustic display generator 23 achieves high speed image construction and updates as a result of multipixel transfers. In addi~ion, and as will be detailed below, the pixel formatter 65 processes the data signals using groups of pixels in a pipeline process. These groups of pixels are expanded, compressed and rotated in various stages of the pipe-line by the pixel forrnatter 65.
With reference to FIG. 3, it shows a data flow diagram illustrating the general operation of the acoustic display generator 23. Data blocks containing data worcls of compressed sonar data, for example, and display lists containing inforn1ation con-lS cerning the display fonDats which are to be displayed on the monitor 31 are initially loaded into the bulk men ory 19. The display lists are transferred to the acoustic pro-cessor 21, which acts as a command interpreter for the acoustic controller 57 which sets up the various components of the display generator 23.
Instructions are loaded into the local memory SS, which functions as a two port command queue that is read by the acoustic controller 57. The acoustic proces-sor 21, in accordance with the instructions contained in the command queue, config-ures the direct memory access controller 63 to generate address locations in the bulk memory 19 to read data to the pixel formatter 65. These address locations are the lo-cations wherein data that is to be displayed on the monitor 31 is located, and this dala is read out of the bulk memory 19 into the formatter 65. The forrnatter 65 includes a two word line buffer which accepts and stores one full raster line of data while the other is processed within the pixel formatter 65.
The formatter 65 operates to format the compressed data words in accordance with forrnat instructions loaded into the local memory 55. The formatter 65 operates on one (4 or 8 bit), two (8 bit) or four (4 bit) pixel sets of data at a time, for example The formatter 65 is a pixel processor which operates independent of the pixel mover 69 and controller 57, once it is set up by the controller 57. The formatter 65 provides for a plurality of formattin~ processes including: expansion of each word of data to a predetermined number of bits per pixel (4 or 8), rotation of the pixels in the four by one pixel array of data, masking of data within the pixel array, compression of a pro-grammed group of pixels to one pixel, and algorithlll processillg to accomplish :a~)Q4'7Z5 I)oulld.lry masking. These processes will be diseussed in more detail below.
'l'he compoilell~s Or Ihe acoustic controller 57 will now be descril)ed in clet.lil.
Wi~h refc rence to FlG. 4, the acoustic controller 57 includes pixel address geller;ltors 58 ancl a synchroniz.ltioll logic module 59, a microsequencer 71, a microsequencer memory 73 having an OUtp~lt control register 74, and a register and a conventioll.ll bit slice arithmetic logic Ullit (RALU) 75. Tlle pixel address generators 58 ancl synchro-nizatioll logic module 59 are coupled to the pixel formatter 65, and operates syncllro-nously to it. It also interfaces to the interfaee unit 67 and the system bus 81 by way of an I IPI port 89. The register alld arithmetic logic unit 75 is eoupled lo the sysl~m 1() bus 81 and to the local nlemory 55. 'lhese components are gener;llly well unclelsloo(l in the art and their interconnection details will not be deseribed.
The controller 57 interpre~s messages that are received from the ;ICOUStiC pro-cessor 21 and stored in the local memory 55. The controller 57 tr~nsl.ltes tllese stored messages into h.ll dware command messages. The controller 57 gener;ltes ras-ter X and Y addresses of the fomlatted pixel data when building new sign;ll ~orln;lts.
The .ICOUStiC controller 57 synchronizes and monitors the operation Or the form;lller 65"address generator 58, direct memory access controller 63 and the memory inler-faee unit 67 by employing conventional discrete synehronization signals and "hillld-shaking" between these eomponents. When building a raster image, the acoustic 2() eontroller 57 reads data from r.lster line deseription tables stored in the lo~al menlory 55, which data is used to upd~te address aeeumulators with offset values inclic.~ g new bit mapped memory locations for the inforrnation.
With reference to l~lG. 5, a more detailed illustration of the controller 57 is showll, specifically detailing the address generator 58 thereof~ In addition to tlle compollents clescribed above with referenee to FIG. 4, the address genera10r 58 in-cludes a plurality of registers 80a-f identified as CONFIG 1, 2 (80a), X ACCUhl (80b), Y ACCUM (80e), A COUNT (80d), B COUNT (80e) and 1/0 ADDR (8()f). A
eomparator 82 whieh provides REI~ and PC signals is provided to mOIlitOr the (:Otll-plelion of a pixel block Or progran-mecl length in the REF register to the CUlTCllt pi.Yel count in PC. A window clipper 84 and two output multiplexers 85, 86 are also pro-vided whieh are eoupled to the A COUNT, B COUNT and ~/0 ADDR registers 80d, 80e, 80f. The window elipper is employed to prevent writing of data to the bit n~apped memory 25 oulside a predeterlnined window area programmed durillg con-figuration. The B address port, multiplexer 86, is the address and handshake conlrol port to the bus 81 employed lo initi.lte the devices thereon.

Z0(~4725 The X acc~ uliltor and Y accumulator are programmed to perforn a repeti-tive operillioll on a group of pi~els (vector processing) by configuratioll regisler I
(8()a). l'lle configuralioll rcgister 1 fields are defined in Table la. The X an(l Y ;lC-cumulator modes are provided in Table I b. The X and Y accumulators provide pixeaddresses to the memory interface Ullit 67 which corresponds to the pixel dalia pro-duced by the pixel form.ltter 65. The accumulator update enable is selected by Illc X
accumulator and Y acculllul.ltor fields given in Tables 1c and ld. The X mode ;Id Y
mode fields define the mo(le of operation of the X and Y accumulators. XAC alld YAC selects the con(litions requirc(l for updating the X and Y accumulators.
Tal)lc la. ConRL~Ilrali~ r cgisler rlel~s Bits Register I Register 2 YMODE ACNTR

YAC BCN'I`R

XAC PCNTR

UNUSED UNUSED

The above register 1 fields .u-e de~lned in the following T~bles lb, 1c al7d kl.

jZ0~?472S

1 .~l)le 11). X or Y ~ddrcss nccumulat1)r 801), 80c (X~C, YAC) lllO(lCS
OUX O to acculllul.l~or ()10 delta registcr Irallsfer to accumulator ()11 accumul;llor lo acculllul.ltor (hold old v;llue) lOX base register lransfer to accumulator 11() base register plus delta rcgister to accumula~or 1 1 I base register plus dclta accumulator to accumulator T~l~lc Ic. X addrcss :Iccumul~lor 801) (XAC) condition select 0 disable upd.l~e uncolldition.ll ul)date 2 A counter C~UTy 3 XY update = (Ll~EQ/kXYUPDATE/*MlUWAlT*Rull~Ialt) 4 Y accu)llulator ca}ry B counter carry Table ld. Y address accumulator ~Oc (YAC) con~ition select 0 disable update uncondition;ll update 2 A counter c.lrry 3 XY upd.lte= (LREQ/*XYUPDATE/*MIUWAlT*RunH;Ilt) 4 X accumulator carry B counter carry The A and B coullters are used to address the read and write adclresses of the line buffer in the pixel form.ltter 65, alld are configured to perfonn a repetitive oper,l-tion by tlle conrlguration registcr 2 (80a). The operations of the configuratioll regis-ters 80a are enabled to rull by the comyarator 82 which is updated by the nun~bel of pixel transfers monitored by the pixel count (PC) register and compared to the rcfer-30 ence (REE~) register. In particul;lr, the A and B counters generate read and write ad-dresses to the line buffers in the formatter 65, enabling a time multiplexed operatioll of reads and writes. The PC counter is used to keep track of the current output pixcl count being drawn in tlle curren~ line. With the REF register as a progr.mlmcd com-p.lrison value, the two registcrs can be con pared by the comparator logic and when 35 Pc is greater or equal to REI:~ the hardw,ure halts further formatter operatioll unlil set up by ~he conLroller. I he ~ e collnlers (A, 13, l'C) are conlrolle(l by the cOnrij~Dura-~O(~ 4 ;J Z5 ~ion regis~er 2 (80a), using the fields in Table la. l'he A, B alld PC counter fiekls OrTal)le la are presented hl 'I`ables le tllrough lg.

T~l)le le. ~ cOu~ r 80tl (ACN'I`R) condition select 0 no COUllt coullt 2 INA (external illpUt) 3 AUPDT= ('l`NEXTkRunE~ lt) 1() T~l)le lf. 1~ counter 80c (I~CNTR) conslitioll select 0 IlO ~oullt coullt 2 lNB (external hlput) 15 3 BUPDT = (TNEXT = *GO*BRDY); TNEXT is a status/syncll bit PC countcr 82 (PCNTR) conditioll sclect 0 no count unconditiollal COUllt 2 lNC (external illpUt) 3 XYUPDT = (LDREQ/*MWAlT*RH) Enabling bits are presented hl Table 1h. ESA enablcs the selection Or llle dat;
25 source of the A ADDR port (mu~c 85) by the SLA bit when ESA = 1. Whell ESA = () the SLA bit has no effect and the source selection is performed by the input line NEXT/ from the formatter 65. SLA selects the source of A ADDR port betweell A
count when zero or B COUllt when enabled by ESA = 1. SLB selects the source of BADDR port (mux 86) between B count when zero or l/O ADDR when 1. ACNTR, 3() BCNTR and PCNTR are conditioll select fields for the A counter, B counter and PC
counter, respectively, whicll select tlle conditions which will enable these coullters to incremellt.

~0047Z5 T~l)lc 11~ n~lL)lil~ l)ils ESA SLA l'NEXT AADR rMUX A!
0 X A counter X B counter 0 X 0 A counter (read) 0 X 1 B counter(write) SLB BADR (MUX B!
0 B coullter 1 IOADR regis~er The I/O ,address register (I/O ADDR) 80f fields are presented in Table li.

T~l~le li. I/O address rc1 ister rlelds Bits Field Al X

DM

BS generates an aclive low signal BUSREQ/ to the bus 81 whel1 BS = 1. DM
30 generates an active low signal DMAREQ/ signal when DM = 1. O~ generatcs all active low signal lNTREQ/ when lR = 1 to indicate that there is an intermpt re(luest from tlle acoustic controller. RD (read) generates an active low RD/ signal whell sct to 1. It is disabled whell the yort has been acknowledged by the external device. WR
(write) generates an active low WR/ signal when set to 1. It is disabled when the l-IPl 35 port 89 has been acknowled~ed by the external device. A represents the five bit ac-live hi~,h addrcss bils Or ll~c I Il'l port wllicll are used by llle acous~ic con~rollel.

Z0(~4~25 Rather thall employ comll1and words, the synchronization logic 59 contaills logic wllich is used to conrlgllre extemal functions. The bits controlled by the syn-chroniz.llion logic 59 arc derlne(l in Table lj.

T~l)lc lj. Syllcllroni7Aa~ioll r~gislcr con~rol bits Bits Field Description To device BR 0 Enable bit to BREQ/ circuit DMA contlol NL 1 Direct to NORM/ formatter VH 2 Vertical or horizontal pixel builds formatter Rll 3 Direct to RUN/~Ialt formalter CR 4 Direct io extern,ll function generator external genel alor PR 5 Direct lo PENA/ (pixel mover run/halt) pixel mover RW 6 spare formatter AS 7 X Y ndclrcss select (ext. functioll generator) ex~ern,ll gencl;ltorSC 8 Direct to STRNCUR/ (stem cursor) formatter IC 9 lConfigure MIU (0=4 bit/pixel, 1=4 bitJpixel memory interface LP 10 Direct ~o LASTPX/ formatter BS 11 Bank select (0 = lower bank, 1 = upper bank The above-described registers configure and control the pixel address, lhle buffer address and syncl-rollizatioll of the display generator 23 during pixel process-ing. This operation will then run until halted by the comparator 82 which indicates lo the controller 57 that a small modification to the process, such as an address iu~p or discontinuity in the process re~luires an adjustment.
The controller processor, comprising components 71-74, updates the disl)l.ly generator 23. Once this processor controller is enabled, it runs in a burst mode. The break points are programmed in the coMparator 82. The controller processor only updates these parameters allowing the display generator 23 to process the next burst of data.
Witll reference to FIG. 6, whicll details the pixel fonnatter 65, it includcs asmajor components, a line buffer 100, word shifter logic 102, bit expantler logic l 04, pixel shifter logic 106, boundary word logic 108, decode logic 110, an algorithn- pro-cessor 112, a command register 114, a control sequencer 116 and a host processor h~-terface 118. Data from the bulk memory 19 is coupled into the pixel forrnatter 65 by way of the line buffer 100 Z0047'~5 T he line buffer 1()0 is coupled to the word shif~er 102 and boundllry word logic 108. I he manipllllllive compollellts of the formatter include the word sl-ifler 102 bit expallder logic 104 alld pixel shifter logic 106 wllich are sequentially inler-- connected along a commoll data patll. The control sequencer 116 interfaces to tl-e host processor interf.lce 1 18 by Wily of the command register 1 14 the algoritlllll pro-cessor 112 and decoder logic 110 by way of the algoritlm1 processor 112. I hese clc-ments are adapted to process algoritllms in order to construct and update bit Mapped iM~geS. The COlltlOl se~luellcer 116 is employed to control the coupling of Ihe syn-chrollizatioll logic address and conlrol signals to bolh the memory interface unil 67 and the acoustic controller 57.
The pixel shifter logic 10G includes disable 7 and blank bit logic 120 pixel rotator logic 122 peak detector 124 output multiplexer 146 and output register 128.
The command register 114 includes the following registers: NORM S~lFT
BIT/CELL CONS RAT DU M RD BACK MIU and MASK as shown. The command register 114 are loaded with configuration parameters which remaill un-changed during the processing sequence. Dynamically changing parametels are computed by tl-e algorithln processor 112. These registers and the oper~tion of lhe form~tter 65 will be expLlilled in luore detail hereinbelow.
The word shifter 102 is a conventional 32 bit shifter allowing 1 to 16 bit shifts per clock cycle. Is is employed to read 4 pixels at a time out of the register witll 4 pixels comprising 1 to 4 bits per pixel. The bit exp~nder 104 exp~nds an input cell of one to 8 bits e~ch to the standard 4 or 8 bits per pixel. It does so by left justifying 4 ~Idjacellt cells thell O or I fill the empty bits. If the cell is 1 bit then 3 bits are fill bits. In this way the stalld~rd 4 or 8 bits per pixel is provided as an output. The dis-able 7 and blank bit logic 12() is logic which overrides the pixel equal to 7 forcing it to zero. The pixel rotator 122 is elllployed to replicate and shift tbe input pixels d ing stretching operations. For example if the incoming pixels comprise pixels PlP2 P3 and P4 then a three times stretching operation (3DU stretch) generates thefollowingpixelsets:Pl P1 P1 P2;P2 P2 P3 P3;P3 P4 P4 P4. Thethreesctsof output pixels are provided by pixel rotation logic. The boundary word shifter 108 is a shifter and decoder which in single pixel mode using a boundary descriptor word contained in a data word header unpacks sparsely ~llled input words by hldicatillg the location of pixels in the data word. Therefore those pixels containing useful in-fomlation are extracted from the sparsely filled input words and employed by the ror-matter 65. The OlltpUt multiplexer 123 is a three input multiplexer that selects the sourcc of the output pi~cls floll~ Lhc pixel rot~tor 122 yeak delector 124 o} cons~

Z0047zs register for output from ~he formatter 65.
The operation of the pixel formatter 65 is such that it receives data by way of the line buffer 100 from the bulk memory 19 under control of the direct memory ac-cess controller 63. The data transfers are accomplished in a conventional manner.
S The line buffer 100 holds two lines of rasters, which perrnits one line to be processed while the other line is loaded. The formatter 65 unpacks 32 bit wide data words re-ceived from the bulk memory 19, formats them into pixels and transfers them into the bit map memory 25 by way of the memory interface unit 67. To accomplish tllis, the word shifter logic 102, bit expander logic 104, pixel shifter logic 106 and boundary descrip~or word (BDW) shirter logic 108 respond to co~r~nands stored in the regis~crs comprising the command register 114. The pixel forrnatter 65 unpa~ks individual cell fields and expands them into pixel fields having 4 or 8 bits per pixel, in aCCOI:
dance with size information provided by the controller 57, and as will be more fully described below. The components of FIG. 6 replicate, and hence stretch the image, or compresses the image using the peak detector 124 as will be detailed below.
More specifically, the pixel formatter 65 is a three stage pipeline processor which processes input data received from the bulk memory 19. This data is input through the line buffer 100 which is loaded by the direct memory access controller 63. This data is manipul.lted by the word shifter logic 102 which aligns the wrrently used cells in the word so that the next four cells can be expanded to four or eight bits per cell by the bit expander logic 104. If the input data cells are not packed end to end, then a boundary descriptor word is supplied by the boundary word descriptorlogic 108 by way of multiplexer 121. A boundary descriptor word is supplied withthe input word and the bounda~y descriptor word shifter is used to decode the re-quired shift following each cell to unpack the pixels.
The bit expander logic 104 provides four expanded cells to the disable 7 cir-cuit 120, which operates as a clamp circuit, that converts all cells whicll are hex E or hex F to a 0 or 1. If the data is not enabled, it passes through this stage unchanged.
The cells then are processed by the pixel rotator logic 122, which performs replica-tion of the cells by selecting the output pixels from among the four input cells. The outputs of the pixel rotator logic 122 are applied to the output multiplexer 126, which selects which pixel is coupled to the memory interface unit 67. A multiplicity of Sill-gle pixel and multipixel modes are available for selection. The selected pixels are loaded into îhe output regisler 128, which comprises four pixel latches. The peak de-tector 124 may be employed during single pixel transfers, which selects the peakvalue of a group of inpuls, p.lssing the result to Ihe output mulliplexer 126. '1 he peak Z0(~472S

dctector 124 m;ly be progr.~ med lo reset for any number of cells sampled an(l ~o ou~put only tlle last peak value thus causing the output to be a compressed peak de-tec~ed line.
The sequellcer 116 uses the algoritllm processor 112 to update tllose par;lme-ters which are constalll]y changing such as the pixel rotator boundaries of pixels en(l of words so ~h;ll ull words in the register are used and conca~enatioll of ncw words to unprocessed por~ions of old words. The sequencer 116 in the form;ll~er 65 is programmed using a format~er assembly language instruc~ion set. l he ins~ruc~ion set is used to program assembler mode bits which generate specific opera~ioll codes from generic ~ypes. The following mode bits are employed and ~re programm;lbIe.
CC = 1 indicates that tlle process is in the concatenation mode. CS indicates that the process is in a s~art of line conc;ltellation mode which involves masking and offse~s of output pixels. When CS ;~nd CC ~re 0 then a normal process mode is en~ble :1.DU specifies to the algoritllltl tl-at tlle I 2 3 or greater than 3 pixel expansion alDo-ri~lllns are to be enabled.
l lle pixel format~cr 65 assellll)ly language instruction se~ is used ~o progra ~he sequencer 116 whicll also uses ~lle algoritllm processor 112 to sequence the ror-mat~er 65 during its operation. Tlle instruction set includes br~nch instructiolls th;lt are defined as ullcollditioll;ll if no colldition is specified or conditioll;llly true if speci-fied or conditioIlally false if specified with a slash in front of the condilion. l he fol-lowing conditions may be specified: NQIVAL NQDVAL OUTRDY NLDRDY
LASTPX RUN M0 Ml DUGR2 NBZERO EMPTY PKDETY CXP M2 CM
BEQZ NORM BGRZ BSlGN NDUEQX DXGR3 JGRZ NCARRY and NTERCT all of wllich are process staLus flags from the algori~hln processor or con-troller Con~rol flags employed in the instruction set are similar to the ~node bits and to the mode flags. They include: CC and CS which define the process mocles. CC =0 and CS = 0 defines a normal process. CC = 1 and CS = 0 defines an interword coll-catenate process. CC = O and CS = I defines a start line concatenate process.
3() OUTENA enables output up~.lles. FBBY is a formalter busy flag. OPINIIB is dis-able forMatter output to the meIllory interf3ce Ullit 67. SHIFTENA enables shiltillg of the word shif~er 102.
Programmable pulse signals generate triggers to various hardware s~ate se-quencers and register loads :ausillg a process to initialize a parameter holding regis-ter. Valid pulsed flags inclllde REQNXT which requests the next input to the line bufler. LL)AREG inilializes lhe conl~ol register of ~he sequencer all(l execu~es lhe process. LOADDU lo.lds the DU reL~ister in the ~Igorithm processor. FLUS11 gen~r-~tcs ;I pulse to the memory interface Ullit to flush out its pipeline. CLDVAL cle.lrs the st~tus n~.g of tlle input d.lta register PKCLR clears the peak detector to zero alld loadsSUCNTR.OFSRQrequests an "offset request word" from the local memory 55.RUNCClo.ldsthecolltrol register of the sequencer and executes that ins~ UCti until ~he stopconditionismet.NCLR clears the sequencer to zero termin.llillg ally sequence.
The adder control rlelds are indicated in Tables 2a-c below.

T~l)le 2a. A(l~ler Cvl~trvl Fielàs: CC/ AND CS/ Modes DU=l DU=2 DU>2 NOOP NOOP NOOP
NX=NX-4,S NX=NX-2,S NX=NX-4,X2=DX
NX=M NX=M NX=M
15 NX=NX-l NX=NX-l NX=NX-l DX=DU DX=DU DX=DU
DX=DX+DU DX=DX+DU DX=DX+DU
DX=DX+RAT DX=DX+RAT DX=DX+RAT
NX=DX~0 NX=DX=0 NX=DX=0 20 DX=DX+J DX=DX+J DX=DX+J
DX=X2 DX=X2 DX=X2 DX=DX-l DX=DX-l DX=DX-l NX=NX-I,S NX=NX-l,S NX=NX-l,S
NX=NX NX=NX NX=NX
Tal~le 2l). Adder Control Fields: CC/ AND CS Modcs DU=I DU=2 DU=3 DU>3 NOOP NOOP NOOP NOOP
NX=NX+J NX=NX DX=DX-4 DX=DU-4 0 NX=NX-4 NX=NX-l,S DX=DX+J DX=DX+J
DX=DX+DU DX=DX+DU
NX=NX-l,S NX=NX

'I';ll)lc 2c. Adder Control l; ields: CC/AND CS/ Mo(lcs DU=l DU=2 DU-3 DU>3 NOOP NX =M NOOP NOOP
NX=NX+M,S NX=NX- 1,S NX=NX- l,S NX=NX
NOOP DX = X2, X2 = DX DX = X2, X2 = DX
NX=M NX=M

FlG. 7 shows a di.lgr.lm of the algorithm processor 112 employed hl the for-m.ltter 65. The algoritllm processor 112 controls the dynamically changhlg control 10 parameters includillg bi~ stretchillg and compression boundaries of the dat,l words The algoritllm processor 112 comprises an adder 130, two accumulators 142, 144 all(l two illpUt multiplexers 136, 138 coupled to the adder 130. A temporary holdillg reg-ister 145 and a DU counLer 142 are provided as shown. The algori~hm processor 112 is controlled and monitored by the sequencer 116 in the formatter 65. The seqLlellcer 15 116 generates clock strobes an control bits and monitors the states of the registers of the algoritllm processor 112. The algorithm processor 112 hlcludes the DU coull~er 142 and Dx accumulator 144 which indicates the remaining stretching pixels star~illg from the value of DU alld decrementing by the output pixel number until it registers zero or minus. The Nx accumulator 140 holds the current remaining cells in the dala 20 shift register, so that when it becomes zero, another input is requested from the line buffer. The two accumulators 140, 144 select inputs from static control registers and immediate data from the sequencer 116 Table 3 indicates the inputs that are con-trolled by the algori~hm processor 112 T~ble 3. Inpuls Contrvlled by the Al~orithlll Processor Code MUX A illpUt FUIlCtiOn 000 NIN lminediate data ~rom microsequencer (-4 to +3) 001 J l, J0 LSB of pixel address (selects boundaly modes) 010 DU stretching faclor 011 0 all zero 100 M Pixels/word 101 S~1Fr Shifter value used by data shifter 110 RAT fractional part of stretch factor 111 X2 holding register of Dx (load with NLDX2) Z0(:~47'ZS

The accumul.ltols 140, 144 are identified in FIG. 7 as Nx ;md Dx. Nx, Dx and zero are fed back to the input of the adder 138, MUX B, controlled by the S~L B
lines. Nx normally contains the remainilIg pixels in the word starth~g with M alld is decremelIted by a predetermhled amount each time a new pixel is shifted by the pixel shifter. Dx is the remainillg stretching amount starting at Dx-DU. Each time theformatter outputs four pixels, DU is decremented by four. The value ren~ailling in Dx is used to control the output by way of the pixel rotator and mask logic. The ac-cumulators 144, 146 are loaded from the following control registers: M, DU, RAT, J, NEN, and SHFT MUX.
The control seqllellcer 116 employs several single pixel all~ multipi,xel .llgo-ri~hms. Flow ch~Arts of tllese algorithms ~re presented in FIGS. 8-12. l he prim.~ry processing loop of tlle algoritllm is shown in FlG. 8, which comprises an initializ;l-tiOll of the flags and an idle which waits for an OUTRDY signal which is sent prior to branching to selected process algorithms. A nortnalizing process is included lS which performs presl1iftil1g of the first word so that the value is normalized alld not starting on pixel one of the first word. This operation is enabled by tl1e NORM sig-nal from the controller 57.
For single pixel buils~s, the algorithm of FIG. 9 is employed. This algorithl11 employs inte~er expallsioll an(l fraction expansioll subalgorithms, alld is used to buil-J
uncompressed, integer expallded vectors or rasters in single pixel modes. lt outputs single pixels at a time to the memory interface unit 67. The second singlc pixel ex-pansion algorithm expallds the input by an integer and a fractional part. This is ac-coMplished by expanding the integer "DU" times and then adding the prograll~ ed fractional part, RATIO, to the accumulator 144 (FIG. 7).
The compression sequence algorithm is shown in FlG. 10. The peak detector 124 of the fom1atter 65 is employed to implement the compression algorithlll. In the algorithm, the OUtpllt is disabled by NCPINHB. Consequently, an output from the formatter 65 does not gener.lte any loads to the memory interface unit 67. Once thc integer "DU" amount is peak detected, then the accumulator 144 adds the RATIO
and if there is a carry thell one more input cell is compared to tlle current peak before the value in the peak detector 124 is output to the memory interface unit 67, after which the peak detector 124 is cleared.
The multipixel buil-l algoritllms which generates stretching for DU equal to one and two is shown in Fl('l. 11. The multipixel algorithm generate four pixel out-puts at a time. In the one all~l two DU modes, the stretching is minimal and several difl`elenl valuc pixels are ou~l~ul a~ a tilllC. rhe mullipixel build ;llgori~l~uls wlliell Z0~47Z5 generales stretching for VU grealer lhan two is shown in FIG. 12. This multipixel mode simultalleously generates stretching on adjacent pixels by a variable amount.
Tlle above-desclibed pixel formatter 65 and the direct memory access control-ler 63 cooperate to perform indepelldellt transfers of several blocks of data in parallel.
The pixel mover 69 howevcr performs a host of operations on the images stored inthe bit mappe(l memory 25 by operatillg on a 4 by 4 matrix of pixels in one trallsfer cycle. The pixel mover 69 detailed in FIG. 13 includes a a sequencer 15() wllich is coupled to a line buffer 152 a line acldress register 154 and a register arilhllIetic logic unit (RALU) 168. Tlle lille buffer 152 is serially couple~l to line rotation logic 156 pixel logic 158 alld a first corner turn multiplexer 160 that interfaces with all image bus port 162. The line b~lffer 152 is also coupled to a register 164 alld to the pixel logic 158. The register 164 is coupled by way of a second corner turn mlllliplexer 166 to the image port 162. The register arithmetic logic unit 154 of the pixel mover 69 is coupled to boll- of thc corner turn n-ultiplexers 16() 166. The image port 16'~ is in turll coupled to tlle bit n);lpped nemory 25 by way of the image bus. The registcr and aritllmetic logic unit 168 is illustra~ed in FIG. 14. It is a programm;lble unit u se(l to generate bit mapped memory addresses for source and destination based on X Y
coordinates as well as the block line and column lengths.
XS~ XD, YS, and Y are the source and destination X and Y coordinates of tlle pixel array in the bit n~apped memory 25. LLD is the line length in 4 pixel blocks of the source in the bit mapped memory 25. LLD is the line length in 4 pixel blocks of the destination in tlle bit mapped memory 25. NL is the number of matrix lilles or colullms moved. Line count and line length are used to keep track of the number of lines moved and number Or pixel blocks moved. Tlle sequencer outputs or proccsses the required addresses or updates counters from the register file or incremellts lllem during transfer in a conventiollal manner.
Moving or rotatillg areas of an image in tlle bit mapped memory 25 is imple-mented by the pixel mover 69. This causes "waterfalling" of rasters and "reorienta-tion" of raster pings. Waterfalling can be effected by reading image data all(l then writing it back horizolltal or vertical strips to the bit mapped memory 25. The pixel mover 69 may blank tlle least significant bit causing part of the image to be invisi-ble. Blanking saves invisiblc pixels so they can be redisplayed without reb~lilding ~he entire display. Blanking is gellerally employed during circlllar rotations.
The pixel mover 69 C;lll make a part or parts of the moved image invisible on the screen by utili%illg one l-it lll;lp n emory pl;lne as a blanking plane ;IS is kllOwn lO
~l-ose in the art. By enal)ling or dis;lbling the blanking plane the corresponditlg pixcls Z1!:)047Z5 will be made invisible or visible. Wllell reorienting the rasters, this feature may be use(l so that lhe rasters (lo not h;lve to be regenerated utilizing data from the bulk memory 19.
lhe basic operations of the pixel mover are illustrated in FIGS. 15 and 16a and b. FlG. 15 is a bubble cll;lrt illustrating the operations performed in the pixel mover 69. FIG. 15 shows tlle actual control sequence used with the programmed varial)les to conlrol lhe pixel mover 69. Table 4 provides values for R1, R2, W I ;llt(l W2, along with transfer mocles associated with each set of values.

'I'ablc ~. l'ixel Mover OP Codes R1 W1 R2 W2 Transrer Modes O O O 1 Write only to bit map memory (BMM) from line buffer 0 0 1 0 Write only from BMM to line buffer 0 0 1 1 Read fron- BMM ~Source), Modify, Write to BMM (Dest.) 0 1 0 0 Write to BMM from HPI (Source) 0 0 0 Read from BMM to HPI

0 0 1 Read from BMM (Source), Write to BMM (Destination) 0 1 1 l~ead from BMM (Source), Read to BMM (Destinatioll), then perÇorm operation on source (OP) dest, wri~e to BMl`il 1 1 1 1 Read from BMM (Source), write back immediale regis~er, ~hen write results to BM~ dest~ write to BMM
Read from BMM (Source), write back immediate register, then write results to BMM dest, perform operation, write to BMM
FIG. 16a shows the concept of moving the data within the memory, while FIG. 16b shows rotation and masking of the pixel data. FIGS. 15 and 16a and b are believed to be self explan;ltory, and will not be described in detail.
Thus, a display ~enclator which constructs acoustic im;lges in a bit m.lppe(l 35 memory has been described whicll permits updating of the display withollt regenela-~iOn of lhe cnlire in1~ge lro~ aL;I store~l in memory. l he displ;ly gener;lLor is a l);U

20(347~5 allcl, pipelined, multipixcl acoustic graphics processor whose m.mipulative compo-nents operate independelltly to construct and update the images in the bit mapped memory. The display gencrator operates on multipixel groups of signals, generally comprising raster lines and matrices of pixels. The display generator is micropro-grammable, thereby enabling it to be optimized for differing application environ-ments~
It is to be understood that the above-described embodiment is merely illustr;l-tive of one of the many specific embodiments which represent applications of theprinciples of the present invention. Clearly, numerous ~nd other arrallgements c;3n bc 10 readily devised by those skilled h1 tlle art without departing from the scopc of the in-venlion.

Claims (6)

1. A display generator (23) which constructs and updates images in a bit mapped memory from data signals stored in a bulk memory (19) and applied signals that are indicative of the manner in which the data signals stored are to be formatted and displayed, said display generator (23) comprising controller means (57) for processing the applied signals and generating source and destination pixel addresses for the data signals stored in the bulk memory (19); and pixel formatting means (65) coupled to the controller means (57) and to the bulk memory (19) for utilizing the source addresses generated by the controller means (57) to read the data signals from the bulk memory (19) for processing multipixel groups of the data signals to format them into predetermined display formats, and for transferring the formatted signals to the bit mapped memory (25) in accordance with the destination addresses generated by the controller means (57)

2. The display generator (23) of Claim 1 which further comprises pixel manipulation means (69) coupled to the bit mapped memory (25) for independently processing two dimensional arrays of signals located in selected areas of the image stored in the bit mapped memory (25) to reformat those selected areas without regenerating individual pixels from the bulk memory ( 19)

3. The display generator (23) of Claim 2 wherein said pixel manipulation (65) comprises:

means for processing a two dimensional matrix comprising 16 pixels stored in the bit mapped memory (19) and manipulating the orientation of the two-dimensional matrix to update a selected area of the bit mapped memory (19).

4. The display generator (23) of Claim 1 wherein said controller means (57) comprises:
address generation means (58) for generating multipixel addresses for use by the pixel formatter means (65) in formatting the data signals; and microsequencer (71) and microprogram memory Means (73) comprising a control algorithm processor coupled to the address generation meansfor providing initislization and command interpretation functions

5. The display generator (23) of Claim 1 wherein said pixel formatting means (65) comprises:
a line buffer (100) for processing a plurality of raster lines of data signals;
algorithm processor means (112) for controlling the reorientation of pluralities of pixels in accordance with a predetermined sequence of instsructions;
and pixel processing means coupled between the line buffer (100) and the algorithm processor means (112) for expanding compressing and rotating groups of pixels under control of the algorithm processor means

6. The display generator (23) of Claim 2 wherein said pixel manipulation means (69) comprises:
a sequencer (150) for sequencing the operations of the pixel manipulation means;
rotation and corner turning means (156) for manipulating matrices of pixels to update selected areas of the image a stored in the bit mapped memory (25); and register and arithmetic logic means (168) coupled to the sequence (150) for responding to signals provided thereby and coupled to the rotation andcorner turning means (156) for processing bit mapped memory addresses, line buffer addresses block lengths and boundary masks for use in manipulating the matrices of pixels.