CA2037708A1 - General purpose compound apparatus for instruction-level parallel processors - Google Patents

General purpose compound apparatus for instruction-level parallel processors

Info

Publication number
CA2037708A1
CA2037708A1 CA2037708A CA2037708A CA2037708A1 CA 2037708 A1 CA2037708 A1 CA 2037708A1 CA 2037708 A CA2037708 A CA 2037708A CA 2037708 A CA2037708 A CA 2037708A CA 2037708 A1 CA2037708 A1 CA 2037708A1
Authority
CA
Canada
Prior art keywords
instructions
instruction
compound
execution
classes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2037708A
Other languages
French (fr)
Other versions
CA2037708C (en
Inventor
Richard J. Eickemeyer
Stamatis Vassiliadis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2037708A1 publication Critical patent/CA2037708A1/en
Application granted granted Critical
Publication of CA2037708C publication Critical patent/CA2037708C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G06F9/30152—Determining start or end of instruction; determining instruction length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions

Abstract

The disclosure deals with a technique for generating compound instructions from a binary instruction stream without knowledge as to where instructions start or which bytes contain data instead of instruction. The disclosure describes pre-processing a set of instructions (or a program) to determine statically which instructions may be combined into compound instructions. Such processing is done in a typical embodiment by software and/or hardware means which will look for classes of instructions that can be executed in parallel in a particular computer system configuration. The instruction classes and the compounding rules are implementation specific and will vary depending on the number and type of functional execution units. While keeping their original sequence and object code intact, individual instructions are selectively grouped and combined with one or more other adjacent scalar instructions to form a compound instruction byte stream having both compounded scalar instructions for parallel execution and non-compounded scalar instructions for execution singly. Control information is appended to identify information relevant to the execution of the compound instructions.
CA002037708A 1990-05-04 1991-03-07 General purpose compound apparatus for instruction-level parallel processors Expired - Fee Related CA2037708C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US51938290A 1990-05-04 1990-05-04
US07/519,382 1990-05-04

Publications (2)

Publication Number Publication Date
CA2037708A1 true CA2037708A1 (en) 1991-11-05
CA2037708C CA2037708C (en) 1998-01-20

Family

ID=24068072

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002037708A Expired - Fee Related CA2037708C (en) 1990-05-04 1991-03-07 General purpose compound apparatus for instruction-level parallel processors

Country Status (8)

Country Link
US (1) US5500942A (en)
EP (1) EP0454984B1 (en)
JP (1) JPH087681B2 (en)
CA (1) CA2037708C (en)
CS (1) CS93591A2 (en)
DE (1) DE69122294T2 (en)
HU (1) HUT57456A (en)
PL (1) PL289723A1 (en)

Families Citing this family (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
WO1992006426A1 (en) * 1990-10-09 1992-04-16 Nexgen Microsystems Method and apparatus for parallel decoding of instructions with branch prediction look-up
DE59301610D1 (en) * 1992-09-22 1996-03-21 Siemens Ag METHOD FOR PROCESSING A USER PROGRAM ON A PARALLEL COMPUTER SYSTEM
DE69427265T2 (en) 1993-10-29 2002-05-02 Advanced Micro Devices Inc Superskalarbefehlsdekoder
DE69434669T2 (en) * 1993-10-29 2006-10-12 Advanced Micro Devices, Inc., Sunnyvale Speculative command queue for variable byte length commands
US5630082A (en) * 1993-10-29 1997-05-13 Advanced Micro Devices, Inc. Apparatus and method for instruction queue scanning
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
DE69433124T2 (en) * 1993-11-05 2004-05-27 Intergraph Corp., Huntsville Command memory with associative crossbar switch
US6360313B1 (en) 1993-11-05 2002-03-19 Intergraph Corporation Instruction cache associative crossbar switch
US5559975A (en) * 1994-06-01 1996-09-24 Advanced Micro Devices, Inc. Program counter update mechanism
US5640526A (en) * 1994-12-21 1997-06-17 International Business Machines Corporation Superscaler instruction pipeline having boundary indentification logic for variable length instructions
US5737550A (en) * 1995-03-28 1998-04-07 Advanced Micro Devices, Inc. Cache memory to processor bus interface and method thereof
US5819056A (en) * 1995-10-06 1998-10-06 Advanced Micro Devices, Inc. Instruction buffer organization method and system
US5926642A (en) * 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5920713A (en) * 1995-10-06 1999-07-06 Advanced Micro Devices, Inc. Instruction decoder including two-way emulation code branching
US6093213A (en) * 1995-10-06 2000-07-25 Advanced Micro Devices, Inc. Flexible implementation of a system management mode (SMM) in a processor
US5794063A (en) * 1996-01-26 1998-08-11 Advanced Micro Devices, Inc. Instruction decoder including emulation using indirect specifiers
US5809273A (en) * 1996-01-26 1998-09-15 Advanced Micro Devices, Inc. Instruction predecode and multiple instruction decode
US5872947A (en) * 1995-10-24 1999-02-16 Advanced Micro Devices, Inc. Instruction classification circuit configured to classify instructions into a plurality of instruction types prior to decoding said instructions
US5796974A (en) * 1995-11-07 1998-08-18 Advanced Micro Devices, Inc. Microcode patching apparatus and method
US8583895B2 (en) * 1996-05-15 2013-11-12 Nytell Software LLC Compressed instruction format for use in a VLIW processor
US5896519A (en) * 1996-06-10 1999-04-20 Lsi Logic Corporation Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions
US6049863A (en) * 1996-07-24 2000-04-11 Advanced Micro Devices, Inc. Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
US5867680A (en) * 1996-07-24 1999-02-02 Advanced Micro Devices, Inc. Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions
US6112299A (en) * 1997-12-31 2000-08-29 International Business Machines Corporation Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching
US6170050B1 (en) 1998-04-22 2001-01-02 Sun Microsystems, Inc. Length decoder for variable length data
US6263429B1 (en) * 1998-09-30 2001-07-17 Conexant Systems, Inc. Dynamic microcode for embedded processors
US6490673B1 (en) * 1998-11-27 2002-12-03 Matsushita Electric Industrial Co., Ltd Processor, compiling apparatus, and compile program recorded on a recording medium
US7376814B1 (en) 1999-09-07 2008-05-20 Nxp B.V. Method for forming variable length instructions in a processing system
US6438664B1 (en) 1999-10-27 2002-08-20 Advanced Micro Devices, Inc. Microcode patch device and method for patching microcode using match registers and patch routines
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
US7401328B2 (en) * 2003-12-18 2008-07-15 Lsi Corporation Software-implemented grouping techniques for use in a superscalar data processing system
US7523295B2 (en) * 2005-03-21 2009-04-21 Qualcomm Incorporated Processor and method of grouping and executing dependent instructions in a packet
US7526633B2 (en) * 2005-03-23 2009-04-28 Qualcomm Incorporated Method and system for encoding variable length packets with variable instruction sizes
US7500023B2 (en) * 2006-10-10 2009-03-03 International Business Machines Corporation Facilitating input/output processing by using transport control words to reduce input/output communications
US7502873B2 (en) * 2006-10-10 2009-03-10 International Business Machines Corporation Facilitating access to status and measurement data associated with input/output processing
US20090055636A1 (en) * 2007-08-22 2009-02-26 Heisig Stephen J Method for generating and applying a model to predict hardware performance hazards in a machine instruction sequence
US8196149B2 (en) * 2008-02-14 2012-06-05 International Business Machines Corporation Processing of data to determine compatability in an input/output processing system
US7840717B2 (en) * 2008-02-14 2010-11-23 International Business Machines Corporation Processing a variable length device command word at a control unit in an I/O processing system
US9052837B2 (en) 2008-02-14 2015-06-09 International Business Machines Corporation Processing communication data in a ships passing condition
US8095847B2 (en) * 2008-02-14 2012-01-10 International Business Machines Corporation Exception condition handling at a channel subsystem in an I/O processing system
US7908403B2 (en) * 2008-02-14 2011-03-15 International Business Machines Corporation Reserved device access contention reduction
US7904605B2 (en) * 2008-02-14 2011-03-08 International Business Machines Corporation Computer command and response for determining the state of an I/O operation
US8176222B2 (en) * 2008-02-14 2012-05-08 International Business Machines Corporation Early termination of an I/O operation in an I/O processing system
US8108570B2 (en) * 2008-02-14 2012-01-31 International Business Machines Corporation Determining the state of an I/O operation
US8478915B2 (en) 2008-02-14 2013-07-02 International Business Machines Corporation Determining extended capability of a channel path
US7917813B2 (en) * 2008-02-14 2011-03-29 International Business Machines Corporation Exception condition determination at a control unit in an I/O processing system
US8312189B2 (en) * 2008-02-14 2012-11-13 International Business Machines Corporation Processing of data to monitor input/output operations
US7840718B2 (en) * 2008-02-14 2010-11-23 International Business Machines Corporation Processing of data to suspend operations in an input/output processing log-out system
US8117347B2 (en) * 2008-02-14 2012-02-14 International Business Machines Corporation Providing indirect data addressing for a control block at a channel subsystem of an I/O processing system
US8166206B2 (en) * 2008-02-14 2012-04-24 International Business Machines Corporation Cancel instruction and command for determining the state of an I/O operation
US8082481B2 (en) * 2008-02-14 2011-12-20 International Business Machines Corporation Multiple CRC insertion in an output data stream
US7890668B2 (en) 2008-02-14 2011-02-15 International Business Machines Corporation Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous
US7899944B2 (en) * 2008-02-14 2011-03-01 International Business Machines Corporation Open exchange limiting in an I/O processing system
US7937507B2 (en) * 2008-02-14 2011-05-03 International Business Machines Corporation Extended measurement word determination at a channel subsystem of an I/O processing system
US8001298B2 (en) * 2008-02-14 2011-08-16 International Business Machines Corporation Providing extended measurement data in an I/O processing system
US7941570B2 (en) * 2008-02-14 2011-05-10 International Business Machines Corporation Bi-directional data transfer within a single I/O operation
US8214562B2 (en) * 2008-02-14 2012-07-03 International Business Machines Corporation Processing of data to perform system changes in an input/output processing system
US8364751B2 (en) * 2008-06-25 2013-01-29 Microsoft Corporation Automated client/server operation partitioning
US7937504B2 (en) * 2008-07-31 2011-05-03 International Business Machines Corporation Transport control channel program message pairing
US8055807B2 (en) 2008-07-31 2011-11-08 International Business Machines Corporation Transport control channel program chain linking including determining sequence order
US7904606B2 (en) * 2008-07-31 2011-03-08 International Business Machines Corporation Transport control channel program chain linked branching
JP2010257199A (en) * 2009-04-24 2010-11-11 Renesas Electronics Corp Processor, and method of controlling instruction issue in processor
US8332542B2 (en) * 2009-11-12 2012-12-11 International Business Machines Corporation Communication with input/output system devices
US8738811B2 (en) 2011-06-01 2014-05-27 International Business Machines Corporation Fibre channel input/output data routing system and method
US8677027B2 (en) 2011-06-01 2014-03-18 International Business Machines Corporation Fibre channel input/output data routing system and method
US8583988B2 (en) 2011-06-01 2013-11-12 International Business Machines Corporation Fibre channel input/output data routing system and method
US8364854B2 (en) 2011-06-01 2013-01-29 International Business Machines Corporation Fibre channel input/output data routing system and method
US8364853B2 (en) 2011-06-01 2013-01-29 International Business Machines Corporation Fibre channel input/output data routing system and method
US9021155B2 (en) 2011-06-01 2015-04-28 International Business Machines Corporation Fibre channel input/output data routing including discarding of data transfer requests in response to error detection
US8312176B1 (en) 2011-06-30 2012-11-13 International Business Machines Corporation Facilitating transport mode input/output operations between a channel subsystem and input/output devices
US8473641B2 (en) 2011-06-30 2013-06-25 International Business Machines Corporation Facilitating transport mode input/output operations between a channel subsystem and input/output devices
US8346978B1 (en) 2011-06-30 2013-01-01 International Business Machines Corporation Facilitating transport mode input/output operations between a channel subsystem and input/output devices
US8549185B2 (en) 2011-06-30 2013-10-01 International Business Machines Corporation Facilitating transport mode input/output operations between a channel subsystem and input/output devices
CN102495726B (en) 2011-11-15 2015-05-20 无锡德思普科技有限公司 Opportunity multi-threading method and processor
US8918542B2 (en) 2013-03-15 2014-12-23 International Business Machines Corporation Facilitating transport mode data transfer between a channel subsystem and input/output devices
US8990439B2 (en) 2013-05-29 2015-03-24 International Business Machines Corporation Transport mode data transfer between a channel subsystem and input/output devices
US9558000B2 (en) * 2014-02-06 2017-01-31 Optimum Semiconductor Technologies, Inc. Multithreading using an ordered list of hardware contexts

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295193A (en) * 1979-06-29 1981-10-13 International Business Machines Corporation Machine for multiple instruction execution
US4506325A (en) * 1980-03-24 1985-03-19 Sperry Corporation Reflexive utilization of descriptors to reconstitute computer instructions which are Huffman-like encoded
CA1174370A (en) * 1980-05-19 1984-09-11 Hidekazu Matsumoto Data processing unit with pipelined operands
US4502111A (en) * 1981-05-29 1985-02-26 Harris Corporation Token generator
US4439828A (en) * 1981-07-27 1984-03-27 International Business Machines Corp. Instruction substitution mechanism in an instruction handling unit of a data processing system
JPS61245239A (en) * 1985-04-23 1986-10-31 Toshiba Corp Logical circuit system
US4847755A (en) * 1985-10-31 1989-07-11 Mcc Development, Ltd. Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies
EP0239081B1 (en) * 1986-03-26 1995-09-06 Hitachi, Ltd. Pipelined data processor capable of decoding and executing plural instructions in parallel
US5051940A (en) * 1990-04-04 1991-09-24 International Business Machines Corporation Data dependency collapsing hardware apparatus
DE68926701T2 (en) * 1988-08-09 1997-02-20 Matsushita Electric Ind Co Ltd Data processing device for parallel decoding and parallel execution of commands with variable word length
US5202967A (en) * 1988-08-09 1993-04-13 Matsushita Electric Industrial Co., Ltd. Data processing apparatus for performing parallel decoding and parallel execution of a variable word length instruction
US5051885A (en) * 1988-10-07 1991-09-24 Hewlett-Packard Company Data processing system for concurrent dispatch of instructions to multiple functional units
US5203002A (en) * 1989-12-27 1993-04-13 Wetzel Glen F System with a multiport memory and N processing units for concurrently/individually executing 2N-multi-instruction-words at first/second transitions of a single clock cycle
US5337415A (en) * 1992-12-04 1994-08-09 Hewlett-Packard Company Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency

Also Published As

Publication number Publication date
JPH0773036A (en) 1995-03-17
EP0454984A2 (en) 1991-11-06
JPH087681B2 (en) 1996-01-29
CA2037708C (en) 1998-01-20
US5500942A (en) 1996-03-19
EP0454984B1 (en) 1996-09-25
HU911102D0 (en) 1991-10-28
DE69122294D1 (en) 1996-10-31
EP0454984A3 (en) 1994-04-27
PL289723A1 (en) 1992-05-04
DE69122294T2 (en) 1997-04-10
HUT57456A (en) 1991-11-28
CS93591A2 (en) 1991-12-17

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