CA2072582C - Power control circuitry for a tdma radio frequency transmitter - Google Patents
Power control circuitry for a tdma radio frequency transmitterInfo
- Publication number
- CA2072582C CA2072582C CA002072582A CA2072582A CA2072582C CA 2072582 C CA2072582 C CA 2072582C CA 002072582 A CA002072582 A CA 002072582A CA 2072582 A CA2072582 A CA 2072582A CA 2072582 C CA2072582 C CA 2072582C
- Authority
- CA
- Canada
- Prior art keywords
- signal
- transmit
- output signal
- value
- tdma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/204—Multiple access
- H04B7/212—Time-division multiple access [TDMA]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/04—TPC
- H04W52/52—TPC using AGC [Automatic Gain Control] circuits or amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
- H03G3/3047—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers for intermittent signals, e.g. burst signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/403—Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/54—Circuits using the same frequency for two directions of communication
- H04B1/56—Circuits using the same frequency for two directions of communication with provision for simultaneous communication in two directions
Abstract
A TDMA cellular telephone (600) includes, in its transmit signal path, microphone (608), vocoder (612), data format circui-try (601), quadrature modulator (602), 90 MHz local oscillator (606), transmitter with mixer (604), transmitter filter (618), and an-tenna (620). In its receive signal path, the TDMA cellular telephone (600) includes receiver filter (622) coupled to antenna (620), quadrature demodulator (624), and data deformat circuitry (625). The channel frequency of TDMA cellular telephone (600) is loaded into synthesizer (616) by microcomputer (614) and applied to transmitter (604) and demodulator (624). TDMA cellular telephone (600) is controlled by microcomputer (614) which includes a memory with a control and signaling computer program stored therein. Transmitter (604) includes novel power control circuitry (100) comprised of variable gain stage (104), mixer (106), bandpass filter (109), and directional coupler (112) in a forward path, and detector (116), A/D converter (118), digital controller (120), and D/A converter (126) in a feedback path.
Description
-1- 2072~82 POWER CONTROL CIRCUITRY
FOR A TDMA RADIO FREQUENCY TRANS~
Ba~k~rolmd of the Invention The present invention is generally related to radiotelephones, and more particularly to power control circuitry for a time-division multiple-access (TDMA) radio frequency (RF) transmitter that may be advantageously used 10 in digital cellular telephones.
Analog cellular telephones currently are continuously transmitting during a telephone call. RF transmitters of such An~lo~ cellular telephones are frequency modulated with voice ~;ign~l~ and continuously operated at one of eight different 15 power levels depentling the quality of the RF signal received therefrom by the cellular system base st~t;Qn. The output power of such RF transmitters are maintained at the desired power level by collvç.~tiQnAl automAt;c output power control circuitry, such as, for example, the ci~c~ shown and 20 described in U.S. Patent No. 4,523,155. How~ver, such coll~entional output power control circuitry is inadequate for TDMA cellular systems where it is necessary to rapidly pulse the RF transmitter on for 6.67 millisecon-l~ and off 13.33 milli~econds every 20 milli~econ~ Furthermore, it is also 25 necessAry that the RF transmitter output follow the envelope of the modulation, which has frequency components in excess of 12.15 KHz. These problems may be solved in part by output power control circuitry employing variable attenuators which attenuate the RF' input to the transmitter power Ampli~er. An 30 example of ~uch output power control circuitry employing a variable attenuator is shown and described in U.S. Patent No.
4,803,440. However, when such output power control circuitry employing a variable attenuator is operated at cellular transmitter frequencies rAn~ing from 824 MHz to 849 MHz, ~, 2 207~S~2 subst~ntiAl degradation in performance occurs due to feedthru, t~mperature stability, manllfactllring variations, and poor linearity of the variable attenuator. For the foregoing reasons, there is a need for improved power control circuitry 5 for precisely and reliably mAint~ining the maint~ining RF
oul~ut, signal from a TDMA RF signal transmitter at one of a plurality of power levels selected by the level control ~ignAl~.
~llmmArv of t~ Tnv~ntion Briefly stated, the present invention çncomrAR6es novel power control cilc~ y responsive to level control signAlR and a transmit intermediate frequency (IF) signal from a signal source for maint~ining the magnitude of a radio frequency 15 (RF) output signal at one of a plurality of power levels selected by the level control RignAlR. The power control circuitry comprises: reference circuitry for generating an RF leferel,ce signAl; adjusting Cil'CUitl~ having variable gain for adjusting the transmit IF signal subst~nti~lly in proportion to the value ao of a gain control signal to produce an adjusted transmit IF
signAl; mi~ing circuitry for combining the adjusted transmit IF signal and the RF reference signal to produce an RF
transmit signAl; amplifying Ci~ for Amrlifying the RF
transmit signal to produce the RF output Rign~l; detecting 25 circuitry coupled to the RF output signal for generating a detector output signal having a value related to the magnitude of the RF output signAl; and control circuitry coupled to the detector output signal for, at a plurality of intervals, sAmpling the value of the detector output signAl, and adjusting the value 30 of the gain control signal in response to the difference between the sampled value of the detector output signal and a desired value selected by the level control gignAlR.
FOR A TDMA RADIO FREQUENCY TRANS~
Ba~k~rolmd of the Invention The present invention is generally related to radiotelephones, and more particularly to power control circuitry for a time-division multiple-access (TDMA) radio frequency (RF) transmitter that may be advantageously used 10 in digital cellular telephones.
Analog cellular telephones currently are continuously transmitting during a telephone call. RF transmitters of such An~lo~ cellular telephones are frequency modulated with voice ~;ign~l~ and continuously operated at one of eight different 15 power levels depentling the quality of the RF signal received therefrom by the cellular system base st~t;Qn. The output power of such RF transmitters are maintained at the desired power level by collvç.~tiQnAl automAt;c output power control circuitry, such as, for example, the ci~c~ shown and 20 described in U.S. Patent No. 4,523,155. How~ver, such coll~entional output power control circuitry is inadequate for TDMA cellular systems where it is necessary to rapidly pulse the RF transmitter on for 6.67 millisecon-l~ and off 13.33 milli~econds every 20 milli~econ~ Furthermore, it is also 25 necessAry that the RF transmitter output follow the envelope of the modulation, which has frequency components in excess of 12.15 KHz. These problems may be solved in part by output power control circuitry employing variable attenuators which attenuate the RF' input to the transmitter power Ampli~er. An 30 example of ~uch output power control circuitry employing a variable attenuator is shown and described in U.S. Patent No.
4,803,440. However, when such output power control circuitry employing a variable attenuator is operated at cellular transmitter frequencies rAn~ing from 824 MHz to 849 MHz, ~, 2 207~S~2 subst~ntiAl degradation in performance occurs due to feedthru, t~mperature stability, manllfactllring variations, and poor linearity of the variable attenuator. For the foregoing reasons, there is a need for improved power control circuitry 5 for precisely and reliably mAint~ining the maint~ining RF
oul~ut, signal from a TDMA RF signal transmitter at one of a plurality of power levels selected by the level control ~ignAl~.
~llmmArv of t~ Tnv~ntion Briefly stated, the present invention çncomrAR6es novel power control cilc~ y responsive to level control signAlR and a transmit intermediate frequency (IF) signal from a signal source for maint~ining the magnitude of a radio frequency 15 (RF) output signal at one of a plurality of power levels selected by the level control RignAlR. The power control circuitry comprises: reference circuitry for generating an RF leferel,ce signAl; adjusting Cil'CUitl~ having variable gain for adjusting the transmit IF signal subst~nti~lly in proportion to the value ao of a gain control signal to produce an adjusted transmit IF
signAl; mi~ing circuitry for combining the adjusted transmit IF signal and the RF reference signal to produce an RF
transmit signAl; amplifying Ci~ for Amrlifying the RF
transmit signal to produce the RF output Rign~l; detecting 25 circuitry coupled to the RF output signal for generating a detector output signal having a value related to the magnitude of the RF output signAl; and control circuitry coupled to the detector output signal for, at a plurality of intervals, sAmpling the value of the detector output signAl, and adjusting the value 30 of the gain control signal in response to the difference between the sampled value of the detector output signal and a desired value selected by the level control gignAlR.
3 2072~
Rrief nescr~Dtion of the Drawin~
FIG. 1 is a block diagram of power control circuitry for an RF transmitter of TDMA cellular telephone 600 in FIG. 6, 5 embodying the present invention.
FIG. 2 is a timing diagram for the power control circuitry in FIG. 1.
FIG. 3 is a flow chart for the process used by controller 120 in FIG. 1.
FIG. 4 is an alternative embo~iment of power control circuitry for an RF transmitter, embodying the present invention.
FIG. 5 is another alternative embo-limçnt of power control circuitry for an RF transmitter, embodying the present invention.
FIG. 6 is a block diagram of a TDMA cellular telephone, which may advantageously utilize the power control circuitry of the present invention, as embodied preferably in FIG. 1 and alternatively in FIG. 4 or FIG. 5.
FIG. 7 is a circuit diagram of long time constant detector 116 in FIG. 1.
Description of the r~ ere~ 1 ed F,mhotlim~nt Referring to FIG. 6, there i9 illustrated a block diagram of a TDMA cellular telephone 600, which may advantageously utilize the power control circuitry of the present invention, as embodied ~lefe~ably in FIG. 1 and alternat*ely in FIG. 4 or FIG. 5. TDMA cellular telephone 600 includes, in its transmit signal path, microphone 608, vocoder 612, data format circuitry 601, quadrature modulator 602, 90 MHz local oscillator 606, transmitter with mixer 604, trans~itter filter 618, and antenna 620. In its leceive signal path, TDMA
cellular telephone 600 includes antenna 620, receiver filter 622, ~4~ 2r)725~2 quadrature demodulator 624, and data deformat circuitry 625.
The rh~nnel frequency of TDMA cellular telephone 600 is loaded into synthesizer 616 by microcomputer 614 and applied to transmitter 604 and demodulator 624. In the preferred embodiment, the duplex radio çh~nnel~ have transmit freqllençies in the range from 824 MHz to 849 MHz and receive frequencies in the range from 869 MHz to 894 MHz. TDMA
cellular telephone 600 is controlled by microcomputer 614 which includes a memory with a control and si~n~1ing computer program stored therein. In the preferred embodiment of TDMA cellular telephone 600, microcomputer 614 i6 implemented with commercially available microcomputers, such as, for example, the Motorola type 68HC11 microcomputer. Although cellular telephone 600 utilizes TDMA RF ch~tnnçl~ the present invention may also be tltilize~3 in conventional frequency division multiple acces&
cellular telephones, in code division multiple access cellular telephones, and in other analog and digital cellular telephones employing different tr~nsmi~sion schemes.
ao In the preferred embodiment of TDMA cellular telephone 600 in FIG. 6, quadrature modulator 602 is implemented as described in the instant assignee's copen~ling patent application no. 07/526,156, (now US patent no. 5,020,076 granted May 28, 1991) entitled aHybrid Modulation Apparatus, invented by Stephen V. Cahill et al., and filed May 21, 1990. Quadrature modulator 602 mo~ t~s TDMA RF signals with voice, data and 8ign~11in~ information according to 1rJ4-shift differential quadrature phase shift keying (DQPSK). DQPSK modulation is described in aDigital Communications", by John G. Proakis, 1st Ed., ISBN 0-07-050927-1, at pages 171-178. Data format ci- c ~it~ .~ 601 combines the output of vocoder 612 with si~lling and overhead information and encode~ the result according to ~I/4-shift DQPSK modulation into the transmit I
,~ ,c ~
~5~ 2Qf 25P~
and Q sign~l~. The 7t/4-shift DQPSK modulation and ~i~n~llin~ information is specified in Interim Standard 54 pllhli~hed by and available from the Electronic Industries Association, ~ngineering Department, 2001 Eye Street N.W., 5 W~shir~ton, D.C. 20006.
The signal vector representin~ the ~/4-shift DQPSK
modulation consists of a cosine component and a sine component. The signal scaling the amplitude of the cosine component is also known as the in-phase or I signal and the 10 signal scaling the a~nplitude of the sine component is also known as the quadrature or Q signal. The I and Q scaled cosine and sine Ri,~n~l~ are the orthogonal quadrature components at the frequency of the 90 MHz signal from local oscillator 606; the modulated transmit IF signal 102 then 15 being created by adding the I and Q sign~qlg.
Symbols representing the vector components of the I
and Q sign~lR are generated in data format ci~cuiL~ 601 by shifting the vector components such that phase shifts of IF
signal 102 of +~/4 or +3~/4 r~ n~ are generated. Each phase ao shift enço-les one of four possible symbols.
Serial digital data from vocoder 612 that is eventually to be modulated by modulator 602 is first collve~ l,ed to bit pairs in data format circuitry 601. Each bit pair specifies a symbol that is the desired vector shift relat*e to the previously transmitted 25 symbol. The mapping of bit pairs to symbol vectors is according to the equations:
I(k) = I(k-1)cos(~0(X(k),Y(k)))-Q(k-1)sin(~0(X(k),Y(k))) Q(k) = I(k-1)sin(~0(X(k),Y(k)))+Q(k-1)cos(~0(X(k),Y(k))) where k is an index of the bit pairs; k=1 for bits one and two paired, k=2 for bits three and four paired, etc. I(k-1) and Q(k-1) are the amplitudes of the cosine and sine components of the previous symbol vector. X(k) represents the first bit of bit pair ~7~ 5 ~2 (k) and Y(k) represents the second bit of bit pair (k). The phase change, ~o, is determined according to the following table:
~k2 ~ A0(X(k).Y(k)) -37~/4 O 1 3~1/4 O O ~1/4 0 -Ir/4 5 Thus, one of four possible symbols are transmitted for each two bits of the serial data stream.
The reason for the modulation nomenclature ~/4-shift DQPSK and how it worka is now evident: the phase shift is in 7c/4 increments in vector space, symbols are differentially 10 encoded with respect to the previous symbol vector, and the information bearing quantity in IF signal 102 is the phase-shift with one of four possible shifts between any two symbols.
The operation of modulator 602 i6 represented by the equation:
VoUt(t)= (I(t))cos(2Jtft)+(Q(t))sin(2~1ft) where VoUt(t) is the modulated IF signal 102 and I(t) and Q(t) are I(k) and Q(k) as defined above as a function of time, and f is the transmit IF of 90 MHz.
ao In the preferred embodiment of TDMA cellular telephone 600 in FIG. 6, quadrature demodulator 624 is implemented as described in the instant ~ gnee~s copending C~n7~ n patent application no. 2,071,869, entitled "A Carrier Recovery Method and Apparatus Having an Adjustable Response Time Determined by Carrier Signal Parameters", invented by Stephen V. Cahill, and filled 24 September, 1991. Quadralure demodulator 624 demod1l1ates TDMA RF signala modulated with information according to 1~J4-shift DQPSK and generates the receive I and 20725~2 Q 8i~nAlfi The receive I and Q si~nAl~ are deformated and ~ccoAe~l by data deformat ~lc~ill ~ 625 to ~cu~er the digitized voice ~ignAla, which are applied to vocoder 612.
In the preferred embodiment of TDMA cellular telephone 600 in FIG. 6, vocoder 612 is implemented as described in the instant assignee's US patent nos. 4,817,157 and 4,896,361. Vocoder 612 encodes and decodes voice Ei~nAl~ according to code excited linear prediction (CELP) cotling. P'ilters 618 and 622 are intercoupled as a duplexer for transmitting TDMA RF signAl~
on, and receiving TDMA RF signAls from antenna 620. Filters 618 and 622 may be any suitable cuuvelltional filters, such as, for example, the filters described in US patent nos. 4,431,977, 4,692,726, 4,716,391, and 4,742,562 (incorporated herein by reference). Vocoder 612, data format circuitry 601, data deformat circuitry 625, quadrature modulator 602, and quadrature demodulator 624 may be implemented with commercially available digital signal processors, such as, for example, the Motorola type DSP 56000 digital signal processor.
According to the present invention, power control circuitry of transmitter 604 in FIG. 6 iB preferably implemented as illustrated in FIG. 1 and may be alternatively implemented as illustrated in FIG. 4 or FIG. 5. Although utilized in TDMA cellular telephones 600, the power control circuitry of the present invention may also be utilized in conventional frequency division multiple access cellular telephones, in code division multiple access cellular telephones, and in other analog and digital cellular telephones employing different transmission schemes. Referring now to FI~. 1, the power control circuitry include~ variable gain stage 104, mixer 106, bandpass filter 109, and directional coupler 112 in a forward path, and detector 116, analog-to digital (A/D) converter 118, digital controller 120 and digital-to analog (D/A) converter 126 in a feedback path. Transmit I~
, ~ ~
-8- 207~ 2 signal 102 from quadrature modulator 602 has a frequency of 90 MHz and is modulated with DQPSK information. Stage 104 has a variable gain for adjusting the magnitude of IF signal 102 in response to DtA co~ . ler output signal 128. Stage 104 5 may be implçmentefl by means of a variable gain Amplifier or a variable gain attenuator, where the gain is adjusted subst~ntiAlly in proportion to the value of gain control signal 128. In the preferred embodiment, stage 104 i8 a variable gain ~mplifier simil~r to the Motorola type MC1350 IF Amplifier.
10 The adjusted IF signal from stage 104 is mixed with the RF
reference signal 108 from srthesi7er 616 to produce the RF
trans_it signal. The RF transmit signal is filtered by bAntlp~s filter 109 and ~mplified by RF Amp1ifier 110 to produce the RF transmit output signal 114. The transmit 15 output signal 114 is coupled by directionAl coupler 112 to transmit filter 618 and thereafter AntennA 620 for transmlssion.
The operation of the power control circuitry in FIG. 1 is further illustrated by the timing diagram in FIG. 2. Timing signal 124 has a waveform ~lefining a series of transmit intervals, which in FIG. 2 correspond to time slot TS1 of three possible time slots TS1, TS2, and TS3 for a TDMA RF chAnnel.
The TDMA RF ~hAnnel consists of multiple frames of 20 milliseconds each cont~ining three time slots TS1, TS2, and 25 TS3 of appro~imAtely 6.67 milliseconds each. During a cellular telephone call in a TDMA cellular system, TDMA
cellular cellular telephone 600 is assigned to a TDMA RF
chAnnel and a time slot of that chAnnel for tr~n~mission of the modulated transmit output signal 114 carrying voice signAl~, nAllin~ information and overhead information.
Accordingly, it is necessary that the transmit output signal 114 be transmitted at the desired power level selected by the power level sign~ls 122 during each of the Acsigned time slots.
9 2072~9~
Acco~Lllg to a feature of the present invention, D/A
c~vel ler 126 is loaded by controller 120 at the be~inning of each ~si ne-l time slot with the value stored in its memory and at the end of each ~ ne-l time slot with a zero value for 5 essentiAlly turning the transmit output signal 114 on and off.
In addition, ~mplifier 110 may also be turned on and off by gating its bias on and offby way of bias control signal 136. The D/A converter output 128 in FIG. 2 has a value which varies from time slot to time slot to m~int~in the output power of 10 transmit output signal 114 at the desired power level. The waveform of detector output 130 in FIG. 2 has an exponçnt~
response due to the relatively long time constant of detector 116 with respect to the time slot length. Due to the relatively long time con~t~nt of detector 116, the output of detector 116 near the 15 end of the time slot has a value related to the average magnitude of the transmit output signal 114. Detector 116, as shown in FIG. 7, includes rectifying circuitry comprised of diode 702 and capacitor 704, and averaging circuitry col,.~l;sed of capacitors 704 and 708 and resistor 706. In the ao preferred embo-liment, averaging circuitry 704, 706 and 708 has a time constant of appro~imP~tsly one millisecond.
Near the end of each time slot as illustrated by the sample times in FIG. 2, the value of the detector output 130 is sampled and used by controller 120 to coulpute a new value of 25 D/A convel ler output 128 by subtracting the sampled value of the detector output 130 from the desired value for the selected power level, scaling the ~ e~ellce by a pre-selected factor, and snmming the scaled difference with the previous value stored in memory. The new value of D/A converter output 128 is 30 stored by controller 120 in its memory and loaded into D/A
converter 126 at the be~inning of the next ~csigned time slot.
Referring next to FIG 3, there is illustrated a flow chart for the process used by controller 120 for maint~ining the output power of the transmit output signal 114 at the desired -lo- 2~725~2 power level. Entering at START block 302, the process proceeds to decision block 304, where a check of timing signal 124 is made to determine if timing signal 124 has a binary one state. If not, NO branch iB taken to wait. If timing signal 124 5 has a binary one state, YES branch is taken from decision block 304 to block 306, where a check of is made to determine if transmitter 604 is initially being keyed up (i.e., turned on). If so, YES branch is taken to block 308 where an initial value for D/A co,lvel ler output 128 is retrieved for a lookup table in the memory of controller 120. If tr?.nfimitter 604 is not being initially keyed up, NO branch is taken from decision block 306 to block 307 where the previously stored value (i.e. stored during previous ~s~qi~ned time slot) for D/A converter output 128 is retrieved from the memory of controller 120. Next, at block 310, the retrieved value of for D/A collvel ler output 128 is applied to D/A converter 126. D/A converter 126 in turn collvel ls the applied value to an analog voltage, which is applied to variable gain stage 104 for adjusting the amount of gain.
Next, at decision block 312 in FIG 3, a check of timing signal 124 is made again to determine if the timing signal 124 has a binary zero state. If not, NO branch iB taken to wait. If timing signal 124 has a binary zero state, YES branch is taken from decision block 312 to block 314, where the value of detector output 130 iB read from A/D co,lveL ler 118. Next, at block 316, transmitter 604 is dekeyed (i.e., shut off) by setting D/A
col~ve, ler output 128 to zero. Then, at block 318, a new value of D/A converter output 128 is calculated by subtracting the sampled value of the detector output 130 from the desired value for the selected power level, scaling the difference by a pre-selected factor, and sllmmin~ the scaled difference with the previous value of D/A converter output 128 stored in memory.
Then, the new value of D/A converter output 128 is stored in the memory of controller 120 at block 320 for use during the -11- 2Q72~82 next ~signe~ time slot, and control returns to decision block 304 to repeat the foregoing process for the next ~ssigned time slot.
Referring next to FIG 4, there is illustrated an alternative embodiment of power control circuitry for TDMA
RF transmitters, embodying the present invention. In this embotlimant, rather than a long time constant detector 116 as in FIG 1, output power is continllously ~etectecl and corrected by means of detector 426, which extracts the modlll~ion envelope of the modulated transmit IF signal prior to level adjustment The output of ~letsct~r 426 is then multiplied by multiplier D/A converter (DAC) 428 in order to produce a scaled modulation envelope sign~l~ the scs~lin~ factor being chosen to produce the desired power level of transmit output signal 114 (i.e., each power level has a predetermined s~linp~
factor). The scaled modulation envelope signal from DAC 428 is applied to the positive input of error ~mplifier 424, which produces a gain control signal for adjusting the gain of variable gain stage 104. Detector 422 (which may be a diode ao detector) receives a portion of transmit output signal 114 via coupler 112, and produces a detector output signal representing the transmit envelope of the transmit output signal 114. This envelope si~n ~l, without time delay, forms the negative input to error ~mplifier 424. Variable gain stage 104, mixer 106, h~n(lp~s filter 130 and ~mplifier 110 then operate to reduce the error between transmit envelope from detector 422 and modulation envelope from DAC 428 to zero, and thus _aintain output power of transmit output signal 114 at a desired power level selected by the scaling factor applied to multiplier DAC 428 by microcomputer 614. The scaling factor applied by microcomputer 614 to DAC 428 is selected by the level control sign~l~, in the substantially the same m~nner which power level sign~l~ 122 are applied to the digital controller 120 of FIG 1. In FIG 4, mixers 404 and 408, phase -12- 2~72~i~2 shif~er 406, and comhiner 410 form a quadrature modulator, such as is ~iscll~se~l in the aforementioned copenfline patent application no. 07/526,156.
Referring next to FIG 5, there is illustrated another 5 alternative embodiment of power control circuitry for TDMA
RF transmitters, embodying the present invention. In the embo~liment of FIG 5, the method of FIG 4 is implemente-l in an Alternate mAnner by means of diode detector 524 and A/D
converter 118, the output of which is connecte~l to a digital 10 controller 502. Digital controller 502, D/A converters 504 and 512, mixers 404 and 408, phase shifter 406, and comhiner 410 together form a quadrature modulator, such as i6 discussed in the aforçmentioned copen~ling patent application no.
07/526,156. A compAring fi~nrt;on is incorporated in digital 15 controller 502, in the mAnner of error Amrlifier 424 of FIG 4, where one input is the output of A/D converter 118 and the other input, G, i8 a scaled magnitude signal derived from the transmit I SIGNAL, transmit Q SIGNAL, and POWER
LEVEL ~ignAl~ 122 using the following equation:
ao G = [(I SIGNAL)2 + (Q SIGNAL)2]l/2 * POWER LEVEL * C
Where C is a sCAline constant correcting for fixed component gain (i.e., each power level has a predetermined power level 25 constant POWER LEVEL and a predetermined sc~ing constant C).
In the embodiment of FIG 5, periodic adjustment of transmit output signal 114 in response to the compAring function in digital controller 502 iB done during each Assiened 30 ~me slot by means of variable gain stage 104, and also by means of gain adjustments applied by digitAl controller 502 to the I SIGNAL and Q SIGNAL as they are pA~se~l to D/A
col,vel lers 604 and 512 through digitAl controller 502. This additional gain adjustment within digital controller 502 -13- 2072~82 permits an increase in the total range of output power for transmit output signal 114, the limiting amount of increase being the usable range of D/A collvel lers 504 and 512.
In the embodiment of FIG 5, the times at which periodic 5 adjustments are made to transmit output signal 114 during each ~signed time slot may be selected to minimi7~e required dynamic range of detector 524. Acco~.lillg to EIA IS-54, the modulation is specified as ~c/4-shift DQPSK with alpha equal to 0.35 SQRC bA~eb~n~l filtering. ~rJ4-shift DQPSK modulation 10 modulates the envelope of the RF carrier signal. Envelope modulation of the RF carrier signal increases the dynamic range over which detector 524 must operate. In the case of ~/4-shift DQPSK with alpha equal to 0.35 SQRC baseband filtering, the peak-to-average envelope power is 3 dB, and the average-to-15 minimum envelope power is 14 dB. As a result, an additional17 dB is added to the 28 dB dyn~mic range of detector 524 in order to cover the eight 4 dB power steps. To minimi7.e the dynamic range over which detector 524 must operate, transmit output signal 114 is preferably sampled at the m~lrimum effect ao points of the ~/4-shift DQPSK modulation. ~mpling at these times reduces the additional dynamic range to 4 dB instead of 17 dB. The point in each time slot at which the m~imum effect points occur is well known, and is determined by the location of the input impulses in the alpha equal to 0.35 SQRC
25 finite impulse response baseband filters. The m~imum effect points are also described in EIA IS-54.
In sllmm~ry, unique output power control circuitry maintains the output power of transmit output signal at a desired power level selected by power level ~ign~l~ during a 30 series of transmit intervals, such as, for e~mple, the ~s~igned time slots of a TDMA RF ch~nnel. In operation, a variable gain stage is used to adjust a modulated IF signS~l, which is then mixed with an RF reference signal to produce the transmit RF signal. The transmit RF signal is ~mplified -14- 2072~2 by an RF ~mplifier to produce the transmit RF output signal which is coupled by a direction~l coupler and transmit Slter to an ~ntenn~ for tr~ncmiR~ion. The novel output power control circuitry of the present invention may be advantageously ntili7.e~l in TDMA cellular telephones as well as in conventional frequency division multiple access cellular telephones, in code division multiple access cellular telephones, and in other analog and digital cellular telephones employing different tr~n~mi~sion sçhemes.
Rrief nescr~Dtion of the Drawin~
FIG. 1 is a block diagram of power control circuitry for an RF transmitter of TDMA cellular telephone 600 in FIG. 6, 5 embodying the present invention.
FIG. 2 is a timing diagram for the power control circuitry in FIG. 1.
FIG. 3 is a flow chart for the process used by controller 120 in FIG. 1.
FIG. 4 is an alternative embo~iment of power control circuitry for an RF transmitter, embodying the present invention.
FIG. 5 is another alternative embo-limçnt of power control circuitry for an RF transmitter, embodying the present invention.
FIG. 6 is a block diagram of a TDMA cellular telephone, which may advantageously utilize the power control circuitry of the present invention, as embodied preferably in FIG. 1 and alternatively in FIG. 4 or FIG. 5.
FIG. 7 is a circuit diagram of long time constant detector 116 in FIG. 1.
Description of the r~ ere~ 1 ed F,mhotlim~nt Referring to FIG. 6, there i9 illustrated a block diagram of a TDMA cellular telephone 600, which may advantageously utilize the power control circuitry of the present invention, as embodied ~lefe~ably in FIG. 1 and alternat*ely in FIG. 4 or FIG. 5. TDMA cellular telephone 600 includes, in its transmit signal path, microphone 608, vocoder 612, data format circuitry 601, quadrature modulator 602, 90 MHz local oscillator 606, transmitter with mixer 604, trans~itter filter 618, and antenna 620. In its leceive signal path, TDMA
cellular telephone 600 includes antenna 620, receiver filter 622, ~4~ 2r)725~2 quadrature demodulator 624, and data deformat circuitry 625.
The rh~nnel frequency of TDMA cellular telephone 600 is loaded into synthesizer 616 by microcomputer 614 and applied to transmitter 604 and demodulator 624. In the preferred embodiment, the duplex radio çh~nnel~ have transmit freqllençies in the range from 824 MHz to 849 MHz and receive frequencies in the range from 869 MHz to 894 MHz. TDMA
cellular telephone 600 is controlled by microcomputer 614 which includes a memory with a control and si~n~1ing computer program stored therein. In the preferred embodiment of TDMA cellular telephone 600, microcomputer 614 i6 implemented with commercially available microcomputers, such as, for example, the Motorola type 68HC11 microcomputer. Although cellular telephone 600 utilizes TDMA RF ch~tnnçl~ the present invention may also be tltilize~3 in conventional frequency division multiple acces&
cellular telephones, in code division multiple access cellular telephones, and in other analog and digital cellular telephones employing different tr~nsmi~sion schemes.
ao In the preferred embodiment of TDMA cellular telephone 600 in FIG. 6, quadrature modulator 602 is implemented as described in the instant assignee's copen~ling patent application no. 07/526,156, (now US patent no. 5,020,076 granted May 28, 1991) entitled aHybrid Modulation Apparatus, invented by Stephen V. Cahill et al., and filed May 21, 1990. Quadrature modulator 602 mo~ t~s TDMA RF signals with voice, data and 8ign~11in~ information according to 1rJ4-shift differential quadrature phase shift keying (DQPSK). DQPSK modulation is described in aDigital Communications", by John G. Proakis, 1st Ed., ISBN 0-07-050927-1, at pages 171-178. Data format ci- c ~it~ .~ 601 combines the output of vocoder 612 with si~lling and overhead information and encode~ the result according to ~I/4-shift DQPSK modulation into the transmit I
,~ ,c ~
~5~ 2Qf 25P~
and Q sign~l~. The 7t/4-shift DQPSK modulation and ~i~n~llin~ information is specified in Interim Standard 54 pllhli~hed by and available from the Electronic Industries Association, ~ngineering Department, 2001 Eye Street N.W., 5 W~shir~ton, D.C. 20006.
The signal vector representin~ the ~/4-shift DQPSK
modulation consists of a cosine component and a sine component. The signal scaling the amplitude of the cosine component is also known as the in-phase or I signal and the 10 signal scaling the a~nplitude of the sine component is also known as the quadrature or Q signal. The I and Q scaled cosine and sine Ri,~n~l~ are the orthogonal quadrature components at the frequency of the 90 MHz signal from local oscillator 606; the modulated transmit IF signal 102 then 15 being created by adding the I and Q sign~qlg.
Symbols representing the vector components of the I
and Q sign~lR are generated in data format ci~cuiL~ 601 by shifting the vector components such that phase shifts of IF
signal 102 of +~/4 or +3~/4 r~ n~ are generated. Each phase ao shift enço-les one of four possible symbols.
Serial digital data from vocoder 612 that is eventually to be modulated by modulator 602 is first collve~ l,ed to bit pairs in data format circuitry 601. Each bit pair specifies a symbol that is the desired vector shift relat*e to the previously transmitted 25 symbol. The mapping of bit pairs to symbol vectors is according to the equations:
I(k) = I(k-1)cos(~0(X(k),Y(k)))-Q(k-1)sin(~0(X(k),Y(k))) Q(k) = I(k-1)sin(~0(X(k),Y(k)))+Q(k-1)cos(~0(X(k),Y(k))) where k is an index of the bit pairs; k=1 for bits one and two paired, k=2 for bits three and four paired, etc. I(k-1) and Q(k-1) are the amplitudes of the cosine and sine components of the previous symbol vector. X(k) represents the first bit of bit pair ~7~ 5 ~2 (k) and Y(k) represents the second bit of bit pair (k). The phase change, ~o, is determined according to the following table:
~k2 ~ A0(X(k).Y(k)) -37~/4 O 1 3~1/4 O O ~1/4 0 -Ir/4 5 Thus, one of four possible symbols are transmitted for each two bits of the serial data stream.
The reason for the modulation nomenclature ~/4-shift DQPSK and how it worka is now evident: the phase shift is in 7c/4 increments in vector space, symbols are differentially 10 encoded with respect to the previous symbol vector, and the information bearing quantity in IF signal 102 is the phase-shift with one of four possible shifts between any two symbols.
The operation of modulator 602 i6 represented by the equation:
VoUt(t)= (I(t))cos(2Jtft)+(Q(t))sin(2~1ft) where VoUt(t) is the modulated IF signal 102 and I(t) and Q(t) are I(k) and Q(k) as defined above as a function of time, and f is the transmit IF of 90 MHz.
ao In the preferred embodiment of TDMA cellular telephone 600 in FIG. 6, quadrature demodulator 624 is implemented as described in the instant ~ gnee~s copending C~n7~ n patent application no. 2,071,869, entitled "A Carrier Recovery Method and Apparatus Having an Adjustable Response Time Determined by Carrier Signal Parameters", invented by Stephen V. Cahill, and filled 24 September, 1991. Quadralure demodulator 624 demod1l1ates TDMA RF signala modulated with information according to 1~J4-shift DQPSK and generates the receive I and 20725~2 Q 8i~nAlfi The receive I and Q si~nAl~ are deformated and ~ccoAe~l by data deformat ~lc~ill ~ 625 to ~cu~er the digitized voice ~ignAla, which are applied to vocoder 612.
In the preferred embodiment of TDMA cellular telephone 600 in FIG. 6, vocoder 612 is implemented as described in the instant assignee's US patent nos. 4,817,157 and 4,896,361. Vocoder 612 encodes and decodes voice Ei~nAl~ according to code excited linear prediction (CELP) cotling. P'ilters 618 and 622 are intercoupled as a duplexer for transmitting TDMA RF signAl~
on, and receiving TDMA RF signAls from antenna 620. Filters 618 and 622 may be any suitable cuuvelltional filters, such as, for example, the filters described in US patent nos. 4,431,977, 4,692,726, 4,716,391, and 4,742,562 (incorporated herein by reference). Vocoder 612, data format circuitry 601, data deformat circuitry 625, quadrature modulator 602, and quadrature demodulator 624 may be implemented with commercially available digital signal processors, such as, for example, the Motorola type DSP 56000 digital signal processor.
According to the present invention, power control circuitry of transmitter 604 in FIG. 6 iB preferably implemented as illustrated in FIG. 1 and may be alternatively implemented as illustrated in FIG. 4 or FIG. 5. Although utilized in TDMA cellular telephones 600, the power control circuitry of the present invention may also be utilized in conventional frequency division multiple access cellular telephones, in code division multiple access cellular telephones, and in other analog and digital cellular telephones employing different transmission schemes. Referring now to FI~. 1, the power control circuitry include~ variable gain stage 104, mixer 106, bandpass filter 109, and directional coupler 112 in a forward path, and detector 116, analog-to digital (A/D) converter 118, digital controller 120 and digital-to analog (D/A) converter 126 in a feedback path. Transmit I~
, ~ ~
-8- 207~ 2 signal 102 from quadrature modulator 602 has a frequency of 90 MHz and is modulated with DQPSK information. Stage 104 has a variable gain for adjusting the magnitude of IF signal 102 in response to DtA co~ . ler output signal 128. Stage 104 5 may be implçmentefl by means of a variable gain Amplifier or a variable gain attenuator, where the gain is adjusted subst~ntiAlly in proportion to the value of gain control signal 128. In the preferred embodiment, stage 104 i8 a variable gain ~mplifier simil~r to the Motorola type MC1350 IF Amplifier.
10 The adjusted IF signal from stage 104 is mixed with the RF
reference signal 108 from srthesi7er 616 to produce the RF
trans_it signal. The RF transmit signal is filtered by bAntlp~s filter 109 and ~mplified by RF Amp1ifier 110 to produce the RF transmit output signal 114. The transmit 15 output signal 114 is coupled by directionAl coupler 112 to transmit filter 618 and thereafter AntennA 620 for transmlssion.
The operation of the power control circuitry in FIG. 1 is further illustrated by the timing diagram in FIG. 2. Timing signal 124 has a waveform ~lefining a series of transmit intervals, which in FIG. 2 correspond to time slot TS1 of three possible time slots TS1, TS2, and TS3 for a TDMA RF chAnnel.
The TDMA RF ~hAnnel consists of multiple frames of 20 milliseconds each cont~ining three time slots TS1, TS2, and 25 TS3 of appro~imAtely 6.67 milliseconds each. During a cellular telephone call in a TDMA cellular system, TDMA
cellular cellular telephone 600 is assigned to a TDMA RF
chAnnel and a time slot of that chAnnel for tr~n~mission of the modulated transmit output signal 114 carrying voice signAl~, nAllin~ information and overhead information.
Accordingly, it is necessary that the transmit output signal 114 be transmitted at the desired power level selected by the power level sign~ls 122 during each of the Acsigned time slots.
9 2072~9~
Acco~Lllg to a feature of the present invention, D/A
c~vel ler 126 is loaded by controller 120 at the be~inning of each ~si ne-l time slot with the value stored in its memory and at the end of each ~ ne-l time slot with a zero value for 5 essentiAlly turning the transmit output signal 114 on and off.
In addition, ~mplifier 110 may also be turned on and off by gating its bias on and offby way of bias control signal 136. The D/A converter output 128 in FIG. 2 has a value which varies from time slot to time slot to m~int~in the output power of 10 transmit output signal 114 at the desired power level. The waveform of detector output 130 in FIG. 2 has an exponçnt~
response due to the relatively long time constant of detector 116 with respect to the time slot length. Due to the relatively long time con~t~nt of detector 116, the output of detector 116 near the 15 end of the time slot has a value related to the average magnitude of the transmit output signal 114. Detector 116, as shown in FIG. 7, includes rectifying circuitry comprised of diode 702 and capacitor 704, and averaging circuitry col,.~l;sed of capacitors 704 and 708 and resistor 706. In the ao preferred embo-liment, averaging circuitry 704, 706 and 708 has a time constant of appro~imP~tsly one millisecond.
Near the end of each time slot as illustrated by the sample times in FIG. 2, the value of the detector output 130 is sampled and used by controller 120 to coulpute a new value of 25 D/A convel ler output 128 by subtracting the sampled value of the detector output 130 from the desired value for the selected power level, scaling the ~ e~ellce by a pre-selected factor, and snmming the scaled difference with the previous value stored in memory. The new value of D/A converter output 128 is 30 stored by controller 120 in its memory and loaded into D/A
converter 126 at the be~inning of the next ~csigned time slot.
Referring next to FIG 3, there is illustrated a flow chart for the process used by controller 120 for maint~ining the output power of the transmit output signal 114 at the desired -lo- 2~725~2 power level. Entering at START block 302, the process proceeds to decision block 304, where a check of timing signal 124 is made to determine if timing signal 124 has a binary one state. If not, NO branch iB taken to wait. If timing signal 124 5 has a binary one state, YES branch is taken from decision block 304 to block 306, where a check of is made to determine if transmitter 604 is initially being keyed up (i.e., turned on). If so, YES branch is taken to block 308 where an initial value for D/A co,lvel ler output 128 is retrieved for a lookup table in the memory of controller 120. If tr?.nfimitter 604 is not being initially keyed up, NO branch is taken from decision block 306 to block 307 where the previously stored value (i.e. stored during previous ~s~qi~ned time slot) for D/A converter output 128 is retrieved from the memory of controller 120. Next, at block 310, the retrieved value of for D/A collvel ler output 128 is applied to D/A converter 126. D/A converter 126 in turn collvel ls the applied value to an analog voltage, which is applied to variable gain stage 104 for adjusting the amount of gain.
Next, at decision block 312 in FIG 3, a check of timing signal 124 is made again to determine if the timing signal 124 has a binary zero state. If not, NO branch iB taken to wait. If timing signal 124 has a binary zero state, YES branch is taken from decision block 312 to block 314, where the value of detector output 130 iB read from A/D co,lveL ler 118. Next, at block 316, transmitter 604 is dekeyed (i.e., shut off) by setting D/A
col~ve, ler output 128 to zero. Then, at block 318, a new value of D/A converter output 128 is calculated by subtracting the sampled value of the detector output 130 from the desired value for the selected power level, scaling the difference by a pre-selected factor, and sllmmin~ the scaled difference with the previous value of D/A converter output 128 stored in memory.
Then, the new value of D/A converter output 128 is stored in the memory of controller 120 at block 320 for use during the -11- 2Q72~82 next ~signe~ time slot, and control returns to decision block 304 to repeat the foregoing process for the next ~ssigned time slot.
Referring next to FIG 4, there is illustrated an alternative embodiment of power control circuitry for TDMA
RF transmitters, embodying the present invention. In this embotlimant, rather than a long time constant detector 116 as in FIG 1, output power is continllously ~etectecl and corrected by means of detector 426, which extracts the modlll~ion envelope of the modulated transmit IF signal prior to level adjustment The output of ~letsct~r 426 is then multiplied by multiplier D/A converter (DAC) 428 in order to produce a scaled modulation envelope sign~l~ the scs~lin~ factor being chosen to produce the desired power level of transmit output signal 114 (i.e., each power level has a predetermined s~linp~
factor). The scaled modulation envelope signal from DAC 428 is applied to the positive input of error ~mplifier 424, which produces a gain control signal for adjusting the gain of variable gain stage 104. Detector 422 (which may be a diode ao detector) receives a portion of transmit output signal 114 via coupler 112, and produces a detector output signal representing the transmit envelope of the transmit output signal 114. This envelope si~n ~l, without time delay, forms the negative input to error ~mplifier 424. Variable gain stage 104, mixer 106, h~n(lp~s filter 130 and ~mplifier 110 then operate to reduce the error between transmit envelope from detector 422 and modulation envelope from DAC 428 to zero, and thus _aintain output power of transmit output signal 114 at a desired power level selected by the scaling factor applied to multiplier DAC 428 by microcomputer 614. The scaling factor applied by microcomputer 614 to DAC 428 is selected by the level control sign~l~, in the substantially the same m~nner which power level sign~l~ 122 are applied to the digital controller 120 of FIG 1. In FIG 4, mixers 404 and 408, phase -12- 2~72~i~2 shif~er 406, and comhiner 410 form a quadrature modulator, such as is ~iscll~se~l in the aforementioned copenfline patent application no. 07/526,156.
Referring next to FIG 5, there is illustrated another 5 alternative embodiment of power control circuitry for TDMA
RF transmitters, embodying the present invention. In the embo~liment of FIG 5, the method of FIG 4 is implemente-l in an Alternate mAnner by means of diode detector 524 and A/D
converter 118, the output of which is connecte~l to a digital 10 controller 502. Digital controller 502, D/A converters 504 and 512, mixers 404 and 408, phase shifter 406, and comhiner 410 together form a quadrature modulator, such as i6 discussed in the aforçmentioned copen~ling patent application no.
07/526,156. A compAring fi~nrt;on is incorporated in digital 15 controller 502, in the mAnner of error Amrlifier 424 of FIG 4, where one input is the output of A/D converter 118 and the other input, G, i8 a scaled magnitude signal derived from the transmit I SIGNAL, transmit Q SIGNAL, and POWER
LEVEL ~ignAl~ 122 using the following equation:
ao G = [(I SIGNAL)2 + (Q SIGNAL)2]l/2 * POWER LEVEL * C
Where C is a sCAline constant correcting for fixed component gain (i.e., each power level has a predetermined power level 25 constant POWER LEVEL and a predetermined sc~ing constant C).
In the embodiment of FIG 5, periodic adjustment of transmit output signal 114 in response to the compAring function in digital controller 502 iB done during each Assiened 30 ~me slot by means of variable gain stage 104, and also by means of gain adjustments applied by digitAl controller 502 to the I SIGNAL and Q SIGNAL as they are pA~se~l to D/A
col,vel lers 604 and 512 through digitAl controller 502. This additional gain adjustment within digital controller 502 -13- 2072~82 permits an increase in the total range of output power for transmit output signal 114, the limiting amount of increase being the usable range of D/A collvel lers 504 and 512.
In the embodiment of FIG 5, the times at which periodic 5 adjustments are made to transmit output signal 114 during each ~signed time slot may be selected to minimi7~e required dynamic range of detector 524. Acco~.lillg to EIA IS-54, the modulation is specified as ~c/4-shift DQPSK with alpha equal to 0.35 SQRC bA~eb~n~l filtering. ~rJ4-shift DQPSK modulation 10 modulates the envelope of the RF carrier signal. Envelope modulation of the RF carrier signal increases the dynamic range over which detector 524 must operate. In the case of ~/4-shift DQPSK with alpha equal to 0.35 SQRC baseband filtering, the peak-to-average envelope power is 3 dB, and the average-to-15 minimum envelope power is 14 dB. As a result, an additional17 dB is added to the 28 dB dyn~mic range of detector 524 in order to cover the eight 4 dB power steps. To minimi7.e the dynamic range over which detector 524 must operate, transmit output signal 114 is preferably sampled at the m~lrimum effect ao points of the ~/4-shift DQPSK modulation. ~mpling at these times reduces the additional dynamic range to 4 dB instead of 17 dB. The point in each time slot at which the m~imum effect points occur is well known, and is determined by the location of the input impulses in the alpha equal to 0.35 SQRC
25 finite impulse response baseband filters. The m~imum effect points are also described in EIA IS-54.
In sllmm~ry, unique output power control circuitry maintains the output power of transmit output signal at a desired power level selected by power level ~ign~l~ during a 30 series of transmit intervals, such as, for e~mple, the ~s~igned time slots of a TDMA RF ch~nnel. In operation, a variable gain stage is used to adjust a modulated IF signS~l, which is then mixed with an RF reference signal to produce the transmit RF signal. The transmit RF signal is ~mplified -14- 2072~2 by an RF ~mplifier to produce the transmit RF output signal which is coupled by a direction~l coupler and transmit Slter to an ~ntenn~ for tr~ncmiR~ion. The novel output power control circuitry of the present invention may be advantageously ntili7.e~l in TDMA cellular telephones as well as in conventional frequency division multiple access cellular telephones, in code division multiple access cellular telephones, and in other analog and digital cellular telephones employing different tr~n~mi~sion sçhemes.
Claims (30)
1. Power control circuitry responsive to level control signals and a transmit intermediate frequency (IF) signal from a signal source for maintaining the magnitude of a radio frequency (RF) output signal at a power level selected from a plurality of power levels by the level control signals, said power control circuitry comprising:
reference means for generating an RF reference signal;
adjusting means having variable gain for adjusting the transmit IF signal substantially in proportion to the value of a gain control signal to produce an adjusted transmit IF signal;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce an RF transmit signal;
amplifying means for amplifying the RF transmit signal to produce the RF output signal;
detecting means coupled to the RF output signal for generating a detector output signal having a value related to the magnitude of the RF output signal; and control means coupled to the detector output signal for, at a plurality of intervals, sampling the value of the detector output signal, and adjusting the value of the gain control signal in response to the difference between the sampled value of the detector output signal and a desired value of the selected power level.
reference means for generating an RF reference signal;
adjusting means having variable gain for adjusting the transmit IF signal substantially in proportion to the value of a gain control signal to produce an adjusted transmit IF signal;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce an RF transmit signal;
amplifying means for amplifying the RF transmit signal to produce the RF output signal;
detecting means coupled to the RF output signal for generating a detector output signal having a value related to the magnitude of the RF output signal; and control means coupled to the detector output signal for, at a plurality of intervals, sampling the value of the detector output signal, and adjusting the value of the gain control signal in response to the difference between the sampled value of the detector output signal and a desired value of the selected power level.
2. The power control circuitry according to claim 1, wherein said control means includes analog to digital converting means coupled to the detecting means, digital to analog converting means coupled to the adjusting means, and processing means coupled to said analog to digital converting means and said digital to analog converting means, said analog to digital converting means for converting the detector output to a digitized signal, said processing means sampling the digitized signal to sample the value of the detector output signal and generating a digitized gain control signal, and said digital to analog converting means converting the digitized gain control signal to the gain control signal.
3. The power control circuitry according to claim 1, further including antenna means and directional coupling means, said directional coupling means coupling a first portion of the RF output signal to the antenna means and coupling a second portion of the RF output signal to the detecting means.
4. The power control circuitry according to claim 1, wherein said detecting means comprises diode detecting means.
5. The power control circuitry according to claim 1, further including filtering means intercoupling said mixing means and said amplifying means.
6. Power control circuitry responsive to a timing signal defining a series of transmit intervals, level control signals, and a transmit intermediate frequency (IF) signal from a signal source for maintaining during the transmit intervals the average magnitude of a radio frequency (RF) output signal at a power level selected from a plurality of power levels by the level control signals, said power control circuitry comprising:
reference means for generating an RF reference signal;
memory means for storing the value of a gain control signal;
adjusting means having variable gain for adjusting the transmit IF signal during the transmit time intervals substantially in proportion to the stored value of the gain control signal to produce an adjusted transmit IF signal, said adjusting means substantially blocking the transmit IF
signal at times other than those during the transmit intervals;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce an RF transmit signal;
amplifying means for amplifying the RF transmit signal to produce the RF output signal;
detecting means coupled to the RF output signal for generating a detector output signal having a value related to the average magnitude of the RF output signal; and control means coupled to the detector output signal for, substantially at the end of each transmit interval, sampling the value of the detector output signal, adjusting the value of the gain control signal in response to the difference between the sampled value of the detector output signal and a desired value of the selected power level, and storing the adjusted value of the gain control signal in the memory means.
reference means for generating an RF reference signal;
memory means for storing the value of a gain control signal;
adjusting means having variable gain for adjusting the transmit IF signal during the transmit time intervals substantially in proportion to the stored value of the gain control signal to produce an adjusted transmit IF signal, said adjusting means substantially blocking the transmit IF
signal at times other than those during the transmit intervals;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce an RF transmit signal;
amplifying means for amplifying the RF transmit signal to produce the RF output signal;
detecting means coupled to the RF output signal for generating a detector output signal having a value related to the average magnitude of the RF output signal; and control means coupled to the detector output signal for, substantially at the end of each transmit interval, sampling the value of the detector output signal, adjusting the value of the gain control signal in response to the difference between the sampled value of the detector output signal and a desired value of the selected power level, and storing the adjusted value of the gain control signal in the memory means.
7. The power control circuitry according to claim 6, wherein said control means includes analog to digital converting means coupled to the detecting means, digital to analog converting means coupled to the adjusting means, and processing means coupled to said analog to digital converting means and said digital to analog converting means, said analog to digital converting means for converting the detector output to a digitized signal, said processing means sampling the digitized signal to sample the value of the detector output signal and generating a digitized gain control signal, and said digital to analog converting means converting the digitized gain control signal to the gain control signal.
8. The power control circuitry according to claim 6, further including antenna means and directional coupling means said directional coupling means coupling a first portion of the RF output signal to the antenna means and coupling a second portion of the RF output signal to the detecting means.
9. The power control circuitry according to claim 6, wherein said detecting means comprises diode detecting means and averaging means coupled in series.
10. The power control circuitry according to claim 6, further including filtering means interconnecting said mixing means and said amplifying means.
11. A time-division multiple-access (TDMA) cellular telephone, comprising:
an antenna;
a TDMA transmitter coupled to the antenna for generating a transmit intermediate frequency (IF) signal and transmitting a TDMA radio frequency (RF) output signal;
a TDMA receiver coupled to the antenna for receiving a TDMA RF input signal;
processing means coupled to the TDMA
transmitter and TDMA receiver for producing a timing signal defining a series of transmit intervals for transmitting the TDMA RF output signal and generating a plurality of level control signals for selecting a power level from a plurality of power levels; and said TDMA transmitter further including power control circuitry coupled to the timing signal and the level control signals for maintaining the magnitude of the TDMA
RF output signal at the selected power level, said power control circuitry further including:
reference means for generating an RF reference signal;
memory means for storing the value of a gain control signal;
adjusting means having variable gain for adjusting the transmit IF signal during the transmit time intervals substantially in proportion to the stored value of the gain control signal to produce an adjusted transmit IF signal, said adjusting means substantially blocking the transmit IF
signal at times other than those during the transmit intervals;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce a TDMA RF transmit signal;
amplifying means for amplifying the TDMA RF
transmit signal to produce the TDMA RF output signal;
detecting means coupled to the TDMA RF output signal for generating a detector output signal having a value related to the average magnitude of the TDMA RF output signal; and control means coupled to the detector output signal for, substantially at the end of each transmit interval, sampling the value of the detector output signal, adjusting the value of the gain control signal in response to the difference between the sampled value of the detector output signal and a desired value of the selected power level, and storing the adjusted value of the gain control signal in the memory means.
an antenna;
a TDMA transmitter coupled to the antenna for generating a transmit intermediate frequency (IF) signal and transmitting a TDMA radio frequency (RF) output signal;
a TDMA receiver coupled to the antenna for receiving a TDMA RF input signal;
processing means coupled to the TDMA
transmitter and TDMA receiver for producing a timing signal defining a series of transmit intervals for transmitting the TDMA RF output signal and generating a plurality of level control signals for selecting a power level from a plurality of power levels; and said TDMA transmitter further including power control circuitry coupled to the timing signal and the level control signals for maintaining the magnitude of the TDMA
RF output signal at the selected power level, said power control circuitry further including:
reference means for generating an RF reference signal;
memory means for storing the value of a gain control signal;
adjusting means having variable gain for adjusting the transmit IF signal during the transmit time intervals substantially in proportion to the stored value of the gain control signal to produce an adjusted transmit IF signal, said adjusting means substantially blocking the transmit IF
signal at times other than those during the transmit intervals;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce a TDMA RF transmit signal;
amplifying means for amplifying the TDMA RF
transmit signal to produce the TDMA RF output signal;
detecting means coupled to the TDMA RF output signal for generating a detector output signal having a value related to the average magnitude of the TDMA RF output signal; and control means coupled to the detector output signal for, substantially at the end of each transmit interval, sampling the value of the detector output signal, adjusting the value of the gain control signal in response to the difference between the sampled value of the detector output signal and a desired value of the selected power level, and storing the adjusted value of the gain control signal in the memory means.
12. The TDMA cellular telephone according to claim 11, wherein said control means includes analog to digital converting means coupled to the detecting means, digital to analog converting means coupled to the adjusting means, and processing means coupled to said analog to digital converting means and said digital to analog converting means, said analog to digital converting means for converting the detector output to a digitized signal, said processing means sampling the digitized signal to sample the value of the detector output signal and generating a digitized gain control signal, and said digital to analog converting means converting the digitized gain control signal to the gain control signal.
13. The TDMA cellular telephone according to claim 11, further including antenna means and directional coupling means, said directional coupling means coupling a first portion of the RF output signal to the antenna means and coupling a second portion of the RF output signal to the detecting means.
14. The TDMA cellular telephone according to claim 11, wherein said detecting means comprises diode detecting means and averaging means coupled in series.
15. The TDMA cellular telephone according to claim 11, further including filtering means intercoupling said mixing means and said amplifying means.
16. Power control circuitry responsive to a timing signal defining a series of transmit intervals, level control signals, and a transmit intermediate frequency (IF) signal from a signal source for maintaining the average magnitude of a radio frequency (RF) output signal at a power level selected from a plurality of power levels by the level control signals during the transmit intervals, said power control circuitry comprising:
reference means for generating an RF reference signal;
quadrature modulating means for modulating the transmit IF signal with I and Q signals from a signal source to produce a modulated transmit IF signal;
adjusting means having variable gain for adjusting the modulated transmit IF signal during the transmit time intervals substantially in proportion to the stored value of a gain control signal to produce an adjusted transmit IF signal, said adjusting means substantially blocking the modulated transmit IF signal at times other than those during the transmit intervals;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce an RF transmit signal;
amplifying means for amplifying the RF transmit signal to produce the RF output signal;
detecting means coupled to the RF output signal for generating a detector output signal having a value related to the magnitude of the RF output signal; and control means coupled to the detector output signal for sampling the value of the detector output signal a plurality of times during each transmit interval, computing a desired value of the selected power level from the I and Q
signals and predetermined constants, adjusting the value of the gain control signal in response to the difference between the sampled value of the detector output signal and the desired value of the selected power level, and applying the adjusted value of the gain control signal to the adjusting means.
reference means for generating an RF reference signal;
quadrature modulating means for modulating the transmit IF signal with I and Q signals from a signal source to produce a modulated transmit IF signal;
adjusting means having variable gain for adjusting the modulated transmit IF signal during the transmit time intervals substantially in proportion to the stored value of a gain control signal to produce an adjusted transmit IF signal, said adjusting means substantially blocking the modulated transmit IF signal at times other than those during the transmit intervals;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce an RF transmit signal;
amplifying means for amplifying the RF transmit signal to produce the RF output signal;
detecting means coupled to the RF output signal for generating a detector output signal having a value related to the magnitude of the RF output signal; and control means coupled to the detector output signal for sampling the value of the detector output signal a plurality of times during each transmit interval, computing a desired value of the selected power level from the I and Q
signals and predetermined constants, adjusting the value of the gain control signal in response to the difference between the sampled value of the detector output signal and the desired value of the selected power level, and applying the adjusted value of the gain control signal to the adjusting means.
17. The power control circuitry according to claim 16, wherein said control means includes analog to digital converting means coupled to the detecting means, digital to analog converting means coupled to the adjusting means, and processing means coupled to said analog to digital converting means and said digital to analog converting means, said analog to digital converting means for converting the detector output to a digitized signal, said processing means sampling the digitized signal to sample the value of the detector output signal and generating a digitized gain control signal, and said digital to analog converting means converting the digitized gain control signal to the gain control signal.
18. The power control circuitry according to claim 16, further including antenna means and directional coupling means, said directional coupling means coupling a first portion of the RF output signal to the antenna means and coupling a second portion of the RF output signal to the detecting means.
19. The power control circuitry according to claim 16, wherein said detecting means comprises diode detecting means.
20. The power control circuitry according to claim 16, further including filtering means intercoupling said mixing means and said amplifying means.
21. A time-division multiple-access (TDMA) cellular telephone, comprising:
an antenna;
a TDMA transmitter coupled to the antenna for generating a transmit intermediate frequency (IF) signal and transmitting a TDMA radio frequency (RF) output signal;
a TDMA receiver coupled to the antenna for receiving a TDMA RF input signal;
processing means coupled to the TDMA
transmitter and TDMA receiver for producing a timing signal defining a series of transmit intervals for transmitting the TDMA RF output signal and generating a plurality of level control signals for selecting a power level from a plurality of power levels; and said TDMA transmitter further including power control circuitry coupled to the timing signal and the level control signals for maintaining the magnitude of the TDMA
RF output signal at the selected power level, said power control circuitry further including:
reference means for generating an RF reference signal;
quadrature modulating means for modulating the transmit IF signal with I and Q signals from a signal source to produce a modulated transmit IF signal;
adjusting means having variable gain for adjusting the modulated transmit IF signal during the transmit time intervals substantially in proportion to the stored value of a gain control signal to produce an adjusted transmit IF signal, said adjusting means substantially blocking the modulated transmit IF signal at times other than those during the transmit intervals;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce an RF transmit signal;
amplifying means for amplifying the RF transmit signal to produce the RF output signal;
detecting means coupled to the RF output signal for generating a detector output signal having a value related to the magnitude of the RF output signal; and control means coupled to the detector output signal for sampling the value of the detector output signal a plurality of times during each transmit interval, computing a desired value of the selected power level from the I and Q
signals and predetermined constants, adjusting the value of the gain control signal in response to the difference between the sampled value of the detector output signal and the desired value of the selected power level, and applying the adjusted value of the gain control signal to the adjusting means.
an antenna;
a TDMA transmitter coupled to the antenna for generating a transmit intermediate frequency (IF) signal and transmitting a TDMA radio frequency (RF) output signal;
a TDMA receiver coupled to the antenna for receiving a TDMA RF input signal;
processing means coupled to the TDMA
transmitter and TDMA receiver for producing a timing signal defining a series of transmit intervals for transmitting the TDMA RF output signal and generating a plurality of level control signals for selecting a power level from a plurality of power levels; and said TDMA transmitter further including power control circuitry coupled to the timing signal and the level control signals for maintaining the magnitude of the TDMA
RF output signal at the selected power level, said power control circuitry further including:
reference means for generating an RF reference signal;
quadrature modulating means for modulating the transmit IF signal with I and Q signals from a signal source to produce a modulated transmit IF signal;
adjusting means having variable gain for adjusting the modulated transmit IF signal during the transmit time intervals substantially in proportion to the stored value of a gain control signal to produce an adjusted transmit IF signal, said adjusting means substantially blocking the modulated transmit IF signal at times other than those during the transmit intervals;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce an RF transmit signal;
amplifying means for amplifying the RF transmit signal to produce the RF output signal;
detecting means coupled to the RF output signal for generating a detector output signal having a value related to the magnitude of the RF output signal; and control means coupled to the detector output signal for sampling the value of the detector output signal a plurality of times during each transmit interval, computing a desired value of the selected power level from the I and Q
signals and predetermined constants, adjusting the value of the gain control signal in response to the difference between the sampled value of the detector output signal and the desired value of the selected power level, and applying the adjusted value of the gain control signal to the adjusting means.
22. The TDMA cellular telephone according to claim 21, wherein said control means includes analog to digital converting means coupled to the detecting means, digital to analog converting means coupled to the adjusting means, and processing means coupled to said analog to digital converting means and said digital to analog converting means, said analog to digital converting means for converting the detector output to a digitized signal, said processing means sampling the digitized signal to sample the value of the detector output signal and generating a digitized gain control signal, and said digital to analog converting means converting the digitized gain control signal to the gain control signal.
23. The TDMA cellular telephone according to claim 21, further including antenna means and directional coupling means, said directional coupling means coupling a first portion of the RF output signal to the antenna means and coupling a second portion of the RF output signal to the detecting means.
24. The TDMA cellular telephone according to claim 21, wherein said detecting means comprises diode detecting means.
25. The TDMA cellular telephone according to claim 21, further including filtering means intercoupling said mixing means and said amplifying means.
26. Power control circuitry responsive to level control signals and a transmit intermediate frequency (IF) signal from a signal source for maintaining the magnitude of a radio frequency (RF) output signal at a power level selected from a plurality of power levels by the level control signals, said power control circuitry comprising:
first detecting means coupled to the transmit IF
signal for generating a first detector output signal having a value related to the magnitude of the transmit IF signal;
reference means for generating an RF reference signal;
adjusting means having variable gain for adjusting the transmit IF signal substantially in proportion to the value of a gain control signal to produce an adjusted transmit IF signal;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce an RF transmit signal;
amplifying means for amplifying the RF transmit signal to produce the RF output signal;
second detecting means coupled to the RF output signal for generating a second detector output signal having a value related to the magnitude of the RF output signal;
control means coupled to the first detector output signal for, at a plurality of intervals, sampling the value of the first detector output signal, and computing a desired value of the selected power level from the sampled value of the first detector output signal and predetermined constants; and comparing means for adjusting the value of the gain control signal in response to the difference between the value of the second detector output signal and the desired value of the selected power level.
first detecting means coupled to the transmit IF
signal for generating a first detector output signal having a value related to the magnitude of the transmit IF signal;
reference means for generating an RF reference signal;
adjusting means having variable gain for adjusting the transmit IF signal substantially in proportion to the value of a gain control signal to produce an adjusted transmit IF signal;
mixing means for combining the adjusted transmit IF signal and the RF reference signal to produce an RF transmit signal;
amplifying means for amplifying the RF transmit signal to produce the RF output signal;
second detecting means coupled to the RF output signal for generating a second detector output signal having a value related to the magnitude of the RF output signal;
control means coupled to the first detector output signal for, at a plurality of intervals, sampling the value of the first detector output signal, and computing a desired value of the selected power level from the sampled value of the first detector output signal and predetermined constants; and comparing means for adjusting the value of the gain control signal in response to the difference between the value of the second detector output signal and the desired value of the selected power level.
27. The power control circuitry according to claim 26, wherein said control means includes analog to digital converting means coupled to the detecting means, digital to analog converting means coupled to the adjusting means, and processing means coupled to said analog to digital converting means and said digital to analog converting means, said analog to digital converting means for converting the detector output to a digitized signal, said processing means sampling the digitized signal to sample the value of the detector output signal and generating a digitized gain control signal, and said digital to analog converting means converting the digitized gain control signal to the gain control signal.
28. The power control circuitry according to claim 26, further including antenna means and directional coupling means, said directional coupling means coupling a first portion of the RF output signal to the antenna means and coupling a second portion of the RF output signal to the detecting means.
29. The power control circuitry according to claim 26, wherein said first and second detecting means comprise first and second diode detecting means, respectively.
30. The power control circuitry according to claim 26, further including filtering means intercoupling said mixing means and said amplifying means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63223190A | 1990-12-20 | 1990-12-20 | |
| US632,231 | 1990-12-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2072582A1 CA2072582A1 (en) | 1992-06-21 |
| CA2072582C true CA2072582C (en) | 1996-04-09 |
Family
ID=24534645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002072582A Expired - Lifetime CA2072582C (en) | 1990-12-20 | 1991-12-18 | Power control circuitry for a tdma radio frequency transmitter |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US5193223A (en) |
| JP (1) | JP2868899B2 (en) |
| KR (1) | KR960007138B1 (en) |
| BR (1) | BR9106405A (en) |
| CA (1) | CA2072582C (en) |
| DE (1) | DE4193230C1 (en) |
| GB (1) | GB2257331B (en) |
| HK (1) | HK67097A (en) |
| MX (1) | MX173851B (en) |
| WO (1) | WO1992011705A1 (en) |
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1992
- 1992-07-27 US US07/920,178 patent/US5193223A/en not_active Expired - Lifetime
- 1992-08-19 GB GB9217653A patent/GB2257331B/en not_active Expired - Lifetime
-
1997
- 1997-05-22 HK HK67097A patent/HK67097A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| WO1992011705A1 (en) | 1992-07-09 |
| CA2072582A1 (en) | 1992-06-21 |
| MX9102726A (en) | 1992-07-01 |
| HK67097A (en) | 1997-05-30 |
| DE4193230C1 (en) | 1997-10-30 |
| KR960007138B1 (en) | 1996-05-27 |
| JP2868899B2 (en) | 1999-03-10 |
| GB2257331A (en) | 1993-01-06 |
| US5193223A (en) | 1993-03-09 |
| MX173851B (en) | 1994-04-06 |
| GB2257331B (en) | 1995-04-26 |
| JPH05508525A (en) | 1993-11-25 |
| KR920704459A (en) | 1992-12-19 |
| GB9217653D0 (en) | 1992-10-28 |
| BR9106405A (en) | 1993-05-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKEX | Expiry |