CA2078303C - Voltage regulator - Google Patents
Voltage regulatorInfo
- Publication number
- CA2078303C CA2078303C CA002078303A CA2078303A CA2078303C CA 2078303 C CA2078303 C CA 2078303C CA 002078303 A CA002078303 A CA 002078303A CA 2078303 A CA2078303 A CA 2078303A CA 2078303 C CA2078303 C CA 2078303C
- Authority
- CA
- Canada
- Prior art keywords
- voltage
- transistor
- current
- producing
- responsive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
- G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
Abstract
A system for regulating an output voltage to a particular value includes a control transistor which produces an output voltage when energized by an energizing voltage. A
voltage divider formed as by a pair of transistors with a particular ratio of transconductances divides the magnitude of this output voltage by a ratio related to the ratio of the transconductances. The transistors in the voltage divider may be respectively CMOS n- and p- transistors. The divided output voltage is introduced to a comparator (formed as from a pair of transistors) for comparison with a fixed reference voltage obtained as from a resistance ladder energized by the energizing voltage. The comparator introduces voltages to a comparator amplifier in accordance with such comparison. The comparator amplifier may include a transistor which produces changes in a current related to changes in the divided output voltage. The comparator amplifier may further include a current mirror which provides changes in a current related to changes in the current through the amplifier transistor. The current changes in the current mirror cause changes to be produced in a voltage (e.g. error voltage) from the current mirror. These error voltage changes are introduced to the control transistor to regulate the output voltage to the particular value.
voltage divider formed as by a pair of transistors with a particular ratio of transconductances divides the magnitude of this output voltage by a ratio related to the ratio of the transconductances. The transistors in the voltage divider may be respectively CMOS n- and p- transistors. The divided output voltage is introduced to a comparator (formed as from a pair of transistors) for comparison with a fixed reference voltage obtained as from a resistance ladder energized by the energizing voltage. The comparator introduces voltages to a comparator amplifier in accordance with such comparison. The comparator amplifier may include a transistor which produces changes in a current related to changes in the divided output voltage. The comparator amplifier may further include a current mirror which provides changes in a current related to changes in the current through the amplifier transistor. The current changes in the current mirror cause changes to be produced in a voltage (e.g. error voltage) from the current mirror. These error voltage changes are introduced to the control transistor to regulate the output voltage to the particular value.
Description
2078303..
1 This invention relates to a voltage regulator. More 2 particularly, the invention relates to a system for regulating 3 an output voltage to a particular value.
1 This invention relates to a voltage regulator. More 2 particularly, the invention relates to a system for regulating 3 an output voltage to a particular value.
Variable delay lines are provided for a number of 6 different purposes. One purpose is to test the operation of 7 semiconductor chips in different operating equipment. The 8 operation of these semiconductor chips is tested by measuring 9 delays in signal transitions at strategic terminals in these chips. These delays are measured at a particular voltage 11 point in the signal transitions. For CMOS circuits, this 12 particular voltage may be 1.5 volts.
14 The particular transition voltage such as +1.5 volts is important. This voltage constitutes substantially the midpoint of the signal transitions. If the transition voltage varies from the particular value, the symmetry of the transitions in the rising and falling edges of the signal 19 being tested is disturbed. In other words, one of the rising ZO and falling transitions will occur above the midpoint of the 21 transitions and the other one of the rising and falling 22 transitions will occur below the mid point of the transitions.
23 This tends to invalidate or at least impair the tests being made on the signal transitions in the integrated circuit chip being tested.
27 In CMOS circuits, an optimal interface has to be 2g provided to the minimum TTL input specifications. The Zg energizing voltage VCC for CMOS circuits is generally +5 volts. A voltage Vpp is generated from the energizing voltage ul V« for use for input, output and delay processing logic. The 32 voltage Vpp is generally at +3 volts. A voltage, generally at 1 +1.5 volts, is provided to serve as the mid point for the 2 signal transitions. It has not been easy to generate these 3 voltages reliably to meet TTL input signal specifications 4 although significant amounts of money have been expended, and considerable effort has been devoted, to provide CMOS
6 circuitry which meets such specifications.
In one embodiment of the invention, a system for 9 regulating an output voltage to a particular value includes a control transistor which produces an output voltage when 11 energized by an energizing voltage. A voltage divider formed 12 as by a pair of transistors with a particular ratio of 13 transconductances divides the magnitude of this output voltage 14 by a ratio related to the ratio of the transconductances. The 7.5 transistors in the voltage divider may be respectively CMOS n-lfi and p- transistors. The divided output voltage is introduced ~_~r to a comparator (formed as from a pair of transistors) for ld comparison with a fixed reference voltage obtained as from a lg resistance ladder energized by the energizing voltage. The 2p comparator introduces voltages to a comparator amplifier in 21 accordance with such comparison. The comparator amplifier may 22 include a transistor which produces changes in a current z3 related to changes in the divided output voltage. The 24 comparator amplifier may further include a current mirror 25 which provides changes in a current related to changes in the current through the amplifier transistor. The current changes 27 in the current mirror cause changes to be produced in a u8 voltage (e. g. error voltage) from the current mirror. These 29 error voltage changes are introduced to the control transistor 30 to regulate the output voltage to the particular value.
In accordance with a first aspect of the invention, there is provided, in combination for providing an output voltage having a regulated value, means for providing an energizing voltage, control means responsive to the energizing voltage for producing a flow of current through the control means to obtain an output voltage, a pair of current means connected in a circuit with the control means for producing a first voltage constituting a particular fraction of the output voltage, means for providing a reference voltage, means including a current mirror responsive to the relative values of the reference voltage and the first voltage for introducing an error voltage to the control means to vary the current through the control means in a direction for producing the regulated value of the output voltage.
In accordance with a second aspect of the invention, there is provided, in combination for providing an output voltage having a regulated value, a transistor having a source, a gate and a drain, first means for introducing an energizing voltage to the source of the transistor to obtain a flow of current through the transistor and a voltage on the drain of the transistor in accordance with such current flow, second means for producing a particular reduction in the voltage on the drain of the transistor, means for providing a reference voltage, 2a s 20783p3 third means including a current mirror responsive to the reduced voltage and to the reference voltage for producing an error voltage in accordance with the relative values of the reduced voltage and the reference voltage, and fourth means responsive to the error voltage for introducing the error voltage to the gate of the transistor to regulate the current through the transistor for the production of the regulated voltage on the drain of the transistor.
In accordance with a third aspect of the invention, there is provided, a combination for providing in combination for providing an output voltage having a regulated value, a transistor having a source, a gate and a drain, first means for introducing an energizing voltage to the source of the transistor to obtain a flow of current through the transistor and a voltage on the drain of the transistor in accordance with such current flow, second means for producing a particular reduction in the voltage on the drain of the transistor, means for providing a reference voltage, third means responsive to the reduced voltage and to the reference voltage for producing an error voltage in accordance with the relative values of the reduced voltage and the reference voltage, and fourth means responsive to the error voltage for introducing the error voltage to the gate of the transistor to regulate the current through the transistor for the production of the regulated voltage on the drain of the transistor, 2b 20 78 30 3 .
the transistor constituting a first transistor, the third means including a second transistor responsive to the reduced voltage for producing a voltage dependent upon the reduced voltage and including a third transistor responsive to the voltage from the second transistor and to the reference voltage for producing the error voltage for introduction to the gate of the first transistor to regulate the current through the first transistor for the production of the regulated voltage on the drain of the first transistor.
In accordance with a fourth aspect of the invention, there is provided, in combination for providing an output voltage having a regulated value, means for providing an energizing voltage, first semiconductor means responsive to the energizing voltage for passing a variable current and for producing an output voltage dependent upon the variations in the current, second semiconductor means responsive to the output voltage for producing a first particular fraction of the output voltage, third semiconductor means responsive to the energizing voltage for producing a second particular fraction of the energizing voltage, fourth semiconductor means responsive to the first particular fraction of the output voltage and the second particular fraction of the energizing voltage for producing an 2c 20783p3 error voltage, and firth means including a current mirror responsive to the error voltage for introducing a voltage related to the error voltage to the first semiconductor means to vary the current through the first semiconductor means in a direction for maintaining the output voltage at the regulated value.
In accordance with a fifth aspect of the invention, there is provided, in combination for providing an output voltage having a regulated value, first means for providing an energizing voltage, control means responsive to the energizing voltage for producing a flow of current through the control means and an output voltage dependent upon such current flow, second means for obtaining a first particular fraction of the output voltage from the control means, third means for providing a second particular fraction of the energizing voltage, comparator means responsive to any difference between the first particular fraction of the output voltage from the control means and the second particular fraction of the energizing voltage for producing a voltage representative of such difference, fourth means responsive to the representative voltage from the comparator means for producing a current dependent upon the magnitude of such representative voltage, and a current mirror responsive to the current through 2d B
. 2078303 the fourth means for producing an error voltage for introduction to the control means for regulating the current through the control means to obtain the regulated value for the output voltage.
2e 1 In the drawings: 2 p 7 8 3 0 3 z 3 Figure 1 is a circuit diagram, almost entirely in 4 block form, of one embodiment of the invention;
Figure 2 is a somewhat detailed circuit diagram of 6 the embodiment of the invention shown in Figure if and 7 Figure 3 is a somewhat detailed circuit diagram of 8 another embodiment of the invention.
In the block diagram shown in Figure 1, a voltage 11 V~~ is provided at 10. The voltage V« may be +5 volts and may 12 be introduced to the source of a pass or control transistor 12 13 which may be a CMOS transistor of the p- type. The voltage on 14 the drain of the transistor 12 may be designated as a supply 1~ or output voltage and is introduced to a line 14 and to an 16 amplifier-inverter 16 to energize the amplifier-inverter. The p output of the amplifier-inverter 16 may be introduced to the 1~ input of the amplifier-inverter and to an input terminal of a 19 comparator/amplifier 18, a second input terminal of which ZO receives a reference voltage such as +1.5 volts. The output 21 of the comparator/amplifier 18 passes to the gate of the zZ control transistor 12.
24 The energizing voltage 10 causes current to pass 25 through the control transistor 12 so that a voltage approximating +3 volts is introduced to the line 14. The ?7 amplifier/inverter 16 is constructed to divide the voltage by 2g two (2) so that a voltage of +1.5 volts is introduced to the 2g comparator/amplifier 18 for comparison with the reference 30 voltage of +1.5 volts. Any difference or error voltage from 31 the comparator/amplifier 18 is introduced to the gate of the control transistor 12 to regulate the current through the ~'207g303 1 transistor 10 as to provide for the production of a regulated 2 output voltage of +3 volts at the drain of the transistor.
4 Figure 2 illustrates in some detail the embodiment of the invention shown in Figure 1 and described above. The 6 embodiment of the invention shown in Figure 2 includes the 7 line 10 for providing the energizing voltage V~~, the control g transistor 12 and the supply or output line 14 for providing g the voltage Vpp. The drain of the transistor 12 is connected to the source of a transistor 22 which may be a CMOS
11 transistor of the p- type. The drain and the gate of the 12 transistor 22 have a common connection with the drain of a 13 transistor 24 which may be a CMOS transistor of the n- type.
1~ The source of the transistor 24 may be at a suitable reference potential such as ground. The transistors 22 and 24 g preferably have substantially equal transconductances.
L 'l A connection is made from the drains of the lg transistors 22 and 24 to the gate of a transistor 30 which may 2p also be a CMOS transistor of the n- type. The sources of the ~ 21 transistor 30 and of a transistor 32 may be at the reference 22 potential such as ground. The transistor 32 may be a CMOS
23 transistor of the n- type and may form a comparator with the 24 transistor 30. The transistors 30 and 32 preferably have substantially equal characteristics. The gate of the 2g transistor 32 receives a reference potential such as +1.5 27 volts from the common terminal between a pair of resistances 2g 34 and 36. The resistances 34 and 36 are in series between 2g the line 10 and the reference potential such as ground and define a resistance ladder network.
3~
1 The drains of the transistors 30 and 32 are 2 respectively common with the drains of a-pair of transistors 3 38 and 40 both of which are CMOS transistors of the p- type.
4 The transistors 38 and 40 are included in a comparator/
amplifier. The transistors 38 and 40 preferably have 6 substantially equal characteristics. The sources of the 7 transistors 38 and 40 receive the voltage V« on the line l0.
8 The drain and the gate of the transistor 38 and the gate of 9 the transistor 40 are common. The voltage on the drain of the transistor 40 is introduced to the gate of the transistor 12.
1~ As previously described, the voltage on the line 14 13 is approximately +3 volts. This voltage is divided by the 14 transistors 22 and 24 so that the voltage on the drain of the transistors 22 and 24 is approximately +1.5 volts. This 16 voltage is introduced to the transistor~30 for comparison with I'7 the reference voltage on the gate of the transistor 32.
1 f3 19 Assume that the voltage introduced to the gate of the transistor 30 from the drains of the transistors 22 and 24 21 is less than the reference voltage of +1.5 volts on the gate 22 of the transistor 32. This causes the current through the 23 transistor 30 to be less than the current through the 24 transistor 32. Because of this, the voltage on the drains of the transistors 30 and 38 is greater than the voltage on the 26 drains of the transistor 32 and 40.
28 The transistor 30 effectively serves as a resistor.
29 Therefore, because of the increased voltage on the drain of the transistor 38, the current through the transistor 38 31 decreases, thereby producing an increased voltage on the drain 32 of the transistor 38 and the gate of the transistor 40. The s f s I.
1 current through the transistor 40 decreases as a result of the 2 increased voltage on the gate of the transistor. This causes 3 the voltage on the drain of the transistor 40 to decrease.
4 When introduced to the gate of the transistor 12, this voltage causes the current through the transistor 12 to increase, 6 thereby increasing the voltage on the drain of the transistor.
7 In this way, the voltage on the line 14 is regulated at +3 8 volts and the voltage on the drains of the transistors 22 and 9 24 is regulated at +1.5 volts.
11 Figure 3 illustrates another embodiment of the 12 invention. In this embodiment, the line 10, the transistor 13 12, the line 14 and the transistors 22 and 24 are provided in 14 the same manner as in the embodiment shown in Figure 2 and described above. However, the gates of the transistors 22 and 7_~, 24 are connected to the terminal common to the resistances 34 and 36. The resistance ladder 34 and 36 is also provided in 1.f3 the embodiment shown in Figure 3 in the same manner as in the 19 embodiment shown in Figure 2.
21 In the embodiment shown in Figure 3, the voltage on 22 the drains of the transistors 22 and 24 and the voltage on the 23 terminal common to the resistances 34 and 36 are respectively 24 introduced to the gates of transistors 50 and 52 in the same manner as in the embodiment shown in Figure 2. The 2g transistors 50 and 52 may be CMOS transistors of the n- type 27 and preferably have substantially equal characteristics. The 2g sources of the transistors are at the reference potential such 2g as ground. A capacitor 54 is connected between the gate and source of the transistor 52 to pass noise on the gate of the 31 transistor 52 to ground.
2078303 s A capacitor 56 is connected between the drain of the 2 transistor 50 and ground to pass any noise on the drain of the 3 transistor to ground. Connections are respectively made from 4 the drains of the transistors 50 and 52 to the drains of transistors 58 and 60, each of which may be a CMOS transistor 6 of the p- type. The transistors 58 and 60 preferably have 7 substantially equal characteristics. The sources of the 8 transistors 58 and 60 receive the energizing voltage v« on 9 the line 10. The gates of the transistors 58 and 60 are common with the drain of the transistor 60. A capacitor 62 is 11 connected between the drain of the transistor 60 and the line 12 10 to eliminate any noise on the drain of the transistor 60.
14 The source of a transistor 64 receives the energizing voltage on the line 10. The transistor 64 may be a 7.f CMOS transistor of the p- type. Connections are made from the 7.7 drain of the transistor 64 to the gate of the control ld transistor 12 and to the drain of a transistor 66, which may lg be a CMOS transistor of the n- type. The gate of the transistor 66 is common with the drain of the transistor 50.
21 The source of the transistor 66 receives the voltage on the 22 drains of the transistors 22 and 24.
Assume that the voltage on the drains of the 26 transistors 22 and 24 is less than 1.5 volts. This causes the 27 current through the transistor 52 to be greater than the 28 current through the transistor 50 and the voltage on the drain 2g of the transistor 52 to be lower than the voltage on the drain of the transistor 50. The reduced voltage on the drain of the 31 transistor 52 causes the current through the transistor 6o to 32 increase since the transistor effectively acts as a _.
1 resistance. This assures that the voltage on the drain of the 2 transistor 60 will be reduced.
4 The reduced voltage on the drain of the transistor 60 is introduced to the gate of the transistor 58 to produce 6 an increased current through the transistor 58 and a decreased 7 voltage drop across the transistor. The resultant increase in 8 the voltage on the drain of the transistor 58 produces an 9 increase in the current through the transistor 66 and accordingly a decrease in the voltage across the transistor.
11 This causes the voltage introduced to the gate of the lZ transistor 12 to decrease and the current through the 13 transistor to increase, thereby producing an increase in the voltage on the line 14.
l6 The increase in the voltage on the line 14 is ~.7 amplified by the transistors 22 and 24 because of the separate lEi connections to the gate and drain of each transistor. In this lg way, the voltage on the line 14 is regulated to provide a voltage of +3 volts. This regulation is even more sensitive 21 than that provided by the embodiment shown in Figure 2 because 22 of the operation of the transistors 22 and 24 in Figure 3 as 23 amplifiers, because of the inclusion of the transistors 64 and z4 66 in a folded-cascode gain stage and because of the inclusion of the capacitors 52, 56 and 62.
27 The circuitry described above has certain important ~g advantages. It provides a sensitive regulation of the voltage ~g Vpp to maintain the voltage at +3 volts. It also provides a sensitive regulation of a voltage of +1.5 volts to provide a 31 stable transition point for measuring signal amplitudes to determine the symmetry of rising and falling edges in such 1 signals. 2 ~ 7 8 3 ~ 3 3 Although this invention has been disclosed and 4 illustrated with reference to particular embodiments, the principles involved are susceptible for use in numerous other 6 embodiments which will be apparent to persons skilled in the 7 art. The invention is, therefore, to be limited only as 8 indicated by the scope of the appended claims.
7. 7
14 The particular transition voltage such as +1.5 volts is important. This voltage constitutes substantially the midpoint of the signal transitions. If the transition voltage varies from the particular value, the symmetry of the transitions in the rising and falling edges of the signal 19 being tested is disturbed. In other words, one of the rising ZO and falling transitions will occur above the midpoint of the 21 transitions and the other one of the rising and falling 22 transitions will occur below the mid point of the transitions.
23 This tends to invalidate or at least impair the tests being made on the signal transitions in the integrated circuit chip being tested.
27 In CMOS circuits, an optimal interface has to be 2g provided to the minimum TTL input specifications. The Zg energizing voltage VCC for CMOS circuits is generally +5 volts. A voltage Vpp is generated from the energizing voltage ul V« for use for input, output and delay processing logic. The 32 voltage Vpp is generally at +3 volts. A voltage, generally at 1 +1.5 volts, is provided to serve as the mid point for the 2 signal transitions. It has not been easy to generate these 3 voltages reliably to meet TTL input signal specifications 4 although significant amounts of money have been expended, and considerable effort has been devoted, to provide CMOS
6 circuitry which meets such specifications.
In one embodiment of the invention, a system for 9 regulating an output voltage to a particular value includes a control transistor which produces an output voltage when 11 energized by an energizing voltage. A voltage divider formed 12 as by a pair of transistors with a particular ratio of 13 transconductances divides the magnitude of this output voltage 14 by a ratio related to the ratio of the transconductances. The 7.5 transistors in the voltage divider may be respectively CMOS n-lfi and p- transistors. The divided output voltage is introduced ~_~r to a comparator (formed as from a pair of transistors) for ld comparison with a fixed reference voltage obtained as from a lg resistance ladder energized by the energizing voltage. The 2p comparator introduces voltages to a comparator amplifier in 21 accordance with such comparison. The comparator amplifier may 22 include a transistor which produces changes in a current z3 related to changes in the divided output voltage. The 24 comparator amplifier may further include a current mirror 25 which provides changes in a current related to changes in the current through the amplifier transistor. The current changes 27 in the current mirror cause changes to be produced in a u8 voltage (e. g. error voltage) from the current mirror. These 29 error voltage changes are introduced to the control transistor 30 to regulate the output voltage to the particular value.
In accordance with a first aspect of the invention, there is provided, in combination for providing an output voltage having a regulated value, means for providing an energizing voltage, control means responsive to the energizing voltage for producing a flow of current through the control means to obtain an output voltage, a pair of current means connected in a circuit with the control means for producing a first voltage constituting a particular fraction of the output voltage, means for providing a reference voltage, means including a current mirror responsive to the relative values of the reference voltage and the first voltage for introducing an error voltage to the control means to vary the current through the control means in a direction for producing the regulated value of the output voltage.
In accordance with a second aspect of the invention, there is provided, in combination for providing an output voltage having a regulated value, a transistor having a source, a gate and a drain, first means for introducing an energizing voltage to the source of the transistor to obtain a flow of current through the transistor and a voltage on the drain of the transistor in accordance with such current flow, second means for producing a particular reduction in the voltage on the drain of the transistor, means for providing a reference voltage, 2a s 20783p3 third means including a current mirror responsive to the reduced voltage and to the reference voltage for producing an error voltage in accordance with the relative values of the reduced voltage and the reference voltage, and fourth means responsive to the error voltage for introducing the error voltage to the gate of the transistor to regulate the current through the transistor for the production of the regulated voltage on the drain of the transistor.
In accordance with a third aspect of the invention, there is provided, a combination for providing in combination for providing an output voltage having a regulated value, a transistor having a source, a gate and a drain, first means for introducing an energizing voltage to the source of the transistor to obtain a flow of current through the transistor and a voltage on the drain of the transistor in accordance with such current flow, second means for producing a particular reduction in the voltage on the drain of the transistor, means for providing a reference voltage, third means responsive to the reduced voltage and to the reference voltage for producing an error voltage in accordance with the relative values of the reduced voltage and the reference voltage, and fourth means responsive to the error voltage for introducing the error voltage to the gate of the transistor to regulate the current through the transistor for the production of the regulated voltage on the drain of the transistor, 2b 20 78 30 3 .
the transistor constituting a first transistor, the third means including a second transistor responsive to the reduced voltage for producing a voltage dependent upon the reduced voltage and including a third transistor responsive to the voltage from the second transistor and to the reference voltage for producing the error voltage for introduction to the gate of the first transistor to regulate the current through the first transistor for the production of the regulated voltage on the drain of the first transistor.
In accordance with a fourth aspect of the invention, there is provided, in combination for providing an output voltage having a regulated value, means for providing an energizing voltage, first semiconductor means responsive to the energizing voltage for passing a variable current and for producing an output voltage dependent upon the variations in the current, second semiconductor means responsive to the output voltage for producing a first particular fraction of the output voltage, third semiconductor means responsive to the energizing voltage for producing a second particular fraction of the energizing voltage, fourth semiconductor means responsive to the first particular fraction of the output voltage and the second particular fraction of the energizing voltage for producing an 2c 20783p3 error voltage, and firth means including a current mirror responsive to the error voltage for introducing a voltage related to the error voltage to the first semiconductor means to vary the current through the first semiconductor means in a direction for maintaining the output voltage at the regulated value.
In accordance with a fifth aspect of the invention, there is provided, in combination for providing an output voltage having a regulated value, first means for providing an energizing voltage, control means responsive to the energizing voltage for producing a flow of current through the control means and an output voltage dependent upon such current flow, second means for obtaining a first particular fraction of the output voltage from the control means, third means for providing a second particular fraction of the energizing voltage, comparator means responsive to any difference between the first particular fraction of the output voltage from the control means and the second particular fraction of the energizing voltage for producing a voltage representative of such difference, fourth means responsive to the representative voltage from the comparator means for producing a current dependent upon the magnitude of such representative voltage, and a current mirror responsive to the current through 2d B
. 2078303 the fourth means for producing an error voltage for introduction to the control means for regulating the current through the control means to obtain the regulated value for the output voltage.
2e 1 In the drawings: 2 p 7 8 3 0 3 z 3 Figure 1 is a circuit diagram, almost entirely in 4 block form, of one embodiment of the invention;
Figure 2 is a somewhat detailed circuit diagram of 6 the embodiment of the invention shown in Figure if and 7 Figure 3 is a somewhat detailed circuit diagram of 8 another embodiment of the invention.
In the block diagram shown in Figure 1, a voltage 11 V~~ is provided at 10. The voltage V« may be +5 volts and may 12 be introduced to the source of a pass or control transistor 12 13 which may be a CMOS transistor of the p- type. The voltage on 14 the drain of the transistor 12 may be designated as a supply 1~ or output voltage and is introduced to a line 14 and to an 16 amplifier-inverter 16 to energize the amplifier-inverter. The p output of the amplifier-inverter 16 may be introduced to the 1~ input of the amplifier-inverter and to an input terminal of a 19 comparator/amplifier 18, a second input terminal of which ZO receives a reference voltage such as +1.5 volts. The output 21 of the comparator/amplifier 18 passes to the gate of the zZ control transistor 12.
24 The energizing voltage 10 causes current to pass 25 through the control transistor 12 so that a voltage approximating +3 volts is introduced to the line 14. The ?7 amplifier/inverter 16 is constructed to divide the voltage by 2g two (2) so that a voltage of +1.5 volts is introduced to the 2g comparator/amplifier 18 for comparison with the reference 30 voltage of +1.5 volts. Any difference or error voltage from 31 the comparator/amplifier 18 is introduced to the gate of the control transistor 12 to regulate the current through the ~'207g303 1 transistor 10 as to provide for the production of a regulated 2 output voltage of +3 volts at the drain of the transistor.
4 Figure 2 illustrates in some detail the embodiment of the invention shown in Figure 1 and described above. The 6 embodiment of the invention shown in Figure 2 includes the 7 line 10 for providing the energizing voltage V~~, the control g transistor 12 and the supply or output line 14 for providing g the voltage Vpp. The drain of the transistor 12 is connected to the source of a transistor 22 which may be a CMOS
11 transistor of the p- type. The drain and the gate of the 12 transistor 22 have a common connection with the drain of a 13 transistor 24 which may be a CMOS transistor of the n- type.
1~ The source of the transistor 24 may be at a suitable reference potential such as ground. The transistors 22 and 24 g preferably have substantially equal transconductances.
L 'l A connection is made from the drains of the lg transistors 22 and 24 to the gate of a transistor 30 which may 2p also be a CMOS transistor of the n- type. The sources of the ~ 21 transistor 30 and of a transistor 32 may be at the reference 22 potential such as ground. The transistor 32 may be a CMOS
23 transistor of the n- type and may form a comparator with the 24 transistor 30. The transistors 30 and 32 preferably have substantially equal characteristics. The gate of the 2g transistor 32 receives a reference potential such as +1.5 27 volts from the common terminal between a pair of resistances 2g 34 and 36. The resistances 34 and 36 are in series between 2g the line 10 and the reference potential such as ground and define a resistance ladder network.
3~
1 The drains of the transistors 30 and 32 are 2 respectively common with the drains of a-pair of transistors 3 38 and 40 both of which are CMOS transistors of the p- type.
4 The transistors 38 and 40 are included in a comparator/
amplifier. The transistors 38 and 40 preferably have 6 substantially equal characteristics. The sources of the 7 transistors 38 and 40 receive the voltage V« on the line l0.
8 The drain and the gate of the transistor 38 and the gate of 9 the transistor 40 are common. The voltage on the drain of the transistor 40 is introduced to the gate of the transistor 12.
1~ As previously described, the voltage on the line 14 13 is approximately +3 volts. This voltage is divided by the 14 transistors 22 and 24 so that the voltage on the drain of the transistors 22 and 24 is approximately +1.5 volts. This 16 voltage is introduced to the transistor~30 for comparison with I'7 the reference voltage on the gate of the transistor 32.
1 f3 19 Assume that the voltage introduced to the gate of the transistor 30 from the drains of the transistors 22 and 24 21 is less than the reference voltage of +1.5 volts on the gate 22 of the transistor 32. This causes the current through the 23 transistor 30 to be less than the current through the 24 transistor 32. Because of this, the voltage on the drains of the transistors 30 and 38 is greater than the voltage on the 26 drains of the transistor 32 and 40.
28 The transistor 30 effectively serves as a resistor.
29 Therefore, because of the increased voltage on the drain of the transistor 38, the current through the transistor 38 31 decreases, thereby producing an increased voltage on the drain 32 of the transistor 38 and the gate of the transistor 40. The s f s I.
1 current through the transistor 40 decreases as a result of the 2 increased voltage on the gate of the transistor. This causes 3 the voltage on the drain of the transistor 40 to decrease.
4 When introduced to the gate of the transistor 12, this voltage causes the current through the transistor 12 to increase, 6 thereby increasing the voltage on the drain of the transistor.
7 In this way, the voltage on the line 14 is regulated at +3 8 volts and the voltage on the drains of the transistors 22 and 9 24 is regulated at +1.5 volts.
11 Figure 3 illustrates another embodiment of the 12 invention. In this embodiment, the line 10, the transistor 13 12, the line 14 and the transistors 22 and 24 are provided in 14 the same manner as in the embodiment shown in Figure 2 and described above. However, the gates of the transistors 22 and 7_~, 24 are connected to the terminal common to the resistances 34 and 36. The resistance ladder 34 and 36 is also provided in 1.f3 the embodiment shown in Figure 3 in the same manner as in the 19 embodiment shown in Figure 2.
21 In the embodiment shown in Figure 3, the voltage on 22 the drains of the transistors 22 and 24 and the voltage on the 23 terminal common to the resistances 34 and 36 are respectively 24 introduced to the gates of transistors 50 and 52 in the same manner as in the embodiment shown in Figure 2. The 2g transistors 50 and 52 may be CMOS transistors of the n- type 27 and preferably have substantially equal characteristics. The 2g sources of the transistors are at the reference potential such 2g as ground. A capacitor 54 is connected between the gate and source of the transistor 52 to pass noise on the gate of the 31 transistor 52 to ground.
2078303 s A capacitor 56 is connected between the drain of the 2 transistor 50 and ground to pass any noise on the drain of the 3 transistor to ground. Connections are respectively made from 4 the drains of the transistors 50 and 52 to the drains of transistors 58 and 60, each of which may be a CMOS transistor 6 of the p- type. The transistors 58 and 60 preferably have 7 substantially equal characteristics. The sources of the 8 transistors 58 and 60 receive the energizing voltage v« on 9 the line 10. The gates of the transistors 58 and 60 are common with the drain of the transistor 60. A capacitor 62 is 11 connected between the drain of the transistor 60 and the line 12 10 to eliminate any noise on the drain of the transistor 60.
14 The source of a transistor 64 receives the energizing voltage on the line 10. The transistor 64 may be a 7.f CMOS transistor of the p- type. Connections are made from the 7.7 drain of the transistor 64 to the gate of the control ld transistor 12 and to the drain of a transistor 66, which may lg be a CMOS transistor of the n- type. The gate of the transistor 66 is common with the drain of the transistor 50.
21 The source of the transistor 66 receives the voltage on the 22 drains of the transistors 22 and 24.
Assume that the voltage on the drains of the 26 transistors 22 and 24 is less than 1.5 volts. This causes the 27 current through the transistor 52 to be greater than the 28 current through the transistor 50 and the voltage on the drain 2g of the transistor 52 to be lower than the voltage on the drain of the transistor 50. The reduced voltage on the drain of the 31 transistor 52 causes the current through the transistor 6o to 32 increase since the transistor effectively acts as a _.
1 resistance. This assures that the voltage on the drain of the 2 transistor 60 will be reduced.
4 The reduced voltage on the drain of the transistor 60 is introduced to the gate of the transistor 58 to produce 6 an increased current through the transistor 58 and a decreased 7 voltage drop across the transistor. The resultant increase in 8 the voltage on the drain of the transistor 58 produces an 9 increase in the current through the transistor 66 and accordingly a decrease in the voltage across the transistor.
11 This causes the voltage introduced to the gate of the lZ transistor 12 to decrease and the current through the 13 transistor to increase, thereby producing an increase in the voltage on the line 14.
l6 The increase in the voltage on the line 14 is ~.7 amplified by the transistors 22 and 24 because of the separate lEi connections to the gate and drain of each transistor. In this lg way, the voltage on the line 14 is regulated to provide a voltage of +3 volts. This regulation is even more sensitive 21 than that provided by the embodiment shown in Figure 2 because 22 of the operation of the transistors 22 and 24 in Figure 3 as 23 amplifiers, because of the inclusion of the transistors 64 and z4 66 in a folded-cascode gain stage and because of the inclusion of the capacitors 52, 56 and 62.
27 The circuitry described above has certain important ~g advantages. It provides a sensitive regulation of the voltage ~g Vpp to maintain the voltage at +3 volts. It also provides a sensitive regulation of a voltage of +1.5 volts to provide a 31 stable transition point for measuring signal amplitudes to determine the symmetry of rising and falling edges in such 1 signals. 2 ~ 7 8 3 ~ 3 3 Although this invention has been disclosed and 4 illustrated with reference to particular embodiments, the principles involved are susceptible for use in numerous other 6 embodiments which will be apparent to persons skilled in the 7 art. The invention is, therefore, to be limited only as 8 indicated by the scope of the appended claims.
7. 7
Claims (20)
1. In combination for providing an output voltage having a regulated value, means for providing an energizing voltage, control means responsive to the energizing voltage for producing a flow of current through the control means to obtain an output voltage, a pair of current means connected in a circuit with the control means for producing a first voltage constituting a particular fraction of the output voltage, means for providing a reference voltage, means including a current mirror responsive to the relative values of the reference voltage and the first voltage for introducing an error voltage to the control means to vary the current through the control means in a direction for producing the regulated value of the output voltage.
2. In a combination as set forth in claim 1, the pair of current means constituting a pair of transistors having transconductances in a particular relationship dependent upon the relative values of the output voltage and the first voltage, the pair of current means being connected to provide an amplification of any changes in the output voltage from the regulated value.
3. In a combination as set forth in claim 2, the pair of current means constituting a p- transistor and an n- transistor in series with the control means and the energizing voltage means and having substantially equal transductances.
4. In a combination as set forth in claim 2, the error voltage means including a comparator for comparing the reference voltage and the first voltage for producing an output representative of any difference between the reference voltage and the first voltage and further including the current mirror responsive to such difference for producing the error voltage for introduction to the control means.
5. In combination for providing an output voltage having a regulated value, a transistor having a source, a gate and a drain, first means for introducing an energizing voltage to the source of the transistor to obtain a flow of current through the transistor and a voltage on the drain of the transistor in accordance with such current flow, second means for producing a particular reduction in the voltage on the drain of the transistor, means for providing a reference voltage, third means including a current mirror responsive to the reduced voltage and to the reference voltage for producing an error voltage in accordance with the relative values of the reduced voltage and the reference voltage, and fourth means responsive to the error voltage for introducing the error voltage to the gate of the transistor to regulate the current through the transistor for the production of the regulated voltage on the drain of the transistor.
6. In a combination as set forth in claim 5, wherein the fourth means include a comparative amplifier responsive to the error voltage from the third means for amplifying the error voltage and for introducing the amplified error voltage to the gate of the transistor to regulate the current through the transistor for the production of the regulated voltage on the drain of the transistor.
7. In a combination as set forth in claims 5 or 6, wherein the second means include a pair of transistors having particular transconductances relative to each other to obtain the particular reduction in the voltage on the drain of the transistor, the pair of transistors being connected to provide an amplification of any changes in the output voltage from the regulated value.
8. In combination for providing an output voltage having a regulated value, a transistor having a source, a gate and a drain, first means for introducing an energizing voltage to the source of the transistor to obtain a flow of current through the transistor and a voltage on the drain of the transistor in accordance with such current flow, second means for producing a particular reduction in the voltage on the drain of the transistor, means for providing a reference voltage, third means responsive to the reduced voltage and to the reference voltage for producing an error voltage in accordance with the relative values of the reduced voltage and the reference voltage, and fourth means responsive to the error voltage for introducing the error voltage to the gate of the transistor to regulate the current through the transistor for the production of the regulated voltage on the drain of the transistor, the transistor constituting a first transistor, the third means including a second transistor responsive to the reduced voltage for producing a voltage dependent upon the reduced voltage and including a third transistor responsive to the voltage from the second transistor and to the reference voltage for producing the error voltage for introduction to the gate of the first transistor to regulate the current through the first transistor for the production of the regulated voltage on the drain of the first transistor.
9. In combination for providing an output voltage having a regulated value, means for providing an energizing voltage, first semiconductor means responsive to the energizing voltage for passing a variable current and for producing an output voltage dependent upon the variations in the current, second semiconductor means responsive to the output voltage for producing a first particular fraction of the ouput voltage, third semiconductor means responsive to the energizing voltage for producing a second particular fracton of the energizing voltage, fourth semiconductor means responsive to the first particular fraction of the output voltage and the second particular fraction of the energizing voltage for producing an error voltage, and fifth means including a current mirror responsive to the error voltage for introducing a voltage related to the error voltage to the first semiconductor means to vary the current through the first semiconductor means in a direction for maintaining the output voltage at the regulated value.
10. In a combination as set forth in claim 9, the first semiconductor means including a CMOS transistor of the p- type and the second semiconductor means including a pair of CMOS transistors connected in series with the CMOS transistor of the p- type and having relative transconductances to produce the first particular fraction of the output voltage.
11. In a combination as set forth in claim 10, the pair of CMOS transistors constituting an n-transistor and a p- transistor in series.
12. In combination for providing an output voltage having a regulated value, first means for providing an energizing voltage, control means responsive to the energizing voltage for producing a flow of current through the control means and an output voltage dependent upon such current flow, second means for obtaining a first particular fraction of the output voltage from the control means, third means for providing a second particular fraction of the energizing voltage, comparator means responsive to any difference between the first particular fraction of the output voltage from the control means and the second particular fraction of the energizing voltage for producing a voltage representative of such difference, fourth means responsive to the voltage from the comparator means for producing a current dependent upon the magnitude of such voltage, and a current mirror responsive to the current through the fourth means for producing an error voltage for introduction to the control means for regulating the current through the control means to obtain the regulated value for the output voltage.
13. In a combination as set forth in claim 12, the second means including a pair of transistors having relative values of transconductance dependent upon the first particular fraction of the output voltage.
14. In a combination as set forth in claim 13, the transistors in the second means being connected to provide an amplification of any changes in the output voltage to enhance the sensitivity in the regulation of the output voltage.
15. In a combination as set forth in claim 11, amplifier means responsive to the error voltage for amplifying the error voltage for introduction to the control means to regulate the output voltage at the regulated value.
16. In a combination as set forth in claim 15, the amplifier means being included in a folded-cascode gain stage.
17. In a combination as set forth in claim 9, the fourth semiconductor means including a first transistor responsive to a particular one of the first particular fraction of the output voltage and the second particular fraction of the energizing voltage for producing a resultant voltage and the current mirror including a second transistor responsive to the resultant voltage and the other one of the first particular fraction of the output voltage and the second particular fraction of the energizing voltage for producing the error voltage for introduction to the first semiconductor means to vary the current through the first semiconductor means in a direction for maintaining the output voltage at the regulated value.
18. In a combination as set forth in claim 1, the error voltage means including means responsive to a particular one of the first voltage and the reference voltage for producing a resultant voltage dependent upon such particular one of such voltages and including means responsive to the resultant voltage and the other one of the first voltage and the reference voltage for producing the error voltage for introduction to the control means to vary the current through the control means in a direction for producing the regulated value of the output voltage.
19. In a combination as set forth in claim 2, the error voltage means including means responsive to a particular one of the first voltage and the reference voltage for producing a resultant voltage dependent upon such particular one of such voltages and including means responsive to the resultant voltage and the other one of the first voltage and the reference voltage for producing a current and including means responsive to the current for producing the error voltage for introduction to the control means to vary the current through the control means in a direction for producing the regulated value of the output voltage.
20. In a combination as set forth in claim 6, the transistor constituting a first transistor, the third means including a second transistor for producing a resultant voltage dependent upon a particular one of the reference voltage and the particular reduction in the voltage on the drain of the first transistor and including a third transistor responsive to the resultant voltage and the other one of the reference voltage and the particular reduction in the voltage on the drain of the first transistor for providing a current through the third transistor and for producing the error voltage in accordance with such current.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/772,218 US5227714A (en) | 1991-10-07 | 1991-10-07 | Voltage regulator |
| US772,218 | 1991-10-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2078303A1 CA2078303A1 (en) | 1993-04-08 |
| CA2078303C true CA2078303C (en) | 1999-12-07 |
Family
ID=25094331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002078303A Expired - Lifetime CA2078303C (en) | 1991-10-07 | 1992-09-15 | Voltage regulator |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5227714A (en) |
| EP (1) | EP0536693A3 (en) |
| JP (1) | JP2974269B2 (en) |
| CA (1) | CA2078303C (en) |
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| DE69216824T2 (en) * | 1992-08-26 | 1997-09-11 | Sgs Thomson Microelectronics | Current mirror with high impedance and precision |
| US5481179A (en) * | 1993-10-14 | 1996-01-02 | Micron Technology, Inc. | Voltage reference circuit with a common gate output stage |
| DE69528967D1 (en) * | 1995-05-31 | 2003-01-09 | St Microelectronics Srl | Transistor current generator stage for integrated analog circuits |
| US5845313A (en) | 1995-07-31 | 1998-12-01 | Lexar | Direct logical block addressing flash memory mass storage architecture |
| US6728851B1 (en) | 1995-07-31 | 2004-04-27 | Lexar Media, Inc. | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
| US6978342B1 (en) | 1995-07-31 | 2005-12-20 | Lexar Media, Inc. | Moving sectors within a block of information in a flash memory mass storage architecture |
| US8171203B2 (en) | 1995-07-31 | 2012-05-01 | Micron Technology, Inc. | Faster write operations to nonvolatile memory using FSInfo sector manipulation |
| JP2766227B2 (en) * | 1995-08-30 | 1998-06-18 | 日本電気アイシーマイコンシステム株式会社 | Semiconductor storage device |
| JP3713324B2 (en) * | 1996-02-26 | 2005-11-09 | 三菱電機株式会社 | Current mirror circuit and signal processing circuit |
| US5892388A (en) * | 1996-04-15 | 1999-04-06 | National Semiconductor Corporation | Low power bias circuit using FET as a resistor |
| DE69912756D1 (en) | 1999-06-30 | 2003-12-18 | St Microelectronics Srl | Voltage regulator for a capacitive load |
| US7102671B1 (en) | 2000-02-08 | 2006-09-05 | Lexar Media, Inc. | Enhanced compact flash memory card |
| US7167944B1 (en) | 2000-07-21 | 2007-01-23 | Lexar Media, Inc. | Block management for mass storage |
| US6271652B1 (en) * | 2000-09-29 | 2001-08-07 | International Business Machines Corporation | Voltage regulator with gain boosting |
| US6469548B1 (en) * | 2001-06-14 | 2002-10-22 | Cypress Semiconductor Corp. | Output buffer crossing point compensation |
| GB0123416D0 (en) | 2001-09-28 | 2001-11-21 | Memquest Ltd | Non-volatile memory control |
| GB0123419D0 (en) | 2001-09-28 | 2001-11-21 | Memquest Ltd | Data handling system |
| GB0123410D0 (en) | 2001-09-28 | 2001-11-21 | Memquest Ltd | Memory system for data storage and retrieval |
| GB0123417D0 (en) | 2001-09-28 | 2001-11-21 | Memquest Ltd | Improved data processing |
| GB0123421D0 (en) | 2001-09-28 | 2001-11-21 | Memquest Ltd | Power management system |
| GB0123415D0 (en) | 2001-09-28 | 2001-11-21 | Memquest Ltd | Method of writing data to non-volatile memory |
| US6950918B1 (en) | 2002-01-18 | 2005-09-27 | Lexar Media, Inc. | File management of one-time-programmable nonvolatile memory devices |
| US6957295B1 (en) | 2002-01-18 | 2005-10-18 | Lexar Media, Inc. | File management of one-time-programmable nonvolatile memory devices |
| US7231643B1 (en) | 2002-02-22 | 2007-06-12 | Lexar Media, Inc. | Image rescue system including direct communication between an application program and a device driver |
| US6973519B1 (en) | 2003-06-03 | 2005-12-06 | Lexar Media, Inc. | Card identification compatibility |
| FR2856856B1 (en) * | 2003-06-24 | 2005-08-26 | Atmel Corp | LOW VOLTAGE CIRCUIT FOR INTERFACING WITH HIGH VOLTAGE ANALOG SIGNALS |
| JP2007515024A (en) | 2003-12-17 | 2007-06-07 | レクサー メディア， インコーポレイテッド | Activation of electronic device sales locations to avoid theft |
| US7725628B1 (en) | 2004-04-20 | 2010-05-25 | Lexar Media, Inc. | Direct secondary device interface by a host |
| US7370166B1 (en) | 2004-04-30 | 2008-05-06 | Lexar Media, Inc. | Secure portable storage device |
| US7151363B1 (en) * | 2004-06-08 | 2006-12-19 | Rf Micro Devices, Inc. | High PSRR, fast settle time voltage regulator |
| US7464306B1 (en) | 2004-08-27 | 2008-12-09 | Lexar Media, Inc. | Status of overall health of nonvolatile memory |
| US7594063B1 (en) | 2004-08-27 | 2009-09-22 | Lexar Media, Inc. | Storage capacity status |
| US7362084B2 (en) * | 2005-03-14 | 2008-04-22 | Silicon Storage Technology, Inc. | Fast voltage regulators for charge pumps |
| DE102005040072B9 (en) * | 2005-08-24 | 2012-02-09 | Infineon Technologies Ag | Device for polarity-safe supply of an electronic component with an intermediate voltage from a supply voltage |
| KR100693821B1 (en) | 2005-10-31 | 2007-03-12 | 삼성전자주식회사 | Differential amplifier and active load for the same |
| JP4953246B2 (en) * | 2007-04-27 | 2012-06-13 | セイコーインスツル株式会社 | Voltage regulator |
| US8618786B1 (en) | 2009-08-31 | 2013-12-31 | Altera Corporation | Self-biased voltage regulation circuitry for memory |
| JP5864086B2 (en) * | 2010-07-28 | 2016-02-17 | ラピスセミコンダクタ株式会社 | Differential amplifier circuit |
| US9520872B2 (en) * | 2014-12-23 | 2016-12-13 | Qualcomm Incorporated | Linear equalizer with variable gain |
| US11689201B2 (en) | 2021-07-26 | 2023-06-27 | Qualcomm Incorporated | Universal serial bus (USB) host data switch with integrated equalizer |
| CN113311896B (en) * | 2021-07-29 | 2021-12-17 | 唯捷创芯(天津)电子技术股份有限公司 | Self-adaptive overshoot voltage suppression circuit, reference circuit, chip and communication terminal |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6077212A (en) * | 1983-10-04 | 1985-05-01 | Nec Corp | Constant voltage regulated power supply circuit |
| JPH0679262B2 (en) * | 1984-02-28 | 1994-10-05 | シャープ株式会社 | Reference voltage circuit |
| JPS60243716A (en) * | 1984-10-24 | 1985-12-03 | Hitachi Ltd | Voltage regulator |
| US4788455A (en) * | 1985-08-09 | 1988-11-29 | Mitsubishi Denki Kabushiki Kaisha | CMOS reference voltage generator employing separate reference circuits for each output transistor |
| JPH0724004B2 (en) * | 1985-09-30 | 1995-03-15 | セイコーエプソン株式会社 | Constant voltage circuit |
| JPH0830742B2 (en) * | 1987-01-26 | 1996-03-27 | セイコーエプソン株式会社 | Analog electronic clock |
| US4779037A (en) * | 1987-11-17 | 1988-10-18 | National Semiconductor Corporation | Dual input low dropout voltage regulator |
| JP2674669B2 (en) * | 1989-08-23 | 1997-11-12 | 株式会社東芝 | Semiconductor integrated circuit |
-
1991
- 1991-10-07 US US07/772,218 patent/US5227714A/en not_active Expired - Fee Related
-
1992
- 1992-09-15 CA CA002078303A patent/CA2078303C/en not_active Expired - Lifetime
- 1992-10-06 EP EP19920117032 patent/EP0536693A3/en not_active Ceased
- 1992-10-06 JP JP4267250A patent/JP2974269B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CA2078303A1 (en) | 1993-04-08 |
| JPH05303436A (en) | 1993-11-16 |
| US5227714A (en) | 1993-07-13 |
| EP0536693A2 (en) | 1993-04-14 |
| JP2974269B2 (en) | 1999-11-10 |
| EP0536693A3 (en) | 1993-10-06 |
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