CA2089437A1 - Adaptive cache miss prediction mechanism - Google Patents

Adaptive cache miss prediction mechanism

Info

Publication number
CA2089437A1
CA2089437A1 CA2089437A CA2089437A CA2089437A1 CA 2089437 A1 CA2089437 A1 CA 2089437A1 CA 2089437 A CA2089437 A CA 2089437A CA 2089437 A CA2089437 A CA 2089437A CA 2089437 A1 CA2089437 A1 CA 2089437A1
Authority
CA
Canada
Prior art keywords
cache
cache miss
miss
ratio
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2089437A
Other languages
French (fr)
Other versions
CA2089437C (en
Inventor
Charles P. Ryan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Inc filed Critical Bull HN Information Systems Inc
Publication of CA2089437A1 publication Critical patent/CA2089437A1/en
Application granted granted Critical
Publication of CA2089437C publication Critical patent/CA2089437C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address. The cache miss prediction mechanism is adaptively selectively enabled by an adaptive circuit that develops a short term operand cache hit ratio history and responds to ratio improving and ratio deteriorating trends by accordingly enabling and disabling the cache miss prediction mechanism.
CA002089437A 1992-03-13 1993-02-12 Adaptive cache miss prediction mechanism Expired - Fee Related CA2089437C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/850,713 US5367656A (en) 1992-03-13 1992-03-13 Controlling cache predictive prefetching based on cache hit ratio trend
US07/850,713 1992-03-13

Publications (2)

Publication Number Publication Date
CA2089437A1 true CA2089437A1 (en) 1993-09-14
CA2089437C CA2089437C (en) 1996-08-27

Family

ID=25308915

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002089437A Expired - Fee Related CA2089437C (en) 1992-03-13 1993-02-12 Adaptive cache miss prediction mechanism

Country Status (4)

Country Link
US (1) US5367656A (en)
EP (1) EP0560100B1 (en)
CA (1) CA2089437C (en)
TW (1) TW270184B (en)

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US5093777A (en) * 1989-06-12 1992-03-03 Bull Hn Information Systems Inc. Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack
SE469402B (en) * 1991-05-02 1993-06-28 Swedish Inst Of Computer Scien PROCEDURE TO Fetch DATA FOR A CACHE MEMORY
US5715421A (en) * 1992-10-16 1998-02-03 Seiko Epson Corporation Apparatus and method of addressing paged mode memory including adjacent page precharging
JPH06314241A (en) * 1993-03-04 1994-11-08 Sharp Corp High-speed semiconductor memory and high-speed associative storage device
US5426764A (en) * 1993-08-24 1995-06-20 Ryan; Charles P. Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor
AU2364095A (en) * 1994-05-12 1995-12-05 Ast Research, Inc. Cpu activity monitoring through cache watching
US5701426A (en) * 1995-03-31 1997-12-23 Bull Information Systems Inc. Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio
EP0752645B1 (en) * 1995-07-07 2017-11-22 Oracle America, Inc. Tunable software control of Harvard architecture cache memories using prefetch instructions
US5790823A (en) * 1995-07-13 1998-08-04 International Business Machines Corporation Operand prefetch table
US5694568A (en) * 1995-07-27 1997-12-02 Board Of Trustees Of The University Of Illinois Prefetch system applicable to complex memory access schemes
US5765213A (en) * 1995-12-08 1998-06-09 Emc Corporation Method providing for the flexible prefetching of data from a data storage system
US5919256A (en) * 1996-03-26 1999-07-06 Advanced Micro Devices, Inc. Operand cache addressed by the instruction address for reducing latency of read instruction
US5761468A (en) * 1996-05-15 1998-06-02 Sun Microsystems Inc Hardware mechanism for optimizing instruction and data prefetching by forming augmented prefetch instructions
US5893930A (en) * 1996-07-12 1999-04-13 International Business Machines Corporation Predictive translation of a data address utilizing sets of associative entries stored consecutively in a translation lookaside buffer
US5822790A (en) * 1997-02-07 1998-10-13 Sun Microsystems, Inc. Voting data prefetch engine
US6138212A (en) * 1997-06-25 2000-10-24 Sun Microsystems, Inc. Apparatus and method for generating a stride used to derive a prefetch address
US6098154A (en) * 1997-06-25 2000-08-01 Sun Microsystems, Inc. Apparatus and method for generating a stride used to derive a prefetch address
US6047363A (en) * 1997-10-14 2000-04-04 Advanced Micro Devices, Inc. Prefetching data using profile of cache misses from earlier code executions
AU2092399A (en) * 1997-12-30 1999-07-19 Genesis One Technologies, Inc. Disk cache enhancer with dynamically sized read request based upon current cachehit rate
US6055650A (en) * 1998-04-06 2000-04-25 Advanced Micro Devices, Inc. Processor configured to detect program phase changes and to adapt thereto
US6341281B1 (en) 1998-04-14 2002-01-22 Sybase, Inc. Database system with methods for optimizing performance of correlated subqueries by reusing invariant results of operator tree
US6401193B1 (en) 1998-10-26 2002-06-04 Infineon Technologies North America Corp. Dynamic data prefetching based on program counter and addressing mode
US6311260B1 (en) 1999-02-25 2001-10-30 Nec Research Institute, Inc. Method for perfetching structured data
US6470427B1 (en) 1999-11-09 2002-10-22 International Business Machines Corporation Programmable agent and method for managing prefetch queues
US6862657B1 (en) * 1999-12-21 2005-03-01 Intel Corporation Reading data from a storage medium
US6934807B1 (en) 2000-03-31 2005-08-23 Intel Corporation Determining an amount of data read from a storage medium
US6973542B1 (en) * 2000-07-18 2005-12-06 International Business Machines Corporation Detecting when to prefetch inodes and then prefetching inodes in parallel
US7257810B2 (en) * 2001-11-02 2007-08-14 Sun Microsystems, Inc. Method and apparatus for inserting prefetch instructions in an optimizing compiler
US7234136B2 (en) * 2001-11-02 2007-06-19 Sun Microsystems, Inc. Method and apparatus for selecting references for prefetching in an optimizing compiler
US7035979B2 (en) * 2002-05-22 2006-04-25 International Business Machines Corporation Method and apparatus for optimizing cache hit ratio in non L1 caches
JP4066833B2 (en) * 2003-02-18 2008-03-26 日本電気株式会社 Disk array control device and method, and disk array control program
US7328309B2 (en) * 2004-10-14 2008-02-05 International Business Machines Corporation On-demand cache memory for storage subsystems
JP4827469B2 (en) * 2005-09-08 2011-11-30 パナソニック株式会社 Cache memory analysis method, processor, and simulated information processing apparatus
US7917702B2 (en) * 2007-07-10 2011-03-29 Qualcomm Incorporated Data prefetch throttle
US7925865B2 (en) * 2008-06-02 2011-04-12 Oracle America, Inc. Accuracy of correlation prefetching via block correlation and adaptive prefetch degree selection
WO2013188460A2 (en) 2012-06-15 2013-12-19 Soft Machines, Inc. A virtual load store queue having a dynamic dispatch window with a distributed structure
WO2013188696A2 (en) 2012-06-15 2013-12-19 Soft Machines, Inc. An instruction definition to implement load store reordering and optimization
EP2862060A4 (en) * 2012-06-15 2016-11-30 Soft Machines Inc A method and system for filtering the stores to prevent all stores from having to snoop check against all words of a cache
TWI599879B (en) 2012-06-15 2017-09-21 英特爾股份有限公司 Disambiguation-free out of order load store queue methods in a processor, and microprocessors
WO2013188306A1 (en) 2012-06-15 2013-12-19 Soft Machines, Inc. Reordered speculative instruction sequences with a disambiguation-free out of order load store queue
WO2013188701A1 (en) 2012-06-15 2013-12-19 Soft Machines, Inc. A method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization
KR101996351B1 (en) 2012-06-15 2019-07-05 인텔 코포레이션 A virtual load store queue having a dynamic dispatch window with a unified structure
US20140189244A1 (en) * 2013-01-02 2014-07-03 Brian C. Grayson Suppression of redundant cache status updates
KR102429903B1 (en) * 2015-12-03 2022-08-05 삼성전자주식회사 The control method of a page fault in the non-volatile main memory system
US10592414B2 (en) * 2017-07-14 2020-03-17 International Business Machines Corporation Filtering of redundantly scheduled write passes

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093777A (en) * 1989-06-12 1992-03-03 Bull Hn Information Systems Inc. Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack
US5285527A (en) * 1991-12-11 1994-02-08 Northern Telecom Limited Predictive historical cache memory

Also Published As

Publication number Publication date
EP0560100B1 (en) 1999-06-09
CA2089437C (en) 1996-08-27
EP0560100A1 (en) 1993-09-15
TW270184B (en) 1996-02-11
US5367656A (en) 1994-11-22

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