CA2093849A1 - Controller for input-queued packet switch - Google Patents

Controller for input-queued packet switch

Info

Publication number
CA2093849A1
CA2093849A1 CA2093849A CA2093849A CA2093849A1 CA 2093849 A1 CA2093849 A1 CA 2093849A1 CA 2093849 A CA2093849 A CA 2093849A CA 2093849 A CA2093849 A CA 2093849A CA 2093849 A1 CA2093849 A1 CA 2093849A1
Authority
CA
Canada
Prior art keywords
output
input
transmission time
unable
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2093849A
Other languages
French (fr)
Other versions
CA2093849C (en
Inventor
Kai Yin Eng
Mark John Karol
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2093849A1 publication Critical patent/CA2093849A1/en
Application granted granted Critical
Publication of CA2093849C publication Critical patent/CA2093849C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection or protection within a single switching element
    • H04L49/505—Corrective measures
    • H04L49/508—Head of Line Blocking Avoidance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3018—Input queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B2201/00—Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
    • B06B2201/50—Application to a particular transducer type
    • B06B2201/55—Piezoelectric transducer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling

Abstract

Significant throughput improvement is achieved for an input queued packet switch using output port schedulers by permitting the output schedulers to recycle or reassign cell transmission times from input ports which are unable to use them.
When an output scheduler assigns a cell transmission time to an input port and that input port is unable to use the assigned transmission time due to a scheduling conflict, for example, the input port makes a new request for the same output port during the next subsequent request period and then returns the unable transmission time assignment back to the output scheduler. The output scheduler stores the returned transmission time in a separate queue for assignment to later requests for the particular output port. Throughput performance is improved from 58% (without time slot recycling) to 92% (with time slot recycling) for random packet cell trafficmodels,
CA002093849A 1992-05-05 1993-04-13 Controller for input-queued packet switch Expired - Fee Related CA2093849C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/878,801 US5255265A (en) 1992-05-05 1992-05-05 Controller for input-queued packet switch
US878,801 1992-05-05

Publications (2)

Publication Number Publication Date
CA2093849A1 true CA2093849A1 (en) 1993-11-06
CA2093849C CA2093849C (en) 1999-06-22

Family

ID=25372874

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002093849A Expired - Fee Related CA2093849C (en) 1992-05-05 1993-04-13 Controller for input-queued packet switch

Country Status (6)

Country Link
US (1) US5255265A (en)
EP (1) EP0569172B1 (en)
JP (1) JP2981082B2 (en)
CA (1) CA2093849C (en)
DE (1) DE69330395T2 (en)
ES (1) ES2160586T3 (en)

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SE515148C2 (en) * 1993-06-23 2001-06-18 Ericsson Telefon Ab L M Control of cell selector
US5542115A (en) 1994-06-24 1996-07-30 Pioneer Tech Development Limited Paging method and apparatus
US5949781A (en) * 1994-08-31 1999-09-07 Brooktree Corporation Controller for ATM segmentation and reassembly
US5517495A (en) * 1994-12-06 1996-05-14 At&T Corp. Fair prioritized scheduling in an input-buffered switch
US5631908A (en) * 1995-03-28 1997-05-20 Digital Equipment Corporation Method and apparatus for generating and implementing smooth schedules for forwarding data flows across cell-based switches
KR100262682B1 (en) * 1995-04-15 2000-08-01 최병석 Multicast atm switch and its multicast contention resolution
US5991296A (en) * 1996-02-22 1999-11-23 Fujitsu, Ltd. Crossbar switch and method with reduced voltage swing and no internal blocking data path
US5838684A (en) * 1996-02-22 1998-11-17 Fujitsu, Ltd. Low latency, high clock frequency plesioasynchronous packet-based crossbar switching chip system and method
US5923644A (en) * 1996-10-03 1999-07-13 The Board Of Trustees Of The Leland Stanford Junior University Apparatus and method for processing multicast cells in an input-queued multicast switch
JP2871650B2 (en) 1997-04-17 1999-03-17 日本電気株式会社 Data transmission system
US5978858A (en) * 1997-09-30 1999-11-02 Compaq Computer Corporation Packet protocol and distributed burst engine
JP3125739B2 (en) * 1998-02-17 2001-01-22 日本電気株式会社 Bus switch
US6044061A (en) * 1998-03-10 2000-03-28 Cabletron Systems, Inc. Method and apparatus for fair and efficient scheduling of variable-size data packets in an input-buffered multipoint switch
US6160812A (en) * 1998-05-04 2000-12-12 Cabletron Systems, Inc. Method and apparatus for supplying requests to a scheduler in an input buffered multiport switch
US6185221B1 (en) 1998-11-09 2001-02-06 Cabletron Systems, Inc. Method and apparatus for fair and efficient scheduling of variable-size data packets in an input-buffered multipoint switch
US6539026B1 (en) 1999-03-15 2003-03-25 Cisco Technology, Inc. Apparatus and method for delay management in a data communications network
US7145869B1 (en) * 1999-03-17 2006-12-05 Broadcom Corporation Method for avoiding out-of-ordering of frames in a network switch
US6895015B1 (en) * 1999-05-05 2005-05-17 Advanced Micro Devices, Inc. Dynamic time slot allocation in internal rules checker scheduler
US7058063B1 (en) * 1999-06-18 2006-06-06 Nec Corporation Pipelined packet scheduler for high speed optical switches
US6731638B1 (en) * 1999-10-14 2004-05-04 Synchrodyne Networks, Inc. Switch scheduling with common time reference
DE10105935B4 (en) * 2000-02-09 2009-06-18 Nec Corp. Multimode scheduler, device with a multimode scheduler and multimode handler
US7023841B2 (en) * 2000-12-15 2006-04-04 Agere Systems Inc. Three-stage switch fabric with buffered crossbar devices
US7161906B2 (en) * 2000-12-15 2007-01-09 Agere Systems Inc. Three-stage switch fabric with input device features
US7158528B2 (en) * 2000-12-15 2007-01-02 Agere Systems Inc. Scheduler for a packet routing and switching system
JP4072315B2 (en) 2000-12-26 2008-04-09 富士通株式会社 Packet switch
US7433683B2 (en) * 2000-12-28 2008-10-07 Northstar Acquisitions, Llc System for fast macrodiversity switching in mobile wireless networks
US7065046B2 (en) * 2001-04-06 2006-06-20 Lucent Technologies Inc. Scalable weight-based terabit switch scheduling method
US20020191588A1 (en) * 2001-06-13 2002-12-19 Drexel University Integrated circuit and packet switching system
US20030035371A1 (en) * 2001-07-31 2003-02-20 Coke Reed Means and apparatus for a scaleable congestion free switching system with intelligent control
FR2830162B1 (en) * 2001-09-27 2003-12-05 Streamcore SHARED MANAGEMENT DEVICE
JP3747839B2 (en) * 2001-11-21 2006-02-22 日本電気株式会社 Code conversion system, conversion method and conversion program
KR100483546B1 (en) * 2002-08-22 2005-04-15 엘지전자 주식회사 Apparatus and method of multicast switching by ATM cell copying
GB2397966B (en) * 2003-02-01 2005-04-20 3Com Corp High-speed switch architecture
GB2401279B (en) * 2003-04-29 2005-06-01 3Com Corp Switch module architecture
WO2006018751A1 (en) * 2004-08-12 2006-02-23 Koninklijke Philips Electronics N.V. A method for allocating data to at least one packet in an integrated circuit
US8054487B2 (en) 2004-12-16 2011-11-08 International Business Machines Corporation Mechanism to create a reservation against a future scheduling object instantiation
US7346050B2 (en) * 2005-01-31 2008-03-18 International Business Machines Corporation Method, system, and storage medium for delay optimization for scheduling in bufferless crossbar switches

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1196791B (en) * 1986-11-18 1988-11-25 Cselt Centro Studi Lab Telecom SWITCHING ELEMENT FOR MULTI-STAGE INTERCONNECTION NETWORKS SELF-SLIDING TO PACKAGE SWITCHING
DE3738177A1 (en) * 1987-11-10 1989-05-18 Siemens Ag INTERMEDIATE NODE FOR THE INTERMEDIATE OF DATA SIGNALS TRANSMITTED IN DATA PACKAGES
JPH0287745A (en) * 1988-09-26 1990-03-28 Nippon Telegr & Teleph Corp <Ntt> Cell contention control circuit
US4979165A (en) * 1989-06-23 1990-12-18 At&T Bell Laboratories Multiple queue bandwidth reservation packet system
JP2803262B2 (en) * 1989-12-15 1998-09-24 日本電気株式会社 Packet switch
US5157654A (en) * 1990-12-18 1992-10-20 Bell Communications Research, Inc. Technique for resolving output port contention in a high speed packet switch

Also Published As

Publication number Publication date
EP0569172A2 (en) 1993-11-10
DE69330395T2 (en) 2002-05-16
EP0569172A3 (en) 1995-01-25
DE69330395D1 (en) 2001-08-09
JP2981082B2 (en) 1999-11-22
US5255265A (en) 1993-10-19
JPH0637805A (en) 1994-02-10
ES2160586T3 (en) 2001-11-16
EP0569172B1 (en) 2001-07-04
CA2093849C (en) 1999-06-22

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