CA2093849C - Controller for input-queued packet switch - Google Patents
Controller for input-queued packet switchInfo
- Publication number
- CA2093849C CA2093849C CA002093849A CA2093849A CA2093849C CA 2093849 C CA2093849 C CA 2093849C CA 002093849 A CA002093849 A CA 002093849A CA 2093849 A CA2093849 A CA 2093849A CA 2093849 C CA2093849 C CA 2093849C
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- transmission time
- input
- output
- cell
- switch
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/50—Overload detection or protection within a single switching element
- H04L49/505—Corrective measures
- H04L49/508—Head of Line Blocking Avoidance
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
- H04L49/254—Centralised controller, i.e. arbitration or scheduling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3018—Input queuing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B2201/00—Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
- B06B2201/50—Application to a particular transducer type
- B06B2201/55—Piezoelectric transducer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5679—Arbitration or scheduling
Abstract
Significant throughput improvement is achieved for an input queued packet switch using output port schedulers by permitting the output schedulers to recycle or reassign cell transmission times from input ports which are unable to use them.
When an output scheduler assigns a cell transmission time to an input port and that input port is unable to use the assigned transmission time due to a scheduling conflict, for example, the input port makes a new request for the same output port during the next subsequent request period and then returns the unable transmission time assignment back to the output scheduler. The output scheduler stores the returned transmission time in a separate queue for assignment to later requests for the particular output port. Throughput performance is improved from 58% (without time slot recycling) to 92% (with time slot recycling) for random packet cell trafficmodels,
When an output scheduler assigns a cell transmission time to an input port and that input port is unable to use the assigned transmission time due to a scheduling conflict, for example, the input port makes a new request for the same output port during the next subsequent request period and then returns the unable transmission time assignment back to the output scheduler. The output scheduler stores the returned transmission time in a separate queue for assignment to later requests for the particular output port. Throughput performance is improved from 58% (without time slot recycling) to 92% (with time slot recycling) for random packet cell trafficmodels,
Description
20938g9 '' -IMPROVED CONTROLLER FOR INPUT-QUEUED PACKET SVVITCH
T~hl~'r~' Fiel~
This invention relates to packet switching and, more particularly, to controllers and schedulers for improving the throughput of input-queued packet switches.
R~ ln~l of th~ Tnvelltion Contention among ~imlllt~nPously arriving packet cells for the same output port of a packet switch is resolved in favor of only one packet cell at a time. As a result, some form of temporary storage is required for the rem~ining packet cells.
Telllpor~u~ storage provided on the input side of the switch is an input queue whereas storage of the packet cells on the output side of the switch is called an output queue.
With respect to each input/output line of the switch, the input queue p~its loading up to a maximum of 58% whereas the output queue ~lmi~ loading up to 100%
when the first in, first out (E~IFO) storage is utili7ed The reason for such poor perfonn~nce in input-queued packet switches is related to a problem known a head-of-line blocking. To ovel~o~ this problem, it has been proposed that the storage devices in the input queue be non-FIFO or random access. In addition, sche~-lling of packet cells from dirrGl~,. t input queues for the same output port is performed in two phases to result in non-conflicting transmission of the packet cells. See, for example, an article by Obara et al., Int'l. J. of Di~ital and Ansl~ Cabled Systen~. Vol. 2, No. 4, pp. 261-7 (1989). This type of scheduling is called output scheduling. It permits improvement of the switch throughput from 58% to 65% for random packet cell traffic models.
S.. ~ of th~ Tnvention Signific~nt throughput improvement is achieved for an input queued packet 25 switch using output port schedulers by permitting the output schecl.llers to recycle or reassign cell transmission times from input ports which are unable to use them.
~ ~ ~ 3 ~-4 9 When an output scheduler assigns a cell tr~nsmission time to an input port and that input port is unable to use the assigned tr~nsmission time due to a scheduling conflict, for example, the input port makes a new request for the same output port during the next S subsequent request period and then returns the unusable tr~nsmission time assignment back to the output scheduler. The output scheduler stores the returned tr~nsmission time in a separate queue for ~ssignment to later requests for the particular output port. Throughput performance, as a result of this invention, is improved from 58% to 92% for random packet cell traffic models.
Further throughput improvements are realizable by employing input port grouping. This requires that a plurality of input queues are grouped or linked together in such a way that packet cell transmissions for a particular tr~n.smis.sion time are selected from any of the input queues in the same group. Input grouping results in a throughput improvement to 95% for random packet cell traffic models.
In accordance with one aspect of the present invention there is provided apparatus for scheduling arriving packet cells for input to a switch having a plurality of input ports and output ports, the apparatus comprising: means, associated with each input port, for storing the packet cells arriving at the associated input port, means, associated with each input port, for controlling the storage of packet cells in the storing means by requesting 20 from a contention control means a tr~nsmission time for a one arriving packet cell in which the one arriving packet cell is granted access to one of the plurality of output ports of the switch from the associated input port, by accepting the tr~nsmission time assigned by the contention control, and by returning a previously assigned tr~nsmission time, contention control means for assigning a tr~nsmission time to each request for access to 25 an output port of the switch and for storing at least one previously assigned tr~nsmi.ssion time returned by the controlling means.
~ ~ ~ 3 ~-4 ~
- 2a -Brief De~ .lion of the D~..wi..~.~
A more complete understanding of the invention may be obtained by reading the following description of specific illustrative embodiments of the invention in conjunction 5 with the appended drawing in which:
FIG. 1 is a simplified block diagram for an input-queued packet switch;
FIG. 2 is a more detailed block diagram for the queue control element of a single input port shown in FIG. l;
FIG. 3 is a more detailed block diagram of the contention control in FIG. 1;
FIG. 4 depicts the address control memory of FIG. 2 in more detail;
FIG. 5 shows the output scheduler for one particular output port of the switch realized in accordance with the principles of the present invention; and FIG. 6 shows a simplified block diagram of an alternative embodiment employing input groupmg.
15 Detailed D~ lion In the move toward high performance packet switching for integrated service networks and multi-processor interconnects, attention has been focused on those ~_ - 3 packet ~wilching architectures which provide many ~imlllt~neous input/output paths through the switch fabric and which allow the intern~l switched paths to be time-multiplexed in a statistical, rather than a dete~ istic, f~hi~n Such arrhitectllres offer the capability for high speed tr~mmi~sion in the range of hundreds of Mbps on 5 each input and output port of the switch thereby creating a total switch capacity on the order of several hundred Gbps. High speed switch operation translates into aneed for substantially hardware-based packet processing to handle the packet headers cont~ining path inform~tion such as source and destination addresses used by theswitch fabric to route the packets.
As the switching speed increases, packet congestion becomes even more problematic and important. Packet alTivals are un~ch~A..lçd. Two or more packetsmay arrive sim--lt~n~oously on dirrt;~.-~ input ports destined for the same output port.
Only one of these packets will be allowed to pass through the switch in a particular time slot. All other contending packets must be stored in a queue for later tr~n~mi~sion to the particular output port. Output schçd~-ling and packet storage in non-FIFO queues are two techniques employed in dealing erreclively in the prior art with this type of congestion problem for input-queued packet switches.
An input-queued packet switch is shown in FIG. 1 in simplified block diagram form. The architçct--re includes N input ports 1-1 through l-N, a plurality of cell ~llclllc,lies 2-1 through 2-N together with an associated plurality of queue controls 3-1 through 3-N, contention control 7, and N-N switch 5 having both N switch input ports 4-1 through 4-N and N switch output ports 6-1 through 6-N. It should be noted that N is a positive integer greater than 1. In the FIG., elements on only the first and N~ input/output ports have been shown to plolllole clarity of plesent~tion and understanding. It is to be understood that the terms "packet", "cell", and "packet cell"
are used herein interch~n e~bly to refer to a block of infol~l~Lion in a pre-l~termin~d format such as asynchronous transfer mode (ATM), for example. In the ATM
format, a cell refers to a fixed length packet definç~ by the standard to have a total of 53 bytes divided between a header (5 bytes) and a payload (48 bytes). Also, the terms "time slot" and "tr~nsmission time" are used interchangeably herein to connote generally a time interval spanning a single packet.
209384~
Many types of switches are conle.ll~lated for re~li7ing N-N switch 5. Usually, a space division switch is provided for re~li7ing a cross-conne~;l capability between the switch input ports and the switch output ports. The use of time division multiplexing with the space division switch permits re~li7~tiQn of a time-slotted space 5 division switch. Both symmetric (e. g., N-N) and asyll letlic (e. g., N-M) switch architectures are contemplated. Also blocking and non-blo~ing architectures are contemplated although the latter have ~i nifi~nt throughput advantages over the former. Finally, it is conl~,lllplated that self-routing switches be used for switch 5.
Various self-routing switches are well known in the art and are useful in achieving 10 a large capacity cross-connect capability. In the particular example from eA~,hll~ntal practice described herein, switch S includes an N-N, non-blocking, self-routing, time-slotted, space division switch.
Cell ~ ly 2-1 is positioned bcl~n input port 1-1 and switch input port 4-1. Cell lllemol ~ 2-1 is reali_ed as a random access lll~,lllUly with sufficient capacity 15 for storing the packets received on input port 1-1. Packets are stored in cell lllellloly 2-1 under control of queue control 3-1. As shown in FIG. 1, queue control 3-1 isresponsive to the received packet or some signific~nt portion thereof such as the packet header or the like. Packets are also retrieved from cell lllem~ 2-1 at the a~pl~pliate tr~n~mi~sion time under control from queue control 3-1. Tr~nsmi~sion20 times for the packets stored in cell n~.ll~.ly 2-1 are negotiated between queue control 3-1 and conten~ on control 7 according to a request and ~l.ill~lion procedure over lead 8-1.
Contention control is pelrolllled in a centralized element for the entire switchfabric to sched~ tr~n~mi~sion times for the packet cells. At the appl~liate 25 tr~nsmi~siQn time, the exemplary self-routing space switch S receives cells from the switch input ports 4 and routes them to the appr~liate switch output ports using self-routing control based on physical routing h~fijllllation contained in the cell.
Contention control 7 pelrolms output schedl~ling according to a two phase schedllling technique so that no two input cells are assigned the same tr~n~mi~sion 30 time to the same switch output port. The two phases are a request phase and an arbitration phase. The article by Obara et al. cited above provides a detailed expl~n~tion of two phase sçhed-lling. In the request phase, each queue control 3notifies contenti- n control 7 about those cells destinçd for a particular switch output port which need ~signm~nt of a tr~n~mi~sion time. In the arbitration phase, contention control 7 checks its internal sch~d..ling table for the particular switch S output port to determine the next available tr~n~mi~sit n time slot or slots which can be assigned. Available tr~n~mi~sion times are then assigned to the cells via therequesting queue control. In the queue control, it is necess~ry to check whether an assigned time is reserved by any other cell. If there is no reservation, then the cell is sent at the ~si nçcl tr~n~mi~sion time. If the tr~n~mi~sion time is already reserved to another cell, the cell via the queue control returns to request a transmission time in the next round of sched~llin~
FIG. 2 shows a more detailed block diagram of the cell memory and queue control. Cell memory 2 is depicted as a random access memory having sufficient capacity to store packet cells input on port 1. Output of cell llle~llUl~ 2 is provided via switch input port 4. Queue control 3 incll~des VPI table 31, l"e"lol.y 32, address control Ille~llUl,~ 33, and input controller 34. VPI table 31 performs cell address tr~nsl~tion and provides physical routing info~ ;on for each cell. VPI table 31 stores a list of virtual path identifier~ used in accordance with the ATM standard.
The virtual path identi~ler is located in the header portion of the ATM cell and is provided to VPI table 31 via lead 37. VPI table 31 responds to the received virtual path identifier to output a cell destin~tion on lead 38. The cell destin~tion tells input controller 34 to which switch output port the particular cell is to be routed.
Memory 32 is a random access llle-llGly which ..~ in~ a list of all vacant llul~ locations in cell lll.,l"~,ly 2. The next cell ~o,y address into which an arriving cell is written is supplied by memory 32 on lead 35. Memory 32 makes this address available to address control memory 33.
Input controller 34 negotiates with contention controller 7 for the assignment of a transmission time for the cell destined for the switch output port provided on lead 38. When the transmission time is received by input controller 34, it is output on lead 39 for storage in address control memo"r 33 with the address in which the cell is stored in cell memory 2. Address control memory m~int~in~ the list of cell 20938~9 tr~n~mi~Sion time ~si ~ e~ from the output port sch~ ler in the cnntention control. Me~vly 33 is read sequentially so that the a~l,l~liate read address is supplied on lead 36 to cell Illellloly 2 causing the conlents of cell Illelll.,l~ 2 to be read and output on lead 4 at the ~signed transmission time. In the exemplary S embodiment, the loc~tion~ in address control m~lllvly 33 relate to the sch~dlllçd or assigned tr~n~mi~sion times. It should be noted that readlwrite and clear control signals for the various Illelllolics have been omitted from the FIGs. and are believed to be understood by persons skilled in the art.
Details of the contention control are shown in FIG. 3. Contention control 7 includes N independent output schedulers 70-1 through 70-N. There is an output sched~ r associated ~,vith each switch output port. Each output sçhed~ r receives inputs from, and negotiates with, the queue controls via leads 8-1 through 8-N. That is, each queue control co....~ tes with each and every output scheduler. Of course, it is con~el~lated that a single output sche~--ler may be employed for 15 sched--ling arriving cells for the switch output ports. However, the use of a single output sched-lllo for all N output ports is culll~ome. It should be noted that the use of independent output sch~..lers limits the achievable throughput to ~lv~ ately 65%. This throughput penalty occurs because a switch output port assumes that the cell assigned a particular tr~n~mi~sion time by the output sch~llPr will actually use 20 that tr~n~mi~sion time. If, because of prior tr~n~mi~sion time l~stl~/alions, the input cannot transmit the cell to the switch and instead ll,.,-~...il~ a cell destined to a dirre~nt switch output port, then an ~signed tr~n~mission time is wasted.
In order to signifir~ntly increase the achievable throughput of an input-queued packet switch with output port schedulers, the output sche~llllers are configured in 25 accordance with the principles of the invention to permit recycling or reassignment of tr~n~mi~sion times found to be unusable because of earlier assignments (reservations). A modified architecture for the input-queued, output sched.-led packet switch is shown in FIGs. 4 and 5; FIG. 4 provides additional details for the address control memory while FIG. S provides ~ lition~l detail for an exemplary output 30 scheduler.
When mlp1ifi~A in accordance with the principles of the invention as shown in the FIGs. and described below, the output sch~AIllçr and queue controls operate as follows. The output sch~AIller assigns a transmission time to a queue control for a particular input. The queue control realizes that the related cell cannot be tr~nsmittçd at the assigned time due to a prior l~S~ aLiOn. In the next sçhçd-lling period, the queue control makes a new request for the same cell (the same output port) and, in return, receives a new a~si~ned tr~n~mi~sion time from the output scheduler. Once the new time is received, the queue control returns the previously a~ign~-l tr~n~mi~sion time to the a~lu~liate output sch~ller. The latter time is referred to as the "recycled transmission time slot" for the particular output. The output schçdlll~r now stores the recycled time slot in a storage device such as a simple latch or ~l~O ~ lluly. Recycled time slots are used for ~si~nm~nt to subsequent requests. That is, when an output schçdlllçr obtains a time slot for recycling and subsequently receives a request for a~signm~nt of a time slot, the output schçAlllçr assigns the recycled time slot to the cell for which this latest request is made. A
recycled time slot is erased from the output scheA~ller's memory when that time slot passes without ~signment to a cell.
Mo-lific~tion of the output sch~lller in accor~lce with the principles of the invention for h~nllling recycled time slots is shown in one exemplaTy embodiment in FIG. S for independent output sche~11l1çr 70-1. Output schç~llllçr 70-1 negotiates with input controllers 34-1 through 34-N of the respective queue controls. The outputscheduler includes controller 702, next-available time slot gen~ ,ator 703, and recycled time slot Il~ ly 704. Next-available time slot gellelaLor 703 is connected to controller 702 via lead 705 whereas recycled time slot memory 704 is connected to controller 702 via lead 706.
When any of input controllers 34 request a tr~nsmission time ~signmçnt for their arriving cells, controller 702 receives the requests and checks recycled time slot memory 704 for the presence of one or more recycled time slots. If memory 704 isempty, then controller 702 activates next-available time slot genel~lor 703. When activated, next-available time slot gene.~or 703 produces the next available time slot.
In an exemplary embodiment, next-available time slot gelle.dtOr 703 is implemented via a simple counter and adder circuit in which the counter keeps the next time slot number available for cell tran~mi~sion, counts the total number of requests, and adds the total number of requests to the next time slot number. In the event that recycled time slot I~ lwly 704 has one or more time slots stored therein, controller 702 causes 5 those time slots from llh,nl~Jly 704 to be Q~ign~l to the request before any new time slots are produced by next-available time slot generator 703. After a tran~mi~~ion time is assigned for a particular input, the output sch~ ler via controller 702 stores any recycled time slots from that particular input in memory 704. If the recycled time slot were to be stored prior to time slot Q~Si nm~nt, then the same tran~mi~sion 10 time lclul-lcd by an input to the sçhedlller might be imm~liQtely rea~signç-l to that same input. The present invention avoids this problem and maximizes the probability that recycled time slots will be a~signçd to inputs other than the input which returned the time slot. In turn, this maximi~s the possibility that all a~signed time slots will be used. By using this a~ignm~nt technique, it is not possible for an input to receive 15 the same tran~mi~sion time a~Signm~nt in two successivc sçh~A-lling athm~ . Also, cleQ~llo~k sitllQtions are avoided because recycled time slots e~,..lually expire and new tran~mi~sion times are a~~i ne~l It is illl~Ol~t to recogni~ that recycled time slots are always chronologically earlier than the next-available time slot in ge.le.ator 703.
Recycled time slot llle.llol y 704 is realizable as a single locQtion ~ l y such20 as a latch or a multiple location memory such as a ~O memory or a random access memory. The multiple locQtion ~ ll..ly permits a plurality of recycled time slots to be stored. A FIFO Illel~ imple.llelllalion permits the plurality of recycled time slots to be stored in the order in which they are received. For a single location Illel~lul~, only one recycled time slot would be stored: the earliest recycled time slot, 25 the latest recycled time slot, or any single time slot in bel~cell the earliest and latest recycled time slot. From e~.imental practice, it has been de~,.lllined that excellent performance and throughput is attQinQble even when the output sched.ller only has space to store a single recycled time slot.
Controller 702 accepts the requests from the N queue controls. It is 30 contemplated that the controller for a scheduler polls the queue controls in sequence from 1 to N or sequentially where the starting point of the sequence is increased by 20938~g _ 9 one or more each time through or the like. Barrel shifting the sequence for responding to requests is conte.llplated for introducing a degree of f~irnçss into the schrdllling process.
In order to m~int~in cell sequence for each input and to f~cilit~te recycling of5 time slots, address control lll~,.llOl~r 33 is mr~ifiçd as shown in FIG. 4 and the operation of queue control 3 is modified as described below. Address control memory 33 incllldPs output control l~mol~ 331 and cell order-of-arrival memory 332. l~emories 331 and 332 are connected via lead 333. Output control memory 331 receives the tr~n~mi~sion time assignment from input controller 34.
10 Output control Illc~ y 331 is randomly written and sequentially read wherein the conle-lls at a particular ll~C.llOl y location design~tç the particular switch output port, if any, to which the input is schçd~lled to transmit a cell. T ~c~tions in output control .llcmoly 331 correspond to successive tr~n~mi~sion time slots. Cell order-of-arrival lllclllol~/ 332 is realized as a FIFO ll~ ny having N iclpntir~l partitions or, 15 ~ltern~tively, as N ~O lll~molies. The number N relates to the number of switch output ports for switch 5. Each FIFO lllc.l~ / or partition relates to a particular switch output port so that it is possible to use the notation ~l~Oj is the FIFO memory in cell order-of-arrival l~ 332 related to switch output port j where j = 1, 2, .
. . N. ~Oj contains a first-in, first-out list of the cell me.lloly addresses co"taining 20 cells destined for output j. The infollllalion stored in FlFOj is obtained from memory 32 on lead 35.
In operation, output control memory 331 is read sequentially. At a particular tr~n~mi~sion time, output control memory 331 may read a ~ ly location whose contents in-lir~te transmission from the related input to switch output port j. This 25 info~lion is transferred to cell order-of-arrival lllc.llGly 332 c~using the next available contents of FIFOj to be read. Since the contents of FIFOj are a first-in, first-out list of cell memory addresses, the next available cell memory address in ~l~Oj of m~ oly 332 is read and output via lead 36 to cell lllcmoly 2. This, in turn, causes the a~r~liate cell to be retrieved from cell memory 2 and sent to switch 5.
Input controller 34 negotiates with the output schP~llllPr for tr~n~mi~sion timeassiglllllen~s for its cells, as described above. In addition, input controller 34 det~....ines whether there is a prior reservation for the same tr~n~mis~ion time just assigned by the output scheduler. That is, controller 34 checks (reads) the appr~l,ate loc~tion in memory 331 to see whether there is an entry. If the location in memory 331 is empty, the controller accepts the as~ignm~nt and complete storage S of the ~sign~ tr~nsmi~sion time for the cell in the address control ~ Ol~. If the loc~tion in Ille~ ly 331 is non-empty, then controller 34 rejects the tr~n~mi~sion time ~signmPnt for the cell. During the next sch~d.lling attempt or sche~lling cycle,controller 34 initiates yet another request for tr~nsmi~sion time ~signm~nt for the cell and, upon receipt of the newly ~si n~l tr~n~mi~ion time from the output sch~ r, 10 returns the unusable (previously ~signed) transmission time to the sched-ller for recycling. As such, input controller 34 keeps requesting tr~n~mi~sion time slot ~si~.,...e~ to output j until it receives an assignment which it can use. All unusable time slots are rblulllcd by the input controller so that another input can possibly make use of the time slot for its own tr~n~mi~sion to output j.
From e~ hl~.l~l practice, it has been dete............ il-ed that an input-queued, output-sched..led switch realized in accordance with the principles of the present invention has a m~rkeflly improved throughput of 92% for a random cell arrival model. Recycling of only one time slot in each output sched~.ler was used to achieve this result. Further improvement of throughput to 95% is possible with the 20 combination of time slot recycling and input groupillg.
An embodiment depicting input grouping is shown in FIG. 6. In this embodiment, k input ports are grouped together so that the cells arriving at the k inputs of input mo~llll~s 9-1 through 9-(N/k) are stored in cell Illelllul~l 2' and so that the cell ~ oly is controlled by a single queue control 3'. Queue control 3' operates 25 in a way to permit a plurality of cells up to k to be output from the cell men~ly to the dirrbrb.~ switch input ports in the group. As such, the address control memory in queue control 3' has locations which store up to k assi~ in any given tr~nsmi~sion time slot. RegaKlless of on which input port 1 of the group a cell is received, the cell may be controlled by the cell memory and queue control to exit on 30 a dirrelbnt switch input port 4 destined for a different output port from the other cells tr~n~mitte~l in the same transmission time slot. The embodiment shown in FIG. 6 is ~ 11 further m~ifie~ in that each input sclledlller in co~.~ç~-~;on control 7' receives inputs from only N/k queue controls becduse of input grouping.
Although not explicitly shown, it is understood that the cell me~ may be read faster than it is written so that cells are sent to the switch 5 at a faster rate than 5 they are received at the input port 1. This is called "speed up" and is another form of input ~upillg which is e~;tcd to produce similar throughput i.llpl~elll~nts when coupled with time slot recycling.
T~hl~'r~' Fiel~
This invention relates to packet switching and, more particularly, to controllers and schedulers for improving the throughput of input-queued packet switches.
R~ ln~l of th~ Tnvelltion Contention among ~imlllt~nPously arriving packet cells for the same output port of a packet switch is resolved in favor of only one packet cell at a time. As a result, some form of temporary storage is required for the rem~ining packet cells.
Telllpor~u~ storage provided on the input side of the switch is an input queue whereas storage of the packet cells on the output side of the switch is called an output queue.
With respect to each input/output line of the switch, the input queue p~its loading up to a maximum of 58% whereas the output queue ~lmi~ loading up to 100%
when the first in, first out (E~IFO) storage is utili7ed The reason for such poor perfonn~nce in input-queued packet switches is related to a problem known a head-of-line blocking. To ovel~o~ this problem, it has been proposed that the storage devices in the input queue be non-FIFO or random access. In addition, sche~-lling of packet cells from dirrGl~,. t input queues for the same output port is performed in two phases to result in non-conflicting transmission of the packet cells. See, for example, an article by Obara et al., Int'l. J. of Di~ital and Ansl~ Cabled Systen~. Vol. 2, No. 4, pp. 261-7 (1989). This type of scheduling is called output scheduling. It permits improvement of the switch throughput from 58% to 65% for random packet cell traffic models.
S.. ~ of th~ Tnvention Signific~nt throughput improvement is achieved for an input queued packet 25 switch using output port schedulers by permitting the output schecl.llers to recycle or reassign cell transmission times from input ports which are unable to use them.
~ ~ ~ 3 ~-4 9 When an output scheduler assigns a cell tr~nsmission time to an input port and that input port is unable to use the assigned tr~nsmission time due to a scheduling conflict, for example, the input port makes a new request for the same output port during the next S subsequent request period and then returns the unusable tr~nsmission time assignment back to the output scheduler. The output scheduler stores the returned tr~nsmission time in a separate queue for ~ssignment to later requests for the particular output port. Throughput performance, as a result of this invention, is improved from 58% to 92% for random packet cell traffic models.
Further throughput improvements are realizable by employing input port grouping. This requires that a plurality of input queues are grouped or linked together in such a way that packet cell transmissions for a particular tr~n.smis.sion time are selected from any of the input queues in the same group. Input grouping results in a throughput improvement to 95% for random packet cell traffic models.
In accordance with one aspect of the present invention there is provided apparatus for scheduling arriving packet cells for input to a switch having a plurality of input ports and output ports, the apparatus comprising: means, associated with each input port, for storing the packet cells arriving at the associated input port, means, associated with each input port, for controlling the storage of packet cells in the storing means by requesting 20 from a contention control means a tr~nsmission time for a one arriving packet cell in which the one arriving packet cell is granted access to one of the plurality of output ports of the switch from the associated input port, by accepting the tr~nsmission time assigned by the contention control, and by returning a previously assigned tr~nsmission time, contention control means for assigning a tr~nsmission time to each request for access to 25 an output port of the switch and for storing at least one previously assigned tr~nsmi.ssion time returned by the controlling means.
~ ~ ~ 3 ~-4 ~
- 2a -Brief De~ .lion of the D~..wi..~.~
A more complete understanding of the invention may be obtained by reading the following description of specific illustrative embodiments of the invention in conjunction 5 with the appended drawing in which:
FIG. 1 is a simplified block diagram for an input-queued packet switch;
FIG. 2 is a more detailed block diagram for the queue control element of a single input port shown in FIG. l;
FIG. 3 is a more detailed block diagram of the contention control in FIG. 1;
FIG. 4 depicts the address control memory of FIG. 2 in more detail;
FIG. 5 shows the output scheduler for one particular output port of the switch realized in accordance with the principles of the present invention; and FIG. 6 shows a simplified block diagram of an alternative embodiment employing input groupmg.
15 Detailed D~ lion In the move toward high performance packet switching for integrated service networks and multi-processor interconnects, attention has been focused on those ~_ - 3 packet ~wilching architectures which provide many ~imlllt~neous input/output paths through the switch fabric and which allow the intern~l switched paths to be time-multiplexed in a statistical, rather than a dete~ istic, f~hi~n Such arrhitectllres offer the capability for high speed tr~mmi~sion in the range of hundreds of Mbps on 5 each input and output port of the switch thereby creating a total switch capacity on the order of several hundred Gbps. High speed switch operation translates into aneed for substantially hardware-based packet processing to handle the packet headers cont~ining path inform~tion such as source and destination addresses used by theswitch fabric to route the packets.
As the switching speed increases, packet congestion becomes even more problematic and important. Packet alTivals are un~ch~A..lçd. Two or more packetsmay arrive sim--lt~n~oously on dirrt;~.-~ input ports destined for the same output port.
Only one of these packets will be allowed to pass through the switch in a particular time slot. All other contending packets must be stored in a queue for later tr~n~mi~sion to the particular output port. Output schçd~-ling and packet storage in non-FIFO queues are two techniques employed in dealing erreclively in the prior art with this type of congestion problem for input-queued packet switches.
An input-queued packet switch is shown in FIG. 1 in simplified block diagram form. The architçct--re includes N input ports 1-1 through l-N, a plurality of cell ~llclllc,lies 2-1 through 2-N together with an associated plurality of queue controls 3-1 through 3-N, contention control 7, and N-N switch 5 having both N switch input ports 4-1 through 4-N and N switch output ports 6-1 through 6-N. It should be noted that N is a positive integer greater than 1. In the FIG., elements on only the first and N~ input/output ports have been shown to plolllole clarity of plesent~tion and understanding. It is to be understood that the terms "packet", "cell", and "packet cell"
are used herein interch~n e~bly to refer to a block of infol~l~Lion in a pre-l~termin~d format such as asynchronous transfer mode (ATM), for example. In the ATM
format, a cell refers to a fixed length packet definç~ by the standard to have a total of 53 bytes divided between a header (5 bytes) and a payload (48 bytes). Also, the terms "time slot" and "tr~nsmission time" are used interchangeably herein to connote generally a time interval spanning a single packet.
209384~
Many types of switches are conle.ll~lated for re~li7ing N-N switch 5. Usually, a space division switch is provided for re~li7ing a cross-conne~;l capability between the switch input ports and the switch output ports. The use of time division multiplexing with the space division switch permits re~li7~tiQn of a time-slotted space 5 division switch. Both symmetric (e. g., N-N) and asyll letlic (e. g., N-M) switch architectures are contemplated. Also blocking and non-blo~ing architectures are contemplated although the latter have ~i nifi~nt throughput advantages over the former. Finally, it is conl~,lllplated that self-routing switches be used for switch 5.
Various self-routing switches are well known in the art and are useful in achieving 10 a large capacity cross-connect capability. In the particular example from eA~,hll~ntal practice described herein, switch S includes an N-N, non-blocking, self-routing, time-slotted, space division switch.
Cell ~ ly 2-1 is positioned bcl~n input port 1-1 and switch input port 4-1. Cell lllemol ~ 2-1 is reali_ed as a random access lll~,lllUly with sufficient capacity 15 for storing the packets received on input port 1-1. Packets are stored in cell lllellloly 2-1 under control of queue control 3-1. As shown in FIG. 1, queue control 3-1 isresponsive to the received packet or some signific~nt portion thereof such as the packet header or the like. Packets are also retrieved from cell lllem~ 2-1 at the a~pl~pliate tr~n~mi~sion time under control from queue control 3-1. Tr~nsmi~sion20 times for the packets stored in cell n~.ll~.ly 2-1 are negotiated between queue control 3-1 and conten~ on control 7 according to a request and ~l.ill~lion procedure over lead 8-1.
Contention control is pelrolllled in a centralized element for the entire switchfabric to sched~ tr~n~mi~sion times for the packet cells. At the appl~liate 25 tr~nsmi~siQn time, the exemplary self-routing space switch S receives cells from the switch input ports 4 and routes them to the appr~liate switch output ports using self-routing control based on physical routing h~fijllllation contained in the cell.
Contention control 7 pelrolms output schedl~ling according to a two phase schedllling technique so that no two input cells are assigned the same tr~n~mi~sion 30 time to the same switch output port. The two phases are a request phase and an arbitration phase. The article by Obara et al. cited above provides a detailed expl~n~tion of two phase sçhed-lling. In the request phase, each queue control 3notifies contenti- n control 7 about those cells destinçd for a particular switch output port which need ~signm~nt of a tr~n~mi~sion time. In the arbitration phase, contention control 7 checks its internal sch~d..ling table for the particular switch S output port to determine the next available tr~n~mi~sit n time slot or slots which can be assigned. Available tr~n~mi~sion times are then assigned to the cells via therequesting queue control. In the queue control, it is necess~ry to check whether an assigned time is reserved by any other cell. If there is no reservation, then the cell is sent at the ~si nçcl tr~n~mi~sion time. If the tr~n~mi~sion time is already reserved to another cell, the cell via the queue control returns to request a transmission time in the next round of sched~llin~
FIG. 2 shows a more detailed block diagram of the cell memory and queue control. Cell memory 2 is depicted as a random access memory having sufficient capacity to store packet cells input on port 1. Output of cell llle~llUl~ 2 is provided via switch input port 4. Queue control 3 incll~des VPI table 31, l"e"lol.y 32, address control Ille~llUl,~ 33, and input controller 34. VPI table 31 performs cell address tr~nsl~tion and provides physical routing info~ ;on for each cell. VPI table 31 stores a list of virtual path identifier~ used in accordance with the ATM standard.
The virtual path identi~ler is located in the header portion of the ATM cell and is provided to VPI table 31 via lead 37. VPI table 31 responds to the received virtual path identifier to output a cell destin~tion on lead 38. The cell destin~tion tells input controller 34 to which switch output port the particular cell is to be routed.
Memory 32 is a random access llle-llGly which ..~ in~ a list of all vacant llul~ locations in cell lll.,l"~,ly 2. The next cell ~o,y address into which an arriving cell is written is supplied by memory 32 on lead 35. Memory 32 makes this address available to address control memory 33.
Input controller 34 negotiates with contention controller 7 for the assignment of a transmission time for the cell destined for the switch output port provided on lead 38. When the transmission time is received by input controller 34, it is output on lead 39 for storage in address control memo"r 33 with the address in which the cell is stored in cell memory 2. Address control memory m~int~in~ the list of cell 20938~9 tr~n~mi~Sion time ~si ~ e~ from the output port sch~ ler in the cnntention control. Me~vly 33 is read sequentially so that the a~l,l~liate read address is supplied on lead 36 to cell Illellloly 2 causing the conlents of cell Illelll.,l~ 2 to be read and output on lead 4 at the ~signed transmission time. In the exemplary S embodiment, the loc~tion~ in address control m~lllvly 33 relate to the sch~dlllçd or assigned tr~n~mi~sion times. It should be noted that readlwrite and clear control signals for the various Illelllolics have been omitted from the FIGs. and are believed to be understood by persons skilled in the art.
Details of the contention control are shown in FIG. 3. Contention control 7 includes N independent output schedulers 70-1 through 70-N. There is an output sched~ r associated ~,vith each switch output port. Each output sçhed~ r receives inputs from, and negotiates with, the queue controls via leads 8-1 through 8-N. That is, each queue control co....~ tes with each and every output scheduler. Of course, it is con~el~lated that a single output sche~--ler may be employed for 15 sched--ling arriving cells for the switch output ports. However, the use of a single output sched-lllo for all N output ports is culll~ome. It should be noted that the use of independent output sch~..lers limits the achievable throughput to ~lv~ ately 65%. This throughput penalty occurs because a switch output port assumes that the cell assigned a particular tr~n~mi~sion time by the output sch~llPr will actually use 20 that tr~n~mi~sion time. If, because of prior tr~n~mi~sion time l~stl~/alions, the input cannot transmit the cell to the switch and instead ll,.,-~...il~ a cell destined to a dirre~nt switch output port, then an ~signed tr~n~mission time is wasted.
In order to signifir~ntly increase the achievable throughput of an input-queued packet switch with output port schedulers, the output sche~llllers are configured in 25 accordance with the principles of the invention to permit recycling or reassignment of tr~n~mi~sion times found to be unusable because of earlier assignments (reservations). A modified architecture for the input-queued, output sched.-led packet switch is shown in FIGs. 4 and 5; FIG. 4 provides additional details for the address control memory while FIG. S provides ~ lition~l detail for an exemplary output 30 scheduler.
When mlp1ifi~A in accordance with the principles of the invention as shown in the FIGs. and described below, the output sch~AIllçr and queue controls operate as follows. The output sch~AIller assigns a transmission time to a queue control for a particular input. The queue control realizes that the related cell cannot be tr~nsmittçd at the assigned time due to a prior l~S~ aLiOn. In the next sçhçd-lling period, the queue control makes a new request for the same cell (the same output port) and, in return, receives a new a~si~ned tr~n~mi~sion time from the output scheduler. Once the new time is received, the queue control returns the previously a~ign~-l tr~n~mi~sion time to the a~lu~liate output sch~ller. The latter time is referred to as the "recycled transmission time slot" for the particular output. The output schçdlll~r now stores the recycled time slot in a storage device such as a simple latch or ~l~O ~ lluly. Recycled time slots are used for ~si~nm~nt to subsequent requests. That is, when an output schçdlllçr obtains a time slot for recycling and subsequently receives a request for a~signm~nt of a time slot, the output schçAlllçr assigns the recycled time slot to the cell for which this latest request is made. A
recycled time slot is erased from the output scheA~ller's memory when that time slot passes without ~signment to a cell.
Mo-lific~tion of the output sch~lller in accor~lce with the principles of the invention for h~nllling recycled time slots is shown in one exemplaTy embodiment in FIG. S for independent output sche~11l1çr 70-1. Output schç~llllçr 70-1 negotiates with input controllers 34-1 through 34-N of the respective queue controls. The outputscheduler includes controller 702, next-available time slot gen~ ,ator 703, and recycled time slot Il~ ly 704. Next-available time slot gellelaLor 703 is connected to controller 702 via lead 705 whereas recycled time slot memory 704 is connected to controller 702 via lead 706.
When any of input controllers 34 request a tr~nsmission time ~signmçnt for their arriving cells, controller 702 receives the requests and checks recycled time slot memory 704 for the presence of one or more recycled time slots. If memory 704 isempty, then controller 702 activates next-available time slot genel~lor 703. When activated, next-available time slot gene.~or 703 produces the next available time slot.
In an exemplary embodiment, next-available time slot gelle.dtOr 703 is implemented via a simple counter and adder circuit in which the counter keeps the next time slot number available for cell tran~mi~sion, counts the total number of requests, and adds the total number of requests to the next time slot number. In the event that recycled time slot I~ lwly 704 has one or more time slots stored therein, controller 702 causes 5 those time slots from llh,nl~Jly 704 to be Q~ign~l to the request before any new time slots are produced by next-available time slot generator 703. After a tran~mi~~ion time is assigned for a particular input, the output sch~ ler via controller 702 stores any recycled time slots from that particular input in memory 704. If the recycled time slot were to be stored prior to time slot Q~Si nm~nt, then the same tran~mi~sion 10 time lclul-lcd by an input to the sçhedlller might be imm~liQtely rea~signç-l to that same input. The present invention avoids this problem and maximizes the probability that recycled time slots will be a~signçd to inputs other than the input which returned the time slot. In turn, this maximi~s the possibility that all a~signed time slots will be used. By using this a~ignm~nt technique, it is not possible for an input to receive 15 the same tran~mi~sion time a~Signm~nt in two successivc sçh~A-lling athm~ . Also, cleQ~llo~k sitllQtions are avoided because recycled time slots e~,..lually expire and new tran~mi~sion times are a~~i ne~l It is illl~Ol~t to recogni~ that recycled time slots are always chronologically earlier than the next-available time slot in ge.le.ator 703.
Recycled time slot llle.llol y 704 is realizable as a single locQtion ~ l y such20 as a latch or a multiple location memory such as a ~O memory or a random access memory. The multiple locQtion ~ ll..ly permits a plurality of recycled time slots to be stored. A FIFO Illel~ imple.llelllalion permits the plurality of recycled time slots to be stored in the order in which they are received. For a single location Illel~lul~, only one recycled time slot would be stored: the earliest recycled time slot, 25 the latest recycled time slot, or any single time slot in bel~cell the earliest and latest recycled time slot. From e~.imental practice, it has been de~,.lllined that excellent performance and throughput is attQinQble even when the output sched.ller only has space to store a single recycled time slot.
Controller 702 accepts the requests from the N queue controls. It is 30 contemplated that the controller for a scheduler polls the queue controls in sequence from 1 to N or sequentially where the starting point of the sequence is increased by 20938~g _ 9 one or more each time through or the like. Barrel shifting the sequence for responding to requests is conte.llplated for introducing a degree of f~irnçss into the schrdllling process.
In order to m~int~in cell sequence for each input and to f~cilit~te recycling of5 time slots, address control lll~,.llOl~r 33 is mr~ifiçd as shown in FIG. 4 and the operation of queue control 3 is modified as described below. Address control memory 33 incllldPs output control l~mol~ 331 and cell order-of-arrival memory 332. l~emories 331 and 332 are connected via lead 333. Output control memory 331 receives the tr~n~mi~sion time assignment from input controller 34.
10 Output control Illc~ y 331 is randomly written and sequentially read wherein the conle-lls at a particular ll~C.llOl y location design~tç the particular switch output port, if any, to which the input is schçd~lled to transmit a cell. T ~c~tions in output control .llcmoly 331 correspond to successive tr~n~mi~sion time slots. Cell order-of-arrival lllclllol~/ 332 is realized as a FIFO ll~ ny having N iclpntir~l partitions or, 15 ~ltern~tively, as N ~O lll~molies. The number N relates to the number of switch output ports for switch 5. Each FIFO lllc.l~ / or partition relates to a particular switch output port so that it is possible to use the notation ~l~Oj is the FIFO memory in cell order-of-arrival l~ 332 related to switch output port j where j = 1, 2, .
. . N. ~Oj contains a first-in, first-out list of the cell me.lloly addresses co"taining 20 cells destined for output j. The infollllalion stored in FlFOj is obtained from memory 32 on lead 35.
In operation, output control memory 331 is read sequentially. At a particular tr~n~mi~sion time, output control memory 331 may read a ~ ly location whose contents in-lir~te transmission from the related input to switch output port j. This 25 info~lion is transferred to cell order-of-arrival lllc.llGly 332 c~using the next available contents of FIFOj to be read. Since the contents of FIFOj are a first-in, first-out list of cell memory addresses, the next available cell memory address in ~l~Oj of m~ oly 332 is read and output via lead 36 to cell lllcmoly 2. This, in turn, causes the a~r~liate cell to be retrieved from cell memory 2 and sent to switch 5.
Input controller 34 negotiates with the output schP~llllPr for tr~n~mi~sion timeassiglllllen~s for its cells, as described above. In addition, input controller 34 det~....ines whether there is a prior reservation for the same tr~n~mis~ion time just assigned by the output scheduler. That is, controller 34 checks (reads) the appr~l,ate loc~tion in memory 331 to see whether there is an entry. If the location in memory 331 is empty, the controller accepts the as~ignm~nt and complete storage S of the ~sign~ tr~nsmi~sion time for the cell in the address control ~ Ol~. If the loc~tion in Ille~ ly 331 is non-empty, then controller 34 rejects the tr~n~mi~sion time ~signmPnt for the cell. During the next sch~d.lling attempt or sche~lling cycle,controller 34 initiates yet another request for tr~nsmi~sion time ~signm~nt for the cell and, upon receipt of the newly ~si n~l tr~n~mi~ion time from the output sch~ r, 10 returns the unusable (previously ~signed) transmission time to the sched-ller for recycling. As such, input controller 34 keeps requesting tr~n~mi~sion time slot ~si~.,...e~ to output j until it receives an assignment which it can use. All unusable time slots are rblulllcd by the input controller so that another input can possibly make use of the time slot for its own tr~n~mi~sion to output j.
From e~ hl~.l~l practice, it has been dete............ il-ed that an input-queued, output-sched..led switch realized in accordance with the principles of the present invention has a m~rkeflly improved throughput of 92% for a random cell arrival model. Recycling of only one time slot in each output sched~.ler was used to achieve this result. Further improvement of throughput to 95% is possible with the 20 combination of time slot recycling and input groupillg.
An embodiment depicting input grouping is shown in FIG. 6. In this embodiment, k input ports are grouped together so that the cells arriving at the k inputs of input mo~llll~s 9-1 through 9-(N/k) are stored in cell Illelllul~l 2' and so that the cell ~ oly is controlled by a single queue control 3'. Queue control 3' operates 25 in a way to permit a plurality of cells up to k to be output from the cell men~ly to the dirrbrb.~ switch input ports in the group. As such, the address control memory in queue control 3' has locations which store up to k assi~ in any given tr~nsmi~sion time slot. RegaKlless of on which input port 1 of the group a cell is received, the cell may be controlled by the cell memory and queue control to exit on 30 a dirrelbnt switch input port 4 destined for a different output port from the other cells tr~n~mitte~l in the same transmission time slot. The embodiment shown in FIG. 6 is ~ 11 further m~ifie~ in that each input sclledlller in co~.~ç~-~;on control 7' receives inputs from only N/k queue controls becduse of input grouping.
Although not explicitly shown, it is understood that the cell me~ may be read faster than it is written so that cells are sent to the switch 5 at a faster rate than 5 they are received at the input port 1. This is called "speed up" and is another form of input ~upillg which is e~;tcd to produce similar throughput i.llpl~elll~nts when coupled with time slot recycling.
Claims (9)
1. Apparatus for scheduling arriving packet cells for input to a switch having a plurality of input ports and output ports, the apparatus comprising:
means, associated with each input port, for storing the packet cells arriving at the associated input port, means, associated with each input port, for controlling the storage of packet cells in the storing means by requesting from a contention control means a transmission time for a one arriving packet cell in which the one arriving packet cell is granted access to one of the plurality of output ports of the switch from the associated input port, by accepting the transmission time assigned by the contention control, and by returning a previously assigned transmission time, contention control means for assigning a transmission time to each request for access to an output port of the switch and for storing at least one previously assigned transmission time returned by the controlling means.
means, associated with each input port, for storing the packet cells arriving at the associated input port, means, associated with each input port, for controlling the storage of packet cells in the storing means by requesting from a contention control means a transmission time for a one arriving packet cell in which the one arriving packet cell is granted access to one of the plurality of output ports of the switch from the associated input port, by accepting the transmission time assigned by the contention control, and by returning a previously assigned transmission time, contention control means for assigning a transmission time to each request for access to an output port of the switch and for storing at least one previously assigned transmission time returned by the controlling means.
2. The apparatus as defined in claim 1 wherein the contention control means includes a plurality of scheduling means, each scheduling means associated with one of the plurality of output ports for scheduling each requestfor the associated one of the plurality of output ports into a different transmission time.
3. The apparatus as defined in claim 2 wherein each scheduling means further includes, means for storing the previously assigned transmission time, means for generating a next-available transmission time, and means responsive to a request for selectively assigning the transmission time from one of the transmission time storing means and the transmission time generating means.
4. The apparatus as defined in claim 3 wherein the means for storing the previously assigned transmission time include means for storing more than one previously assigned transmission time.
5. The apparatus as defined in claim 3 wherein the scheduling means further includes means for erasing the previously assigned transmission time from the transmission time storing means.
6. The apparatus as defined in claim 2 wherein the controlling means includes, means for maintaining the packet cells in their original order-of-arrival, and means for storing the transmission time assigned to the packet cell for transmission through the switch.
7. The apparatus as defined in claim 6 wherein the controlling means includes, means for determining whether the presently assigned transmission time has been reserved in the transmission time storing means for another transmission, and means responsive to the determining means for returning the presently assigned transmission time to the contention control means when the transmission time has been previously reserved.
8. The apparatus as defined in claim 7 wherein the controlling means further includes means for delaying return of the previously assigned transmission time by the means for returning.
9. The apparatus as defined in claim 1 wherein the controlling means further includes means for retrieving the stored packet cell from the storing means at the assigned transmission time.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US878,801 | 1992-05-05 | ||
| US07/878,801 US5255265A (en) | 1992-05-05 | 1992-05-05 | Controller for input-queued packet switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2093849A1 CA2093849A1 (en) | 1993-11-06 |
| CA2093849C true CA2093849C (en) | 1999-06-22 |
Family
ID=25372874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002093849A Expired - Fee Related CA2093849C (en) | 1992-05-05 | 1993-04-13 | Controller for input-queued packet switch |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5255265A (en) |
| EP (1) | EP0569172B1 (en) |
| JP (1) | JP2981082B2 (en) |
| CA (1) | CA2093849C (en) |
| DE (1) | DE69330395T2 (en) |
| ES (1) | ES2160586T3 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1196791B (en) * | 1986-11-18 | 1988-11-25 | Cselt Centro Studi Lab Telecom | SWITCHING ELEMENT FOR MULTI-STAGE INTERCONNECTION NETWORKS SELF-SLIDING TO PACKAGE SWITCHING |
| DE3738177A1 (en) * | 1987-11-10 | 1989-05-18 | Siemens Ag | INTERMEDIATE NODE FOR THE INTERMEDIATE OF DATA SIGNALS TRANSMITTED IN DATA PACKAGES |
| JPH0287745A (en) * | 1988-09-26 | 1990-03-28 | Nippon Telegr & Teleph Corp <Ntt> | Cell contention control circuit |
| US4979165A (en) * | 1989-06-23 | 1990-12-18 | At&T Bell Laboratories | Multiple queue bandwidth reservation packet system |
| JP2803262B2 (en) * | 1989-12-15 | 1998-09-24 | 日本電気株式会社 | Packet switch |
| US5157654A (en) * | 1990-12-18 | 1992-10-20 | Bell Communications Research, Inc. | Technique for resolving output port contention in a high speed packet switch |
-
1992
- 1992-05-05 US US07/878,801 patent/US5255265A/en not_active Expired - Lifetime
-
1993
- 1993-04-13 CA CA002093849A patent/CA2093849C/en not_active Expired - Fee Related
- 1993-04-26 EP EP93303225A patent/EP0569172B1/en not_active Expired - Lifetime
- 1993-04-26 DE DE69330395T patent/DE69330395T2/en not_active Expired - Fee Related
- 1993-04-26 ES ES93303225T patent/ES2160586T3/en not_active Expired - Lifetime
- 1993-04-30 JP JP12485193A patent/JP2981082B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2981082B2 (en) | 1999-11-22 |
| EP0569172A3 (en) | 1995-01-25 |
| US5255265A (en) | 1993-10-19 |
| DE69330395D1 (en) | 2001-08-09 |
| ES2160586T3 (en) | 2001-11-16 |
| JPH0637805A (en) | 1994-02-10 |
| EP0569172B1 (en) | 2001-07-04 |
| DE69330395T2 (en) | 2002-05-16 |
| EP0569172A2 (en) | 1993-11-10 |
| CA2093849A1 (en) | 1993-11-06 |
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