CA2098414A1 - Register Architecture for a Super Scalar Computer - Google Patents

Register Architecture for a Super Scalar Computer

Info

Publication number
CA2098414A1
CA2098414A1 CA2098414A CA2098414A CA2098414A1 CA 2098414 A1 CA2098414 A1 CA 2098414A1 CA 2098414 A CA2098414 A CA 2098414A CA 2098414 A CA2098414 A CA 2098414A CA 2098414 A1 CA2098414 A1 CA 2098414A1
Authority
CA
Canada
Prior art keywords
data
destination
source
registers
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2098414A
Other languages
French (fr)
Other versions
CA2098414C (en
Inventor
Faraydon Karim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2098414A1 publication Critical patent/CA2098414A1/en
Application granted granted Critical
Publication of CA2098414C publication Critical patent/CA2098414C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Abstract

A super scalar computer architecture and method of operation for executing instructions out-of-order while managing for data dependencies, data anti-dependencies, and integrity of sequentiality for precise interrupts, restarts and branch deletions. Multiple registers and tables are used to rename and recycle source and destination addresses referenced to a general purpose register. Access to destination data in the general purpose register is locked until the instruction associated with the data is fully executed. Renaming of both the source and destination registers avoids anti-dependency problems while integrity of sequentiality is maintained by ordered retirement of instruction results consistent with the order of the input instructions. The system and method operate with multiple input instructions and multiple execution units. The control words generated by the renaming of the source and destination registers differ insignificantly from the original instructions, obviating the practice of adding status and sequence information to processor control words.
CA002098414A 1992-10-30 1993-06-15 Register architecture for a super scalar computer Expired - Fee Related CA2098414C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US96969592A 1992-10-30 1992-10-30
US969,695 1992-10-30

Publications (2)

Publication Number Publication Date
CA2098414A1 true CA2098414A1 (en) 1994-05-01
CA2098414C CA2098414C (en) 1997-05-13

Family

ID=25515870

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002098414A Expired - Fee Related CA2098414C (en) 1992-10-30 1993-06-15 Register architecture for a super scalar computer

Country Status (9)

Country Link
US (1) US5481683A (en)
EP (1) EP0600611B1 (en)
JP (1) JP2698033B2 (en)
KR (1) KR970004509B1 (en)
CN (1) CN1053508C (en)
AT (1) ATE189071T1 (en)
CA (1) CA2098414C (en)
DE (1) DE69327637T2 (en)
TW (1) TW306987B (en)

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Also Published As

Publication number Publication date
KR940009820A (en) 1994-05-24
EP0600611A2 (en) 1994-06-08
TW306987B (en) 1997-06-01
KR970004509B1 (en) 1997-03-28
ATE189071T1 (en) 2000-02-15
JP2698033B2 (en) 1998-01-19
CA2098414C (en) 1997-05-13
US5481683A (en) 1996-01-02
CN1053508C (en) 2000-06-14
EP0600611A3 (en) 1995-01-11
JPH06214784A (en) 1994-08-05
DE69327637T2 (en) 2000-07-06
DE69327637D1 (en) 2000-02-24
EP0600611B1 (en) 2000-01-19
CN1105138A (en) 1995-07-12

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