CA2098414A1 - Register Architecture for a Super Scalar Computer - Google Patents
Register Architecture for a Super Scalar ComputerInfo
- Publication number
- CA2098414A1 CA2098414A1 CA2098414A CA2098414A CA2098414A1 CA 2098414 A1 CA2098414 A1 CA 2098414A1 CA 2098414 A CA2098414 A CA 2098414A CA 2098414 A CA2098414 A CA 2098414A CA 2098414 A1 CA2098414 A1 CA 2098414A1
- Authority
- CA
- Canada
- Prior art keywords
- data
- destination
- source
- registers
- instructions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 abstract 2
- 238000012217 deletion Methods 0.000 abstract 1
- 230000037430 deletion Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
Abstract
A super scalar computer architecture and method of operation for executing instructions out-of-order while managing for data dependencies, data anti-dependencies, and integrity of sequentiality for precise interrupts, restarts and branch deletions. Multiple registers and tables are used to rename and recycle source and destination addresses referenced to a general purpose register. Access to destination data in the general purpose register is locked until the instruction associated with the data is fully executed. Renaming of both the source and destination registers avoids anti-dependency problems while integrity of sequentiality is maintained by ordered retirement of instruction results consistent with the order of the input instructions. The system and method operate with multiple input instructions and multiple execution units. The control words generated by the renaming of the source and destination registers differ insignificantly from the original instructions, obviating the practice of adding status and sequence information to processor control words.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US96969592A | 1992-10-30 | 1992-10-30 | |
US969,695 | 1992-10-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2098414A1 true CA2098414A1 (en) | 1994-05-01 |
CA2098414C CA2098414C (en) | 1997-05-13 |
Family
ID=25515870
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002098414A Expired - Fee Related CA2098414C (en) | 1992-10-30 | 1993-06-15 | Register architecture for a super scalar computer |
Country Status (9)
Country | Link |
---|---|
US (1) | US5481683A (en) |
EP (1) | EP0600611B1 (en) |
JP (1) | JP2698033B2 (en) |
KR (1) | KR970004509B1 (en) |
CN (1) | CN1053508C (en) |
AT (1) | ATE189071T1 (en) |
CA (1) | CA2098414C (en) |
DE (1) | DE69327637T2 (en) |
TW (1) | TW306987B (en) |
Families Citing this family (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06242948A (en) * | 1993-02-16 | 1994-09-02 | Fujitsu Ltd | Pipeline processing computer |
US6378062B1 (en) * | 1994-01-04 | 2002-04-23 | Intel Corporation | Method and apparatus for performing a store operation |
US5724536A (en) * | 1994-01-04 | 1998-03-03 | Intel Corporation | Method and apparatus for blocking execution of and storing load operations during their execution |
US5537559A (en) * | 1994-02-08 | 1996-07-16 | Meridian Semiconductor, Inc. | Exception handling circuit and method |
US6205538B1 (en) * | 1994-08-24 | 2001-03-20 | Sun Microsystems, Inc. | Instruction result labeling in a counterflow pipeline processor |
US5625789A (en) * | 1994-10-24 | 1997-04-29 | International Business Machines Corporation | Apparatus for source operand dependendency analyses register renaming and rapid pipeline recovery in a microprocessor that issues and executes multiple instructions out-of-order in a single cycle |
US5675759A (en) * | 1995-03-03 | 1997-10-07 | Shebanow; Michael C. | Method and apparatus for register management using issue sequence prior physical register and register association validity information |
US5974240A (en) * | 1995-06-07 | 1999-10-26 | International Business Machines Corporation | Method and system for buffering condition code data in a data processing system having out-of-order and speculative instruction execution |
GB2308470B (en) * | 1995-12-22 | 2000-02-16 | Nokia Mobile Phones Ltd | Program memory scheme for processors |
US5761524A (en) * | 1996-03-15 | 1998-06-02 | Renditon, Inc. | Method and apparatus for performing and operation multiple times in response to a single instruction |
US5765016A (en) * | 1996-09-12 | 1998-06-09 | Advanced Micro Devices, Inc. | Reorder buffer configured to store both speculative and committed register states |
US5802338A (en) * | 1996-10-01 | 1998-09-01 | International Business Machines Corporation | Method of self-parallelizing and self-parallelizing multiprocessor using the method |
US5872949A (en) * | 1996-11-13 | 1999-02-16 | International Business Machines Corp. | Apparatus and method for managing data flow dependencies arising from out-of-order execution, by an execution unit, of an instruction series input from an instruction source |
US5889974A (en) * | 1996-12-30 | 1999-03-30 | Intel Corporation | Method and apparatus for the detection of reordering hazards |
US5805849A (en) * | 1997-03-31 | 1998-09-08 | International Business Machines Corporation | Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions |
US6098167A (en) * | 1997-03-31 | 2000-08-01 | International Business Machines Corporation | Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution |
US5913048A (en) * | 1997-03-31 | 1999-06-15 | International Business Machines Corporation | Dispatching instructions in a processor supporting out-of-order execution |
US5870582A (en) * | 1997-03-31 | 1999-02-09 | International Business Machines Corporation | Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched |
US5887161A (en) * | 1997-03-31 | 1999-03-23 | International Business Machines Corporation | Issuing instructions in a processor supporting out-of-order execution |
US5987598A (en) * | 1997-07-07 | 1999-11-16 | International Business Machines Corporation | Method and system for tracking instruction progress within a data processing system |
US6128728A (en) * | 1997-08-01 | 2000-10-03 | Micron Technology, Inc. | Virtual shadow registers and virtual register windows |
US5901299A (en) * | 1997-09-19 | 1999-05-04 | International Business Machines Corporation | Method and apparatus for transferring data between buses having differing ordering policies |
US6016526A (en) * | 1997-09-19 | 2000-01-18 | International Business Machines Corporation | Method and apparatus for transferring data between buses having differing ordering policies via the use of autonomous units |
US5938753A (en) * | 1997-09-19 | 1999-08-17 | International Business Machines Corporation | Method and apparatus for controlling autonomous units transferring data between buses having different ordering policies |
US5961636A (en) * | 1997-09-22 | 1999-10-05 | International Business Machines Corporation | Checkpoint table for selective instruction flushing in a speculative execution unit |
US6065110A (en) * | 1998-02-09 | 2000-05-16 | International Business Machines Corporation | Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue |
US6061785A (en) * | 1998-02-17 | 2000-05-09 | International Business Machines Corporation | Data processing system having an apparatus for out-of-order register operations and method therefor |
US6067644A (en) * | 1998-04-15 | 2000-05-23 | International Business Machines Corporation | System and method monitoring instruction progress within a processor |
US6212619B1 (en) | 1998-05-11 | 2001-04-03 | International Business Machines Corporation | System and method for high-speed register renaming by counting |
US6134645A (en) * | 1998-06-01 | 2000-10-17 | International Business Machines Corporation | Instruction completion logic distributed among execution units for improving completion efficiency |
US6324640B1 (en) * | 1998-06-30 | 2001-11-27 | International Business Machines Corporation | System and method for dispatching groups of instructions using pipelined register renaming |
US6243786B1 (en) * | 1998-12-23 | 2001-06-05 | Industrial Technology Research Institute | Apparatus and method for generating an interrupt prohibited zone in pipelined data processors |
US7191309B1 (en) | 1999-09-01 | 2007-03-13 | Intel Corporation | Double shift instruction for micro engine used in multithreaded parallel processor architecture |
ATE475930T1 (en) | 1999-09-01 | 2010-08-15 | Intel Corp | BRANCH INSTRUCTION FOR A MULTIPLE PROCESSOR |
US7546444B1 (en) | 1999-09-01 | 2009-06-09 | Intel Corporation | Register set used in multithreaded parallel processor architecture |
US7681018B2 (en) * | 2000-08-31 | 2010-03-16 | Intel Corporation | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set |
US20020053017A1 (en) * | 2000-09-01 | 2002-05-02 | Adiletta Matthew J. | Register instructions for a multithreaded processor |
JP3817436B2 (en) | 2000-09-28 | 2006-09-06 | 株式会社東芝 | Processor and renaming device |
US6671794B1 (en) * | 2000-10-02 | 2003-12-30 | International Business Machines Corporation | Address generation interlock detection |
US7020871B2 (en) * | 2000-12-21 | 2006-03-28 | Intel Corporation | Breakpoint method for parallel hardware threads in multithreaded processor |
US7191315B2 (en) | 2001-06-04 | 2007-03-13 | Sun Microsystems, Inc. | Method and system for tracking and recycling physical register assignment |
US6868476B2 (en) | 2001-08-27 | 2005-03-15 | Intel Corporation | Software controlled content addressable memory in a general purpose execution datapath |
US7216204B2 (en) | 2001-08-27 | 2007-05-08 | Intel Corporation | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment |
US7225281B2 (en) * | 2001-08-27 | 2007-05-29 | Intel Corporation | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms |
US7487505B2 (en) | 2001-08-27 | 2009-02-03 | Intel Corporation | Multithreaded microprocessor with register allocation based on number of active threads |
US7610451B2 (en) * | 2002-01-25 | 2009-10-27 | Intel Corporation | Data transfer mechanism using unidirectional pull bus and push bus |
US7437724B2 (en) * | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
US7337275B2 (en) * | 2002-08-13 | 2008-02-26 | Intel Corporation | Free list and ring data structure management |
US6941438B2 (en) | 2003-01-10 | 2005-09-06 | Intel Corporation | Memory interleaving |
US7272701B2 (en) * | 2003-10-22 | 2007-09-18 | Intel Corporation | Method and apparatus for limiting ports in a register alias table having high-bandwidth and low-bandwidth structures |
US7478276B2 (en) * | 2005-02-10 | 2009-01-13 | International Business Machines Corporation | Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor |
US7409589B2 (en) * | 2005-05-27 | 2008-08-05 | International Business Machines Corporation | Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor |
US7873625B2 (en) * | 2006-09-18 | 2011-01-18 | International Business Machines Corporation | File indexing framework and symbolic name maintenance framework |
US20080242560A1 (en) * | 2006-11-21 | 2008-10-02 | Gunderson Kevin L | Methods for generating amplified nucleic acid arrays |
US8677050B2 (en) * | 2010-11-12 | 2014-03-18 | International Business Machines Corporation | System, method and computer program product for extending a cache using processor registers |
US9072325B2 (en) | 2012-08-30 | 2015-07-07 | Shelby Group International, Inc. | Glove finger attachment system |
US9588770B2 (en) | 2013-03-15 | 2017-03-07 | Samsung Electronics Co., Ltd. | Dynamic rename based register reconfiguration of a vector register file |
US9510628B2 (en) | 2013-03-15 | 2016-12-06 | Shelby Group International, Inc. | Glove thermal protection system |
CN104598201A (en) * | 2013-10-31 | 2015-05-06 | 国际商业机器公司 | Instruction performance analysis method and device |
US10216523B2 (en) | 2015-07-17 | 2019-02-26 | General Electric Company | Systems and methods for implementing control logic |
CN107329936A (en) * | 2016-04-29 | 2017-11-07 | 北京中科寒武纪科技有限公司 | A kind of apparatus and method for performing neural network computing and matrix/vector computing |
US10694795B2 (en) | 2017-01-10 | 2020-06-30 | Shelby Group International, Inc. | Glove construction |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3346851A (en) * | 1964-07-08 | 1967-10-10 | Control Data Corp | Simultaneous multiprocessing computer system |
US4574349A (en) * | 1981-03-30 | 1986-03-04 | International Business Machines Corp. | Apparatus for addressing a larger number of instruction addressable central processor registers than can be identified by a program instruction |
US4807115A (en) * | 1983-10-07 | 1989-02-21 | Cornell Research Foundation, Inc. | Instruction issuing mechanism for processors with multiple functional units |
US4847755A (en) * | 1985-10-31 | 1989-07-11 | Mcc Development, Ltd. | Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies |
US4903196A (en) * | 1986-05-02 | 1990-02-20 | International Business Machines Corporation | Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor |
US4992938A (en) * | 1987-07-01 | 1991-02-12 | International Business Machines Corporation | Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers |
US5134561A (en) * | 1987-07-20 | 1992-07-28 | International Business Machines Corporation | Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries |
US4901233A (en) * | 1987-07-20 | 1990-02-13 | International Business Machines Corporation | Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries |
US4972470A (en) * | 1987-08-06 | 1990-11-20 | Steven Farago | Programmable connector |
EP0312764A3 (en) * | 1987-10-19 | 1991-04-10 | International Business Machines Corporation | A data processor having multiple execution units for processing plural classes of instructions in parallel |
US5155817A (en) * | 1988-04-01 | 1992-10-13 | Kabushiki Kaisha Toshiba | Microprocessor |
US5487156A (en) * | 1989-12-15 | 1996-01-23 | Popescu; Valeri | Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched |
US5280615A (en) * | 1990-03-23 | 1994-01-18 | Unisys Corporation | Out of order job processing method and apparatus |
US5197132A (en) * | 1990-06-29 | 1993-03-23 | Digital Equipment Corporation | Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery |
JPH0480824A (en) * | 1990-07-23 | 1992-03-13 | Nec Corp | Data processor |
US5261071A (en) * | 1991-03-21 | 1993-11-09 | Control Data System, Inc. | Dual pipe cache memory with out-of-order issue capability |
US5355457A (en) * | 1991-05-21 | 1994-10-11 | Motorola, Inc. | Data processor for performing simultaneous instruction retirement and backtracking |
US5386562A (en) * | 1992-05-13 | 1995-01-31 | Mips Computer Systems, Inc. | Circular scheduling method and apparatus for executing computer programs by moving independent instructions out of a loop |
-
1993
- 1993-03-19 US US08/034,193 patent/US5481683A/en not_active Expired - Fee Related
- 1993-06-15 CA CA002098414A patent/CA2098414C/en not_active Expired - Fee Related
- 1993-09-08 TW TW082107359A patent/TW306987B/zh not_active IP Right Cessation
- 1993-09-28 KR KR1019930020072A patent/KR970004509B1/en not_active IP Right Cessation
- 1993-10-25 JP JP5265946A patent/JP2698033B2/en not_active Expired - Fee Related
- 1993-10-28 CN CN93119608A patent/CN1053508C/en not_active Expired - Fee Related
- 1993-11-01 EP EP93308705A patent/EP0600611B1/en not_active Expired - Lifetime
- 1993-11-01 DE DE69327637T patent/DE69327637T2/en not_active Expired - Fee Related
- 1993-11-01 AT AT93308705T patent/ATE189071T1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CA2098414C (en) | 1997-05-13 |
JPH06214784A (en) | 1994-08-05 |
JP2698033B2 (en) | 1998-01-19 |
KR970004509B1 (en) | 1997-03-28 |
DE69327637D1 (en) | 2000-02-24 |
EP0600611A3 (en) | 1995-01-11 |
EP0600611A2 (en) | 1994-06-08 |
CN1053508C (en) | 2000-06-14 |
EP0600611B1 (en) | 2000-01-19 |
KR940009820A (en) | 1994-05-24 |
DE69327637T2 (en) | 2000-07-06 |
US5481683A (en) | 1996-01-02 |
TW306987B (en) | 1997-06-01 |
CN1105138A (en) | 1995-07-12 |
ATE189071T1 (en) | 2000-02-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA2098414A1 (en) | Register Architecture for a Super Scalar Computer | |
US7496733B2 (en) | System and method of execution of register pointer instructions ahead of instruction issues | |
EP0638183B1 (en) | A system and method for retiring instructions in a superscalar microprocessor | |
US5923863A (en) | Software mechanism for accurately handling exceptions generated by instructions scheduled speculatively due to branch elimination | |
US5699536A (en) | Computer processing system employing dynamic instruction formatting | |
US5928349A (en) | Mixed-endian computing environment for a conventional bi-endian computer system | |
EP0762270B1 (en) | Microprocessor with load/store operation to/from multiple registers | |
US7228402B2 (en) | Predicate register file write by an instruction with a pending instruction having data dependency | |
KR100335745B1 (en) | High performance speculative misaligned load operations | |
DE69525277D1 (en) | Data processor for operands with variable width | |
EP0849665A3 (en) | System and method for register renaming | |
CN100362474C (en) | Time-multiplexed speculative multi-threading to support single-threaded applications | |
JPH10301778A (en) | Method and device for managing name change of register | |
US5944810A (en) | Superscalar processor for retiring multiple instructions in working register file by changing the status bits associated with each execution result to identify valid data | |
US6253310B1 (en) | Delayed deallocation of an arithmetic flags register | |
US20050102494A1 (en) | Method and apparatus for register stack implementation using micro-operations | |
US6266761B1 (en) | Method and system in an information processing system for efficient maintenance of copies of values stored within registers | |
JPH10283178A (en) | Method and system for issuing instruction | |
Sima | 6.2 Register Renaming Techniques1 | |
WO2000000878A2 (en) | Methods for increasing instruction-level parallelism in microprocessors and digital systems |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |