CA2143490A1 - Multimedia Graphics System - Google Patents

Abstract

Bytes of different types of digital information, including standard interframe video (SIF), graphics, television and audio are transferred between a controller, storage memory and shift registers (e.g. FIFO's) individually associated with the different information types. For a VRAM memory, information is transferred in parallel, controlled by tag bus information, from the controller to the memory and then serially to the FIFO's, all at a frequency higher than a clock frequency in a monitor raster scan. The tag bus information is decoded and introduced to an additional FIFO. A state machine processes such additional FIFO information and transfers the digital information to the different FIFO's at times controlled in each line by such additional FIFO- e.g. particular times in each line for the SIF and graphics and thereafter, for television and audio, at times unrelated to any times in such line. The graphics transfer is timed to substantially fill, but not overflow, in such line the limited capacity of the associated FIFO. Their limited capacities cause the television and audio FIFO's to stop receiving bytes when filled to particular limits. For a DRAM memory, information is transferred, dependent upon the tag bus information, in parallel between the controller, memory and FIFO's at the clock frequency. In a "Rambus" system, a bus common with the controller, memory and FIFO's provides control and timing bytes. The information in successive bytes transferred through the common bus to the controller, memory and FIFO's dependent upon such timing and control information in such bytes.