CA2145361C - Buffer manager - Google Patents

Buffer manager

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Publication number
CA2145361C
CA2145361C CA002145361A CA2145361A CA2145361C CA 2145361 C CA2145361 C CA 2145361C CA 002145361 A CA002145361 A CA 002145361A CA 2145361 A CA2145361 A CA 2145361A CA 2145361 C CA2145361 C CA 2145361C
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Canada
Prior art keywords
buffer
state
data
display
address generator
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CA002145361A
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French (fr)
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CA2145361A1 (en
Inventor
Martin William Sotheran
Helen Rosemary Finch
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Chartoleaux KG LLC
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Discovision Associates
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Priority claimed from GB9405914A external-priority patent/GB9405914D0/en
Priority claimed from GB9503964A external-priority patent/GB2287808B/en
Application filed by Discovision Associates filed Critical Discovision Associates
Publication of CA2145361A1 publication Critical patent/CA2145361A1/en
Application granted granted Critical
Publication of CA2145361C publication Critical patent/CA2145361C/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

This invention provides a method to control the buffering of encoded video data organized as frames or fields.
This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture number is on or after the presentation number.

Description

~14~361 BUFFER MANAGER
REFERENCE TO RELATED APPLICATIONS
This application is related to British Patent Application entitled "Video Decompression" as U.K. Serial No.
9405914.4 filed on March 24, 1994 and British Patent Application entitled "Method and Apparatus for Interfacing with RAM" as U.K. Serial No. 9503964.0 filed on February 28, 1995.
BACKGROUND OF THE INVENTION
The present invention is directed to a decompression circuit which operates to decompress or decode a plurality of differently encoded input signals, and, more particularly) to a method of controlling the buffering of encoded video data in said circuit.
Previous buffer manager systems were hardwired to implement certain predetermined conversions, for example, 3-2 pulldown systems. The present buffer manager does not use a predefined sequence of replication or skipping of frames, as in conventional 3-2 pulldown systems, and thus any ratio of encoded frame rate and display frame rate can be accommodated.
The present buffer manager is thus more flexible with respect to its strategy for dropping or duplicating frames in order to account for differences in the encoded data frame rate and the display frame rate.

! t SUMMARY OF THE INVENTION
The invention provides a method for buffering encoded video data organized as frames comprising determining the picture number of a frame, determining the desired presentation number of a frame and marking the buffer as ready when the picture number is on or after the desired presentation number.
In accordance with the present invention there is provided an image formatter for processing encoded video data comprising: an input element for receiving encoded data representing video frames, said data arriving as a sequence of tokens at an encoded frame rate for output or display at a display frame rate; a memory defining at least three buffers for storage of the encoded data, wherein said received data is initially stored in a first said buffer; a write address generator for generating addresses for data being stored in said first buffer; a read address generator for generating addresses for reading data stored in said first buffer; a presentation number counter; an output interface linked to said read address generator that produces output data at said display frame rate; and a buffer manager responsive to control information in said tokens, to said encoded frame rate, and to said display frame rate, said buffer manager dynamically allocating and deallacating said at least three buffers as arrival buffers for reference by said write address generator, and as display buffers for reference by said read address generator, said buffer manager clearing said buffers for occupation by subsequently arriving data, and maintaining status information of said buffers wherein said status information comprises a state VACANT, wherein a said buffer is available, a state INUSE, wherein a said buffer can be referenced by said write address generator, a state FULL, wherein a said buffer is occupied by data, and a state READY
wherein a said buffer is reallocated as a display buffer;
wherein responsive to said presentation number counter and a current picture number contained in the encoded data said buffer manager asserts a late arrival signal indicating that a buffer in said state READY is not in synchronization with said display frame rate; a state machine for controlling said buffer manager, said state machine transitioning among a plurality of states, including: a first transition from a first state PRESO, to a second state PRES1, wherein said status information of said buffers are evaluated; a second transition from said state PRES1 to a third state DRQ wherein a pending request for said display buffers is evaluated; and a third transition from said stage DRQ to a fourth state TOKEN, wherein tokens of received data are examined; whereby a status of said arrival buffer can be updated; and a plurality of 2-wire interfaces each comprising: a sender a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready, wherein said buffer manager communicates with said read address generator, and with said write address generator via said 2-wire interfaces.
2a ...
In accordance with the present invention there is further provided an image formatter for processing encoded video data comprising: an input element for receiving encoded data having a frame rate and arrival rate; a memory defining at least three buffers for storage of the encoded data, one of said buffers being a display buffer) and another of said buffers being an arrival buffer; a write address generator for generating write addresses for data being stored thereat in said memory; a read address generator for generating read addresses for reading data stored thereat in said memory; an output interface linked to said read address generator that produces decoded data at a display rate; and a buffer manager responsive to said arrival rate, said display rate, and said frame rate for allocating said buffers to said write address generator and said read address generator, wherein said buffers are allocated to said write address generator in response to a timing regime.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram of an image formatter.
Fig. 2 is a diagram of the buffer manager state machine.
Fig. 3 illustrates the main loop of the state machine in Fig. 2.
Before one embodiment of the invention is explained in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The invention is 2b :.~~'. 74078-29 capable of other embodiments and of being practiced or carried out in various ways. Also, it should be understood that the phraseology and terminolagy used herein is for the purpose of description and should not be regarded as limiting.
DETAILED DESCRIPTION OF THE INVENTION
An image formatter is shown in Figure 1. There are two address generators, one for writing 10 and one for reading 20, a buffer manager 30 which supervises the two address 2c 2~~~~~~
generators 10 and 20 and provides frame-rate conversion, a data processing pipeline including vertical and horizontal upsamplers, colour-space conversion and gamma correction, and a final control block which regulates the output of the processing pipeline.
Tokens arriving at the input to the image formatter are buffered in the FIFO 40 and transferred into the buffer manager 30. This block detects the arrival of new pictures and determines the availability of a buffer in which to store each one. If there is a buffer available, it is allocated to the arriving picture and its index is transferred to the write address generator 10. If there is no buffer available, the incoming picture will be stalled until one does become free.
All tokens are passed on to the write address generator 10.
This operation is described in greater detail in U.K. Serial No. 9405914.4 filed on March 24, 1994, which is incorporated herein by reference.
Each time the read address generator 20 receives a VSYNC signal from the display system, a request is made to the buffer manager 30 for a new display buffer index. If there is a buffer containing complete picture data, and that picture is deemed to be ready for display, that buffer's index will be passed to the display address generator. If not, the buffer manager sends the index of the last buffer to be displayed. At start-up, zero is passed as the index until the first buffer is full. A picture is deemed to be ready for display if its number (calculated as each picture is input) is greater than or equal to the picture number which is expected at the 2I~~~~I
display (presentation number) given the encoding frame rate.
The expected picture number is determined by counting picture clock pulses, where picture clock can be generated either locally by the clock dividers, or externally. This technology allows frame-rate conversion (e. g.2-3 pull-down).
External DRAM is used for the buffers, which can be either twa or three in number. Three are necessary if frame-rate conversion is to be effected.
The purpose of the buffer manager 30 is to supply the address generators with indices indicating any of either two or three external buffers for writing and reading of picture data. The allocation of these indices is influenced by three principal factors, each representing the effect of one of the timing regimes in operation: the rate at which picture data arrives at the input to image formatter (coded data rate), the rate at which data is displayed (display data rate), and the frame rate of the encoded video sequence (presentation rate).
A three-buffer system enables the presentation rate and the display rate to differ (eg. 2-3 pull-down), so that frames are either repeated or skipped as necessary to achieve the best possible sequence of frames given the timing constraints of the system. Pictures which present some difficulty in decoding may also be accommodated in a similar way, so that if a picture takes longer than the available display time to decode, the previous frame will be repeated while everything else 'catches up'. In a two-buffer system the three timing regimes must be locked - it is the third buffer 214~3~i which provides the flexibility for taking up slack.
The buffer manager operates by maintaining certain status information associated with each external buffer - this includes flags indicating if the buffer is in use, full of data, or ready for display, and the picture number within the sequence of the picture currently stored in the buffer. The presentation number is also recorded, this being a number which increments every time a picture clock pulse is received, and represents the picture number which is currently expected for display based on the frame rate of the encoded sequence.
An arrival buffer (a buffer to which incoming data will be written} is allocated every time a PICTURE_START token is detected at the input, and this buffer is then flagged as IN USE; on PICTURE_END, the arrival buffer will be de-allocated (reset to zero) and the buffer flagged as either FULL or READY depending on the relationship between the picture number and the presentation number.
The display address generator requests a new display buffer, once every vsync, via a two-wire-interface. If there is a buffer flagged as READY, then that will be allocated to display by the buffer manager. If there is no READY buffer, the previously displayed buffer will be repeated.
Each time the presentation number changes this is detected and every buffer containing a complete picture is tested for READY-ness by examining the relationship between its picture number and the presentation number. Buffers are considered in turn, and when any is deemed to be READY this automatically cancels the READY-ness of any which was 2.~4~3~I
previously flagged as READY, this then being flagged as EMPTY.
This works because later picture numbers are stored, by virtue of the allocation scheme, in the buffers that are considered later.
TEMPORAL REFERENCE tokens in H261 cause a buffer's picture number to be modified if skipped pictures in the input stream are indicated. TEMPORAL REFERENCE tokens in MPEG have no effect .
A FLUSH token causes the input to stall until every buffer is either EMPTY or has been allocated as the display buffer; presentation number and picture number are then reset and a new sequence can commence.
All data is input to the buffer manager from the input fifo, bm_front . This transfer takes place via a two-wire interface, the data being 8 bits wide plus an extension bit.
All data arriving at the buffer manager is guaranteed to be complete tokens, a necessity for the continued processing of presentation numbers and display buffer requests in the event of significant gaps in the data upstream.
Tokens (8 bit data, 1 bit extension) are transferred to the write address generator via a two-wire interface. The arrival buffer index is also transferred on the same interface, so that the correct index is available for address generation at the same time as the PICTURE_START token arrives at waddrgen.
The interface to the read address generator comprises two separate two-wire interfaces which can be considered to act as 'request' and 'acknowledge' signals 2~~~~~~
respectively - single wires are not adequate, however, because of the two two-wire-based state machines at either end.
The sequence of events normally assaciated with the dispaddr interface is as follows: dispaddr invokes a request, in response to a vsync from the display device, by asserting the drq-valid input to the buffer manager; when the buffer manager reaches an appropriate point in its state machine it will accept the request and go about allocating a buffer to be displayed; the lisp valid wire is then asserted, the buffer index is transferred, and this will normally be accepted immediately by dispaddr. There is an additional wire associated with this last two-wire interface (rst_fld} which indicates that the field number associated with the current index must be reset regardless of the previous field number.
The buffer manager block uses four bits of microprocessor address space, together with the 8-bit data bus and read and write strobes. There are two select signals, one indicating user-accessible locations and the other indicating test locations which should not require access under normal operation conditions.
The buffer manager is capable of producing two different events: index found and late arrival. The first of these is asserted when a picture arrives whose PICTURE_START
extension byte (picture index} matches the value written into the BU BM TARGET-IX register at setup. The second event occurs when a display buffer is allocated whose picture number is less than the current presentation number, i.e. the processing in the system pipeline up to the buffer manager has not ~.~~~3~I
managed to keep up with the presentation requirements.
Picture clock is the clock signal for the presentation number counter and is either generated on-chip or taken from an external source (normally the display system).
The buffer manager accepts both of these signals and selects one based on the value of pclk_ext (a bit in the buffer manager's control register). This signal also acts as the enable for the pad picoutpad, so that if the Image Formatter is generating its own picture clock this signal is also IO available as an output from the chip.
There are 19 states in the buffer manager's state machine. These interact as shown in Figure 2. The reset state is PRESO, with flags set to zero such that the main loop is circulated initially.
The rnain loop of the state machine comprises the states shown in Figure 3 (highlighted in the main diagram -Figure 2). States PRESO and PRES1 are concerned with detecting a picture clock via the signal presflg. Two cycles are allowed for the tests involved since they all depend on the value of 20 rdytst . If a presentation flag is detected, all of the buffers are examined for possible 'readiness', otherwise the state machine just advances to state DRQ. Each cycle around the PRESO-PRES1 loop examines a different buffer, checking for full and ready conditions: if these are met, the previous ready buffer (if one exists) is cleared, the new ready buffer is allocated and its status is updated. This process is repeated until all buffers have been examined (index = - max buf) and the state then advances. A buffer is deemed to be 2.~~~~ ~~
ready for display when any of the following is true:
(pic num>pres-num)&&((pic_num - pres num)> = 128}
or (pic num<pres num)&&({pres num - pic num)< = 128) or pic num = - pres num State DRQ checks for a request for a display buffer (drq_valid_reg && disp acc_reg). If there is no request the state advances {normally to state TOKEN - more on this later), otherwise a display buffer index is issued as follows: if there is no ready buffer, the previous index is re-issued or, if there is no previous display buffer, a null index (zero) is issued; if a buffer is ready for display, its index is issued and its state is updated - if necessary the previous display buffer is cleared. The state machine then advances as before.
State TOKEN is the usual option for completing the main loop: if there is valid input and the output is not stalled, tokens are examined for strategic values (described in later sections}, otherwise control returns to state PRESO.
Control only diverges from the main loop when certain conditians are met. These are described in the following sections.
If during the PRESO-PRES1 loop a buffer is determined to be ready, any previous ready buffer needs to be vacated because only one buffer can be designated ready at any time. State VACATE RDY clears the old ready buffer by setting its state to UACANT, and it resets the buffer index to 1 so that when control returns to the PRESO state, all buffers will 2~4~3~I
be tested for readiness. The reason for this is that the index is by now pointing at the previous ready buffer (for the purpose of clearing it) and there is no record of our intended new ready buffer index - it is necessary therefore to re-test all of the buffers.
Allocation of the display buffer index takes place either directly from state DRQ (state USE RDY) or via state VACATE DISP which clears the old display buffer state. The chosen display buffer is flagged as IN USE, the value of rdy_buf is set to zero, and the index is reset to 1 to return to state DRQ. lisp buf is given the required index and the two-wire interface wires (disp_valid and drq_acc) are controlled accordingly. Control returns to state DRQ only so that the decision between states TOKEN, FLUSH and ALLOC does not need to be made in state USE RDY.
On receipt of a PICTURE_END token control transfers from state TOKEN to state PICTURE_END where, if the index is not already pointing at the current arrival buffer, it is set to point there so that its status can be updated. Assuming both out acc_reg and en_full are true, status can be updated as described below; if not, control remains in state PICTURE_END until they are both true. The en_full signal is supplied by the write address generator to indicate that the swing buffer has swung, i.e. the last block has been successfully written and it is therefore safe to update the buffer status.
The just-completed buffer is tested for readiness and given the status either FULL or READY depending on the 2.~4~~~~
result of the test. If it is ready, rdy_buf is given the value of its index and the set_Ia_ev signal (late arrival event) is set high (indicating that the expected display has got ahead in time of the decoding). The new value of arr buf now becomes zero, and, if the previous ready buffer needs its status clearing, the index is set to point there and control moves to state VACATE RDY; otherwise index is reset to 1 and control returns to the start of the main loop.
When a PICTURE START token arrives during state TOKEN, the flag from_ps is set, causing the basic state machine loop to be changed such that state ALLOC is visited instead of state TOKEN. State ALLOC is concerned with allocating an arrival buffer (into which the arriving picture data can be written), and cycles through the buffers until it finds one whose status is VACANT. A buffer will only be allocated if out acc_reg is high, since it is output on the data two-wire interface, so cycling around the loop will continue until this is the case. Once a suitable arrival buffer has been found, the index is allocated to arr buf and its status is flagged as IN USE. Index is set to 1, the flag from_ps is reset, and the state is set to advance to NEW EXP TR. A check is made on the picture's index (contained in the word following the PICTURE_START) to determine if it the same as targ_ix (the target index specified at setup) and, if so, set_if_ev (index found event) is set high.
The three states NEW EXP_TR, SET ARR_IX and NEW P1C NUM set up the new expected temporal reference and picture number for the incoming data - the middle state dust sets the index to be arr_buf so that the correct picture number register is updated (note that this_pnum is also updated). Control then goes to state OUTPUT TAIL which outputs data (assuming favourable two-wire interface signals) until a low extension is encountered, at which point the main loop is re-started. This means that whole data blocks (64 items) are output, within which there are no tests for presentation flag or display request.
A FLUSH token in the data st ream indicates that sequence information (presentation number, picture number, rst_fld) should be reset. This can only happen when all of the data leading up to the FLUSH has been correctly processed and so it is necessary, having received a FLUSH, to monitor the status of all of the buffers until it is certain that all frames have been handed over to the display, i.e. all but one of the buffers have status EriPTY, and the other is IN USE (as the display buffer). At that point a 'new sequence' can safely be started.
When a FLUSH token is detected in state TOKEN, the flag from_fl is set, causing the basic state machine loop to be changed such that state FLUSH is visited instead of state TOKEN. State FLUSH examines the status of each buffer in turn, waiting for it to become VACANT or IN USE as display. The state machine simply cycles around the loop until the condition is true, then increments its index and repeats the process until all of the buffers have been visited. When the last buffer fulf ils the condit ion, present at ion number, picture number and all of the temporal reference registers ~~~CI~
assume their reset values; rst_fld is set to 1. The flag from fl is reset and the normal main loop operation is resumed.
When a TEMPORAL REFERENCE token is encountered, a check is made on the H261 bit and, if set, the four states TEMP REFO to TEMP REF3 are visited. These perform the following operations:
TEMP REFO: temp_ref = in data_reg;
TErIP REF1: delta = temp_ref - exp_tr; index =
ZO arr buf;
TEMP REF2: exp_tr = delta + exp tr;
TEMP REF3: pic num[i] - this_pnum + delta;index = Z;
State TOKEN passes control to state OUTPUT TAIL in all cases other than those outlined above. Control remains here until the last word of the token is encountered (in_extn_reg is low) and the main loop is then re-entered.
The requirement to repeatedly check for the 'asynchronous' timing events of picture clock and display buffer request, and the necessary to have the buffer manager 20 input stalled during these checks, means that when there is a continuous supply of data at the input to the buffer manager there will be a restriction on the data rate through the buffer manager. A typical sequence of states may be PRESO, PRES1, DRQ, TOKEN, OUTPUT TAIL, each, with the exception of OUTPUT TAIL, lasting one cycle. This means that for each block of 64 data items, there will be an overhead of 3 cycles during which the input is stalled (during states PRESO, PRES1 and DRg) thereby slowing the write rate by 3/64 or approximately ~~ 4 ~~ ~1 5~. This number may occasionally increase to up to 13 cycles overhead when auxiliary branches of the state machine are executed under worst-case conditions. Note that such large overheads will only apply on a once-per-frame basis.
Presentation number free-runs during upi accesses;
if presentation number is required to be the same when access is relinquished as it was when access was gained, this can be effected by reading presentation number after access is granted, and writing it back just before it is relinquished.
Note that this is asynchronous, so it may be necessary to repeat the accesses several times to be sure they are effective.
The write address generator 10 receives tokens from the buffer manager 30 and detects the arrival of each new DATA
token. As each arrives, it calculates a new address for the DRAM interface 50 in which to store the arriving block. The raw data is then passed to the DRAM interface 50 where it is written in to a swing buffer. Note that DRAM addresses are block addresses, and pictures in the DRAM are organised as rasters of blocks. Incoming picture data, however, is organised as sequences of macroblocks, so the address generation algorithm must take account of this.

Claims (19)

1. An image formatter for processing encoded video data comprising:
an input element for receiving encoded data representing video frames, said data arriving as a sequence of tokens at an encoded frame rate for output or display at a display frame rate;
a memory defining at least three buffers for storage of the encoded data, wherein said received data is initially stored in a first said buffer;
a write address generator for generating addresses for data being stored in said first buffer;
a read address generator for generating addresses for reading data stored in said first buffer;
a presentation number counter;
an output interface linked to said read address generator that produces output data at said display frame rate; and a buffer manager responsive to control information in said tokens, to said encoded frame rate, and to said display frame rate, said buffer manager dynamically allocating and deallocating said at least three buffers as arrival buffers for reference by said write address generator, and as display buffers for reference by said read address generator, said buffer manager clearing said buffers for occupation by subsequently arriving data, and maintaining status information of said buffers wherein said status information comprises a state VACANT, wherein a said buffer is available, a state INUSE, wherein a said buffer can be referenced by said write address generator, a state FULL, wherein a said buffer is occupied by data, and a state READY wherein a said buffer is reallocated as a display buffer;
wherein responsive to said presentation number counter and a current picture number contained in the encoded data said buffer manager asserts a late arrival signal indicating that a buffer in said state READY is not in synchronization with said display frame rate;
a state machine for controlling said buffer manager, said state machine transitioning among a plurality of states, including:
a first transition from a first state PRES0, to a second state PRES1, wherein said status information of said buffers are evaluated;
a second transition from said state PRES1 to a third state DRQ wherein a pending request for said display buffers is evaluated; and a third transition from said stage DRQ to a fourth state TOKEN, wherein tokens of received data are examined; whereby a status of said arrival buffer can be updated; and a plurality of 2-wire interfaces each comprising: a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready, wherein said buffer manager communicates with said read address generator, and with said write address generator via said 2-wire interfaces.
2. The image formatter according to claim 1, wherein said tokens each comprise a plurality of data words, said data words each including an extension bit which indicates a presence of additional words in said token.
3. The image formatter according to claim 1, wherein said plurality of states of said state machine further comprises:
a fifth state VACATERDY, wherein a ready state of a said buffer is cleared.
4. The image formatter according to claim 1, wherein said plurality of states of said state machine further comprises:
a sixth state VACATESISP, wherein a state of said display buffer is cleared.
5. The image formatter according to claim 3, wherein said plurality of states of said state machine further comprises a seventh state USERDY, wherein allocation of a display buffer index occurs.
6. The image formatter according to claim 1, wherein said plurality of states of said state machine further comprises an eighth state PICTUREEND, wherein an index is set to a current arrival buffer.
7. The image formatter according to claim 1, wherein said plurality of states of said state machine further comprises a ninth state ALLOC, wherein an arrival buffer for new data is allocated.
8. The image formatter according to claim 2, wherein said plurality of states of said state machine further comprises a tenth state NEWEXP, an eleventh state NEWPICNUM, wherein an expected temperate reference and picture number are set up for incoming data.
9. The image formatter according to claim 7, wherein said plurality of states of said state machine further comprises a twelfth state SETARRIX, wherein a picture number register is updated.
10. The image formatter according to claim 1, wherein said plurality of states of said state machine further comprises a thirteenth state OUTPUTTAIL, wherein data is output from the formatter.
11. The image formatter according to claim 1, wherein said plurality of states of said state machine further comprises a fourteenth state FLUSH, wherein said buffers become vacant or enter a state of use for display.
12. An image formatter for processing encoded video data comprising:
an input element for receiving encoded data having a frame rate and arrival rate;
a memory defining at least three buffers for storage of the encoded data, one of said buffers being a display buffer, and another of Said buffers being an arrival buffer;
a write address generator for generating write addresses for data being stored thereat in said memory;
a read address generator for generating read addresses for reading data stored thereat in said memory;
an output interface linked to said read address generator that produces decoded data at a display rate; and a buffer manager responsive to said arrival rate, said display rate, and said frame rate for allocating said buffers to said write address generator and said read address generator, wherein said buffers are allocated to said write address generator in response to a timing regime.
13. The image formatter according to claim 12, wherein said read address generator and said buffer manager are connected by a plurality of two-wire interfaces, wherein said two-wire interfaces each comprise: a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready.
14. The image formatter according to claim 12, wherein said input element and said buffer manager are connected by a two-wire interface, wherein said two-wire interface comprises:
a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready.
15. The image formatter according to claim 12, wherein said write address generator and said buffer manager are connected by a two-wire interface, wherein said two-wire interface comprises: a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready.
16. The image formatter according to claim 12, further comprising a setup register having a picture index stored therein, wherein said buffer manager asserts a first signal when received encoded data represents a picture having an index corresponding to said picture index, and wherein said buffer manager asserts a second signal when said display buffer has a picture number that is less than a current presentation number.
17. The image formatter according to claim 12, wherein said timing regime comprises an arrival rate of video data.
18. The image formatter according to claim 12. wherein said timing regime comprises a display rate of video data.
19. The image formatter according to claim 12, wherein said timing regime comprises a presentation rate of an encoded video sequence.
CA002145361A 1994-03-24 1995-03-23 Buffer manager Expired - Lifetime CA2145361C (en)

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GB9405914A GB9405914D0 (en) 1994-03-24 1994-03-24 Video decompression
GB9503964A GB2287808B (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with ram
GB9405914.4 1995-02-28
GB9503964.0 1995-02-28

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US5956741A (en) 1999-09-21
CA2145363A1 (en) 1995-09-25
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CA2145361A1 (en) 1995-09-25
CA2145363C (en) 1999-07-13
US5724537A (en) 1998-03-03

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