CA2202517A1 - M & a for dynamically determining and managing connection topology of an hierarchical serial bus assembly - Google Patents

M & a for dynamically determining and managing connection topology of an hierarchical serial bus assembly

Info

Publication number
CA2202517A1
CA2202517A1 CA002202517A CA2202517A CA2202517A1 CA 2202517 A1 CA2202517 A1 CA 2202517A1 CA 002202517 A CA002202517 A CA 002202517A CA 2202517 A CA2202517 A CA 2202517A CA 2202517 A1 CA2202517 A1 CA 2202517A1
Authority
CA
Canada
Prior art keywords
serial bus
bus
elements
assembly
hierarchical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002202517A
Other languages
French (fr)
Other versions
CA2202517C (en
Inventor
Shaun Knoll
Jeff Charles Morriss
Shelagh Callahan
Ajay V. Bhatt
Sudarshan Bala Cadambi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Shaun Knoll
Jeff Charles Morriss
Shelagh Callahan
Ajay V. Bhatt
Sudarshan Bala Cadambi
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shaun Knoll, Jeff Charles Morriss, Shelagh Callahan, Ajay V. Bhatt, Sudarshan Bala Cadambi, Intel Corporation filed Critical Shaun Knoll
Publication of CA2202517A1 publication Critical patent/CA2202517A1/en
Application granted granted Critical
Publication of CA2202517C publication Critical patent/CA2202517C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40058—Isochronous transmission
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40078—Bus configuration

Abstract

Circuitry and complementary logic are provided to a bus controller (14), a number of 1:n bus signal distributor (18), and a number of bus interfaces (22) of a hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support a hierarchical view of the serial bus elements (16), logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e. the system unit and the interconnected peripheral, as well as assignment of addresses to the serial bus elements and the functions, at power on, reset, and during operation when serial bus elements are hot attached to or detached from the serial bus assembly.
CA002202517A 1994-10-31 1995-10-31 M & a for dynamically determining and managing connection topology of an hierarchical serial bus assembly Expired - Fee Related CA2202517C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/332,375 US5623610A (en) 1994-10-31 1994-10-31 System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset
US08/332,375 1994-10-31
PCT/US1995/014242 WO1996013769A1 (en) 1994-10-31 1995-10-31 M & a for dynamically determining and managing connection topology of a hierarchical serial bus assembly

Publications (2)

Publication Number Publication Date
CA2202517A1 true CA2202517A1 (en) 1996-05-09
CA2202517C CA2202517C (en) 2003-12-30

Family

ID=23297947

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002202517A Expired - Fee Related CA2202517C (en) 1994-10-31 1995-10-31 M & a for dynamically determining and managing connection topology of an hierarchical serial bus assembly

Country Status (5)

Country Link
US (1) US5623610A (en)
EP (1) EP0789867B1 (en)
AU (1) AU3972995A (en)
CA (1) CA2202517C (en)
WO (1) WO1996013769A1 (en)

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Also Published As

Publication number Publication date
EP0789867A4 (en) 1999-10-27
AU3972995A (en) 1996-05-23
EP0789867B1 (en) 2011-12-07
WO1996013769A1 (en) 1996-05-09
EP0789867A1 (en) 1997-08-20
CA2202517C (en) 2003-12-30
US5623610A (en) 1997-04-22

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