CA2329100A1 - Phase and amplitude detector and method of determining errors - Google Patents

Abstract

This invention relates to a phase and amplitude detector (160) required to identify small signal errors in a signal envelope having a large dynamic range, especially in the content of linearization of a power amplifier (122) arrangement employing a pre-distortion technique. A vector generator (300, 352, 372) responsive to a reference signal R (110) produces a frame of reference vectors R1-Rn (274-280) generated by a combination of the reference signal R (110) with first A (270) and P(272) offset vectors that provide an amplitude and phase displacement of the reference signal R (110). A signal combiner (290-296, 360-366, 390 396) is arranged to generate difference vectors E1-En by combining the frame of reference vectors R1-Rn (274-280) and the feedback signal F (124, 150), with the difference vectors E1-En expressing the phase (p, 254) and the gain (a, 252) error terms relative to the reference signal R
(110) and the first A (270) and second P (272) offset vectors. An error signal detector, (330-336) responsive to the difference vectors E1-En and arranged to provide a measure of the phase (p1 254) and the gain (a, 252) error terms, provides signal amplitudes that can be combined to generate error signals (182 (Y), 184. X)).
The error signals take the general form:
X = P1 - P2 - P3 + P4 = -8PpR:
Y = P1 + P2 - P3 - P4 = -8AaR

Description

-PHASE AND AMPLITUDL DETECTOR
AND METHOD OF DETERMINING ERRORS
Field Of The Invention This invention relates, in gr~rrdrdl, tc~ a plrastr arrcl c~rrylitude detector and a method of determining errors, and is particularly, but not exclusively, applicable to the measuromont of phase and amplitude erroru for compensation purposes in the linearisation of power amplifiers.
Background Of The Invention First and second generation cellular systems have historically used forms of signal modulation which are either constant ~nvelope (e.g. Gaussian Minimum Shift Keying (GMSK) ~n the global system for mobile communication (GSM) or which result in relatively low levels of amplitude modulation. The linearity of thA
high power amplifiem used fur Suc;Il 5y5ic~rrlS las lileletUre rTUI been an important technical issue. Indeed, for constant ~nvelope systems, it is standard practice to operate amplifier's either close to or actually in compression in order to maximise power efficiency. That is to say, the amplifiers are intentionally PmplnyPd in a nnn-linaar mode.
Third qener-ation cellular systems, i7owe~ver, lypir;ally usc~ IirTC~dr Spread-spectrum modulation schemes with a large amount of amplitude modulation on the signal envolopo. When passed through a high power amplifier, the output is typically distorted in amplitude and phase by the inherent non-linearity of the amplifier.
The amplitud~ and phase distorkivn effects are commonly referred to as AM-AM
conversion and AM-PM conversion, respectively_ Both distortion PffPCas are principally a function of the amplitude envelope of the Input sl~nal and are insensitive to the input phase envelope.
In Code Divir;ion Multiple /lccocc (CDMA) modulation 3chcmcs, quadrature amplitude modulation (QAM) and systems employing similar linear transmission SS0 ib00 ' ~nHd 0bb82E2E T 9 T 006 nl dfln~n MHO d I ~ln~aHH LIn~~ Z T : 9 T
00 . ~3r3 02 _2_ mechanisms, a plurality of signals are simultaneously amplified and transmitted which cause the generation of a large amplitude component in the signal envnlnpP. Untortunately, when a large amplitude component is applied to a linear amplifier, its non-linear characteristics will tend to produce Interm~dnlation products that reduces sic~nnl quality and can cause spectral spillage outside a particular licensed spectrum. Intermodulation products must, therefore, k~e controlled, but such control, as will be appreciated, should not be at the expense of reducing wanted signal strength.
Intermodulatlon products and associated distortion can ha reduced by negativ~
feedback of the disl~riiuo cUrry~rmnts, pre-distortion of the signal to be amplified to cancel the amplifier generated distortion, or by sdparrdtiry the distortion oomponent~ from the amplifier output and feeding forward the distortion components to cancel the distortion of the amplifier output signal.
In a power amplifier, where Ilnearlsatlon Is performed by correction as a function of signal envelops (dither via feedback or via pre-distortion), there Is a need for nn accurate amplitude and phase comparator that can operate over the full dynamic rango of the input signal. In addition, it is desirable for the detector to have a high processing speed to cope with wideband spread spectrum signals.
In other wnrrf~, whilst maintaining low cost and high efficiency design, power r~rnplifiers require ancillary error detection circuitry that can identify ancf a~lr~w correction for rwrrlinearity. Indeed, such correction circuitry is critically dependent upon an ability to measure accurately the phase and ampliludc~ of both the input and output ~ignal~ to tho power amplifier, whioh signals generally (and, in the exemplary case of CDMA-based Eyetem~, inherently) have signal Qnvelopes with associated large dynamic ranges (typically .-20 decibels). In fact, with this ancillary error dPtaction circuitry, there Is a requirem~nt to measure srndll error components (typically of the order of a few tenths of a decihal) in amplitude and phase with respect to relatively large wanted signal excurslons/envelopes.
SS0 X500 ~ 3nHd 0bb82~2E T 9 T 006 n1 d~n~ln ~1H~ d I mn~~IHH LIn~I~ Z T : 9 T
00 . 93r3 02 Typical amplifier architecturoo inoorpomtc a plow fcodback loop to track out unit-to-unit variations, thermal drift and long-term component dr9ft. The slow fe~dbaok loop eases amplifier SAt-rrp and allows a fast feedback or a pre-distortion mtrofrarri5rtt lv operate only on the amplifier induced, envelope-dependant distortion components. hiowever, ournverrliuoal phase and amplitude deteCtorS
Of ~ufficiont performanoe (associated with linearisation and specifically phase and amplitude error correction in a fast loop) havE proven to be extremely difficult to set-up and to replicate on a commercial basis. In any ~vent, it is desirable that a common dptpca~r mechanism is used to close both th~ fast error loop and th~
(somewhat auxiliary) slow feedbacK loop to ensure that both loops convPrc~ra on a single phase/amplitude state.
Summ~rv Of The Invention In accordance with a first aspect of thc> present invention there is prcwided a detector operable to provide at least one error Signal d55r,ciated with at least one of a pha9e error term and an gain error term between a r~ference signs) R anci r~
feedback signal _F, the deteotor characterived by: a vector gonerator responsiv~
to the reference signal $, the vector generator producing a frame of reforenoe vectors $,-$r, generated by a comhinatinn of the retPrence signal R with first and second P offsal veatvrs that provide an amplitude and phase displacement of the reference signal R; a signal combincr drr~rrTC~ad tv generate difference vectors ~,-~, by oombining the frame of reference vectors $~-R and the feedback signal F, the difference vectors E,~~E, expressing the phase (p) and the gain (a) error terms relative to the reference signal $ and the first A and vcoond P offset vectors; and a.n error signal detector responsive to the difference vectors E_,-~~ and arranged to provide a measure of the phase (p) and the gain (a) error terms required to support subsequer'rl gerTerdtivn of the at least one error slc~nal.
In a pr~ferred embodiment, a combinatory circuitry coupled to the error signal detector is arranged to rec~ive output vlgnalv from the error signal detector, the combinatory circr.r'rtry configured tv isolate the phas~ error term and the gain Ss0 X900 ' 3nHd 0bb82~2sr T 9 T 006 n1 dfln~In MHO d I Mn~~IHH LIn~I~ Z T : g T 00 . ~~Q 02 error term in terms of the first 4 anti sPCnnd P offswt vwctnrs and the reference vr~rrier vector $.
Proforably, the oombinatory oirvuitry generates the at least one error signal through isolation of the phase error term from the gain error term, the at toast one error term satisfying the general form:
X = N, - N~ - N3 + N4 =- -8~PE:
Y=P~+P2-Ps-Pa._-BeaB
where a is the gain error ldrrrr, ~ i5 the ptTe~a error term and P" are output amplitudes from the signal ~rror detector for corresponding difference vectors E~-E ,.
In another aspect of the present invention thPrP is pmvici~ari a phase and amplitude comparator operable to provide signals relatlnp to the difference in phase and amplitud~ between a reference signal $ and a feedback sic~oal R, wherein the comparator comprises vector generating means to produce four reference v~ctors $~-R, which are related tv thv input roferoncv vootor Signal R
by the addition of turther vectors ~ (270) and tP (272) which are, respectively, in phase and in quadratnrP with $ snnh that:
$~ _$+~+,~;
~_$+~-~~
~_$_~_~~
$a~$-A i P;
wherein the four reference vectors ~R,-R (274-280) are added to four samples of the fepdhaak signal ~ to prodcrce four corresponding error v~ctors ~~-E4 whereby the vectors ~,-~,a can be used to generate phase (X,184) and amplitude (Y,182) comparative signals .
In another aspect of tho prc~cnt invention there is provided an amplifi~r circuit comprising: an input coupled to receive, in use, a refercnee :.ignal $; phaso and gain mor~ulators coupled to the input; an amplifier coupled to the phase and gain modulators; a first directional cAlylAr rn~ylPd to the input and arranged to SS0iL00' 3hHd 0bb82~2E T 9 T 006 01 drl0~ln ~1H1 d I ~10'I?JHH LIf1?~d 8 T : 9 T 00 . 13Q 02 _5_ sample the reference signal $; a second directional coupler cauplAri to the amplifi~sr and ar'r'ar'Tgc~~i Lu 5arylc~ dT1 arrIpIiFlc~d version of the reference signal R , thereby to provide a feedback signal F; and a detector accoirlinq to the firbl aspECt, the detector coupled to the fiat diroetional coupler and the second directional coupler to r~ceive, in us~, the ref~rence signal R and the feedback signal F; whr~rr~in the phase (118) and gain (116) modulators are arranged to receive phase and gain corrections signals derived from the at Ir?ast cane error signal (182 (Y), 184 X)) germrr~lad by the detector.
In a preferred embodiment the amplifier circuit further comprises an adaptive pre-distorter coupled to receive the at least one error signal from the detoctor, the adaptive pre-distorter further coupled to the phase and gain modulators, the adaptive pre-distorter arranged to determine the gain and phase error c~rrACaion signals with respect to a set of look-up values, thereby to linearlse pertormanCe of the amplifier.
Preferably, a slow fa~dback loop containing a phas~/amplitude equalizer having a second amplitude modulator and a second phase modulator coupled to th~
amplifier, the phase/amplitude equalizer further containing baseband processincd elements coupled to the date~~tor and arrar~gad to r~c;eive, irr use, the at least one error signal as a control signal for the baseband processing elements, whereby the phaEO/amplitudo equalizer io arranged to track out circuit variations arising from at I~ast on~ of unit-to-unit variations, th~rmal drift and long-torn cc~mponant draft through amplitude and phase control of, respectively, the second amplltudP modulator and the second phew modulator.
The phase amplitude equalizer may further include: a quadrature to amplitude/phase (R, e) domain converter coupled to receive the at least one error signal and arranged to provide distinct phase angle 0 and amplitude R
components; a phase integrator coupled to the quadrature to amplitude/phase (R, 0) domain converter and arranged to receive, in use, the phase angle a component, thereby to provide a first time-integrated signal having a wrap-S60 X800 ' 9nHd abb82~2~ T 9 T 006 n1 dfln~n MHO d I MO~~IHH LIn~I~ 8 T : 9 T
00 . X34 a2 around phase correction function: an amplitude integrator coupled tv the quadrature to amplitude/ptiase (R. 8) domain converter and arranged to recr~ive, irT use. the phase angle A component. thereby to provide a second time-integrated sigr'rdl, drrd arr arrrNlilucfd/NlrdSd (R, 8) durrrairr lu yudr~rdlurr~ currverter a coupled to the phase integrator and the amplitude intec~ratvr and arranged, in use, to combine the first time-integrated signal and the second time-integrated signal to exereice control of the glow feedback loop.
1 he amplitier circuit may have at least one delay line operable to compensate for t 0 any delay skew Induced by processing delay In a correction path between the reference signal and correction signals.
The detector, the phase and amplitude comparator or the amplifier circuit may be incorporated within a base station or a subscriber unit of a c~Ilular 15 communication system or other signaling scheme rpquirinc~ linear pprtormanc:w.
In a further aspect of the present invention there is provided a method c~f detecting at least one of a phase error terra and an amplitude error term between a reference signal R and a feedback signal F and generating a 20 corresponding error signal in response to the least one of the phase error term and the amplitude error term, the method characterised by: producing a frame of refrrrence vectors ~,-t~" generated by a combination of the reference signal $
with first A_ and second _P offset vectors that provide an amplitude and phase displacement of the reference signal R; generating difference vectors Ei-E by 25 combining the frame of reference veetor'~ R~~~R, and the feedback Signal F, the difference vectors ~~-~,, expressing the phase and the amplitude error terms relative to the reference signal R and the first I~ and second P offset vectors; and providing a measure of the phase and the amplitude error terms in response to tire diffdrer'rce vec:lur5 E~-~ , llm phr~5e r~rrd the amplitude er'rur lerrrm required tv 30 support subsequent generation of the at least one error signal.
In a particular embodiment, the method further comprises: generating the at SS01600 ' 3nHd 0bfir82~2~ T 9 T 006 O1 dn0?Jn MH1 d I M0121HH IaIQ~I~ 8 T : 9 T 00 < '134 02 -T
least one error signs through isolation of the phase error term from the amplitude error term, the at least one error term Eatiefying the gcnoral form:
X - Pi - P2 - P~ * P.~ - .8_PpR;
Y - P~ + Pa - P3 - P.r - -tiAaR
where a is ttte amplitude error term, p Is the phase error term and P" arcs natput amplitudes from the signal error detector for corraspurrdirrc~ difference vectors E,-E , The detector of the present invention and its corresponding method of operation may be employed within, fir example, a cellular base station or the lik~ to improvd lirrc~arily.
The present invention therefore provides an improved phase and antplilude comparator particularly, but not exclusively, woeful in an amplifier linearisation process. In overview, the preferred embodiments of the pros~nt invention operate to isolate small error terms from large signal terms and then to caus~
corrective opemtivr~ urT the small error terms only. In accordance with the prcf~rred embodiments of the present invention, an improveri linear power amplifier i: beneficially provided in which linearisation is performed by corrbc;tion to the signal envelope. Ind~~d, in contrast with prior art systoms, the present invention advantageously overcomes two effects exhibited by conventional phase and amplitude Comparator techniques, namely an ability to resolve accurately small differences between relatively large signals with high dynamic range and, second, an ability to reduce dynamic range requirements of detectors employed to ease their associated tracking requirements.
While the detector of the preferred embodiment is optimized to resolve small signal error/offsets in large dynamic ranges, the detector can, beneficially, otill provide useful output even when offsets are large. C.',nnsectuently, the present invention can be used irr d c~rnplementary sense within a slow feedback loop.
The detector of the proferred embodiment is able to operate sufficiently fast to SS0~0 T 0' 3nHd 8bh82E2~ T 9 T 006 n1 dfln~In ~1H~ d I ~ln~~IHH LIOi:ld 6 T :
9 T 00. 93rI 02 . _. ~ .._ . . .... _ ...... ~.w..."...n....~ _,~....-...
~....~.."~,~,.,~...._..~.",".~., "~.~...".~.,..~,".."~.,~..,.~.~ ~,~
.~........~.,....~..

.6.
cope with wideband spread spectnrm signals and, beneficially, has a generally simplified and robust circuit design.
Brief Descrietion Of The Drawings In order that the present invention can be more fully understood and to show how the same may be carried into effect, reference shall now be made, by way of example only, to the figures in the accompanying drawing sheets, in which:
Fir~ure 1 shows an crnbudirnerrl of d lirrdar Nuwc~r drrrplifier arrangement able to support the underlying concepts and principles of the present invention;
Figure 2 shows, in detail, a conventional architecture of a gain and phase rarrnr clatACtor suitahle for use in Figure 7 ;
Figure 3 shows an alternative linear power amplifier arrangement able tn support tl-re underlying r:orrc;epts drrd prirrciple~5 of the present invention:
Figure 4 shows an analysis of signdls input to a linear power amplifier and phaee comparator of Figure 1;
Figures 5a and 5b show the construction of reference vectors Ri-R4 and thAir intar-rAlationship with a main reterence vector R of Figure d.
Figures 6a and 6b diagrammatically Illustrate how difference vectors ~,-,~~
are determined for use in the linear power amplifier arrangement of Figures 1 and 3;
Figure 7 shows an application of the difference vectorE E,-~4 of Figures 6a and 6b;
Figures Sa and 8b show, in accnrrlanca with the principles of the present invention, plots of variations In amplitude detector output x and phase detector output Y, rc~speclively, ds functions of phase error for different amplitude errors;
Figures 0 and 10 illustrate alternative mechanism for generating reference vectors $, . R4;
3t7 Figure 11 shows a schematic block diagram of the phase-amplitude comparator of Figures 1 and 3;
Figure 12 shows a slow feedback loop of Figure 1;
SS0 ~ T T 0 ' 3nHd 0bfi82~2ar T 9 T 006 nl dfl0~l~ ~1H~ d I mn~~IHH I~In~ld 6 T : 9 1 00 . ~3rI 02 FPUSOOS9s -.9-Figure 13 shows a schematic block diagram of an IQ modulator block used in Figures 1 and 3;
Figure 14 chowa a preferred functional configuration of a stow loop control circuit for Figure 3;
l-igrrrp 15 show graphical representations of variations in phase, amplitude, calculated phase offset and amplitude offset of a pertect power detector arranged to support ~ implementation of the preferred embodiment of the present invention;
Figure 16 shows the phase; amplitude; calculated phase offset; and calculated amplitude offset for a voltage-law detector arranged to support implemPntatron of the preterred embodiment of the present invention;
Figure 17 shows a preferred flow chart of an aidAd long acctuisitton scheme ire nuc;cr~idnc:c~ with the present invention.
Detailod Do~criation Of The Preferred Embodiments There will now be described, by way of example only, at Ipast a best mode contemplated by the invdnlurs ~~r carrying out the invention. In the following description, numerous specific details are set out in order to provide a curnplete undErst3nding of the prESent invention. It will be apparent, however, to those skilled in the art that the present invention may be put into practice with variations of the specitic.
Figure 1 5trcrwa a block diagram of a linear power amplifier 100 constructed In accordance with a preferred embodiment of the present invention, In use, an RF
input Signal 110 is applied to a high power amplifier 122 via a directional coupler 112, a first delay line 11 ~L, an amplitude modulator 116 and a pha~ce modulator ~ i 8. An output of the amplifier 122 provides an amplified output signal 128 which is sampled by a riirr~Minnal nrnrriAr 1z6. I he sampled HF output from the directional coupler 112 is applied to a power splltter 132, the outputs of which are connected to dry drmdlo~re cielectvr 134 and a second delay line 140. The output of the envelope detector is connected to an adaptive pre-distorter subsyatom 170. The adaptive pre-distorter subsystem 170 generates two SS0 iz T 0 ' 3nNd 0bb82~2E T 9 T 006 nl drln~ln ~1H1 d I m0-121HH 1.10214 6 T
: 9 T 00 . 133 02 outputE: a gain correction signal 192 which is eonnooted to the control port of first amplitude modulator 116; and a phase correction signal 194 which is connpMPd to the cnntrnl nnrt of rhasP mod~rlator 118.
3 The adaptive pre-distorter 170 generates fhe arnplilu~id am plrd5e correction signals 192, 194 as functions of input 136 in such a way that the input signal, delayod by 114 and modulated by modulators 116, 118, on passing through the high power amplifier 122, emerges with lower distortion than if no pr~-distortion m.WsystRm had been employed. The purpose of the adaptive pre-distorter's gain 1 o and phase transfer functions Is therefore to cancel the gain and phase distortion produced in the power amplifier 122. The purpose of delay line 114 is to compensate for any delay skew between the signal 110 modulation and the correction signals 182, 1 A4 induced by procc~~ing delay in the oorreetion path 112, 130, 134, 170.
A gain drrd Nlrdse drrc~r deleclion subsystem 160 requires, as inputs, a sample 142 of the input signal 110 and a sample 154 of the output signal 128, normaliocd to the Same Signal level and aligned in time. Output sample 154 is normalised to the same level ae aamplo 142 by attenuating the coupled output of ~U coupler 126 in attenuator 152_ Input sample 142 is time-aligned with 1 S4 by delaying one output of powcar splittAr 132 in delay line 740.
In order to compensate for changes In tl-re I-righ pr~wer a,rrTplifier 122 gain and phase di3tortion characteristic, for example due to temperature or channel frequency changes, the pre~distorter 7 70 vperatee on an adaptive ba~i~. That is, the pre-distorter 170 adaptively adjusts its gain and phase transfer funetione in response to residual gain ermr 182 and residual phase error 18d signals fed back from the error detection subsystem 160. ThA pr'ra-rlist~rtinn functions therefore optimally r;unvc~rc~a ~ the system operates.
The path that genorato~ the amplitude and phase correction signals 192, 194 (i.e. the path from the directional coupler 126 through tho attenuator 152 and SS0 i~ T 0 ' 3nHd ObbSZl;2~ T 9 T 006 nl df1021n ~1N~ d I ~1n~~HH LIO~Id 02 :
9 T 00 . ~3Q 02 -1 'I-then through the gain and phase error detector 160 and the adaptive pre-distortar s~rbsy$tem 170) is not a classic feedback loop. The path, in fact, is used to update coefficients in a look-up table over a relatively long period of time and so the path sup~TCTrtS, inherently, a wideband technique. More specifically, the gain and phase error detector 180 i5 arrr~nc~ed to update the look-up table to optimize traoking of the adaptive pre,distorter to a requisite transfer function. Tim adaptive pre-dietorter 170 looks at an input envelope emanating from the Anvelope detector 134 and then, with knowl~dg~ of the requisite tranofor function that the circuit nc~cads to attain to provide phase and amplitude compensation, the adaNlive pre-distorter 170 selects an appropriate coeffiriAnt from the look-up table to improve amplifier linearity.
Reference signal 1 X12, as will bo appreoiatcd, i3 an accurate representation of the input signal 110 that is to b~ amplified. Any deviation (in pha~c or amplitude) between the reference signal 14~ anrl the sampled output signal 154., subj~ct to the taking into ac~ounl ~f fixed gain requirements and offsAt provided by the amplifier 122 and the attenuator 152, is therefurs~ r'dpresentative of error.
According to the present invention, the residual gain error signal 102 and the residual phases prrnr 184 signal, produced by the gain and phase error detector 160, operate linearly over small dltterences in the phase and amplitude; the generation mdc;im~ibrtT will be described In greater detail later.
To frame the invention in context, Figure 2 shows, in detail, a typical architecture of a gain and phas~ ~rror detector 160 that has been used conventionally. The iny.~t signals 142 and 154 are each split by power splitters 602 and 604, respectively. An output of splittQr 602 is fed to envelope detector 610 and an output ~f 5plitter 604 is tad to envelope dPtPCt~r 612. ~fhe envelope detectors 610, G12 produce output volldye5 proportional to the amplitude envPInpP of oignals 142 and 154, respectively. The output voltage of detector 610 is subtract~d from the output of detector 612 by a differential amplifier 818 to produce a signal 618 proportional to the amplitude error between 142 and 154.
SSOib T 0' 3nHd 0bb82~2~ T 9 T 086 n1 dflO~l~1 MN1 d I f~'IflIZIHH LIOJ~ 0Z :
9 T 00 . 1~Q 02 FPU,SUU6y:i -I2~
The difference signal G16 is divided in analogue divider block G20 by signal being the output of envelope dotoetor 610 to produce a signal 182 that is proportional to the gain error betw~~n 142 and 154. The implication of this is that the residual gain error signal 1 tiv is a metric nniy of thp gain distortion (ampl~t~~de compression or expansion) In the power amplifier and Is Independent of the input signal dnvelcrpd Irwdl. Tlnis uan irTyruve llm 5ldlrilily of dry arrylilude ddaplalicrn loop allowing parameter ~r9 to be set more closely fvr rapid conversions.
Derivation of the residual gain error signal 182 and the residual phase error signal 184 will become apparent in the description relating to Figure 4.
The remaining outputs of splitters 602 and 604 are fed to a phase comparator 630 which has two outputs G32 and G34. If the RF input from spotter Q02 is represented in polar form by Ri.cos(wot +a) and the R~ input from splitter f04 is represented by fi2.cos(w~t +p), then the response of phase comparator G30 is such that output G32 is proportional to R~.R2.cos(p-a) and output f34 is proportional to Rr.RZ.sin(~-a). Analogue divider block G3G divides output 034 by 632 to give phase error signal 184. It should be noted that this divider is merely correcting for the amplitude response of the differential phase deteotor and hence pertorms a different role to that 620 in the gain error loop. Phase error signal 184 is then equal to tan(~i--a), but for small values of (~3.-a) then tan(~i-a) approximates to ([i-a).
Figure 3 shows a block diagram of the second lin~ar power amplifier in which the system includes secur7d art~piilude 120 dr ~d 5~sr;or~d phase 121 moriulalur5 arid baseband processing elements 1 D6, 147, 1 i3~, 1 E39. These form a slow feedback loop 1 J1 operating in the gain and phase domain3, the glow feedbaok loop 191 arrang~d to centre tho op~ration of the adaptiv~ pre-dictorter 170 and to allow system components of greatly reduced operating range to be used. The slow 3D feedback loop 191 provides circuit stabilization for gross error, e.g. unit-to-unit variations and component temperature dependence.
SS0 ~S T 0 W nHd 0bb82E2~ t 9 T 006 n1 dflndn MHO d I Mn~I~IHH LIObd T 2 : 9 T
00 . ~~4 02 -la-In previous, prior art systems, operdliun of a slow gain feedhark loop was as follows. The gain error signal 182 is integrated by intec~ratvr 188 and amplifir~d by r.,~ain block 189. A resultant loop gain correction signal ("y") is then applied to d second amplitude modulator 120 that adjusts the signal level into the second phase rrwdulator 121 and high powwr amplifier 122. The arrangement fOrm9 a control loop with inter~rdl dclivn such that the output IpvRl is adjusted to set the sampled output 152 at the same avdrac~e envelope voltage as the sampled input 142. Similarly, operation of s slow phase feedback loop was as follows. The phase ~rror signal 181 is intograted by integrator lBEi and amplified by gain block 187. A resultant loop phase correction signal (°x") i~ then applied to a slew phase modulator 121 that adjusts the phase of the signal into the high power amplifier 122. The arrdryement forms a control hip with integral action whereby the avorage phase of the sampled output 152 is adjusted to the same average phase as the sampled input 142.
the sampled RF output from directional coupler 112 is applied to a power splitter 132, the ~ulWuts of which era connPC:tari to an envelope deteotor 134 and a delay line 140. The output of tine c~rrvelvpe detector is ~:onneeted to an adaptive pre-distortcr subsystem 170. The adaWlive pre-dlstorter subsystem 170 2ci generates two outputs: i) a gain correction signal 192 which is connected to the control port of first amplitude modulator 116; and ii) a phase cvrrecliun signal 194 which Is connected to the control port of first phase modulator 118. As described in relation to the first embodiment, the pre-distorter 170 adaptively adjusts its gain and phase lrdnsfer functions in response to residual gain error 182 ("Y") and residual phase error 184 ("X") signals fed back from an error detection subsystem 160 that operates as described abuvc~.
The 'slow feedhack' control system nulls out tho average gain and phase errors in the actdptatfon loop. The output of the gain error detector mentioned sbov~
is integrated and drnplified to provide a control signal that modulates a gain oontrvl element between the pre-disturler and the power amplifier itselt_ Similarly, the output of the phase en~or detector mentiorrad above is Integrated and amplifi~d SS0 i9 T 0 ' ~nNd 0fit~82~2~ T 9 T 006 O1 dflO~Jn MH'1 d I M0~21NH IAlnbd T 2 : 9 T 00 . l3fl 02 "..~..".....A,.~.~..d....~......r...- _..w~....-._....~... .,w..... . _. ..
... . , ....,._ ~ .... ~ ~...~..~,~~..~. ~~,~.~.~..,..~~ ~ ~, _,-...,.."~..~.,...., . . ,.. ...-. ~,~.~.~w~~...~

FPUS0069~
->4-to provide a control signal that modulates a phase control ~lement between the pre-distorter and the power amplifier. These feedback cnntrnl IonpS arl)ust tn trim out the amplitude and phase errors between the two signal paths into the gain and phase error detectors 1 f0, ensuring that these the fast modulators 116, 11 p and the pre-distorter 170 are opere~ted at their optimum operating point. A
further benefit is that with the slow loopsa controlling the average gain and phase response of the high power amplifier, the range of gain and phase adjustment rEaq~rirPr! from thc~ adaptive pre-distorter 170 is greatly reduced.
A5 will k~a dppraciatad, thr~ mechanism adopted in the preferred embodiment for providing pre-distorted amplification is relatively easily realisablo in diacrctc form and provide a completely polar-domain design which is capable of providing pre-distortion to a standalone radio frequency power amplifier rather than necessarily beinrd. inr.~.orpnrratAri into an raxisting DSP system. The analogue signal processing used to condition error signals and to prvvidr~ input signals eliminates tire rreeci ar.;c:uratr3ly to JiNitise wideband signals at the carrier frequency in order to drive DS(' implementstion9 of the error feedback System and prc-di~torter. The oorrection signals from the pre-distorter are applied to the input signal via analogue radio frequency control elements such that, at no stage, is the input signal to the power amplifier required to be in the digital domain. The use of stow loops can be used to stabilise the prawc~r amplifier gain and phase response, thereby reducing the dynamic range required from a con-ective look-up table of the adaptive pre-distorter i 70. This is of advantage for many applications ouch as in th~ provision of high pow~r linear amplifiers in the transmission of signals in cellular radio base stations.
Tn this point, the description has concentrated on the structural configuration of a linear amplification circuit (e,c~. Fic~ure5 1 to 3), with an overview provided in terms of functional operation of the various circuit components thereof. It is now appropriate to discuss in detail a preferred mechanism for generating correction signals (X and 1~ for compensating for phase error and amplitude (i.e. gain) error.
SS0 W T 0 ' 3nHd 0btr82s;2E T 9 T 006 n1 dMn?~n MHO d I Mn~~IHH LIn~I~ T 2 : 9 T 00 . ~3Q 02 FPUS00~95 Figure 4 shows th~ construction and generation of vector components 250-258 that are subject to amplitude and phase comparison in acoordance with the Nrdsent invention. From an illustrative pwrsnACtive, it is assumed that voltage components of carrier vectors (namely reference carrier vector R and feedback oarrier vector F~' can b~ represented as voltage vectors. The two carrier vectors R and ~ are nominally in anti-phase; this eases impldmentatlon and does not compromis~ generality. The reference carrier vector $ can be described as having an amplitude R. The feedback carrier vootor F can be described as having a wanted component equal to, but in anti-phase with, the reference vector (i.e, -R), wilts the feedback carrier vector iF further having an amplitude error term a.(-i~ and a phase error tarrn p.(-~ orthogonal to the amplitucip error term. R* is equal in amplitude but orthogonal to ~, The vector summation of the reference carrier vector R with the orthogonal error terms a.(-i~ and p.(-i~
therefore definAS feedback carrier vector ~, According to the underlying principle of the present inv~antion (Figure 5), phase and amplitude errors isolated by a vector manipulation technique Involving the g~neration of a frame of reference vectors R~.~ related to the reference Carrier 2r't vPrtor ~ by amplitud~ and phase vector of predetermined magnitude. More specifically, the present invention andertakes an addition or subtraction of two further offset vectors ~ and ,~ of known magnitude to the reference carrier vector R, where A (rdference numeral 270) is an amplitrrriP offset in-phase with ~
and P (reference numeral 272) is a plnasd offset in quadrature with ~; this iS
shown in Figures 5a and 6b. In other words, IRI - R, I~I = A and I~I = P. Ths frame of ref~rence vectors R, to R, is therefore bounded by the known ~A arrd tie offset veeto rs.
According to the present invention, there are two alternative prepositions to curTSider in relation to the generation of the frame of reference veotors R»,.
Specifically, in a fir~sl iri5tance, the reference carrier amplitude offset and the reference carrier phase offset can both bc~ prvpartianal to R. Alternatively, A can SS0 i8 T 0 ' 3nHd 0trt~82~2~ T 9 T 006 O1 dflfl?Jn I''IH'1 d I h'If_11~IHH
LIf_1?Jd 22 : 9 T 00 . 'l3fl 02 FPUS0~695 -is-be generated by limiting R to a constant amplitude so that A is fixed in amplitude and Is not prnporthnal to R. In the latter instance, P Is preferably than simply in phase quadrature offset with respect to A and P_.
It should be notod that a quadrature relationship betwoon tho amplitude offset and phase offset vectors A and P is desirable, but not essential, with the quadrature relationship merely simplifying vectorial computation associated with Isolation of the actual amplitude again) and phase errors and the generation of suitable correction coefficients. Indeed, an in-phase relationship between one of the amplitude offset and phase offset vectors A_ and P with the reference carrier vector io dcoirablo, but not cosential, although the computational mathematics involv~d with th~ isolation of the amplitude and phase error is again increased in its r:~mplpXity.
Irr dccvrddrtce willr a preferred ernbvdirnenl, a frarne of refl~rerwe vec,~tvrs $, to R4 (reference numerals 274-280) is produced relative to reference carrier vector R (reference numeral 250) through the vector additional and subtraction of amplitude offset and phase offset vectors A and _P. The construction of refer~nce vector $~ is shown in Figure 5b in some detail, Le. through the inclusion of the constituent vector components of $ + a + E. The frame of reference vectors $, tv Rd can be represented mathematically a5:
Rt ~-R_~A+P;
~e=~+A__ Pi R9=R_A_P;
R4=R-A+P_ It has been appreciated ltral error lerrrrs irr plm5d dnd arrrplitude carp be i5uldtesi by a combinatorial mechanism in which the wanted feedback carrier vector F is added to the various reference vectors $~ to $q of the reference frame. In other words, the wanted foodbaek carrier vector ~ is added on an individual ba: is to reference v~ctors of the refgrenee frame to produce, in the preferred embodiment, four new difference vectors (or error terms) E~, E~, E~ and Ea.
SS0 ~6 T 0 ~ 3nHd 0bb82~2sr T 9 T 006 01 drl0?Jn MHO d i Mn~IaHH LIObd 22 : 9 T 00 . X34 a2 FPUSooesS
s ~-Looking first to Figure 6a, a vector gener>amr ;~~n is responsive to the reference carrier vector R. The vector generator 300 operates to prvducc~ ltm frdrr~m of refr3rerrce vc~ulor5 R~ to Ra from the reference carrier vector $. In a parallel arrangement, distinct adder circuits 290-2'76 arc each reepansive to the feEdback carrier vector ~ and individual ones of the reference vectors R, to R4 of the reference frame, with outputs of the adder circuits 290~296 producing respective difference vectors E1, E2, ~a and ~4. Flpure 6b 1s a vectorlsl reprw_sentatiQn of the summing function pertormed, with the feedback vac;W r P
256 shown to comprise d wanted signal compvn~nt with amplitude 252 and phase 2~4 error terms.
In relation to the difference (error) vectors E~, E~, ~a and E4, these can be represented math~matically by the Pxprr~ssinns:
E~~E~,~, t F~(R-~-A+~+(-$+a(-~+p(-~).--A+P-a$-p$;
Ez=Rz+F-(8+~-~)-~-(-R+a(-~+p(-~)=A-P-a$-PR:
=Ra+F=~-A-~+(-$+a(-~+P(-~)=-A-P-dR-W~;
E_a=,Fla+E=($-,~+~+(-R+a(-Vii)+N(-,~)=-~+P-aR-pR.
It will now be appreciated that the difference (error) vectors E~, E~, ~ and ~ø now only include the known (i.e. pre-s~I~cted) amplitude and phase offset vectors A_ and _P, as well as error terms a and p that modify the reference carrier vector $
such that the prnducas a$ and p$ are small. In other words. the large reference carrier vector ~, has been elirnindleJ by a simple addition of the reference frame vectors with lira far~dback cam~r vector F. Individual E~ vector component) (which are, at this point, e9aentially radio frequency signals) are now f~d to power detectors (or the like) for amplitude d~termination purposes. For perfect square-law power detectors, individual E, vector components yield amplitudes:
Pi=l,~,lj=E,~=(A-3~Zt L-PR)Z;
P2 ~ 112 = Ez2 = (~ - a$)Z+ (-p - P~Z;
P3 = IEal2 = E3E - (-A - a~'+ (-P - p~z:
I-'4 v lE4iz = E.~z a (-p~ - A~z+ (E - p~2.
SS01020 ' 3nNd 0bb9zsr2s~ T 9 T 006 O1 dfln~n MHO d I MO'I~IHN LIn~I~ z2 : 9 T
00 . ~3rI 0z -~8-Th~ actual~relatlonship betwPwn the ~" vector cvrnponents and their amplitudes is subject to a seating factor which in the above equations has been normalised to unity; this dues not affect the generality of the mechanism. .
As will be appreciated, th~ in-phase components relate, to the known gain offset and gain error terms (A and aF~, rPSpPatively) whereas the quadrature components relate tn Lthe known phase offset and phase error terms (P and p~, respectively). In essence, therefore, thc~ Nrocess involves the expansion of the various polynvrnial terms to leave terms proportional to the gain and phase error terms a and p.
In the abs~nc~ of error signals, for in:;tance, when a feedback I~~p is closed and has converged, all tour riifference vectors E have r~qual amplitude. If A and r arra independent (or nearly indc~Nerrdent) of R, then the magnitudcc of tha difference vectors E at zero error will be approximately constant; this has important implications for detectors employed to measure vector ma~c~nitudes of E , as will be described.
Figure 7 rs illustrative of an arrangerndrrl suitable for detecting in-pha:3o and c~nadrature components; Figurd i is based on Figure 6a but further includes (in each difference vector path an (optional) amplifier 320-326 and a path-specitic cfdtector 330-33G. The detectors 330-336 are preferably matched and pmvide, respectively, outputs P, to P4.

Analysis of the proces:~ shown in Figure 4 is simplified, initially, by assuming that tru~ power detectors are used drrd so the detector outputs P~ are proportional to the square of the voltdc~e siGnals, E~. Although this is the ideal case, it is not nece55r~ry and voltage detection or any law in betw~~n will work watt.
In order to arrive at correction terms for thA power amplifier confic~urdlion of Figures 1 pr 3, gain error (Y) anct phase error (X) values rriu5t be produced by SS0 i T Z0 ' 3nHd 0bb82~2~ T 9 T 006 O1 dflnbn MH'I d I ~1n121HH I~10~1~ ~2 :
9 T 00 . X34 0Z

_ i 9_ the detectors in Figure 7. In this respec.~t, in the preferred exr~rnple (indicative of an optimised case), it is necessary to undertake two separate computations with respect to detected signals P~ to P4. in order to isolate the orror torms p and a (otherwise than through simple scaling factors of multiples of ~, it can be shown that signal processing of the detected signals N1 to N4 rPndr~rs solntrons for the gain (Y) and phase (X) errors, namely:
X - P, - PQ - P3 .~ P4 .- -B~PR
Y = P~ + P~ - P3 - P~ _ -BAaR_ It will be appreciated that X and Y are therefore purely proportional to signal errors. Indeed, referrinrt back tv Fiqure 4, X is proportional to the quadrature error (phase) term p and Y is proportional to the in-phaoe (gain) error tens a.
When the error terms are zero, X and Y are zero. By normalising X and Y by dividing by R and invoking small angle theory, the exact error signals can be determined (by signal prncessinc~), the exact error signals being.
e~Tane=(p.$)/($+a~ap;
k~1+a.
where k is the degree of gain. The analysis above has assumed perfect power detection in which PocF"2 + drift. The drift temt can, in fact, be made to disappear with appropriate combination (wither subtraction or addition) of the detected Pi to P" terms. In a perfect power detector instance, it will be appreciated that if _P~c,.",1R, then X«:~2.
In practice, howevor, thorn i~ a degradation in orthogonality of the pha~c and amplitude error terms p and a caused, for example, by variations in circuit pertormance. This affeot of the error terms p and a can be illustrated by assuming that thp dPtPCt~rs (~f FignrP 7) act as voltage detectors (P"ocE"), rather than pertect power detectors where P"~rE"~_ Figures 8a and 8b. respectively, show the variation of Y and X (ordinate axis) as a function of pYrase drrvr (absci55a) for c~iffdrdr~t amplitude errors; each curve represents a different amplitude error, k. t-igure 8a shows that, in accardance SS0 i2z0 ~ 3nHd 0bb82~2~ T 9 T 006 01 dnn~In MH1 d I ~101~IHH Ia1021~ ~2 : 9 T
00 . 1~Q 02 with the principles of the presAnt invention, Y does not vary very much with phase error and thA amplitude response is rnvr»tonic. Figure eb shows that X
is a good measure of phase error independent of amplitude error. in other words, correct operation of the circuit doe3 not critioally depend vn the nature of the operational nature of the dotoctor circuit.
Referring briefly to Figure 9, this sr:hernatic diagram embodies the principle by which the phase and gale offset vectors are rrrade proportional to the reference carrier vector $. Operation of the circuit of Figure 9 is responsive to receipt of ltm reference carrier vector ~, by a signal splitter 350 that provides a first path to a vector generator 352 via an attenuator 354 that causes attenuation ~f the incident reference carrier v~ctor R. Outputs from the vACt~r generator 352 are then combined (in srimming units ;~60-366) with the reference carrier vdclur R
to produce the frame of reference vectors $~ to ,F~" (where n is at least three and most preferably four). Ttrd vector venerator 352 actually acts a3 a 3plittor and phase shifter network tv generate the known 1.~ and ~$ offset vectors that are ltrerr subsequently added to the main referonoo carrier v~ctor $. It will be appreciated that the circuit of Figuro A is entirely passive and should remain stable over a wide variety of conditions. A disadvantac~c~ of the configuration and operation of 1- -rc~rrrn.~ y is that IAI and IEI (I.e. the respeclivrr n7ac~nitudes of A and p~ arA proportional to I$I. This proportionality r~oeans that X and Y will contain a term in R2 as vppv5r~d to R; making normalisation relative to $ harder from a signal Nrocessing perspective. More seriously, the difference vectors E
(generated consequential to this. proportionality process) at zero phase and amplitude srror will be proportional to R and hence the level dHtPCtOrS (of Figure 7, for example) must to operate anct track each other over an entire dyrTarrric range of the input signal.
In another r~rnbodiment of the present invention, Figurcc 10 and 11 illustrate a mecliarrisms _by which the offset vectors IAI and IPI are mad~ independent of IRI. By using a combined limiter and harmonic filter 370 in sub:;titntinn for the attenuator 361 (of Figure 9) between the signal splitter 350 and a vector SS0iE20' ~nNd 0bt~82E2~ T 9 T 006 01 dnObn ~1H'I d I M01~INH LIOb~ ~2 : 9 T 00 ~ 1~~ 02 _>1_ rdanerator ,~72, a frame of reference vectors R, lu R~ can be generated. More specifically, oulpul5 from the vector generator 3?2 are combined (in summing units 390-396) with the reference carrier vector R to produce the frame of referenco vootoro $, to R, (where n is at least three and most prefPrahly,fnur).
The vector generator 372 actually acts as a splittAr and phase shifter network to generate the known t4 and t_P offset vectors that are then subsequently added to the main reference carrier vector R.
The basic structure of Figure 10 is incorporated into Figure 11, which latter figure further includes a second array of summing units 290-296 that operate to combine the feedback carrier vector F 256 with each of the reference vectors R~
to R, of the reference frame, In the limiting case, with the known rain and offset error terms A and ~ suh~tantially constant, detectors 400-406 responsive to assignRri difference (error) vectors ~, to ~~ are cvn5lr~rirned to work within the i 5 reference frame defined by tA and tP offset and are further restricted to operate on error signals only. Furtherrnvrc~, if A and P_ are kept substantially~constant, the in-line detectors 400-406 can operate at a substantially constant I~vel. To produce the solutions for the gain (Y) and phase (?r7 Arrors, combinatory circuitry (represented by summing blocks 410-412 coupled to Arch output of the various detectors 400-406) isolates the phase and gain errors in terrns of ll7e known pha:~P (~ and gain (~ offset vectors and lira reference carrier vector R, as indicated above.. If required, digital linearisation can be applied to detected Signals.
The majority of thit; system is passive and should remain stahle aver a wide variety of conditions. Combiners and Sputters can be Implemented either as resistive networks that are compact and widr~tadr7d but lossy, or as printed structures; the choice being somewhat arbitrary and generally dependent on the available Space and sictnal levels. If no correction of the detectors 400-406 is required, X and Y can be generated using pimple differential amplifier techniques; this is particular so with detectors obeying a power law.
Amphficatinn of tho X and Y outputs in amplifiers 414-d16 may occur, if desired.
SS0 ~b20 ~ 3nHd 0bb82E2~ T 9 T 006 n1 drln~In ~1H~ d I ~1O~21HH IxIn~I~ b2 : 9 T 00 . X34 02 FPUSOOS9s _2'_ 1-figure 11, which is diagrammatically indicative of the underlying principles to the present invention, allows use of detectors that are only rrcdlcicdd at d sircgld amplitude. Additionally, the circuit architecture inherently allows the detectors to track each other's variations. The subsequent mathematical combination c3ncele offVet~ between the detectors.
LonsequAntiy, the system of the present invention (and partlculariy Figure I t ) operates to converge to an origin of the wanted signal and hence to isolate phase and gain r~rrc~r lerrrcs.
A further source of error may be present due to imperfect generation of the r~f~rence vectors. A qualitative argument suggests that such Arrors will ha small, since, in general, A and P era much smaller than R. The presence of the Ilmlter 370 In Figures '10 and 1 1 also presents the taobsibiiity of AM:PM distortion in the limiter 370 which will rotate the reference frame about its centre. t3ecause the complete system of the present invention is arrangod to oonverge on the centre of the frame, a Might rotation will not affect the final convergence point, but will however affect the orthogonality of the phase and amplit~rcfP error signals.
~c.~
The Implementation of a vector generator and cUrrrbiner's 390-398 and 290-296 can be simplified by combining the reference carriers 257 and feedback carriers 2GGbefore four-way addition, as is known. Extensive uoc oan be made of Wilkinson splitter/oombiners which are broadband and non critical, simplifying 26 bulk design and implementation. The four-way splitter used for the comparative signal need not tae a minimum Inns design and does not need to provide Infinite isnlsthn across ports. Nevertheless, a splatter should bd nyatched on all ports and, importantly. the t~pral~gy allows for a simple coplanar layout. A phase shift rrdlwork for the reference vector signal can be based on a series of 7J4 lines.
30 Impedance transformation in each line would ensure that power is split equally between phases. There need be no i3olation between sections but pads can provide isolation and maintain a good 50SZ match on all ports.
SS0~SZ0 ~ 3nHd 0bfi82EZ~ T 9 T 006 n1 dfl0~ln MN~ d I MO~~IHH 1.1021 b2 : g T
00 . ~3rI 02 -,23-As described in relation to Figure 3, a typical cirouil drc;hritectum associated with an amplifier will incorporate a slew feedback loop 191 designed to track out unit-to-unit variations, thermal drift and long term drift. U~o of each a scow control loop eases amplifier oct up and allowe a fast feedback mechanism to operate only on amplifier induc~d, envelope-dependant distortion components. A slow feedback loop is illustrated in Figure 12, with its configuration and general operation previously described In relation to Figure 3, Il will be appreciated that certain elements, e.g. delay element 140, ~f Figure 3 are omitted from Figure since they do not affect slow loop operation. The functional block labolled "glow feedback prove~sing" porforme an equivalent function to the baseband processing elements (of Figure 3) that provide the slow teedback loop phasr::
and gain corr~ction signals (x anti y).
According to a prr~farred embodiment of the present invention it is desirable to use the same phase/amplitude comparator (i.e. gain and pha~o error detector 160) for both the pre di3tortion loop (having fast modulators) and the slow loop.
Use of common det~ctor circuitry ensures that cost and complexity arA
minimised and, more importantly, it ensures that both the fast and the slow loops 2Cli have exactly the same phase/amplitude cvnverc~arrue state since detector offsets are common to both la~p5. The stow feedback loop 191 operates to correct both the amplitude and the phase of the signal boing fed to the amplifier 122. In theory, correction can be achieved in two ways, namely; i) directly using a phase modulator 121 and an amplitude modulator 120 or as a cartrssian pair of in-phase and quadrature (Ip) amplitude modulators. However, it has been appreciated that, from a practical Implementation standpvir~t, feedback needs to be applied as a carteslan pair (x, y) as vppvsed lu amplitude/phase (R, 8) to avoid the need for potentially unlirnited dr~d-stops vn the phase modulator and lfmrdfor~ to support wrap-around.
More particularly, the glow feedback loop 191 has one characteristic not pros~nt in the pre-distorter loop, namely the existence of an arbitrary phase offset across SS0 X920 W nHd 0bb82f;2~ T 9 T 006 n1 df102ln ~1H~ d I MO~bHH Lln~ld b2 : g T
00 . X34 02 -~4-an r~rnplifier and between elements, With time, this random phase offset will drift and so, in order to avoid a complex (and at least initial) aliqnmEnt procedure.
any phase vhifting control elements must be continuous. In other words, phase shifting control elements must be capable of seamlessly wrapping round from 360° to 0° and have no effective end-stop. Practical analog phase shift networks are not generally continuous and have a limited range of, say, ~180°.
To appreciate the problem posed by this limited range, one can consider a case where the rwc~nirArl phase shift in the control device is +179°. Over temp~rature, however, the control device may suffer a drift of, say, +2°.
Consequently, the required phase shift correction of +181 ° is not available from the control device, and there is no mechanism for switching back to -179° (i.~, the complement to +i 81 °).
Accordingly, to construct a phase shift network that seamlessly wraps around 360° to 0°, it is necessary to use a complex IQ architecture, as shown In Figurds 13 drrd 14, In relation to Figure 13, this i~ a diagrammatic representation of what the slow feedback loop is trying to achieve, with the circuit of Figure 13 corresponding to t1 a Schematic of the complex phase/amplitude equaliser of Figures 3 and 12.
An input signal (which may have been subject to phase and gain correction from the adaptive predistorter 170) is applied to a splitter 470 providing ire-phase and quadrature signal components that are respectively applied to first 472 and eecond 474 multipliarc. The first and second multipliers respectively modulate the quadrature and in-phase signal components with loop correction signal:. (y and x, respectively) 452, 450. Following modulation (to correct for gain and phase errors pertaining to the rPqnirpmPnt for thA slow faeriheck loop 191 ), the irr-phase and quadrature components are combined in a combiner 476 that provides an output to the power amplifier 122.
SS0 iZ20 WnH~ 0bb82~2~ T 9 T 006 O1 dflf_tbn MH1 d T f~1f_1'121HH 1.10214 S2 :
9 T 00 . 'l~fl 02 rPUSoosss Referring now to !''=igurP 14, the slow feedback loop can be considered to be comprised from two sub-loops a55ocialed with phase and amplitude (or IQ
loops). An irnpvrls,rrl Noint to notice is that the variables are orthogonal and so the behaviours of the two loops do not interact, llilith application of thv residual gain error 182 ("Y") and residual phas~ ~rror 184 ("X") signals (produced from the gain and phase error detectors 160 of thA preferred embodiment of the pr~sent invention) to a quadrature to amplitude/phasp (R, a) domain converter 490, distinct phase angle A (reference numeral 5UU) and amplitude R (reference numeral 502) components are generated. Thp amplitude 502 and phase 500 signals are integrated by irrespective amplitude 504 and phase 50B inteqiatom with resultant lime-integrated signals converted back into the IQ domain by converter 508 to provide the loop correction signals x and y (identified as referenos numerals 450 and 452 in Figures 12 and 14). It is the phase integrator 606 that provides th~ requisite wrap-around function for slaw-Ic~np phasra cnntrnl in Figure 3.
There dre rru frarticular speed or transient response requirements from the glow loop; once lock~d, changes are slow and continuous in nature. This simplifies the design of tho two constituent loops in that simple first order loops with integrators, which are unconditionally stat~la, arr~ generally adequate. An integrator is preferrAri tn a simple low pass network because the (theoretically) infinite DC gala ensures that phase am arnplitude errors are tracked exactly.
Extra phase mdrc~irT rnay be desirable if there is considerable inter-reaction between the loops. The operation of the twv integrators now are quite different.
The phase integrator has to be continuous and mu3t wrap round from 360° back to 0~. The output of the amplitude integrator necd~ to be bounded; once the maximum or minimum allowable amplitude i~ reached, the integrator output must hold constant and not wrap from maximum to minimum amplitude.
The circuitry of Figure 14 is preferably realised as logic functions in a digital signal procesSlng (DSP) platform. Advantageously, by performing processing in the digital domdirT, errors in the analog to digital conversion process remain SS0 X820 ' 3nHd 0bb82~2sr T 9 T 006 n1 dfl0~ln f~H~ d I mn~bHH Lln~l~ SZ : 9 T
00 . ~3rI 02 ~26 enmmon to the tast and slow loops wher'~by the loops retain their common convergence point. In addition, in contrast with the analog domain, processing in tlue tiic~ilal domain is more repeatable and flexible and the necessary cnnt~nuous pha3e response is simple to achieve.
The skilled addressee will appreciate that, prima favie, error signals provided by a phasP~/amplitude comparator are cart~sian (approxfrnating to phase and amplitude for small errors) in nature, therAhy allowing a slow loop to be closed ~iirc~c;lly. Unfortunately, direct loop elosur~ is only possible in the case where th~
phase shift in a reference carrier ann is llrd same as a phase shift to an equaliser input of the comparator; this, in practice, is difficult to achieve.
Consequently, from a practical pcrspoctive, it has been assumed that there is an arbitrary phase shift in the loop. Consequently, in accordance with a preferred embodlmerlt, in order to track nut arbitrary phase shifts, the process is 1 ~ performed in thd phd5d (IQ) domain.
SS0 X620 ' ~nHd Bbb82E2~ T 9 T 006 nl dfl0~ln MHO d I f~n~~IHH Lln~l~ 92 : g r 00 . ~3Q 02 As way shown above, for perfect power law detection:
X=-t~PpR;and Y=-8AaR.
where X is propvrtiurml to the quadrature error term, p, and Y i~ proportional to the irr-phase error term, a. When the error terms arc zero, X and Y are zero.
Normalisation by R and addition of a constant merely produces the rAdnisitP
form of error signal stipulated by the prefect~d embodiment of the present invention. Unfortunately, with detectors generally following an imperfect detector law, detector tracking Armrs become more and more significnr7t with ctreater 1 n displacement from the converc~ertce point of the frame of reference vectors (SIIUWII in Figure 5b). Ficlure 15 shows circuit performance of a perfect power Ir~w detector over a phase range of ~180° and amplitude range of tSdB.
Figure is therefore an extended varsion of the plot of Figure 8. Figure 15 can hp contrasted with Figure 16 which shows operational pertom~anee of a voltage law 15 dotoetor configuration over a corresponding phase range of ~180° and amplitude range of ~5dB.
In both Figures 15 and 1 ti, the abscissa axis is phase error, with the ordinate axes of Figures 15a, 15b. 16a arT~ 16b being phase detector output and the ordirmld axes of Figures 1 ~c, 1 Sd, 7 6c and 16d being amplitude detector outputs far different amplitude errors. !n Figure 15a, a pert~ct power detector is assumed and the values of p and a are derived for the case of R = 1; A = 0.1 and P =
0.1 (as in Figur~s 8a and 8b). Next, the value ~f the phase and amplitude offsets were calculated from p and a and are plotted vn Figures 15b and 15d (i.e.
signals 500 and 502 of Figure 14). Figure 16 shows the affect of use of an Imperfect power detector.
It can be shown, mathematically, that the phase offset P = Arctan {p/(a+1 )}
and that the amplitude offset A = ~l{p2+(a+1 )2} - 1. From the plots in Figures 15 and 16, it should be noted that there is no correlation between the calculated phase offset and the calculated amplitudr~ offset.
SS0 ~0~0 ' 3nHd 0bb82~2~ T 9 T 006 nl df102Jn mN~ d I ~IO~bHH LIn~~ 92 : 9 T
00 , ~3rI 02 The graphical representations in Figure 15 demonstrate that, with use of perfect power detectors in the preferred embodiment and emit~d processing capabilities, the phase and amplitude errors can be calculated with sufficient accuracy to generate perfect error signals x and y for the feedback control integrators of Figure 12.
It has also been appreciated that, with the ~xception of an error signal at exactly 180° (which is an unstable equilibrium), the polarity of p can be used as an indicator of whether the phase needs to be advanced or retarded. Feeding p directly Into the phase integrator of Figure 16 therefore produces a converging loop that will become lirmar drrcf wall t~dW odd d5 lhc~ phase error diminishes.
Using the Arctan function (instead of p) provides some additional benefit, but this is achieved at the expense of an overall (and generally significant) increase in signal processing.
Looking at the amplitude response of Figure 15 and 16, it can be seen that the polarity of both a and the calculated amplitude uffsel will rnul dlluw an amplitude loop to converge until the phase has converged within about ~30°. A
detailed offset calculation may improve accuracy, but at the cost of increased processing requirements, as will now be appreciated.
Unlike the detec:tlon pmcc~ss of thA preferred embodiment, the generation of x and y (Le. the control signals for the complex phase/amplitude equaliser) mast have sufficient resolution to er i5ure lhdt r~ny phc~ae and amplitude dither is well within acceptable limits.
It will be appreciat~d that there are alternative mechanism for generating x and y, although a preterred embodiment utilises a look-up table in which are stor~d Correction Codes for detected gain and phase errors. Clearly, a particular embodiment may take advantage of the fact that processing required in each quadrant (or even octant) is es$entially equivalent with other quddrr~rrts (or oatant9), albeit that there is a sign shift. Furthermore, in generality, the SS0 ~ T s0 ' 3nHd 0bb82>rZS; T 9 T 006 01 dfln~ln f~H~ d I ~ln~~IHH LIn~I~ 92 : g T 00 . ~3~i 02 conversion of amplitude and phase to x and y needs to take account of any non-linear response of the control elements, as shown in Figure 1 a, as will be appreciated.
The preferred embodiment of the present invention provides error and gain detection that can support, In the context of a perfect power detector having sufficient processing capabilities, orthogonal error signals. With a voltage detector, an error signal derived directly front X and Y works as well as processed error signals. In practice, with the detector law actually fluctuating between a power regime and a voltage regime over a range of input levels, the use of X and Y to provide the phase error and the amplitude error directly to their respective integrators greatly simplifies processing.
From an implementation perspective, it has been appreciated that the amplitude loop will. only converge once the phase loop is within about 130", so it is preferable that the phase loop be made to operate considerably faster than the amplitude loop.
With non-perfect power law detectors, tracking between detectors oan affect perfr~rmance. More specifically, al fife currvercdc~nce point in llitr retc~rence frame (i.e. when the loop has converged to correct vperativn), all detectors operate on nominally the same constant power and so offsets in P" arising from the use of different detectors can be calibrated at this point. Significantly, away from convergence, the situation chang~s with th~ magnitudes of Pn potentially hPCOmlnr~ larc~p In cnmparlsnn wish X nr Y. GnnsP~nPntly, peen small pArc:entage errors in tracking of the detectors can become very significant once X and Y
are derived. A robust solution to this pot~ntial problem of false locking of the slow feedback loop relies on digitising the power detector outputs, P", and performing tha processing of X and Y digitally. The powar accociated with products of the digital processing can be used to detect when the loop is a long way from lock, e.g. dOE7R thw c:nmr~lativP power of the detectors exceed a predetermined threshold. Le. P, + P2 + P3 + P4 > Threshold. Provided that the threshold sso ~zeo wnHd ofi~ezczc r g r eras of dno~n mH~ d i mo~~HH i.io~~ zz : 9 T 00 . aaa ez ,~.w..,",........ ..................,...,.. ......"
,..,.wu......,..,.",.."~...Mm,",."".".. ..,~...,..~,.w..-...",..~.".
...,".....,.....,..,. . "..
"....,..,.....~."."..,..,.,"".p..~,",:..._.."..,..".."".......~.~..w....~...:..
.M..,......~,....~....."..d.......»,.,.~:......,....~

.n-condition has been satisfied, then a hunting algorithm cr~n bra in5tigalesd (starting from low pain and scanning phase, then incrementing the amplitude and repeating). The slow feedback loop can be closed ones cumulativo powEr value of P~ + PZ + P~ + P,~ drops below the threshold; this is shown in Figure 17.
While the preferred embodiment of the present Invention Is described In the context of a four-vector solution, it will be appreciated that a frame of reference vectors R~ to R~ can contain fewer or more reference vector components (where n is an int~ger equal or greater than three). In this respect, the increase or decrease in the number of vector components within the frame has the affect of increasing processing requirements. The tour-vPCtor frame snlntinn riiarussAd in the c:~ntext of the preferred embodiment is, however, believed to represent an (but exemplary) optimum solution.
It will, of course, be understood that the above desoription has; boon givon by way of example only and that modifications in d~tail may be made within th~
scope of the present invention, e.g. variations of thR error rtPtRCtnr 1 BO
arP
possible. For example, depending on the performance required, the amplitude analogue divider 820 rnay tie ornilled (alliwuc~f Na will rmr~d lu be srrl lu a luwdr value in order to preserve a loop stability), An aRemative configuration of amplitude detectors and signal processing elements rnay be used. Altemativo types of phase discriminator may also be used. A variation of the error detector 1 fi0 may be implemented which generates error signals 182, 184 relating to the signs of the amplitude and phase errors only, as are commonly employed elsewhere in the Pir~ld ref c;vrilrol syslc~ms.
The error detection block 160 may be partially or entirely replaced by digital implomontation, whoroin the RF cignr~lc 142, 164 are digitised and the error signals 82, 84 are computed by a digital signal processing (DSP). The feeding of these error signals to gain blocks 724, 754 into the ariraptiva pre-cliatnrtr~r (70) can then be performed In the digital domain. Indeed, attemative embodiments of the invention rnay 1Je irrrWlernerrleci d5 cUrryuldr prrrgram code encoded r~o a SS0 ~~~0 ~ 3nHd 0bb82sr2~ T 9 T 006 n1 dfln~In ~1H~ d I ~10~~IHH Lln~l~ ZZ : 9 T f~0 . ~3r~ 02 -3 i-computer program product for usp with a computer system. A series of computer instr<ictions emhodles all or part of the furu;liur~ality previously described herein with respect to the syslern. Software embodiments of the invention may be implemented in any conventional computer programming language. For example, preferred embodiments may be implemented in a procedural programming language (e.g. °C°) or an object oriented programmlna language (e.g. "C++").
Although the preferred operating rrmthod may b~ realised by general or specific-purpr~sa processor or logic circuits programmed with euitable maehina-executable inatruotiona, hardware components may be used to implement certain feature: of the pres~nt inv~ntion. Of course, the presr~nt invrantion is likely to be performed by a c~mhinatinn of hardware and software.
We claim:
The embodiment:; of the invention in which an exclusive property or privilege is claimod are defined as follows:
SS0 ib60 ' 3nHd 0bb8262E T 9 T 006 O1 dfl0bn MN~ d 1 M0~21HH 1.10214 Z2 : g T
00 . ~8Q 02

Claims (20)

Claims

1. A detector operable to provide at least one error signal associated with at least one of phase error term and an gain error term between a reference signal R and a feedback signal F, the detector characterised by:
a vector generator responsive to the reference signal R, the vector generator producing a frame of reference vectors R1-Rn generated by a combination of the reference signal R with first A and second P offset vectors that provide an amplitude and phase displacement of the reference signal R;
a signal combiner arranged to generate difference vectors E1-En by combining the frame of reference vectors R1-Rn and the feedback signal F, the difference vectors E1-En expressing the phase (p) and the gain (a) error terms relative to the reference signal R and the first A and second P offset vectors; and an error signal detector responsive to the difference victors E1-En and arranged to provide a measure of the phase (p) and the gain (a) error terms required to support subsequent generation of the at least one error signal.

2. The detector according to claim 1, wherein the frame of reference vectors has at least three reference vectors R1-Rn and preferably four reference vectors R1-Rn.

3. The detector according to claim 2, wherein the frame of reference vectors R1-Rn are defined as:

R1=R+A+P;
R2=R+A-P;
R3=R-A-P;
R4=R-A+P;

4. The detector according to claim 1, 2 or 3, wherein the first and second offset vectors are one of:
Independent of R with R limited to a constant amplitude and such that the first offset vector is fixed in amplitude and is not proportional to R; and proportional to R.

5. The detector according to any preceding claim, wherein the first A and second P offset vectors that are in-phase and in quadrature with the reference signal R.

6. The detector according to any preceding claim, wherein magnitudes of the first A and second P offset vectors are equal.

7. The detector according to any preceding claim, wherein the feedback vector is related to the reference signal R.

8. The detector according to any preceding claim, wherein isolation of the phase and gain error terms contains a term proportional to the reference signal R.

9. The detector according to any preceding claim, further comprising a combinatory circuitry coupled to the error signal detector and arranged to receive output signals from the error signal detector, the combinatory circuitry configured to isolate the phase error term and the gain error term in terms of the first A and second P offset vectors and the reference carrier vector R.

10. The detector according to claim 9, wherein the combinatory circuitry generates the at least one error signal through isolation of the phase error term from the gain error term, the at least one error term satisfying the general form;
X = P1 - P2 - P3 + P4 = -8PpR;
Y = P1 + P2 - P3 - P4 = -8AaR
where a is the gain error term, p is the phase error term and Pn are output amplitudes from the signal error detector for corresponding difference vectors E1-En-

11. The detector of any preceding claim, further comprising a splitter coupled to receive, in use, the reference signal R, the splitter coupled to the vector generator through a first path containing one of:
an attenuator arranged to cause attenuation of tire incident reference carrier vector R; and a combined limiter and harmonic filter.

12. A phase and amplitude comparator operable to provide signals relating to the difference in phase and amplitude between a reference signal R and a feedback signal F, wherein the comparator comprises vector generating means to produce four reference vectors R1-Rn which are related to the input reference vector signal R by the addition of further vectors ~A and ~P which are, respectively, in phase and in quadrature with R such that:
R1=R+A+P;
R2=R+A-P;
R3=R-A-P;
R4=R-A+P;
wherein the four reference vectors R1-Rn are added to four samples of the feedback signal F to produce four corresponding error vectors E1-E4 whereby the vectors E1-E4 can be used to generate phase () and amplitude () comparative signals.

13. An amplifier circuit comprising:

an input coupled to receive, in use, a reference signal R;
phase and gain (modulators coupled to the input;
an amplifier coupled to the phase and gain (modulators;
a first directional coupler coupled to the input and arranged to sample the references signal R; a second directional coupler coupled to the amplifier and arranged to sample an amplified version of the reference signal R, thereby to provide a feedback signal F; and a detector according to any of claim 1 to 11, the detector coupled to the first directional coupler and the second directional coupler to receive, in use, the reference signal R and the feedback signal F;
wherein the phase and gain (modulators are arranged to receive phase and gain corrections signals derived from the at least one error signal generated by the detector.

14. The amplifier circuit of claim 13, further comprising an adaptive pre-distorter coupled to receive the at least one error signal from the detector, the adaptive pre-distorter further coupled to the phase and gain (modulators, the adaptive pre-distorter arranged to determine the gain and phase error correction signals with respect to a set of look-up values, thereby to linearise performance of the amplifier.

16. The amplifier circuit of claim 13 or 14, further comprising a slow feedback loop containing a phase/amplitude equalizer having a second amplitude modulator and a second phase modulator coupled to the amplifier, the phase/amplitude equalizer further containing baseband processing elements coupled to the detector and arranged to receive, in use, the at least one error signal as a control signal for the baseband processing elements, whereby the phase/amplitude equalizer is arranged to track out circuit variations arising from at least one of unit-to-unit variations, thermal drift and long-term component drift through amplitude and phase control of, respectively, the second amplitude modulator and the second phase modulator.

16. The amplifier circuit of claim 15, wherein the phase amplitude equalizer further includes:
a quadrature to amplitude/phase (R,.THETA.) domain converter coupled to receive the at least one error signal(YX) and arranged to provide distinct phase angle .THETA. and amplitude R components;
a phase integrator coupled to the quadrature to amplitude/phase (R, 0) domain converter and arranged to receive, in use, the phase angle .THETA.
component, thereby to provide a first time-integrated signal having a wrap-around phase correction function;
an amplitude integrator coupled to the quadrature to amplitude/phase (R, 0) domain converter and arranged to receive, in use, the phase angle .THETA.
component, thereby to provide a second time-integrated signal;
an amplitude/phase (R, .THETA.) domain to quadrature converter coupled to the phase integrator and the amplitude integrator and arranged, in use, to combine the first time-integrated signal and the second time-integrated signal to exercise control of the slow feedback loop.

17. The amplifier circuit of any of claims 13 to 16, further comprising at least one delay line operable to compensate for any delay skew induced by processing delay in a correction path between the reference signal and correction signals.

18. A cellular base station including the detector of any of claims 11, the phase and amplitude comparator of claim 12 or the amplifier circuit of any of claims 13 to 17.

19. A method of detecting at least one of a phase error term and an amplitude error term between a reference signal R and a feedback signal F and generating a corresponding error signal(Y,X) in response to the least one of the phase error term and the amplitude error term, the method characterised by:

produoing a frame of reference vectors R1-R n generated by a combination of the reference signal R with first A and second P offset vectors that provide an amplitude and phase displacement of the reference signal R;
generating difference vectors E1-E n by combining the frame of reference vectors R1-R n and the feedback signal F, the difference vectors E1-E n expressing the phase (p) and the amplitude (a) error terms relative to the reference signal R
and the first A and second P offset vectors; and providing a measure of the phase (p) and the amplitude (a) error terms in response to the difference vectors E1-E n, the phase (p) and the amplitude (a) error terms required to support subsequent generation of the at least one error signal.

20. The method of detecting according to claim 19, further comprising:
generating the at least one error signal through isolation of the phase error term from the amplitude error term, the at least one error term satisfying the general form:
X-P1-P2-P3+P4=8P p R;
Y=P1 l P2-P3-P4=8A a R
where a is the amplitude error term, p is the phase error term and P n, are output amplitudes from the signal error detector for corresponding difference vectors E1-E n.