CA2358729A1 - Computer aided method of circuit extraction - Google Patents

Computer aided method of circuit extraction Download PDF

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Publication number
CA2358729A1
CA2358729A1 CA002358729A CA2358729A CA2358729A1 CA 2358729 A1 CA2358729 A1 CA 2358729A1 CA 002358729 A CA002358729 A CA 002358729A CA 2358729 A CA2358729 A CA 2358729A CA 2358729 A1 CA2358729 A1 CA 2358729A1
Authority
CA
Canada
Prior art keywords
physical
layers
circuit
images
schematic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002358729A
Other languages
French (fr)
Other versions
CA2358729C (en
Inventor
Jason Abt
Thomas Kapler
Stephen Begg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TechInsights Inc
Original Assignee
Semiconductor Insights Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Insights Inc filed Critical Semiconductor Insights Inc
Priority to CA002358729A priority Critical patent/CA2358729C/en
Priority to US10/267,994 priority patent/US6907583B2/en
Publication of CA2358729A1 publication Critical patent/CA2358729A1/en
Application granted granted Critical
Publication of CA2358729C publication Critical patent/CA2358729C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Abstract

A method and apparatus for extracting circuit design information from a pre-- existing semiconductor integrated circuit (IC) or at least a portion thereof is described. It includes imaging at least a portion of two or more physical layers of the pre--existing IC to obtain stored electronic images of the physical IC layers, converting the stored electronic images of the physical IC layers to a vector format, horizontally and vertically aligning the vector format data of the electronic images of the physical IC layers, and providing a multi-layer display of the aligned vector data. A net- list or schematic is generated from the multi-layer display of the vector data. The netlist and/or schematic may be generated as a number of individual pages by providing a template of circuit elements and placing a circuit element over a portion of the display corresponding to the circuit element. The template of circuit elements may include transistors, logic gates or complex circuit blocks. The vector data may be altered to correct errors in the images or manipulated to correct the alignment of the images. In addition, the schematic may be traced to the image of the physical IC layer.
CA002358729A 2001-10-12 2001-10-12 Computer aided method of circuit extraction Expired - Lifetime CA2358729C (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA002358729A CA2358729C (en) 2001-10-12 2001-10-12 Computer aided method of circuit extraction
US10/267,994 US6907583B2 (en) 2001-10-12 2002-10-10 Computer aided method of circuit extraction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA002358729A CA2358729C (en) 2001-10-12 2001-10-12 Computer aided method of circuit extraction

Publications (2)

Publication Number Publication Date
CA2358729A1 true CA2358729A1 (en) 2003-04-12
CA2358729C CA2358729C (en) 2008-07-08

Family

ID=4170227

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002358729A Expired - Lifetime CA2358729C (en) 2001-10-12 2001-10-12 Computer aided method of circuit extraction

Country Status (2)

Country Link
US (1) US6907583B2 (en)
CA (1) CA2358729C (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7503021B2 (en) * 2002-12-17 2009-03-10 International Business Machines Corporation Integrated circuit diagnosing method, system, and program product
US7441219B2 (en) * 2003-06-24 2008-10-21 National Semiconductor Corporation Method for creating, modifying, and simulating electrical circuits over the internet
US7260810B2 (en) * 2003-10-16 2007-08-21 International Business Machines Corporation Method of extracting properties of back end of line (BEOL) chip architecture
US7188329B2 (en) * 2004-02-13 2007-03-06 Inventec Corporation Computer-assisted electronic component schematic linking method
US20050226521A1 (en) * 2004-03-31 2005-10-13 Chipworks Inc. Method and apparatus for producing a 3-D model of a semiconductor chip from mosaic images
US7643665B2 (en) * 2004-08-31 2010-01-05 Semiconductor Insights Inc. Method of design analysis of existing integrated circuits
US7562328B1 (en) * 2005-01-14 2009-07-14 Altera Corporation Navigation tool for connectors
CA2507174C (en) * 2005-05-13 2013-07-16 Semiconductor Insights Inc. Method of registering and aligning multiple images
US20070031027A1 (en) * 2005-08-04 2007-02-08 Chipworks Inc. Method and system for vertically aligning tile images of an area of interest of an integrated circuit
US7498181B2 (en) * 2005-09-29 2009-03-03 Chipworks Inc. Method of preparing an integrated circuit die for imaging
CA2521675C (en) * 2005-09-29 2009-11-24 Chipworks Inc Method of preparing an integrated circuit die for imaging
US20070256037A1 (en) * 2006-04-26 2007-11-01 Zavadsky Vyacheslav L Net-list organization tools
CA2605234C (en) * 2007-10-03 2015-05-05 Semiconductor Insights Inc. A method of local tracing of connectivity and schematic representations produced therefrom
US7937678B2 (en) * 2008-06-11 2011-05-03 Infineon Technologies Ag System and method for integrated circuit planar netlist interpretation
US8464191B2 (en) * 2011-07-21 2013-06-11 R3 Logic, Inc. System and method for identifying circuit components of an integrated circuit
US9304981B1 (en) * 2011-09-09 2016-04-05 Cadence Design Systems, Inc. System and method for providing an inter-application overlay to communicate information between users and tools in the EDA design flow
CA2791249C (en) 2011-11-10 2014-02-25 Semiconductor Insights Inc. Method and system for ion beam delayering of a sample and control thereof
US8664589B2 (en) * 2011-12-29 2014-03-04 Electro Scientific Industries, Inc Spectroscopy data display systems and methods
US9230050B1 (en) 2014-09-11 2016-01-05 The United States Of America, As Represented By The Secretary Of The Air Force System and method for identifying electrical properties of integrate circuits
US10515181B2 (en) 2017-05-10 2019-12-24 International Business Machines Corporation Integrated circuit identification
US20220005669A1 (en) * 2018-11-21 2022-01-06 Techinsights Inc. Ion beam delayering system and method, topographically enhanced delayered sample produced thereby, and imaging methods and systems related thereto

Family Cites Families (13)

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Publication number Priority date Publication date Assignee Title
EP0186874B1 (en) * 1984-12-26 1994-06-08 Hitachi, Ltd. Method of and apparatus for checking geometry of multi-layer patterns for IC structures
US4835704A (en) * 1986-12-29 1989-05-30 General Electric Company Adaptive lithography system to provide high density interconnect
US5210699A (en) 1989-12-18 1993-05-11 Siemens Components, Inc. Process for extracting logic from transistor and resistor data representations of circuits
US5384710A (en) 1990-03-13 1995-01-24 National Semiconductor Corporation Circuit level netlist generation
US5572437A (en) 1990-04-06 1996-11-05 Lsi Logic Corporation Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
GB2247345B (en) 1990-07-05 1995-04-05 Haroon Ahmed Integrated circuit structure analysis
US5086477A (en) 1990-08-07 1992-02-04 Northwest Technology Corp. Automated system for extracting design and layout information from an integrated circuit
JPH05198593A (en) 1992-01-22 1993-08-06 Hitachi Ltd Method of extracting parameter
US5629858A (en) 1994-10-31 1997-05-13 International Business Machines Corporation CMOS transistor network to gate level model extractor for simulation, verification and test generation
US5903469A (en) 1994-11-08 1999-05-11 Synopsys, Inc. Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach
CA2216900C (en) 1996-10-01 2001-12-04 Semiconductor Insights Inc. Method to extract circuit information
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US6577793B2 (en) * 2000-06-28 2003-06-10 Megasense, Inc. Optical switch

Also Published As

Publication number Publication date
US20030084409A1 (en) 2003-05-01
CA2358729C (en) 2008-07-08
US6907583B2 (en) 2005-06-14

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