CA2392370A1 - A transform, lighting and rasterization system embodied on a single semiconductor platform - Google Patents
A transform, lighting and rasterization system embodied on a single semiconductor platform Download PDFInfo
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- CA2392370A1 CA2392370A1 CA002392370A CA2392370A CA2392370A1 CA 2392370 A1 CA2392370 A1 CA 2392370A1 CA 002392370 A CA002392370 A CA 002392370A CA 2392370 A CA2392370 A CA 2392370A CA 2392370 A1 CA2392370 A1 CA 2392370A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T11/00—2D [Two Dimensional] image generation
- G06T11/40—Filling a planar surface by adding surface attributes, e.g. colour or texture
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/005—General purpose rendering architectures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/04—Texture mapping
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/50—Lighting effects
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/50—Lighting effects
- G06T15/503—Blending, e.g. for anti-aliasing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/50—Lighting effects
- G06T15/506—Illumination models
Abstract
A graphics pipeline system is provided for graphics processing. Such system includes a transform module (52) adapted for being coupled to a vertex attribute buffer (5) for receiving vertex data. The transform module (52) serves to transform the vertex data from object space to screen space. Coupled to the transform module is a lighting module (54) which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. Also included is a rasterizer (56) coupled to the lighting module (54) and positioned on the single semiconductor platform for rendering the vertex data received from the lighting module (54).
Claims (26)
1. A graphics pipeline system for graphics processing, comprising:
(a) a transform module adapted for being coupled to a buffer to receive vertex data therefrom, the transform module being positioned on a single semiconductor platform for transforming the vertex data from object space to screen space;
(b) a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module for performing lighting operations on the vertex data received from the transform module; and (c) a rasterizer coupled to the lighting module and positioned on the same single semiconductor platform as the transform module and lighting module for rendering the vertex data received from the lighting module;
(d) wherein at least one of the transform module and the lighting module includes a sequencer for executing multiple threads of operation in parallel through a plurality of logic units thereof.
(a) a transform module adapted for being coupled to a buffer to receive vertex data therefrom, the transform module being positioned on a single semiconductor platform for transforming the vertex data from object space to screen space;
(b) a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module for performing lighting operations on the vertex data received from the transform module; and (c) a rasterizer coupled to the lighting module and positioned on the same single semiconductor platform as the transform module and lighting module for rendering the vertex data received from the lighting module;
(d) wherein at least one of the transform module and the lighting module includes a sequencer for executing multiple threads of operation in parallel through a plurality of logic units thereof.
2. The system as recited in claim 1, wherein the lighting module includes:
(a) a plurality of input buffers adapted for receiving the vertex data;
(b) a multiplication logic unit having a first input coupled to an output of one of the input buffers and a second input coupled to an output of one of the input buffers;
(c) an arithmetic logic unit having a first input coupled to an output of one of the input buffers and a second input coupled to an output of the multiplication logic unit;
(d) a first register unit having an input coupled to the output of the arithmetic logic unit and an output coupled to the first input of the arithmetic logic unit;
(e) a second register unit having an input coupled to the output of the arithmetic logic unit and an output coupled to the first input and the second input of the multiplication logic unit;
(f) a lighting logic unit having a first input coupled to the output of the arithmetic logic unit, a second input coupled to the output of one of the input buffers, and an output coupled to the first input of the multiplication logic unit; and (g) a memory coupled to at least one of the inputs of the multiplication logic unit and the output of the arithmetic logic unit.
(a) a plurality of input buffers adapted for receiving the vertex data;
(b) a multiplication logic unit having a first input coupled to an output of one of the input buffers and a second input coupled to an output of one of the input buffers;
(c) an arithmetic logic unit having a first input coupled to an output of one of the input buffers and a second input coupled to an output of the multiplication logic unit;
(d) a first register unit having an input coupled to the output of the arithmetic logic unit and an output coupled to the first input of the arithmetic logic unit;
(e) a second register unit having an input coupled to the output of the arithmetic logic unit and an output coupled to the first input and the second input of the multiplication logic unit;
(f) a lighting logic unit having a first input coupled to the output of the arithmetic logic unit, a second input coupled to the output of one of the input buffers, and an output coupled to the first input of the multiplication logic unit; and (g) a memory coupled to at least one of the inputs of the multiplication logic unit and the output of the arithmetic logic unit.
The system as recited in claim 2, wherein an output of one of the input buffers is coupled to an output of the lighting module via a delay.
4. The system as recited in claim 3, wherein the output of the arithmetic logic unit and an output of one of the input buffers are coupled to the output of the lighting module by way of a multiplexer.
The system as recited in claim 2, wherein the output of the multiplication logic unit has a feedback loop coupled to the second input thereof.
6. The system as recited in claim 2, wherein the second input of the lighting logic unit is coupled to an output of one of the input buffers via a delay.
7. The system as recited in claim 2, wherein the output of the lighting logic unit is coupled to the first input of the multiplication logic unit via a first-in first-out register unit.
8. The system as recited in claim 2, wherein the output of the lighting logic unit is coupled to the first input of the multiplication logic unit via a conversion module adapted for converting scalar vertex data to vector vertex data.
9. The system as recited in claim 1, wherein the transform module includes:
(a) an input buffer adapted for receiving vertex data;
(b) a multiplication logic unit having a first input coupled to an output of the input buffer;
(c) an arithmetic logic unit having a first input coupled to an output of the multiplication logic unit;
(d) a register unit having an input coupled to an output of the arithmetic logic unit;
(e) an inverse logic unit including an input coupled to the output of the arithmetic logic unit or the register unit for performing an inverse or an inverse square root operation;
(f) a conversion module coupled between an output of the inverse logic unit and a second input of the multiplication logic unit, the conversion module adapted to convert scalar vertex data to vector vertex data; and (g) a memory coupled to the multiplication logic unit and the arithmetic logic unit.
(a) an input buffer adapted for receiving vertex data;
(b) a multiplication logic unit having a first input coupled to an output of the input buffer;
(c) an arithmetic logic unit having a first input coupled to an output of the multiplication logic unit;
(d) a register unit having an input coupled to an output of the arithmetic logic unit;
(e) an inverse logic unit including an input coupled to the output of the arithmetic logic unit or the register unit for performing an inverse or an inverse square root operation;
(f) a conversion module coupled between an output of the inverse logic unit and a second input of the multiplication logic unit, the conversion module adapted to convert scalar vertex data to vector vertex data; and (g) a memory coupled to the multiplication logic unit and the arithmetic logic unit.
10. The system as recited in claim 9, wherein the memory is coupled to the second input of the multiplication logic unit.
11. The system as recited in claim 9, wherein the memory has a write terminal coupled to the output of the arithmetic logic unit.
12. The system as recited in claim 9, wherein the output of the multiplication logic unit has a feedback loop coupled to the first input thereof.
13. The system as recited in claim 9, wherein the output of the register unit is coupled to the first input of the multiplication logic unit.
14. The system as recited in claim 13, wherein the output of the register unit is coupled to the second input of the multiplication logic unit.
15. The system as recited in claim 9, wherein the output of the arithmetic logic unit has a feedback loop connected to the second input thereof.
16. The system as recited in claim 15, wherein the feedback loop has a delay coupled thereto.
17. The system as recited in claim 1, wherein the rasterizer operates in homogeneous clip space.
18. The system as recited in claim 1, wherein the rasterizer is adapted for receiving a primitive defined by a plurality of vertices each including a W-value; and identifying an area based on the W-values, wherein the area is representative of a portion of a display to be drawn corresponding to the primitive.
19. A graphics pipeline system for graphics processing, comprising:
(a) transform means adapted for being coupled to a buffer to receive vertex data therefrom, the transform means positioned on a single semiconductor platform for transforming the vertex data from object space to screen space;
(b) lighting means positioned on the same single semiconductor platform as the transform means for performing lighting operations on the vertex data received from the transform means; and (c) rasterizer means positioned on the same single semiconductor platform as the transform means and lighting means for rendering the vertex data received from the lighting means;
(d) wherein at least one of the transform means and the lighting means includes a sequencer means for executing multiple threads of operation in parallel through each of a plurality of logic units thereof.
(a) transform means adapted for being coupled to a buffer to receive vertex data therefrom, the transform means positioned on a single semiconductor platform for transforming the vertex data from object space to screen space;
(b) lighting means positioned on the same single semiconductor platform as the transform means for performing lighting operations on the vertex data received from the transform means; and (c) rasterizer means positioned on the same single semiconductor platform as the transform means and lighting means for rendering the vertex data received from the lighting means;
(d) wherein at least one of the transform means and the lighting means includes a sequencer means for executing multiple threads of operation in parallel through each of a plurality of logic units thereof.
20. A method for graphics processing, comprising:
(a) transforming vertex data from object space to screen space;
(b) lighting the vertex data;
(c) executing multiple threads of operation in parallel through a plurality of logic units while at least one of transforming and lighting the vertex data; and (d) rendering the vertex data, wherein the vertex data is transformed, lighted, and rendered on a single semiconductor platform.
(a) transforming vertex data from object space to screen space;
(b) lighting the vertex data;
(c) executing multiple threads of operation in parallel through a plurality of logic units while at least one of transforming and lighting the vertex data; and (d) rendering the vertex data, wherein the vertex data is transformed, lighted, and rendered on a single semiconductor platform.
21. The method as recited in claim 20, wherein prior to rendering, the graphics processing avoids a clipping operation by: receiving a primitive defined by a plurality of vertices each including a W-value;
and identifying an area based on the W-values, wherein the area is representative of a portion of a display to be drawn corresponding to the primitive.
and identifying an area based on the W-values, wherein the area is representative of a portion of a display to be drawn corresponding to the primitive.
22. A graphics pipeline system for graphics processing, comprising:
(a) a lighting module adapted for being coupled to a transform module to receive vertex data therefrom, the lighting module being positioned on a single semiconductor platform for performing lighting operations on the vertex data received from the transform module;
and (b) a rasterizer coupled to the lighting module and positioned on the same single semiconductor platform as the lighting module for rendering the vertex data received from the lighting module;
(c) wherein a clipping operation is avoided prior to rasterization by the rasterizer using W-values of the vertex data.
(a) a lighting module adapted for being coupled to a transform module to receive vertex data therefrom, the lighting module being positioned on a single semiconductor platform for performing lighting operations on the vertex data received from the transform module;
and (b) a rasterizer coupled to the lighting module and positioned on the same single semiconductor platform as the lighting module for rendering the vertex data received from the lighting module;
(c) wherein a clipping operation is avoided prior to rasterization by the rasterizer using W-values of the vertex data.
23. A method for graphics processing, comprising:
(a) lighting vertex data;
(b) avoiding a clipping operation using W-values of the vertex data; and (c) rendering the vertex data, wherein the vertex data is lighted and rendered on a single semiconductor platform.
(a) lighting vertex data;
(b) avoiding a clipping operation using W-values of the vertex data; and (c) rendering the vertex data, wherein the vertex data is lighted and rendered on a single semiconductor platform.
24. A graphics pipeline system for graphics processing, comprising:
(a) a transform module adapted for being coupled to a buffer to receive vertex data therefrom, the transform module being positioned on a single semiconductor platform for transforming the vertex data from object space to screen space; and (b) a rasterizer positioned on the same single semiconductor platform as the transform module for rendering the vertex data;
(c) wherein a clipping operation is avoided prior to rasterization by the rasterizer using W-values of the vertex data.
(a) a transform module adapted for being coupled to a buffer to receive vertex data therefrom, the transform module being positioned on a single semiconductor platform for transforming the vertex data from object space to screen space; and (b) a rasterizer positioned on the same single semiconductor platform as the transform module for rendering the vertex data;
(c) wherein a clipping operation is avoided prior to rasterization by the rasterizer using W-values of the vertex data.
25. A method for graphics processing, comprising:
(a) transforming vertex data from object space to screen space;
(b) avoiding a clipping operation using W-values of the vertex data; and (c) rendering the vertex data, wherein the vertex data is transformed and rendered on a single semiconductor platform.
(a) transforming vertex data from object space to screen space;
(b) avoiding a clipping operation using W-values of the vertex data; and (c) rendering the vertex data, wherein the vertex data is transformed and rendered on a single semiconductor platform.
26. The method as recited in claim 25, wherein prior to rendering, the graphics processing avoids the clipping operation by: receiving a primitive defined by a plurality of vertices each including a W-value;
and identifying an area based on the W-values, wherein the area is representative of a portion of a display to be drawn corresponding to the primitive.
and identifying an area based on the W-values, wherein the area is representative of a portion of a display to be drawn corresponding to the primitive.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/454,516 | 1999-12-06 | ||
| US09/454,516 US6198488B1 (en) | 1999-12-06 | 1999-12-06 | Transform, lighting and rasterization system embodied on a single semiconductor platform |
| PCT/US2000/033092 WO2001041073A1 (en) | 1999-12-06 | 2000-12-05 | A transform, lighting and rasterization system embodied on a single semiconductor platform |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2392370A1 true CA2392370A1 (en) | 2001-06-07 |
| CA2392370C CA2392370C (en) | 2010-10-05 |
Family
ID=23804927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2392370A Expired - Fee Related CA2392370C (en) | 1999-12-06 | 2000-12-05 | A transform, lighting and rasterization system embodied on a single semiconductor platform |
Country Status (7)
| Country | Link |
|---|---|
| US (9) | US6198488B1 (en) |
| EP (1) | EP1238371B9 (en) |
| JP (2) | JP4306995B2 (en) |
| AT (1) | ATE512427T1 (en) |
| AU (1) | AU2064501A (en) |
| CA (1) | CA2392370C (en) |
| WO (1) | WO2001041073A1 (en) |
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