CA2399282A1 - Method for low temperature bonding and bonded structure - Google Patents
Method for low temperature bonding and bonded structure Download PDFInfo
- Publication number
- CA2399282A1 CA2399282A1 CA002399282A CA2399282A CA2399282A1 CA 2399282 A1 CA2399282 A1 CA 2399282A1 CA 002399282 A CA002399282 A CA 002399282A CA 2399282 A CA2399282 A CA 2399282A CA 2399282 A1 CA2399282 A1 CA 2399282A1
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- Prior art keywords
- bonding
- recited
- forming
- bonding surfaces
- etching
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- 238000000034 method Methods 0.000 title claims abstract 128
- 238000005530 etching Methods 0.000 claims abstract 41
- 239000000463 material Substances 0.000 claims abstract 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract 19
- 230000003746 surface roughness Effects 0.000 claims abstract 10
- 239000006227 byproduct Substances 0.000 claims abstract 9
- 239000000377 silicon dioxide Substances 0.000 claims abstract 9
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract 9
- 239000000126 substance Substances 0.000 claims abstract 9
- 238000001020 plasma etching Methods 0.000 claims abstract 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract 5
- 239000010703 silicon Substances 0.000 claims abstract 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract 3
- 238000006116 polymerization reaction Methods 0.000 claims abstract 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims abstract 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims abstract 2
- 239000000908 ammonium hydroxide Substances 0.000 claims abstract 2
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 235000012431 wafers Nutrition 0.000 claims 70
- 239000010410 layer Substances 0.000 claims 53
- 239000000758 substrate Substances 0.000 claims 25
- 238000005498 polishing Methods 0.000 claims 24
- 239000004065 semiconductor Substances 0.000 claims 16
- 238000000151 deposition Methods 0.000 claims 12
- 230000001788 irregular Effects 0.000 claims 11
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims 8
- 238000005516 engineering process Methods 0.000 claims 8
- 230000003213 activating effect Effects 0.000 claims 6
- 125000004429 atom Chemical group 0.000 claims 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 4
- 125000005647 linker group Chemical group 0.000 claims 4
- 229910052760 oxygen Inorganic materials 0.000 claims 4
- 239000001301 oxygen Substances 0.000 claims 4
- 239000002356 single layer Substances 0.000 claims 4
- 229910021529 ammonia Inorganic materials 0.000 claims 3
- 238000000137 annealing Methods 0.000 claims 3
- 230000002950 deficient Effects 0.000 claims 3
- 239000003989 dielectric material Substances 0.000 claims 3
- 125000001153 fluoro group Chemical group F* 0.000 claims 3
- 125000005372 silanol group Chemical group 0.000 claims 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- 230000007547 defect Effects 0.000 claims 2
- 230000001902 propagating effect Effects 0.000 claims 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 claims 1
- 229910052786 argon Inorganic materials 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 claims 1
- 229910017604 nitric acid Inorganic materials 0.000 claims 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 claims 1
- 229920000642 polymer Polymers 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 claims 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims 1
- 238000005382 thermal cycling Methods 0.000 claims 1
- 238000004140 cleaning Methods 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000004913 activation Effects 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000001039 wet etching Methods 0.000 abstract 1
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Abstract
A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity (2). VSE may use reactive ion etching or wet etching to slighthly etch the surfaces being bonded (3). The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces (4).
Claims (146)
1. A bonding method, comprising:
forming first and second bonding surfaces;
etching said first and second bonding surfaces; and bonding together at room temperature said first and second bonding surfaces after said etching step.
forming first and second bonding surfaces;
etching said first and second bonding surfaces; and bonding together at room temperature said first and second bonding surfaces after said etching step.
2. A method as recited in claim 1, wherein said etching step comprises:
etching said first and second bonding surfaces such that respective surface roughnesses of said first and second bonding surfaces after said etching are substantially the same as respective surface roughnesses before said etching.
etching said first and second bonding surfaces such that respective surface roughnesses of said first and second bonding surfaces after said etching are substantially the same as respective surface roughnesses before said etching.
3. A method as recited in claim 2, comprising:
forming said first and second bonding surfaces to have a surface roughness in a range of 0.1 to 3.0 nm.
forming said first and second bonding surfaces to have a surface roughness in a range of 0.1 to 3.0 nm.
4. A method as recited in claim 1, wherein said etching step comprises:
activating said first and second bonding surfaces and forming selected bonding groups on said first and second bonding surfaces.
activating said first and second bonding surfaces and forming selected bonding groups on said first and second bonding surfaces.
5. A method as recited in claim 4, comprising:
forming bonding groups capable of forming chemical bonds at approximately room temperature.
forming bonding groups capable of forming chemical bonds at approximately room temperature.
6. A method as recited in claim 1, comprising:
forming chemical bonds between said bonding surfaces allowing bonded groups to diffuse or dissociate away from an interface of said first and second bonding surfaces.
forming chemical bonds between said bonding surfaces allowing bonded groups to diffuse or dissociate away from an interface of said first and second bonding surfaces.
7. A method as recited in claim 6, comprising:
increasing bonding strength between said first and second bonding surfaces by diffusing or dissociating away said bonding groups.
increasing bonding strength between said first and second bonding surfaces by diffusing or dissociating away said bonding groups.
8. A method as recited in claim 1, wherein said etching step comprises:
forming a monolayer of one of a desired atom and a desired molecule on said bonding surface.
forming a monolayer of one of a desired atom and a desired molecule on said bonding surface.
9. A method as recited in claim 8, wherein said etching step comprises:
forming a few monolayers of one of a desired atom and a desired molecule on said bonding surface.
forming a few monolayers of one of a desired atom and a desired molecule on said bonding surface.
10. A method as recited in claim 1, comprising:
after said etching step, immersing said first and second bonding surfaces in a solution to form bonding surfaces terminated with desired species.
after said etching step, immersing said first and second bonding surfaces in a solution to form bonding surfaces terminated with desired species.
11. A method as recited in claim 10, wherein said species comprise at least one of a silanol group, an NH2 group, a fluorine group and an HF group.
12. A method as recited in claim 10, wherein said etching step comprises:
forming a monolayer of one of a desired atom and a desired molecule on said bonding surface.
forming a monolayer of one of a desired atom and a desired molecule on said bonding surface.
13. A method as recited in claim 1, wherein said etching comprises:
exposing said first and second bonding surfaces to a plasma.
exposing said first and second bonding surfaces to a plasma.
14. A method as recited in claim 1, comprising:
exposing said first and second bonding surfaces to one of an oxygen, argon, NH3 and CF4 plasma process.
exposing said first and second bonding surfaces to one of an oxygen, argon, NH3 and CF4 plasma process.
15. A method as recited in claim 14, comprising:
conducting said plasma process in one of RIE mode, ICP mode, plasma mode and sputtering mode.
conducting said plasma process in one of RIE mode, ICP mode, plasma mode and sputtering mode.
16. A method as recited in claim 1, comprising:
polishing respective first and second bonding surfaces to respective desired surface roughnesses and planarity; and etching said first and second bonding surfaces after said polishing to activate said first and second bonding surfaces.
polishing respective first and second bonding surfaces to respective desired surface roughnesses and planarity; and etching said first and second bonding surfaces after said polishing to activate said first and second bonding surfaces.
17. A method as recited in claim 16, wherein:
forming at least one of said first and second bonding surfaces comprises depositing a polishable material on a non-planar surface.
forming at least one of said first and second bonding surfaces comprises depositing a polishable material on a non-planar surface.
18. A method as recited in claim 17, wherein depositing said polishable material comprises depositing one of silicon oxide, silicon nitride or a dielectric polymer.
19. A method as recited in claim 1, wherein said etching step comprises:
increasing available bonding energy of bonding pairs on said first and second bonding surfaces at approximately room temperature.
increasing available bonding energy of bonding pairs on said first and second bonding surfaces at approximately room temperature.
20. A method as recited in claim 19, comprising:
obtaining a bond of at least 500 mJ/m2.
obtaining a bond of at least 500 mJ/m2.
21. A method as recited in claim 19, comprising:
obtaining a bond of at least 1000 mJ/m2.
obtaining a bond of at least 1000 mJ/m2.
22. A method as recited in claim 19, comprising:
obtaining a bond of at least 2000 mJ/m2.
obtaining a bond of at least 2000 mJ/m2.
23. A method as recited in claim 1, comprising:
forming a bond of at least 500 mJ/m2.
forming a bond of at least 500 mJ/m2.
24. A method as recited in claim 1, comprising:
obtaining a bond of at least 1000 mJ/m2.
obtaining a bond of at least 1000 mJ/m2.
25. A method as recited in claim 1, comprising:
obtaining a bond of at least 2000 mJ/m2.
obtaining a bond of at least 2000 mJ/m2.
26. A method as recited in claim 1, comprising:
forming chemical bonds between said bonding surfaces.
forming chemical bonds between said bonding surfaces.
27. A method as recited in claim 26, comprising:
forming chemical bonds between said bonding surfaces in one of ambient and vacuum.
forming chemical bonds between said bonding surfaces in one of ambient and vacuum.
28. A method as recited in claim 26, comprising:
forming chemical bonds between said bonding surfaces in one of low and ultra high and vacuum.
forming chemical bonds between said bonding surfaces in one of low and ultra high and vacuum.
29. A method as recited in claim 1, comprising:
forming a bond of sufficient energy to virtually eliminate wafer bowing during subsequent processing of said bonded bonding surfaces.
forming a bond of sufficient energy to virtually eliminate wafer bowing during subsequent processing of said bonded bonding surfaces.
30. A method as recited in claim 29, comprising:
forming a bond of sufficient energy to virtually eliminate wafer bowing during subsequent thermal cycling of said bonded bonding surfaces.
forming a bond of sufficient energy to virtually eliminate wafer bowing during subsequent thermal cycling of said bonded bonding surfaces.
31. A method as recited in claim 1, wherein said etching step comprises:
increasing available bonding energy of bonding pairs on said first and second bonding surfaces at approximately room temperature; and propagating said bonding at room temperature.
increasing available bonding energy of bonding pairs on said first and second bonding surfaces at approximately room temperature; and propagating said bonding at room temperature.
32. A method as recited in claim 31, comprising:
propagating chemical bonding at room temperature.
propagating chemical bonding at room temperature.
33. A method as recited in claim 1, comprising:
depositing silicon dioxide as first and second bonding materials having said first and second bonding surfaces; and etching said first and second bonding surfaces using an oxygen plasma.
depositing silicon dioxide as first and second bonding materials having said first and second bonding surfaces; and etching said first and second bonding surfaces using an oxygen plasma.
34. A method as recited in claim 33, comprising:
rinsing said bonding materials in an ammonia-based solution after said etching.
rinsing said bonding materials in an ammonia-based solution after said etching.
35. A method as recited in claim 34, comprising:
rinsing said bonding materials in ammonium hydroxide after said etching.
rinsing said bonding materials in ammonium hydroxide after said etching.
36. A method as recited in claim 34, comprising:
rinsing said bonding materials in ammonium fluoride after said etching.
rinsing said bonding materials in ammonium fluoride after said etching.
37. A method as recited in claim 1, comprising:
etching said first and second bonding surfaces under vacuum; and bonding said first and second bonding surfaces without breaking said vacuum.
etching said first and second bonding surfaces under vacuum; and bonding said first and second bonding surfaces without breaking said vacuum.
38. A method as recited in claim 1, comprising:
depositing a bonding material on each of first and second surfaces to obtain said first and second bonding surfaces.
depositing a bonding material on each of first and second surfaces to obtain said first and second bonding surfaces.
39. A method as recited in claim 38, comprising:
depositing one of silicon dioxide and silicon nitride as said bonding material.
depositing one of silicon dioxide and silicon nitride as said bonding material.
40. A method as recited in claim 1, comprising:
depositing silicon dioxide as said bonding material;
etching said silicon dioxide using one of oxygen, CF4, and Ar plasma RIE; and rinsing said silicon dioxide in an ammonia-based solution after said etching.
depositing silicon dioxide as said bonding material;
etching said silicon dioxide using one of oxygen, CF4, and Ar plasma RIE; and rinsing said silicon dioxide in an ammonia-based solution after said etching.
41. A method as recited in claim 1, comprising:
etching said first and second bonding materials using a wet etch process.
etching said first and second bonding materials using a wet etch process.
42. A method as recited in claim 42, comprising:
immersing said first and second bonding surfaces into a solution after said etching.
immersing said first and second bonding surfaces into a solution after said etching.
43. A method as recited in claim 1, comprising:
depositing silicon dioxide as said bonding material;
etching said silicon dioxide using one of diluted HF and diluted NH4F.
depositing silicon dioxide as said bonding material;
etching said silicon dioxide using one of diluted HF and diluted NH4F.
44. A method as recited in claim 43, comprising:
rinsing said silicon dioxide in an ammonia-based solution after said etching.
rinsing said silicon dioxide in an ammonia-based solution after said etching.
45. A method as recited in claim 1, comprising:
forming said first and second bonding surfaces as silicon: and etching said bonding surfaces using a solution of HNO3 and diluted HF.
forming said first and second bonding surfaces as silicon: and etching said bonding surfaces using a solution of HNO3 and diluted HF.
46. A method as recited in claim 1, comprising:
forming said first and second bonding surfaces as silicon each having a native oxide layer; and activating said native oxide layer using said etching step.
forming said first and second bonding surfaces as silicon each having a native oxide layer; and activating said native oxide layer using said etching step.
47. A method as recited in claim 1, comprising:
forming said first and second bonding surfaces each as silicon having a native oxide layer; and exposing said first and second bonding surfaces to an oxygen plasma to etch said native oxide layers.
forming said first and second bonding surfaces each as silicon having a native oxide layer; and exposing said first and second bonding surfaces to an oxygen plasma to etch said native oxide layers.
48. A method as recited in claim 47, creating a defective zone in said silicon during plasma etching.
49. A method as recited in claim 1, comprising:
etching said first and second bonding materials using a plasma RIE process;
forming a region having defects proximate to said bonding surface; and removing bonding by-products using said region.
etching said first and second bonding materials using a plasma RIE process;
forming a region having defects proximate to said bonding surface; and removing bonding by-products using said region.
50. A method as recited in claim 1, wherein said etching comprises:
activating said first and second bonding surfaces; and creating a region under said first and second bonding surfaces for removing bonding by-products.
activating said first and second bonding surfaces; and creating a region under said first and second bonding surfaces for removing bonding by-products.
51. A method as recited in claim 1, comprising:
creating a region proximate to said first and second bonding surfaces for at least one of removal and conversion of bonding by-products to a species capable of being absorbed by or diffusing away from said bonding surfaces.
creating a region proximate to said first and second bonding surfaces for at least one of removal and conversion of bonding by-products to a species capable of being absorbed by or diffusing away from said bonding surfaces.
52. A method as recited in claim 1, comprising:
forming said first bonding surface by depositing an oxide layer on a first semiconductor wafer;
forming said second bonding surface by depositing an oxide layer on a second semiconductor wafer; and bonding said first and second semiconductor wafers.
forming said first bonding surface by depositing an oxide layer on a first semiconductor wafer;
forming said second bonding surface by depositing an oxide layer on a second semiconductor wafer; and bonding said first and second semiconductor wafers.
53. A method as recited in claim 1, comprising:
forming said first bonding surface as a deposited oxide layer on a first semiconductor wafer, said first wafer comprising a first substrate and a first active region;
forming said second bonding surface as a deposited oxide layer on a second semiconductor wafer, said second wafer comprising a second substrate and a second active region;
bonding said first and second semiconductor wafers; and removing at least a substantial portion of one of said first and second substrates after said bonding.
forming said first bonding surface as a deposited oxide layer on a first semiconductor wafer, said first wafer comprising a first substrate and a first active region;
forming said second bonding surface as a deposited oxide layer on a second semiconductor wafer, said second wafer comprising a second substrate and a second active region;
bonding said first and second semiconductor wafers; and removing at least a substantial portion of one of said first and second substrates after said bonding.
54. A method as recited in claim 1, comprising:
forming said first bonding surface as a deposited oxide layer on a semiconductor wafer, said wafer comprising a substrate and an active region;
forming said second bonding surface as a surrogate substrate;
bonding said wafer and said surrogate substrate; and removing at least a substantial portion of said first substrate after said bonding.
forming said first bonding surface as a deposited oxide layer on a semiconductor wafer, said wafer comprising a substrate and an active region;
forming said second bonding surface as a surrogate substrate;
bonding said wafer and said surrogate substrate; and removing at least a substantial portion of said first substrate after said bonding.
55. A method as recited in claim 1, wherein said bonding comprises:
maintaining contact between said first and second bonding surfaces for a specified period to produce bonding polymerization and allow removal of by-products.
maintaining contact between said first and second bonding surfaces for a specified period to produce bonding polymerization and allow removal of by-products.
56. A method as recited in claim 55, comprising:
maintaining said contact between said first and second bonding surfaces for a period less than about 20 hours.
maintaining said contact between said first and second bonding surfaces for a period less than about 20 hours.
57. A method as recited in claim 1, wherein said bonding comprises:
maintaining said first and second bonding surfaces for a specified period in ambient to remove bonding by-products.
maintaining said first and second bonding surfaces for a specified period in ambient to remove bonding by-products.
58. A method as recited in claim 1, comprising:
etching said first and second bonding surfaces using a bonding fixture under vacuum;
bonding said first and second bonding surfaces using said fixture to bring together said first and second bonding surfaces while maintaining said vacuum.
etching said first and second bonding surfaces using a bonding fixture under vacuum;
bonding said first and second bonding surfaces using said fixture to bring together said first and second bonding surfaces while maintaining said vacuum.
59. A method as recited in claim 1, comprising:
forming a first oxide layer on a first wafer containing electrical devices;
and polishing said first oxide layer to form said first bonding surface.
forming a first oxide layer on a first wafer containing electrical devices;
and polishing said first oxide layer to form said first bonding surface.
60. A method as recited in claim 59, comprising:
forming a second oxide layer on a second wafer containing electrical devices;
and polishing said second oxide layer to form said second bonding surface.
forming a second oxide layer on a second wafer containing electrical devices;
and polishing said second oxide layer to form said second bonding surface.
61. A method as recited in claim 60, comprising:
forming said first oxide layer on said first wafer containing electrical devices of a first technology; and forming said second oxide layer on said second wafer containing electrical devices of a second technology different from said first technology.
forming said first oxide layer on said first wafer containing electrical devices of a first technology; and forming said second oxide layer on said second wafer containing electrical devices of a second technology different from said first technology.
62. A method as recited in claim 60, comprising:
interconnecting said first and second devices.
interconnecting said first and second devices.
63. A method as recited in claim 60, comprising:
forming said first bonding surface on a surface of a one of a thermal spreader, surrogate substrate, antenna, wiring layer, and pre-formed multi-layer interconnect.
forming said first bonding surface on a surface of a one of a thermal spreader, surrogate substrate, antenna, wiring layer, and pre-formed multi-layer interconnect.
64. A method as recited in claim 60, comprising:
forming said second bonding surface on a surface of a one of a thermal spreader, surrogate substrate, antenna, wiring layer, and pre-formed multi-layer interconnect.
forming said second bonding surface on a surface of a one of a thermal spreader, surrogate substrate, antenna, wiring layer, and pre-formed multi-layer interconnect.
65. A method as recited in claim 1, comprising:
forming said first bonding surface on a first wafer containing a first integrated circuit.
forming said first bonding surface on a first wafer containing a first integrated circuit.
66. A method as recited in claim 65, comprising:
forming said second bonding surface on a second wafer containing a second integrated circuit.
forming said second bonding surface on a second wafer containing a second integrated circuit.
67. A method as recited in claim 66, comprising:
forming said first bonding surface on said first wafer containing said first integrated circuit of a first technology; and forming said second bonding surface on said second wafer containing said second integrated circuit of a second technology different from said first technology.
forming said first bonding surface on said first wafer containing said first integrated circuit of a first technology; and forming said second bonding surface on said second wafer containing said second integrated circuit of a second technology different from said first technology.
68. A method as recited in claim 66, comprising:
interconnecting said first and second integrated circuits.
interconnecting said first and second integrated circuits.
69. A method as recited in claim 1, comprising:
said first and second bonding surfaces being substantially planar.
said first and second bonding surfaces being substantially planar.
70. A method as recited in claim 1, wherein:
forming said first and second bonding surfaces comprises depositing a dielectric material.
forming said first and second bonding surfaces comprises depositing a dielectric material.
71. A method as recited in claim 70, comprising:
polishing said dielectric material to a desired planarity and surface roughness.
polishing said dielectric material to a desired planarity and surface roughness.
72. A method as recited in claim 70, comprising:
depositing said dielectric material on a non-planar surface.
depositing said dielectric material on a non-planar surface.
73. A method as recited in claim 72, wherein:
said polishing comprises chemical-mechanical polishing.
said polishing comprises chemical-mechanical polishing.
74. A method as recited in claim 1, comprising:
forming said first and second bonding surfaces to be non-planar; and polishing said first and second bonding surfaces to a desired planarity and surface roughness
forming said first and second bonding surfaces to be non-planar; and polishing said first and second bonding surfaces to a desired planarity and surface roughness
75. A method as recited in claim 74, wherein:
said polishing comprises chemical-mechanical polishing.
said polishing comprises chemical-mechanical polishing.
76. A method as recited in claim 1, where said etching comprises:
activating said bonding surfaces; and terminating said bonding surfaces with a desired species.
activating said bonding surfaces; and terminating said bonding surfaces with a desired species.
77. A method as recited in claim 1, wherein said etching comprises:
a first etching step to activate said bonding surfaces; and a second etching step to terminate said bonding surfaces with a desired species.
a first etching step to activate said bonding surfaces; and a second etching step to terminate said bonding surfaces with a desired species.
78. A method as recited in claim 1, comprising:
obtaining etched bonding surfaces using said etching step; and exposing said bonding surfaces to a gaseous chemical environment to terminate said etched bonding surfaces with a desired species.
obtaining etched bonding surfaces using said etching step; and exposing said bonding surfaces to a gaseous chemical environment to terminate said etched bonding surfaces with a desired species.
79. A method as recited in claim 1, comprising:
forming a first oxide layer on a first wafer containing electrical devices and having a non-planar surface; and forming a second oxide layer on a second wafer containing electrical devices;
and polishing said first and second oxide layers to form said first and second bonding surfaces, respectively.
forming a first oxide layer on a first wafer containing electrical devices and having a non-planar surface; and forming a second oxide layer on a second wafer containing electrical devices;
and polishing said first and second oxide layers to form said first and second bonding surfaces, respectively.
80. A method as recited in claim 79, comprising:
forming said second oxide layer on said second wafer having a non-planar surface.
forming said second oxide layer on said second wafer having a non-planar surface.
81. A method as recited in claim 1, comprising:
forming a first oxide layer on a first wafer containing electrical devices and having an irregular surface topology; and forming a second oxide layer on a second wafer containing electrical devices;
and polishing said first and second oxide layers to form said first and second bonding surfaces, respectively.
forming a first oxide layer on a first wafer containing electrical devices and having an irregular surface topology; and forming a second oxide layer on a second wafer containing electrical devices;
and polishing said first and second oxide layers to form said first and second bonding surfaces, respectively.
82. A method as recited in claim 81, comprising:
forming said second oxide layer on said second wafer having an irregular surface topology.
forming said second oxide layer on said second wafer having an irregular surface topology.
83. A bonding method, comprising:
forming first and second bonding surfaces each having a surface roughness in a range of 0.1 to 3 nm;
removing material from said first and second bonding surfaces while maintaining said surface roughness; and directly bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 500 mJ/m2.
forming first and second bonding surfaces each having a surface roughness in a range of 0.1 to 3 nm;
removing material from said first and second bonding surfaces while maintaining said surface roughness; and directly bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 500 mJ/m2.
84. A method as recited in claim 83, comprising:
directly bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 1000 mJ/m2.
directly bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 1000 mJ/m2.
85. A method as recited in claim 83, comprising:
directly bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 2000 mJ/m2.
directly bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 2000 mJ/m2.
86. A method as recited in claim 83, comprising:
activating said first and second bonding surfaces and forming selected bonding groups on said first and second bonding surfaces.
activating said first and second bonding surfaces and forming selected bonding groups on said first and second bonding surfaces.
87. A method as recited in claim 83, comprising:
polishing respective first and second bonding surfaces to said surface roughness; and etching said first and second bonding surfaces after said polishing to activate said first and second bonding surfaces.
polishing respective first and second bonding surfaces to said surface roughness; and etching said first and second bonding surfaces after said polishing to activate said first and second bonding surfaces.
88. A method as recited in claim 83, comprising:
converting bonding by-products to a species capable of being absorbed by or diffusing away from said bonding surfaces during said bonding step.
converting bonding by-products to a species capable of being absorbed by or diffusing away from said bonding surfaces during said bonding step.
89. A method as recited in claim 83, comprising:
etching said first and second bonding surfaces using a plasma RIE process;
forming a subsurface layer having defects; and removing bonding by-products using said subsurface layer.
etching said first and second bonding surfaces using a plasma RIE process;
forming a subsurface layer having defects; and removing bonding by-products using said subsurface layer.
90. A method as recited in claim 83, comprising:
forming said first bonding surface as a surface of a first semiconductor wafer having devices formed therein; and forming said second bonding surface as a surface of a second semiconductor wafer having devices formed therein.
forming said first bonding surface as a surface of a first semiconductor wafer having devices formed therein; and forming said second bonding surface as a surface of a second semiconductor wafer having devices formed therein.
91. A method as recited in claim 90, comprising:
removing a substantial portion of said one of said first and second wafers.
removing a substantial portion of said one of said first and second wafers.
92. A method as recited in claim 90, comprising:
interconnecting devices in said first and second wafers.
interconnecting devices in said first and second wafers.
93. A method as recited in claim 83, comprising:
forming a first insulating layer on a first wafer containing electrical devices;
polishing said first insulating layer to form said first bonding surface;
forming a second insulating layer on a second wafer containing electrical devices; and polishing said second oxide layer to form said second bonding surface.
forming a first insulating layer on a first wafer containing electrical devices;
polishing said first insulating layer to form said first bonding surface;
forming a second insulating layer on a second wafer containing electrical devices; and polishing said second oxide layer to form said second bonding surface.
94. A method as recited in claim 83, comprising:
forming a first insulating layer on a first wafer containing electrical devices and having an irregular surface topology;
polishing said first insulating layer to form said first bonding surface:
forming a second insulating layer on a second wafer containing electrical devices and having an irregular surface topology; and polishing said second oxide layer to form said second bonding surface.
forming a first insulating layer on a first wafer containing electrical devices and having an irregular surface topology;
polishing said first insulating layer to form said first bonding surface:
forming a second insulating layer on a second wafer containing electrical devices and having an irregular surface topology; and polishing said second oxide layer to form said second bonding surface.
95. A bonding method, comprising:
forming first and second bonding surfaces;
etching said first and second bonding surfaces;
terminating said first and second bonding surfaces with a species allowing formation of chemical bonds at about room temperature; and bonding said first and second bonding surfaces at about room temperature.
forming first and second bonding surfaces;
etching said first and second bonding surfaces;
terminating said first and second bonding surfaces with a species allowing formation of chemical bonds at about room temperature; and bonding said first and second bonding surfaces at about room temperature.
96. A method as recited in claim 95, comprising:
bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 500 mJ/m2.
bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 500 mJ/m2.
97. A method as recited in claim 95, comprising:
bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 1000 mJ/m2.
bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 1000 mJ/m2.
98. A method as recited in claim 95, comprising:
bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 2000 mJ/m2.
bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 2000 mJ/m2.
99. A method as recited in claim 95, comprising:
activating said first and second bonding surfaces prior to said bonding step.
activating said first and second bonding surfaces prior to said bonding step.
100. A method as recited in claim 95, comprising:
polishing said first and second bonding surfaces; and etching said first and second bonding surfaces after said polishing to activate said first and second bonding surfaces.
polishing said first and second bonding surfaces; and etching said first and second bonding surfaces after said polishing to activate said first and second bonding surfaces.
101. A method as recited in claim 95, comprising:
converting bonding by-products to a species capable of being absorbed by or diffusing away from said bonding surfaces during said bonding step.
converting bonding by-products to a species capable of being absorbed by or diffusing away from said bonding surfaces during said bonding step.
102. A method as recited in claim 95, comprising:
forming said first bonding surface as a surface of a first semiconductor wafer having devices formed therein; and forming said second bonding surface as a surface of a second semiconductor wafer having devices formed therein.
forming said first bonding surface as a surface of a first semiconductor wafer having devices formed therein; and forming said second bonding surface as a surface of a second semiconductor wafer having devices formed therein.
103. A method as recited in claim 102, wherein one of said first and second wafers comprises a substrate, said method comprising:
removing a substantial portion of said one of said first and second wafers.
removing a substantial portion of said one of said first and second wafers.
104. A method as recited in claim 102, comprising:
interconnecting devices in said first and second wafers.
interconnecting devices in said first and second wafers.
105. A method as recited in claim 95, comprising:
forming a first insulating layer on a first wafer containing electrical devices;
polishing said first insulating layer to form said first bonding surface;
forming a second insulating layer on a second wafer containing electrical devices; and polishing said second oxide layer to form said second bonding surface.
forming a first insulating layer on a first wafer containing electrical devices;
polishing said first insulating layer to form said first bonding surface;
forming a second insulating layer on a second wafer containing electrical devices; and polishing said second oxide layer to form said second bonding surface.
106. A method as recited in claim 95, comprising:
forming a first insulating layer on a first wafer containing electrical devices and having an irregular surface topology;
polishing said first insulating layer to form said first bonding surface;
forming a second insulating layer on a second wafer containing electrical devices and having an irregular surface topology; and polishing said second oxide layer to form said second bonding surface.
forming a first insulating layer on a first wafer containing electrical devices and having an irregular surface topology;
polishing said first insulating layer to form said first bonding surface;
forming a second insulating layer on a second wafer containing electrical devices and having an irregular surface topology; and polishing said second oxide layer to form said second bonding surface.
107. A bonded device, comprising:
a first material having a first etched bonding surface; and a second material having a second etched bonding surface directly bonded to said first bonding surface at room temperature having a bonding strength of at least 500 to 2000 mJ/m2.
a first material having a first etched bonding surface; and a second material having a second etched bonding surface directly bonded to said first bonding surface at room temperature having a bonding strength of at least 500 to 2000 mJ/m2.
108. A device as recited in claim 107, comprising:
said first and second bonding surfaces being activated and terminated with a desired bonding species.
said first and second bonding surfaces being activated and terminated with a desired bonding species.
109. A device as recited in claim 108, wherein said desired species comprise:
a monolayer of one of a desired atom and a desired molecule on said bonding surface.
a monolayer of one of a desired atom and a desired molecule on said bonding surface.
110. A device as recited in claim 108, wherein said desired species comprise at least one of a silanol group, an NH2 group, a fluorine group and an HF group.
111. A device as recited in claim 107, comprising:
said first and second bonding surfaces each having a defective region located proximate to said first and second bonding surfaces, respectively.
said first and second bonding surfaces each having a defective region located proximate to said first and second bonding surfaces, respectively.
112. A device as recited in claim 107, wherein:
said first material comprises a surface of a first semiconductor wafer having devices formed therein; and said second material comprises a surface of a second semiconductor wafer having devices formed therein.
said first material comprises a surface of a first semiconductor wafer having devices formed therein; and said second material comprises a surface of a second semiconductor wafer having devices formed therein.
113. A device as recited in claim 112, wherein one of said first and second wafers comprises a device region after removing a substantial portion of a substrate of said one of said first and second wafers.
114. A device as recited in claim 112, comprising:
devices in said first and second wafers being interconnected.
devices in said first and second wafers being interconnected.
115. A device as recited in claim 112, comprising:
said first and second wafers being different technologies.
said first and second wafers being different technologies.
116. A device as recited in claim 107, wherein:
one of said first and second wafers comprises an integrated circuit.
one of said first and second wafers comprises an integrated circuit.
117. A device as recited in claim 116, comprising:
devices in said first and second wafers being interconnected.
devices in said first and second wafers being interconnected.
118. A device as recited in claim 116, comprising:
said first and second wafers having an irregular surface topology.
said first and second wafers having an irregular surface topology.
119. A device as recited in claim 107, wherein:
said first material comprises a first wafer containing electrical devices and having a first non-planar surface; and said first bonding surface comprises a polished and etched deposited oxide layer on said first non-planar surface.
said first material comprises a first wafer containing electrical devices and having a first non-planar surface; and said first bonding surface comprises a polished and etched deposited oxide layer on said first non-planar surface.
120. A device as recited in claim 119, wherein:
said second material comprises a second wafer containing electrical devices and having a second non-planar surface; and said second bonding surface comprises a polished, planarized and etched deposited oxide layer on said second non-planar surface.
said second material comprises a second wafer containing electrical devices and having a second non-planar surface; and said second bonding surface comprises a polished, planarized and etched deposited oxide layer on said second non-planar surface.
121. A method as recited in claim 107, wherein:
said first material comprises a first wafer containing electrical devices and having a first surface with irregular topology; and said first bonding surface comprises a polished, planarized and etched deposited oxide layer on said first surface.
said first material comprises a first wafer containing electrical devices and having a first surface with irregular topology; and said first bonding surface comprises a polished, planarized and etched deposited oxide layer on said first surface.
122. A method as recited in claim 121, comprising:
said second material comprises a second wafer containing electrical devices and having a second surface with irregular topology; and said second bonding surface comprises a polished, planarized and etched deposited oxide layer on said second surface.
said second material comprises a second wafer containing electrical devices and having a second surface with irregular topology; and said second bonding surface comprises a polished, planarized and etched deposited oxide layer on said second surface.
123. A bonded device, comprising:
a first material having a first etched and activated bonding surface terminated with a first desired bonding species; and a second material having a second etched and activated bonding surface terminated with a second desired bonding species bonded to said first bonding surface at room temperature.
a first material having a first etched and activated bonding surface terminated with a first desired bonding species; and a second material having a second etched and activated bonding surface terminated with a second desired bonding species bonded to said first bonding surface at room temperature.
124. A device as recited in claim 123, wherein said species comprise at least one of a silanol group, an NH2 group, a fluorine group and an HF group.
125. A device as recited in claim 123, comprising:
said first and second bonding surfaces each having a defective region located proximate to said surfaces.
said first and second bonding surfaces each having a defective region located proximate to said surfaces.
126. A device as recited in claim 123, wherein said desired species comprises:
a monolayer of one of a desired atom and a desired molecule on said bonding surface.
a monolayer of one of a desired atom and a desired molecule on said bonding surface.
127. A device as recited in claim 123, comprising:
said second bonding surface bonded to said first bonding surface at room temperature having a bonding strength of at least 500 to 2000 mJ/m2.
said second bonding surface bonded to said first bonding surface at room temperature having a bonding strength of at least 500 to 2000 mJ/m2.
128. A device as recited in claim 123, wherein:
said first bonding surface comprises a surface of a first semiconductor wafer having devices formed therein; and said second bonding surface comprises a surface of a second semiconductor wafer having devices formed therein.
said first bonding surface comprises a surface of a first semiconductor wafer having devices formed therein; and said second bonding surface comprises a surface of a second semiconductor wafer having devices formed therein.
129. A device as recited in claim 128, wherein one of said first and second wafers comprises a device region after removing a substantial portion of a substrate of said one of said first and second wafers.
130. A device as recited in claim 123, comprising:
devices in said first and second wafers being interconnected.
devices in said first and second wafers being interconnected.
131. A device as recited in claim 123, comprising:
said first and second wafers being different technologies.
said first and second wafers being different technologies.
132. A device as recited in claim 123, wherein:
one of said first and second wafers comprises an integrated circuit.
one of said first and second wafers comprises an integrated circuit.
133. A device as recited in claim 123, comprising:
devices in said first and second wafers being interconnected.
devices in said first and second wafers being interconnected.
134. A device as recited in claim 123, wherein:
said first material comprises a first wafer containing electrical devices and having a first non-planar surface; and said first bonding surface comprises a polished and etched deposited oxide layer on said first non-planar surface.
said first material comprises a first wafer containing electrical devices and having a first non-planar surface; and said first bonding surface comprises a polished and etched deposited oxide layer on said first non-planar surface.
135. A device as recited in claim 134, wherein:
said second material comprises a second wafer containing electrical devices and having a second non-planar surface; and said second bonding surface comprises a polished, planarized and etched deposited oxide layer on said second non-planar surface.
said second material comprises a second wafer containing electrical devices and having a second non-planar surface; and said second bonding surface comprises a polished, planarized and etched deposited oxide layer on said second non-planar surface.
136. A method as recited in claim 123, wherein:
said first material comprises a first wafer containing electrical devices and having a first surface with irregular topology; and said first bonding surface comprises a polished, planarized and etched deposited oxide layer on said first surface.
said first material comprises a first wafer containing electrical devices and having a first surface with irregular topology; and said first bonding surface comprises a polished, planarized and etched deposited oxide layer on said first surface.
137. A method as recited in claim 123. wherein:
said second material comprises a second wafer containing electrical devices and having a second surface with irregular topology; and said second bonding surface comprises a polished, planarized and etched deposited oxide layer on said second surface.
said second material comprises a second wafer containing electrical devices and having a second surface with irregular topology; and said second bonding surface comprises a polished, planarized and etched deposited oxide layer on said second surface.
138. A method as recited in claim 1, wherein said first and second bonding surfaces are respective surfaces of first and second substrates, the method comprising:
removing a substantial portion of one of said first and second substrates.
removing a substantial portion of one of said first and second substrates.
139. A method as recited in claim 138, comprising:
annealing said bonded substrates after said removing step.
annealing said bonded substrates after said removing step.
140. A method as recited in claim 138, wherein said first and second substrates have first and second electrical devices, the method comprising:
interconnecting said first and second devices after said removing step.
interconnecting said first and second devices after said removing step.
141. A method as recited in claim 91, comprising:
annealing said bonded substrates after said removing step.
annealing said bonded substrates after said removing step.
142. A method as recited in claim 91, comprising:
interconnecting devices in said first and second semiconductor wafers after said removing step.
interconnecting devices in said first and second semiconductor wafers after said removing step.
143. A method as recited in claim 103, comprising:
annealing said bonded substrates after said removing step.
annealing said bonded substrates after said removing step.
144. A device as recited in claim 113, wherein:
said device region comprises an annealed device region.
said device region comprises an annealed device region.
145. A device as recited in claim 129, wherein;
said first and second materials comprise respective first and second substrates; and one of said first and second substrates comprises a substrate region obtained by removing a substantial portion of a substrate of said one of said first and second substrate.
said first and second materials comprise respective first and second substrates; and one of said first and second substrates comprises a substrate region obtained by removing a substantial portion of a substrate of said one of said first and second substrate.
146. A device as recited in claim 145, wherein:
said substrate region comprises an annealed substrate region.
said substrate region comprises an annealed substrate region.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/505,283 US6902987B1 (en) | 2000-02-16 | 2000-02-16 | Method for low temperature bonding and bonded structure |
US09/505,283 | 2000-02-16 | ||
PCT/US2001/003683 WO2001061743A1 (en) | 2000-02-16 | 2001-02-15 | Method for low temperature bonding and bonded structure |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2399282A1 true CA2399282A1 (en) | 2001-08-23 |
CA2399282C CA2399282C (en) | 2012-07-03 |
Family
ID=24009686
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA2399282A Expired - Fee Related CA2399282C (en) | 2000-02-16 | 2001-02-15 | Method for low temperature bonding and bonded structure |
Country Status (7)
Country | Link |
---|---|
US (15) | US6902987B1 (en) |
EP (2) | EP1275142A4 (en) |
JP (3) | JP5496439B2 (en) |
KR (3) | KR101298859B1 (en) |
AU (1) | AU2001241447A1 (en) |
CA (1) | CA2399282C (en) |
WO (1) | WO2001061743A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9331149B2 (en) | 2000-02-16 | 2016-05-03 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US9431368B2 (en) | 1999-10-01 | 2016-08-30 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
CN109518129A (en) * | 2017-09-18 | 2019-03-26 | 南昌欧菲光学技术有限公司 | The preparation method of bend glass |
US10434749B2 (en) | 2003-05-19 | 2019-10-08 | Invensas Bonding Technologies, Inc. | Method of room temperature covalent bonding |
Families Citing this family (324)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261B1 (en) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | METHOD FOR THE TRANSFER OF A THIN FILM COMPRISING A STEP OF CREATING INCLUSIONS |
US6500694B1 (en) | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6563133B1 (en) * | 2000-08-09 | 2003-05-13 | Ziptronix, Inc. | Method of epitaxial-like wafer bonding at low temperature and bonded structure |
US7294563B2 (en) * | 2000-08-10 | 2007-11-13 | Applied Materials, Inc. | Semiconductor on insulator vertical transistor fabrication and doping process |
US6893907B2 (en) * | 2002-06-05 | 2005-05-17 | Applied Materials, Inc. | Fabrication of silicon-on-insulator structure using plasma immersion ion implantation |
US6939434B2 (en) | 2000-08-11 | 2005-09-06 | Applied Materials, Inc. | Externally excited torroidal plasma source with magnetic control of ion distribution |
US7094670B2 (en) * | 2000-08-11 | 2006-08-22 | Applied Materials, Inc. | Plasma immersion ion implantation process |
US7816188B2 (en) * | 2001-07-30 | 2010-10-19 | Sandisk 3D Llc | Process for fabricating a dielectric film using plasma oxidation |
US6793759B2 (en) * | 2001-10-09 | 2004-09-21 | Dow Corning Corporation | Method for creating adhesion during fabrication of electronic devices |
US20030113947A1 (en) | 2001-12-19 | 2003-06-19 | Vandentop Gilroy J. | Electrical/optical integration scheme using direct copper bonding |
US20060127599A1 (en) * | 2002-02-12 | 2006-06-15 | Wojak Gregory J | Process and apparatus for preparing a diamond substance |
US6822326B2 (en) * | 2002-09-25 | 2004-11-23 | Ziptronix | Wafer bonding hermetic encapsulation |
FR2846788B1 (en) * | 2002-10-30 | 2005-06-17 | PROCESS FOR PRODUCING DETACHABLE SUBSTRATES | |
FR2847077B1 (en) | 2002-11-12 | 2006-02-17 | Soitec Silicon On Insulator | SEMICONDUCTOR COMPONENTS, PARTICULARLY OF THE MIXED SOI TYPE, AND METHOD OF MAKING SAME |
JP2006520088A (en) * | 2002-12-04 | 2006-08-31 | ズス・マイクロテック・リソグラフィ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツング | Method and apparatus for pretreatment of substrates to be bonded |
US20040126993A1 (en) * | 2002-12-30 | 2004-07-01 | Chan Kevin K. | Low temperature fusion bonding with high surface energy using a wet chemical treatment |
US6962835B2 (en) | 2003-02-07 | 2005-11-08 | Ziptronix, Inc. | Method for room temperature metal direct bonding |
FR2857953B1 (en) * | 2003-07-21 | 2006-01-13 | Commissariat Energie Atomique | STACKED STRUCTURE, AND METHOD FOR MANUFACTURING THE SAME |
US7122481B2 (en) * | 2003-07-25 | 2006-10-17 | Intel Corporation | Sealing porous dielectrics with silane coupling reagents |
FR2858461B1 (en) * | 2003-07-30 | 2005-11-04 | Soitec Silicon On Insulator | IMPLEMENTING A STRUCTURE COMPRISING A PROTECTIVE LAYER AGAINST CHEMICAL TREATMENTS |
JP3980539B2 (en) * | 2003-08-29 | 2007-09-26 | 唯知 須賀 | Substrate bonding method, irradiation method, and substrate bonding apparatus |
DE10344113A1 (en) * | 2003-09-24 | 2005-05-04 | Erich Thallner | Apparatus and method for joining wafers |
FR2861497B1 (en) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | METHOD FOR CATASTROPHIC TRANSFER OF A FINE LAYER AFTER CO-IMPLANTATION |
US7084460B2 (en) * | 2003-11-03 | 2006-08-01 | International Business Machines Corporation | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates |
FR2863405B1 (en) | 2003-12-08 | 2006-02-03 | Commissariat Energie Atomique | MOLECULAR BONDING OF MICROELECTRONIC COMPONENTS ON A POLYMERIC FILM |
FR2864336B1 (en) * | 2003-12-23 | 2006-04-28 | Commissariat Energie Atomique | METHOD FOR SEALING TWO PLATES WITH FORMATION OF AN OHMIC CONTACT BETWEEN THEM |
FR2864970B1 (en) * | 2004-01-09 | 2006-03-03 | Soitec Silicon On Insulator | SUPPORT SUBSTRATE WITH THERMAL EXPANSION COEFFICIENT DETERMINED |
US7422384B2 (en) * | 2004-03-17 | 2008-09-09 | Hewlett-Packard Development, L.P. | System and a method for printing small print jobs |
JP4411123B2 (en) * | 2004-03-31 | 2010-02-10 | 新光電気工業株式会社 | Manufacturing method of heat sink |
US7087134B2 (en) * | 2004-03-31 | 2006-08-08 | Hewlett-Packard Development Company, L.P. | System and method for direct-bonding of substrates |
CN1942281A (en) * | 2004-04-08 | 2007-04-04 | 松下电器产业株式会社 | Joining method and device therefor |
FR2871291B1 (en) * | 2004-06-02 | 2006-12-08 | Tracit Technologies | PROCESS FOR TRANSFERRING PLATES |
FR2872627B1 (en) * | 2004-06-30 | 2006-08-18 | Commissariat Energie Atomique | MOLECULAR ADHESION ASSEMBLY OF TWO SUBSTRATES |
US7261793B2 (en) * | 2004-08-13 | 2007-08-28 | Hewlett-Packard Development Company, L.P. | System and method for low temperature plasma-enhanced bonding |
JP2006080314A (en) * | 2004-09-09 | 2006-03-23 | Canon Inc | Manufacturing method of coupled substrate |
US7262495B2 (en) | 2004-10-07 | 2007-08-28 | Hewlett-Packard Development Company, L.P. | 3D interconnect with protruding contacts |
WO2006047326A1 (en) * | 2004-10-21 | 2006-05-04 | Fujifilm Dimatix, Inc. | Sacrificial substrate for etching |
ATE536263T1 (en) * | 2004-10-26 | 2011-12-15 | Hewlett Packard Development Co | METHOD FOR PLASMA-REINFORCED BONDING AND COMPOSITE STRUCTURES PRODUCED BY PLASMA-REINFORCED BONDING |
US7563691B2 (en) * | 2004-10-29 | 2009-07-21 | Hewlett-Packard Development Company, L.P. | Method for plasma enhanced bonding and bonded structures formed by plasma enhanced bonding |
US7238589B2 (en) * | 2004-11-01 | 2007-07-03 | International Business Machines Corporation | In-place bonding of microstructures |
FR2879208B1 (en) * | 2004-12-15 | 2007-02-09 | Commissariat Energie Atomique | METHOD OF BONDING TWO FREE SURFACES, RESPECTIVELY OF FIRST AND SECOND DIFFERENT SUBSTRATES |
FR2879183B1 (en) * | 2004-12-15 | 2007-04-27 | Atmel Grenoble Soc Par Actions | METHOD FOR THE COLLECTIVE MANUFACTURE OF MICROSTRUCTURES WITH OVERLAPPING ELEMENTS |
US7372145B2 (en) * | 2005-02-28 | 2008-05-13 | Silverbrook Research Pty Ltd | Bonded assembly having improved adhesive bond strength |
US7425052B2 (en) * | 2005-02-28 | 2008-09-16 | Silverbrook Research Pty Ltd | Printhead assembly having improved adhesive bond strength |
JP2006258958A (en) * | 2005-03-15 | 2006-09-28 | Shibaura Mechatronics Corp | Method and device for bonding substrate |
US9153645B2 (en) | 2005-05-17 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US20070267722A1 (en) * | 2006-05-17 | 2007-11-22 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
CN101300663B (en) * | 2005-05-17 | 2010-12-01 | 台湾积体电路制造股份有限公司 | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
JP2007012788A (en) * | 2005-06-29 | 2007-01-18 | Elpida Memory Inc | Method of manufacturing semiconductor device |
FR2888402B1 (en) * | 2005-07-06 | 2007-12-21 | Commissariat Energie Atomique | METHOD FOR ASSEMBLING SUBSTRATES BY DEPOSITING A THIN OXIDE OR NITRIDE BONDING LAYER AND STRUCTURE THUS ASSEMBLED |
FR2888663B1 (en) * | 2005-07-13 | 2008-04-18 | Soitec Silicon On Insulator | METHOD OF REDUCING THE ROUGHNESS OF A THICK LAYER OF INSULATION |
KR101329388B1 (en) * | 2005-07-26 | 2013-11-14 | 앰버웨이브 시스템즈 코포레이션 | Solutions for integrated circuit integration of alternative active area materials |
US7674687B2 (en) * | 2005-07-27 | 2010-03-09 | Silicon Genesis Corporation | Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process |
US8217473B2 (en) * | 2005-07-29 | 2012-07-10 | Hewlett-Packard Development Company, L.P. | Micro electro-mechanical system packaging and interconnect |
US20070023850A1 (en) * | 2005-07-30 | 2007-02-01 | Chien-Hua Chen | Bonding surfaces together via plasma treatment on both surfaces with wet treatment on only one surface |
US20070032044A1 (en) * | 2005-08-08 | 2007-02-08 | Silicon Genesis Corporation | Method and structure for fabricating devices using one or more films provided by a layer transfer process and etch back |
US20070029043A1 (en) * | 2005-08-08 | 2007-02-08 | Silicon Genesis Corporation | Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process |
US7166520B1 (en) * | 2005-08-08 | 2007-01-23 | Silicon Genesis Corporation | Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process |
US7485968B2 (en) | 2005-08-11 | 2009-02-03 | Ziptronix, Inc. | 3D IC method and device |
US7427554B2 (en) * | 2005-08-12 | 2008-09-23 | Silicon Genesis Corporation | Manufacturing strained silicon substrates using a backing material |
FR2889887B1 (en) | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | METHOD FOR DEFERING A THIN LAYER ON A SUPPORT |
US20070048980A1 (en) * | 2005-08-24 | 2007-03-01 | International Business Machines Corporation | Method for post-rie passivation of semiconductor surfaces for epitaxial growth |
US7638842B2 (en) * | 2005-09-07 | 2009-12-29 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures on insulators |
FR2891281B1 (en) | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A THIN FILM ELEMENT |
US7601271B2 (en) * | 2005-11-28 | 2009-10-13 | S.O.I.Tec Silicon On Insulator Technologies | Process and equipment for bonding by molecular adhesion |
US7863157B2 (en) * | 2006-03-17 | 2011-01-04 | Silicon Genesis Corporation | Method and structure for fabricating solar cells using a layer transfer process |
US7371662B2 (en) * | 2006-03-21 | 2008-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a 3D interconnect and resulting structures |
US7777250B2 (en) | 2006-03-24 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures and related methods for device fabrication |
US7378339B2 (en) * | 2006-03-30 | 2008-05-27 | Freescale Semiconductor, Inc. | Barrier for use in 3-D integration of circuits |
US7598153B2 (en) * | 2006-03-31 | 2009-10-06 | Silicon Genesis Corporation | Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species |
CN101512721A (en) | 2006-04-05 | 2009-08-19 | 硅源公司 | Method and structure for fabricating solar cells using a layer transfer process |
US7476289B2 (en) * | 2006-06-29 | 2009-01-13 | Applied Materials, Inc. | Vacuum elastomer bonding apparatus and method |
US8153513B2 (en) * | 2006-07-25 | 2012-04-10 | Silicon Genesis Corporation | Method and system for continuous large-area scanning implantation process |
EP2062290B1 (en) | 2006-09-07 | 2019-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect reduction using aspect ratio trapping |
WO2008036256A1 (en) * | 2006-09-18 | 2008-03-27 | Amberwave Systems Corporation | Aspect ratio trapping for mixed signal applications |
EP2067165A2 (en) * | 2006-09-18 | 2009-06-10 | Nxp B.V. | Method of manufacturing an integrated circuit |
WO2008039534A2 (en) | 2006-09-27 | 2008-04-03 | Amberwave Systems Corporation | Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures |
US7799592B2 (en) | 2006-09-27 | 2010-09-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tri-gate field-effect transistors formed by aspect ratio trapping |
WO2008051503A2 (en) | 2006-10-19 | 2008-05-02 | Amberwave Systems Corporation | Light-emitter-based devices with lattice-mismatched semiconductor structures |
FR2910179B1 (en) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING THIN LAYERS OF GaN BY IMPLANTATION AND RECYCLING OF A STARTING SUBSTRATE |
FR2912839B1 (en) * | 2007-02-16 | 2009-05-15 | Soitec Silicon On Insulator | IMPROVING THE QUALITY OF COLD CLEANING INTERFACE BY COLD CLEANING AND HOT COLLAGE |
JP5433927B2 (en) * | 2007-03-14 | 2014-03-05 | 株式会社Sumco | Manufacturing method of bonded wafer |
US8304805B2 (en) | 2009-01-09 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor diodes fabricated by aspect ratio trapping with coalesced films |
US9508890B2 (en) | 2007-04-09 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photovoltaics on silicon |
US7825328B2 (en) | 2007-04-09 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-based multi-junction solar cell modules and methods for making the same |
US8237151B2 (en) | 2009-01-09 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
US8329541B2 (en) | 2007-06-15 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | InP-based transistor fabrication |
SG182214A1 (en) * | 2007-06-20 | 2012-07-30 | Semiconductor Energy Lab | Method of manufacturing semiconductor device |
FR2919427B1 (en) * | 2007-07-26 | 2010-12-03 | Soitec Silicon On Insulator | STRUCTURE A RESERVOIR OF LOADS. |
KR101093588B1 (en) | 2007-09-07 | 2011-12-15 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Multi-junction solar cells |
US20090206275A1 (en) * | 2007-10-03 | 2009-08-20 | Silcon Genesis Corporation | Accelerator particle beam apparatus and method for low contaminate processing |
JP5522917B2 (en) * | 2007-10-10 | 2014-06-18 | 株式会社半導体エネルギー研究所 | Manufacturing method of SOI substrate |
FR2923079B1 (en) * | 2007-10-26 | 2017-10-27 | S O I Tec Silicon On Insulator Tech | SUBSTRATES SOI WITH INSULATED FINE LAYER ENTERREE |
JP4348454B2 (en) * | 2007-11-08 | 2009-10-21 | 三菱重工業株式会社 | Device and device manufacturing method |
DE102007060785B4 (en) * | 2007-12-17 | 2011-12-15 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method for producing a (multi) component based on ultra-planar metal structures |
FR2925221B1 (en) * | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | METHOD FOR TRANSFERRING A THIN LAYER |
DE102008011354B3 (en) * | 2008-02-27 | 2009-09-24 | Carl Zeiss Smt Ag | Method for joining two components to a composite structure by "fusion bonding" and composite structure, optical element, holding device, projection lens and projection exposure apparatus produced thereby |
DE102008014119B4 (en) * | 2008-03-13 | 2013-11-14 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | A method for producing a 3-dimensional, polymeric material having shaped body, method for producing a coating of polymeric material and a 3-dimensional molded body |
FR2931585B1 (en) * | 2008-05-26 | 2010-09-03 | Commissariat Energie Atomique | NITROGEN PLASMA SURFACE TREATMENT IN A DIRECT COLLECTION PROCESS |
US8183667B2 (en) | 2008-06-03 | 2012-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial growth of crystalline material |
US7972938B2 (en) * | 2008-06-05 | 2011-07-05 | Ues, Inc. | Methods of splitting CdZnTe layers from CdZnTe substrates for the growth of HgCdTe |
US8763682B2 (en) * | 2008-06-20 | 2014-07-01 | Orbital Technologies Corporation | Condensing heat exchanger with hydrophilic antimicrobial coating |
US8274097B2 (en) | 2008-07-01 | 2012-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
US8981427B2 (en) | 2008-07-15 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
KR101548173B1 (en) * | 2008-09-18 | 2015-08-31 | 삼성전자주식회사 | Wafer temporary bonding method using Si direct bondingSDB and semiconductor device and fabricating method thereof using the same bonding method |
EP2528087B1 (en) | 2008-09-19 | 2016-06-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of devices by epitaxial layer overgrowth |
US20100072515A1 (en) | 2008-09-19 | 2010-03-25 | Amberwave Systems Corporation | Fabrication and structures of crystalline material |
US8253211B2 (en) | 2008-09-24 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor sensor structures with reduced dislocation defect densities |
US7863097B2 (en) | 2008-11-07 | 2011-01-04 | Raytheon Company | Method of preparing detectors for oxide bonding to readout integrated chips |
FR2938202B1 (en) * | 2008-11-07 | 2010-12-31 | Soitec Silicon On Insulator | SURFACE TREATMENT FOR MOLECULAR ADHESION |
FR2942911B1 (en) * | 2009-03-09 | 2011-05-13 | Soitec Silicon On Insulator | METHOD FOR PRODUCING A HETEROSTRUCTURE WITH LOCAL ADAPTATION OF THERMAL EXPANSION COEFFICIENT |
WO2010114956A1 (en) | 2009-04-02 | 2010-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices formed from a non-polar plane of a crystalline material and method of making the same |
WO2010127320A2 (en) | 2009-04-30 | 2010-11-04 | Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University | Methods for wafer bonding, and for nucleating bonding nanophases |
JP2012526391A (en) | 2009-05-05 | 2012-10-25 | スリーエム イノベイティブ プロパティズ カンパニー | Semiconductor devices grown on indium-containing substrates using an indium depletion mechanism. |
JP2012526394A (en) | 2009-05-05 | 2012-10-25 | スリーエム イノベイティブ プロパティズ カンパニー | Re-emitting semiconductor carrier element for use with LED and method of manufacture |
WO2011008476A1 (en) | 2009-06-30 | 2011-01-20 | 3M Innovative Properties Company | Cadmium-free re-emitting semiconductor construction |
US8072056B2 (en) | 2009-06-10 | 2011-12-06 | Medtronic, Inc. | Apparatus for restricting moisture ingress |
US8172760B2 (en) | 2009-06-18 | 2012-05-08 | Medtronic, Inc. | Medical device encapsulated within bonded dies |
FR2947098A1 (en) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | METHOD OF TRANSFERRING A THIN LAYER TO A TARGET SUBSTRATE HAVING A THERMAL EXPANSION COEFFICIENT DIFFERENT FROM THAT OF THE THIN LAYER |
KR20120032487A (en) * | 2009-06-24 | 2012-04-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method reprocessing semiconductor substrate and method for manufacturing soi substrate |
US8278187B2 (en) * | 2009-06-24 | 2012-10-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate by stepwise etching with at least two etching treatments |
US8304976B2 (en) | 2009-06-30 | 2012-11-06 | 3M Innovative Properties Company | Electroluminescent devices with color adjustment based on current crowding |
CN102474932B (en) | 2009-06-30 | 2015-12-16 | 3M创新有限公司 | There is the white-light electroluminescence device of adjustable color temperature |
FR2947481B1 (en) * | 2009-07-03 | 2011-08-26 | Commissariat Energie Atomique | SIMPLIFIED COPPER-COPPER BONDING PROCESS |
US8669588B2 (en) * | 2009-07-06 | 2014-03-11 | Raytheon Company | Epitaxially-grown position sensitive detector |
WO2011024619A1 (en) * | 2009-08-25 | 2011-03-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing soi substrate |
US8318588B2 (en) * | 2009-08-25 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
SG178179A1 (en) * | 2009-10-09 | 2012-03-29 | Semiconductor Energy Lab | Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate |
US20110180896A1 (en) * | 2010-01-25 | 2011-07-28 | International Business Machines Corporation | Method of producing bonded wafer structure with buried oxide/nitride layers |
CN102742004B (en) * | 2010-02-04 | 2015-02-25 | 索泰克公司 | Bonded semiconductor structures and methods of forming same |
US8507966B2 (en) | 2010-03-02 | 2013-08-13 | Micron Technology, Inc. | Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same |
US8288795B2 (en) | 2010-03-02 | 2012-10-16 | Micron Technology, Inc. | Thyristor based memory cells, devices and systems including the same and methods for forming the same |
US9608119B2 (en) | 2010-03-02 | 2017-03-28 | Micron Technology, Inc. | Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures |
US9646869B2 (en) | 2010-03-02 | 2017-05-09 | Micron Technology, Inc. | Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices |
US8557679B2 (en) * | 2010-06-30 | 2013-10-15 | Corning Incorporated | Oxygen plasma conversion process for preparing a surface for bonding |
JP5517800B2 (en) | 2010-07-09 | 2014-06-11 | キヤノン株式会社 | Member for solid-state imaging device and method for manufacturing solid-state imaging device |
SG177816A1 (en) | 2010-07-15 | 2012-02-28 | Soitec Silicon On Insulator | Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods |
US8481406B2 (en) | 2010-07-15 | 2013-07-09 | Soitec | Methods of forming bonded semiconductor structures |
FR2963159B1 (en) * | 2010-07-21 | 2018-01-19 | Soitec | METHODS OF FORMING BOUND SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM |
FR2963982B1 (en) | 2010-08-20 | 2012-09-28 | Soitec Silicon On Insulator | LOW TEMPERATURE BONDING PROCESS |
US8666505B2 (en) | 2010-10-26 | 2014-03-04 | Medtronic, Inc. | Wafer-scale package including power source |
CN105374667B (en) * | 2011-01-25 | 2019-01-11 | Ev 集团 E·索尔纳有限责任公司 | Method for permanent engagement chip |
WO2012100786A1 (en) * | 2011-01-25 | 2012-08-02 | Ev Group E. Thallner Gmbh | Method for the permanent bonding of wafers |
US8424388B2 (en) | 2011-01-28 | 2013-04-23 | Medtronic, Inc. | Implantable capacitive pressure sensor apparatus and methods regarding same |
DE102011012834A1 (en) * | 2011-02-22 | 2012-08-23 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method for producing lightweight structural elements |
US8952418B2 (en) | 2011-03-01 | 2015-02-10 | Micron Technology, Inc. | Gated bipolar junction transistors |
US8519431B2 (en) | 2011-03-08 | 2013-08-27 | Micron Technology, Inc. | Thyristors |
CN103477420B (en) | 2011-04-08 | 2016-11-16 | Ev集团E·索尔纳有限责任公司 | The method of permanent adhesive wafer |
CN103460342B (en) * | 2011-04-08 | 2016-12-07 | Ev 集团 E·索尔纳有限责任公司 | The permanent adhesive method of wafer |
US8637800B2 (en) | 2011-04-19 | 2014-01-28 | Altasens, Inc. | Image sensor with hybrid heterostructure |
US8912017B2 (en) | 2011-05-10 | 2014-12-16 | Ostendo Technologies, Inc. | Semiconductor wafer bonding incorporating electrical and optical interconnects |
US9123529B2 (en) | 2011-06-21 | 2015-09-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
US8441087B2 (en) | 2011-07-22 | 2013-05-14 | Raytheon Company | Direct readout focal plane array |
US9064808B2 (en) * | 2011-07-25 | 2015-06-23 | Synopsys, Inc. | Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same |
US8772848B2 (en) | 2011-07-26 | 2014-07-08 | Micron Technology, Inc. | Circuit structures, memory circuitry, and methods |
US10115764B2 (en) | 2011-08-15 | 2018-10-30 | Raytheon Company | Multi-band position sensitive imaging arrays |
US9540545B2 (en) * | 2011-09-02 | 2017-01-10 | Schlumberger Technology Corporation | Plasma treatment in fabricating directional drilling assemblies |
US8609550B2 (en) | 2011-09-08 | 2013-12-17 | Synopsys, Inc. | Methods for manufacturing integrated circuit devices having features with reduced edge curvature |
FR2981940B1 (en) * | 2011-10-26 | 2014-06-06 | Commissariat Energie Atomique | PROCESS FOR DIRECTLY BONDING A SILICON OXIDE LAYER |
FR2981941B1 (en) * | 2011-10-26 | 2014-06-06 | Commissariat Energie Atomique | METHOD FOR DIRECTLY TREATING AND BONDING A LAYER OF MATERIAL |
US8778737B2 (en) | 2011-10-31 | 2014-07-15 | International Business Machines Corporation | Flattened substrate surface for substrate bonding |
US9589801B2 (en) | 2011-10-31 | 2017-03-07 | Arizona Board Of Regents, A Body Corporated Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Methods for wafer bonding and for nucleating bonding nanophases using wet and steam pressurization |
KR101870155B1 (en) | 2012-02-02 | 2018-06-25 | 삼성전자주식회사 | Via Connection Structures and Semiconductor Devices Having the Same, and methods of Fabricating the Sames |
US10543662B2 (en) | 2012-02-08 | 2020-01-28 | Corning Incorporated | Device modified substrate article and methods for making |
US8748885B2 (en) | 2012-02-10 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Soft material wafer bonding and method of bonding |
US10052848B2 (en) * | 2012-03-06 | 2018-08-21 | Apple Inc. | Sapphire laminates |
US9221289B2 (en) | 2012-07-27 | 2015-12-29 | Apple Inc. | Sapphire window |
US8735219B2 (en) | 2012-08-30 | 2014-05-27 | Ziptronix, Inc. | Heterogeneous annealing method and device |
US9418963B2 (en) | 2012-09-25 | 2016-08-16 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State University | Methods for wafer bonding, and for nucleating bonding nanophases |
US10086584B2 (en) | 2012-12-13 | 2018-10-02 | Corning Incorporated | Glass articles and methods for controlled bonding of glass sheets with carriers |
US10014177B2 (en) | 2012-12-13 | 2018-07-03 | Corning Incorporated | Methods for processing electronic devices |
TWI617437B (en) | 2012-12-13 | 2018-03-11 | 康寧公司 | Facilitated processing for controlling bonding between sheet and carrier |
US9340443B2 (en) | 2012-12-13 | 2016-05-17 | Corning Incorporated | Bulk annealing of glass sheets |
CN205159286U (en) * | 2012-12-31 | 2016-04-13 | 菲力尔系统公司 | A device for declining wafer scale of bolometer vacuum packaging subassembly encapsulates |
US9232672B2 (en) | 2013-01-10 | 2016-01-05 | Apple Inc. | Ceramic insert control mechanism |
US8921992B2 (en) * | 2013-03-14 | 2014-12-30 | Raytheon Company | Stacked wafer with coolant channels |
US9678540B2 (en) | 2013-09-23 | 2017-06-13 | Apple Inc. | Electronic component embedded in ceramic material |
US9632537B2 (en) | 2013-09-23 | 2017-04-25 | Apple Inc. | Electronic component embedded in ceramic material |
US10510576B2 (en) | 2013-10-14 | 2019-12-17 | Corning Incorporated | Carrier-bonding methods and articles for semiconductor and interposer processing |
US20160260602A1 (en) * | 2013-11-04 | 2016-09-08 | Applied Materials, Inc. | Adhesion improvements for oxide-silicon stack |
US9154678B2 (en) | 2013-12-11 | 2015-10-06 | Apple Inc. | Cover glass arrangement for an electronic device |
WO2015112958A1 (en) | 2014-01-27 | 2015-07-30 | Corning Incorporated | Articles and methods for controlled bonding of thin sheets with carriers |
US9225056B2 (en) | 2014-02-12 | 2015-12-29 | Apple Inc. | Antenna on sapphire structure |
US20150262902A1 (en) | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
EP3129221A1 (en) | 2014-04-09 | 2017-02-15 | Corning Incorporated | Device modified substrate article and methods for making |
WO2016018288A1 (en) | 2014-07-30 | 2016-02-04 | Hewlett-Packard Development Company, L.P. | Hybrid multilayer device |
WO2016018285A1 (en) | 2014-07-30 | 2016-02-04 | Hewlett-Packard Development Company, L.P. | Optical waveguide resonators |
US9536853B2 (en) | 2014-11-18 | 2017-01-03 | International Business Machines Corporation | Semiconductor device including built-in crack-arresting film structure |
US11069734B2 (en) | 2014-12-11 | 2021-07-20 | Invensas Corporation | Image sensor device |
JP2016171307A (en) * | 2015-03-10 | 2016-09-23 | 株式会社デンソー | Substrate bonding method |
KR102573207B1 (en) | 2015-05-19 | 2023-08-31 | 코닝 인코포레이티드 | Articles and methods for bonding sheets and carriers |
JP6415391B2 (en) * | 2015-06-08 | 2018-10-31 | 東京エレクトロン株式会社 | Surface modification method, program, computer storage medium, surface modification apparatus, and bonding system |
US9741620B2 (en) | 2015-06-24 | 2017-08-22 | Invensas Corporation | Structures and methods for reliable packages |
US11905201B2 (en) | 2015-06-26 | 2024-02-20 | Corning Incorporated | Methods and articles including a sheet and a carrier |
US10406634B2 (en) | 2015-07-01 | 2019-09-10 | Apple Inc. | Enhancing strength in laser cutting of ceramic components |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US9953941B2 (en) | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
CN106653675B (en) * | 2015-08-28 | 2020-07-10 | 中芯国际集成电路制造(北京)有限公司 | Method for forming shallow trench isolation structure |
US10658177B2 (en) | 2015-09-03 | 2020-05-19 | Hewlett Packard Enterprise Development Lp | Defect-free heterogeneous substrates |
EP3141941B1 (en) | 2015-09-10 | 2019-11-27 | ams AG | Semiconductor device with photonic and electronic functionality and method for manufacturing a semiconductor device |
JP6106239B2 (en) * | 2015-09-30 | 2017-03-29 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | Method for permanently bonding a wafer |
US9496239B1 (en) | 2015-12-11 | 2016-11-15 | International Business Machines Corporation | Nitride-enriched oxide-to-oxide 3D wafer bonding |
US9852988B2 (en) | 2015-12-18 | 2017-12-26 | Invensas Bonding Technologies, Inc. | Increased contact alignment tolerance for direct bonding |
FR3045939B1 (en) * | 2015-12-22 | 2018-03-30 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR DIRECT COLLAGE BETWEEN TWO STRUCTURES |
US10446532B2 (en) | 2016-01-13 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Systems and methods for efficient transfer of semiconductor elements |
WO2017123245A1 (en) | 2016-01-15 | 2017-07-20 | Hewlett Packard Enterprise Development Lp | Multilayer device |
US10373830B2 (en) | 2016-03-08 | 2019-08-06 | Ostendo Technologies, Inc. | Apparatus and methods to remove unbonded areas within bonded substrates using localized electromagnetic wave annealing |
US9673220B1 (en) | 2016-03-09 | 2017-06-06 | Globalfoundries Inc. | Chip structures with distributed wiring |
US11088244B2 (en) | 2016-03-30 | 2021-08-10 | Hewlett Packard Enterprise Development Lp | Devices having substrates with selective airgap regions |
US10109983B2 (en) * | 2016-04-28 | 2018-10-23 | Hewlett Packard Enterprise Development Lp | Devices with quantum dots |
US10354975B2 (en) | 2016-05-16 | 2019-07-16 | Raytheon Company | Barrier layer for interconnects in 3D integrated device |
US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
US9941241B2 (en) | 2016-06-30 | 2018-04-10 | International Business Machines Corporation | Method for wafer-wafer bonding |
US9620479B1 (en) | 2016-06-30 | 2017-04-11 | International Business Machines Corporation | 3D bonded semiconductor structure with an embedded resistor |
US9716088B1 (en) | 2016-06-30 | 2017-07-25 | International Business Machines Corporation | 3D bonded semiconductor structure with an embedded capacitor |
US10079471B2 (en) * | 2016-07-08 | 2018-09-18 | Hewlett Packard Enterprise Development Lp | Bonding interface layer |
US10020281B2 (en) | 2016-08-30 | 2018-07-10 | International Business Machines Corporation | Metal bonding pads for packaging applications |
TW202216444A (en) | 2016-08-30 | 2022-05-01 | 美商康寧公司 | Siloxane plasma polymers for sheet bonding |
TWI810161B (en) | 2016-08-31 | 2023-08-01 | 美商康寧公司 | Articles of controllably bonded sheets and methods for making same |
US10193634B2 (en) | 2016-09-19 | 2019-01-29 | Hewlett Packard Enterprise Development Lp | Optical driver circuits |
US9640509B1 (en) | 2016-09-29 | 2017-05-02 | International Business Machines Corporation | Advanced metal-to-metal direct bonding |
US10446487B2 (en) | 2016-09-30 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
US10401099B2 (en) | 2016-10-05 | 2019-09-03 | Raytheon Company | Transparent heat exchanger |
US10762420B2 (en) | 2017-08-03 | 2020-09-01 | Xcelsis Corporation | Self repairing neural network |
US10580735B2 (en) | 2016-10-07 | 2020-03-03 | Xcelsis Corporation | Stacked IC structure with system level wiring on multiple sides of the IC die |
US10566765B2 (en) | 2016-10-27 | 2020-02-18 | Hewlett Packard Enterprise Development Lp | Multi-wavelength semiconductor lasers |
JP2020502786A (en) | 2016-12-16 | 2020-01-23 | ザ ガバメント オブ ザ ユナイテッド ステイツ オブ アメリカ,アズ リプレゼンテッド バイ ザ セクレタリー オブ ザ ネイビー | Selective oxidation of transition metal nitride layers in compound semiconductor device structures |
US10002844B1 (en) | 2016-12-21 | 2018-06-19 | Invensas Bonding Technologies, Inc. | Bonded structures |
JP6673183B2 (en) * | 2016-12-21 | 2020-03-25 | 株式会社Sumco | Method for manufacturing pn junction silicon wafer |
JP2020503692A (en) | 2016-12-29 | 2020-01-30 | インヴェンサス ボンディング テクノロジーズ インコーポレイテッド | Joint structure with integrated passive components |
US10276909B2 (en) | 2016-12-30 | 2019-04-30 | Invensas Bonding Technologies, Inc. | Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein |
US10168475B2 (en) | 2017-01-18 | 2019-01-01 | Juniper Networks, Inc. | Atomic layer deposition bonding for heterogeneous integration of photonics and electronics |
US9998698B1 (en) | 2017-02-01 | 2018-06-12 | Omnivision Technologies, Inc. | Circuitry and method for readout of hybrid-bonded image sensors |
US10375338B2 (en) | 2017-02-01 | 2019-08-06 | Omnivision Technologies, Inc. | Two stage amplifier readout circuit in pixel level hybrid bond image sensors |
US10263031B2 (en) | 2017-02-01 | 2019-04-16 | Omnivision Technologies, Inc. | Feedback capacitor and method for readout of hybrid bonded image sensors |
US10522499B2 (en) | 2017-02-09 | 2019-12-31 | Invensas Bonding Technologies, Inc. | Bonded structures |
US10141391B2 (en) | 2017-02-23 | 2018-11-27 | International Business Machines Corporation | Microstructure modulation for 3D bonded semiconductor containing an embedded resistor structure |
US10141392B2 (en) | 2017-02-23 | 2018-11-27 | International Business Machines Corporation | Microstructure modulation for 3D bonded semiconductor structure with an embedded capacitor |
US10217725B2 (en) | 2017-02-23 | 2019-02-26 | International Business Machines Corporation | Microstructure modulation for metal wafer-wafer bonding |
US10629577B2 (en) | 2017-03-16 | 2020-04-21 | Invensas Corporation | Direct-bonded LED arrays and applications |
US10515913B2 (en) | 2017-03-17 | 2019-12-24 | Invensas Bonding Technologies, Inc. | Multi-metal contact structure |
US10508030B2 (en) | 2017-03-21 | 2019-12-17 | Invensas Bonding Technologies, Inc. | Seal for microelectronic assembly |
WO2018183739A1 (en) | 2017-03-31 | 2018-10-04 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
US10680407B2 (en) | 2017-04-10 | 2020-06-09 | Hewlett Packard Enterprise Development Lp | Multi-wavelength semiconductor comb lasers |
US10515837B2 (en) | 2017-04-13 | 2019-12-24 | Raytheon Company | Method of wafer bonding of dissimilar thickness die |
US10269756B2 (en) | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
US10879212B2 (en) | 2017-05-11 | 2020-12-29 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
US10242967B2 (en) | 2017-05-16 | 2019-03-26 | Raytheon Company | Die encapsulation in oxide bonded wafer stack |
US10446441B2 (en) | 2017-06-05 | 2019-10-15 | Invensas Corporation | Flat metal features for microelectronics applications |
US10217720B2 (en) | 2017-06-15 | 2019-02-26 | Invensas Corporation | Multi-chip modules formed using wafer-level processing of a reconstitute wafer |
US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
US11195748B2 (en) | 2017-09-27 | 2021-12-07 | Invensas Corporation | Interconnect structures and methods for forming same |
US10396521B2 (en) | 2017-09-29 | 2019-08-27 | Hewlett Packard Enterprise Development Lp | Laser |
US11031285B2 (en) | 2017-10-06 | 2021-06-08 | Invensas Bonding Technologies, Inc. | Diffusion barrier collar for interconnects |
US10677542B2 (en) * | 2017-10-23 | 2020-06-09 | Trustees Of Boston University | Enhanced thermal transport across interfaces |
WO2019118660A1 (en) | 2017-12-15 | 2019-06-20 | Corning Incorporated | Method for treating a substrate and method for making articles comprising bonded sheets |
US10923408B2 (en) | 2017-12-22 | 2021-02-16 | Invensas Bonding Technologies, Inc. | Cavity packages |
US11380597B2 (en) | 2017-12-22 | 2022-07-05 | Invensas Bonding Technologies, Inc. | Bonded structures |
US10727219B2 (en) | 2018-02-15 | 2020-07-28 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
US11169326B2 (en) | 2018-02-26 | 2021-11-09 | Invensas Bonding Technologies, Inc. | Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects |
US10847419B2 (en) | 2018-03-14 | 2020-11-24 | Raytheon Company | Stress compensation and relief in bonded wafers |
US11256004B2 (en) * | 2018-03-20 | 2022-02-22 | Invensas Bonding Technologies, Inc. | Direct-bonded lamination for improved image clarity in optical devices |
US11062915B2 (en) | 2018-03-29 | 2021-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Redistribution structures for semiconductor packages and methods of forming the same |
US11056348B2 (en) | 2018-04-05 | 2021-07-06 | Invensas Bonding Technologies, Inc. | Bonding surfaces for microelectronics |
US10790262B2 (en) | 2018-04-11 | 2020-09-29 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
US10964664B2 (en) | 2018-04-20 | 2021-03-30 | Invensas Bonding Technologies, Inc. | DBI to Si bonding for simplified handle wafer |
US10381801B1 (en) | 2018-04-26 | 2019-08-13 | Hewlett Packard Enterprise Development Lp | Device including structure over airgap |
US10319696B1 (en) | 2018-05-10 | 2019-06-11 | Micron Technology, Inc. | Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages |
US11004757B2 (en) | 2018-05-14 | 2021-05-11 | Invensas Bonding Technologies, Inc. | Bonded structures |
US11139402B2 (en) | 2018-05-14 | 2021-10-05 | Synopsys, Inc. | Crystal orientation engineering to achieve consistent nanowire shapes |
US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
KR20210009426A (en) | 2018-06-13 | 2021-01-26 | 인벤사스 본딩 테크놀로지스 인코포레이티드 | TV as a pad |
US11393779B2 (en) | 2018-06-13 | 2022-07-19 | Invensas Bonding Technologies, Inc. | Large metal pads over TSV |
US10910344B2 (en) | 2018-06-22 | 2021-02-02 | Xcelsis Corporation | Systems and methods for releveled bump planes for chiplets |
WO2020010056A1 (en) | 2018-07-03 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Techniques for joining dissimilar materials in microelectronics |
JP7258992B2 (en) * | 2018-07-05 | 2023-04-17 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | Wafer permanent bonding method |
JP6986105B2 (en) * | 2018-07-05 | 2021-12-22 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | Permanent bonding method of wafer |
WO2020010136A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
US11462419B2 (en) | 2018-07-06 | 2022-10-04 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
US10700094B2 (en) * | 2018-08-08 | 2020-06-30 | Xcelsis Corporation | Device disaggregation for improved performance |
US11515291B2 (en) | 2018-08-28 | 2022-11-29 | Adeia Semiconductor Inc. | Integrated voltage regulator and passive components |
US11011494B2 (en) | 2018-08-31 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
CN109461695A (en) * | 2018-10-11 | 2019-03-12 | 德淮半导体有限公司 | A kind of wafer bonding method |
US11158573B2 (en) | 2018-10-22 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Interconnect structures |
CN109411340A (en) * | 2018-10-31 | 2019-03-01 | 德淮半导体有限公司 | Wafer bonding method |
CN109786229B (en) * | 2018-12-05 | 2021-07-02 | 中北大学 | Wafer bonding method and corresponding heterogeneous substrate preparation method |
US11244920B2 (en) | 2018-12-18 | 2022-02-08 | Invensas Bonding Technologies, Inc. | Method and structures for low temperature device bonding |
WO2020150159A1 (en) | 2019-01-14 | 2020-07-23 | Invensas Bonding Technologies, Inc. | Bonded structures |
US11901281B2 (en) | 2019-03-11 | 2024-02-13 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures with integrated passive component |
US10854578B2 (en) | 2019-03-29 | 2020-12-01 | Invensas Corporation | Diffused bitline replacement in stacked wafer memory |
US11373963B2 (en) | 2019-04-12 | 2022-06-28 | Invensas Bonding Technologies, Inc. | Protective elements for bonded structures |
US11205625B2 (en) | 2019-04-12 | 2021-12-21 | Invensas Bonding Technologies, Inc. | Wafer-level bonding of obstructive elements |
US11610846B2 (en) * | 2019-04-12 | 2023-03-21 | Adeia Semiconductor Bonding Technologies Inc. | Protective elements for bonded structures including an obstructive element |
US11264458B2 (en) | 2019-05-20 | 2022-03-01 | Synopsys, Inc. | Crystal orientation engineering to achieve consistent nanowire shapes |
US11385278B2 (en) | 2019-05-23 | 2022-07-12 | Invensas Bonding Technologies, Inc. | Security circuitry for bonded structures |
US10886168B2 (en) | 2019-06-04 | 2021-01-05 | International Business Machines Corporation | Surface modified dielectric refill structure |
US20200395321A1 (en) | 2019-06-12 | 2020-12-17 | Invensas Bonding Technologies, Inc. | Sealed bonded structures and methods for forming the same |
US10971472B2 (en) * | 2019-07-09 | 2021-04-06 | Mikro Mesa Technology Co., Ltd. | Method of liquid assisted bonding |
US11443981B2 (en) * | 2019-08-16 | 2022-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding method of package components and bonding apparatus |
CN110767541A (en) * | 2019-10-28 | 2020-02-07 | 苏师大半导体材料与设备研究院(邳州)有限公司 | Wafer bonding method |
US11862602B2 (en) | 2019-11-07 | 2024-01-02 | Adeia Semiconductor Technologies Llc | Scalable architecture for reduced cycles across SOC |
CN114730714A (en) | 2019-11-21 | 2022-07-08 | 邦德泰克株式会社 | Component mounting system, component supply device, and component mounting method |
US11762200B2 (en) | 2019-12-17 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded optical devices |
US11876076B2 (en) | 2019-12-20 | 2024-01-16 | Adeia Semiconductor Technologies Llc | Apparatus for non-volatile random access memory stacks |
US11842894B2 (en) | 2019-12-23 | 2023-12-12 | Adeia Semiconductor Bonding Technologies Inc. | Electrical redundancy for bonded structures |
US11721653B2 (en) | 2019-12-23 | 2023-08-08 | Adeia Semiconductor Bonding Technologies Inc. | Circuitry for electrical redundancy in bonded structures |
US11854879B2 (en) | 2020-02-26 | 2023-12-26 | Raytheon Company | Cu3Sn via metallization in electrical devices for low-temperature 3D-integration |
US11742314B2 (en) | 2020-03-31 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Reliable hybrid bonded apparatus |
KR20210129346A (en) | 2020-04-20 | 2021-10-28 | 삼성전자주식회사 | Semiconductor device |
WO2021236361A1 (en) | 2020-05-19 | 2021-11-25 | Invensas Bonding Technologies, Inc. | Laterally unconfined structure |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11264357B1 (en) | 2020-10-20 | 2022-03-01 | Invensas Corporation | Mixed exposure for large die |
TW202236439A (en) * | 2020-10-29 | 2022-09-16 | 美商英帆薩斯邦德科技有限公司 | Direct bonding methods and structures |
DE102020131832A1 (en) | 2020-12-01 | 2022-06-02 | Universität Kassel, Körperschaft des öffentlichen Rechts | Process for the manufacture of casting molds or casting cores |
DE102021200230A1 (en) | 2021-01-13 | 2022-07-14 | Robert Bosch Gesellschaft mit beschränkter Haftung | Low temperature bonding method, substrate assembly |
US20230238287A1 (en) * | 2022-01-26 | 2023-07-27 | Applied Materials, Inc. | Methods and apparatus for processing a substrate |
CN114988723A (en) * | 2022-06-01 | 2022-09-02 | 北方夜视技术股份有限公司 | Optical light-transmitting element bonding method based on water glass |
CN114920468B (en) * | 2022-06-01 | 2023-12-05 | 北方夜视技术股份有限公司 | Borosilicate glass hydrophilic bonding method |
CN114975501A (en) * | 2022-07-28 | 2022-08-30 | 晶芯成(北京)科技有限公司 | Wafer bonding method and method for forming backside illuminated image sensor |
US20240105674A1 (en) * | 2022-09-07 | 2024-03-28 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure and method of forming same |
CN116092953B (en) * | 2023-03-07 | 2023-07-18 | 天津中科晶禾电子科技有限责任公司 | Wafer bonding device and method and composite substrate assembly |
Family Cites Families (220)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3587166A (en) | 1965-02-26 | 1971-06-28 | Texas Instruments Inc | Insulated isolation techniques in integrated circuits |
US3423823A (en) | 1965-10-18 | 1969-01-28 | Hewlett Packard Co | Method for making thin diaphragms |
US3488834A (en) | 1965-10-20 | 1970-01-13 | Texas Instruments Inc | Microelectronic circuit formed in an insulating substrate and method of making same |
DE1665794C3 (en) | 1966-10-28 | 1974-06-12 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Method for producing a magnetic field-dependent resistor arrangement |
US3579391A (en) | 1967-01-05 | 1971-05-18 | Trw Inc | Method of producing dielectric isolation for monolithic circuit |
NL158024B (en) | 1967-05-13 | 1978-09-15 | Philips Nv | PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY APPLYING THE PROCEDURE. |
US3508980A (en) | 1967-07-26 | 1970-04-28 | Motorola Inc | Method of fabricating an integrated circuit structure with dielectric isolation |
GB1206308A (en) | 1967-11-22 | 1970-09-23 | Sony Corp | Method of making semiconductor wafer |
GB1186340A (en) | 1968-07-11 | 1970-04-02 | Standard Telephones Cables Ltd | Manufacture of Semiconductor Devices |
NL6910274A (en) | 1969-07-04 | 1971-01-06 | ||
US3888708A (en) | 1972-02-17 | 1975-06-10 | Kensall D Wise | Method for forming regions of predetermined thickness in silicon |
JPS54116888A (en) | 1978-03-03 | 1979-09-11 | Hitachi Ltd | Manufacture of dielectric separate substrate |
JPS54155770A (en) | 1978-05-29 | 1979-12-08 | Nec Corp | Manufacture of semiconductor device |
US4416054A (en) | 1980-07-01 | 1983-11-22 | Westinghouse Electric Corp. | Method of batch-fabricating flip-chip bonded dual integrated circuit arrays |
US4649930A (en) * | 1981-03-06 | 1987-03-17 | Siemens Gammasonics, Inc. | Apparatus for beat buffering techniques varified by arrhythmias detection for stopaction frames of cardiac function |
JPS60167439A (en) | 1984-02-10 | 1985-08-30 | Nec Corp | Manufacture of complementary dielectric isolation substrate |
JPS6130059A (en) | 1984-07-20 | 1986-02-12 | Nec Corp | Manufacture of semiconductor device |
US4617160A (en) | 1984-11-23 | 1986-10-14 | Irvine Sensors Corporation | Method for fabricating modules comprising uniformly stacked, aligned circuit-carrying layers |
US4754544A (en) | 1985-01-30 | 1988-07-05 | Energy Conversion Devices, Inc. | Extremely lightweight, flexible semiconductor device arrays |
JPH0770476B2 (en) * | 1985-02-08 | 1995-07-31 | 株式会社東芝 | Method for manufacturing semiconductor device |
US4649630A (en) | 1985-04-01 | 1987-03-17 | Motorola, Inc. | Process for dielectrically isolated semiconductor structure |
NL8501773A (en) | 1985-06-20 | 1987-01-16 | Philips Nv | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES |
JPS623113A (en) | 1985-06-28 | 1987-01-09 | Nissan Motor Co Ltd | Multi-cylinder internal-combustion engine |
JPS6231138A (en) | 1985-08-02 | 1987-02-10 | Nec Corp | Dielectric isolation semiconductor integrated circuit device |
US4829018A (en) | 1986-06-27 | 1989-05-09 | Wahlstrom Sven E | Multilevel integrated circuits employing fused oxide layers |
EP0251767A3 (en) | 1986-06-30 | 1988-09-07 | Canon Kabushiki Kaisha | Insulated gate type semiconductor device and method of producing the same |
JP2579979B2 (en) | 1987-02-26 | 1997-02-12 | 株式会社東芝 | Method for manufacturing semiconductor device |
JPS63237408A (en) | 1987-03-26 | 1988-10-03 | Sumitomo Metal Mining Co Ltd | Substrate for semiconductor device |
JPS63246841A (en) | 1987-04-02 | 1988-10-13 | Toshiba Corp | Dielectric isolating method of silicon crystal body |
US5196375A (en) | 1987-07-24 | 1993-03-23 | Kabushiki Kaisha Toshiba | Method for manufacturing bonded semiconductor body |
US5121706A (en) * | 1987-10-16 | 1992-06-16 | The Curators Of The University Of Missouri | Apparatus for applying a composite insulative coating to a substrate |
US4963505A (en) | 1987-10-27 | 1990-10-16 | Nippondenso Co., Ltd. | Semiconductor device and method of manufacturing same |
JPH01259546A (en) | 1988-04-08 | 1989-10-17 | Fujitsu Ltd | Manufacture of semiconductor device |
US5354695A (en) | 1992-04-08 | 1994-10-11 | Leedy Glenn J | Membrane dielectric isolation IC fabrication |
JPH0670921B2 (en) * | 1988-06-03 | 1994-09-07 | 松下電器産業株式会社 | Magnetic fluid, method of manufacturing the same, and magnetic seal device using the same |
US4992847A (en) | 1988-06-06 | 1991-02-12 | Regents Of The University Of California | Thin-film chip-to-substrate interconnect and methods for making same |
US5270259A (en) | 1988-06-21 | 1993-12-14 | Hitachi, Ltd. | Method for fabricating an insulating film from a silicone resin using O.sub. |
NL8801981A (en) | 1988-08-09 | 1990-03-01 | Philips Nv | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE |
US4939101A (en) * | 1988-09-06 | 1990-07-03 | General Electric Company | Method of making direct bonded wafers having a void free interface |
JPH0691147B2 (en) | 1988-10-14 | 1994-11-14 | 信越半導体株式会社 | Bonding wafer inspection method |
US4962879A (en) | 1988-12-19 | 1990-10-16 | Duke University | Method for bubble-free bonding of silicon wafers |
JPH02177435A (en) | 1988-12-28 | 1990-07-10 | Sony Corp | Manufacture of semiconductor substrate |
US5070026A (en) | 1989-06-26 | 1991-12-03 | Spire Corporation | Process of making a ferroelectric electronic component and product |
JPH0344067A (en) | 1989-07-11 | 1991-02-25 | Nec Corp | Laminating method of semiconductor substrate |
US5071792A (en) | 1990-11-05 | 1991-12-10 | Harris Corporation | Process for forming extremely thin integrated circuit dice |
CH679158A5 (en) | 1989-07-20 | 1991-12-31 | Recytec S A C O Orfigest S A | |
JP2750163B2 (en) | 1989-08-10 | 1998-05-13 | 沖電気工業株式会社 | Method of manufacturing dielectric separated semiconductor device |
US5383993A (en) | 1989-09-01 | 1995-01-24 | Nippon Soken Inc. | Method of bonding semiconductor substrates |
JPH03101128A (en) | 1989-09-13 | 1991-04-25 | Casio Comput Co Ltd | Manufacture of semiconductor chip |
GB2237929A (en) | 1989-10-23 | 1991-05-15 | Philips Electronic Associated | A method of manufacturing a semiconductor device |
US4978421A (en) | 1989-11-13 | 1990-12-18 | International Business Machines Corporation | Monolithic silicon membrane device fabrication process |
US5849627A (en) | 1990-02-07 | 1998-12-15 | Harris Corporation | Bonded wafer processing with oxidative bonding |
US5387555A (en) * | 1992-09-03 | 1995-02-07 | Harris Corporation | Bonded wafer processing with metal silicidation |
US5081061A (en) | 1990-02-23 | 1992-01-14 | Harris Corporation | Manufacturing ultra-thin dielectrically isolated wafers |
US5034343A (en) | 1990-03-08 | 1991-07-23 | Harris Corporation | Manufacturing ultra-thin wafer using a handle wafer |
US5024723A (en) | 1990-05-07 | 1991-06-18 | Goesele Ulrich M | Method of producing a thin silicon on insulator layer by wafer bonding and chemical thinning |
JPH0719738B2 (en) | 1990-09-06 | 1995-03-06 | 信越半導体株式会社 | Bonded wafer and manufacturing method thereof |
EP0493747B1 (en) * | 1990-12-25 | 1996-07-10 | Matsushita Electric Industrial Co., Ltd. | Anti-contaminating adsorbed film and method of manufacturing the same |
JPH07118505B2 (en) | 1990-12-28 | 1995-12-18 | 信越半導体株式会社 | Method for manufacturing dielectric isolation substrate |
CA2059733C (en) * | 1991-01-23 | 1999-10-05 | Kazufumi Ogawa | Water- and oil-repelling film and method of manufacturing the same |
US5747857A (en) | 1991-03-13 | 1998-05-05 | Matsushita Electric Industrial Co., Ltd. | Electronic components having high-frequency elements and methods of manufacture therefor |
US5668057A (en) | 1991-03-13 | 1997-09-16 | Matsushita Electric Industrial Co., Ltd. | Methods of manufacture for electronic components having high-frequency elements |
JP2812405B2 (en) | 1991-03-15 | 1998-10-22 | 信越半導体株式会社 | Semiconductor substrate manufacturing method |
US5162251A (en) | 1991-03-18 | 1992-11-10 | Hughes Danbury Optical Systems, Inc. | Method for making thinned charge-coupled devices |
DE4115046A1 (en) | 1991-05-08 | 1992-11-12 | Fraunhofer Ges Forschung | DIRECT SUBSTRATE BONDING |
US5451547A (en) | 1991-08-26 | 1995-09-19 | Nippondenso Co., Ltd. | Method of manufacturing semiconductor substrate |
US5270261A (en) | 1991-09-13 | 1993-12-14 | International Business Machines Corporation | Three dimensional multichip package methods of fabrication |
JP3134391B2 (en) * | 1991-09-19 | 2001-02-13 | 株式会社デンソー | Silicon substrate bonding method |
US5266511A (en) | 1991-10-02 | 1993-11-30 | Fujitsu Limited | Process for manufacturing three dimensional IC's |
US5561303A (en) | 1991-11-07 | 1996-10-01 | Harris Corporation | Silicon on diamond circuit structure |
US5207864A (en) * | 1991-12-30 | 1993-05-04 | Bell Communications Research | Low-temperature fusion of dissimilar semiconductors |
JP3187109B2 (en) | 1992-01-31 | 2001-07-11 | キヤノン株式会社 | Semiconductor member and method of manufacturing the same |
US5234860A (en) | 1992-03-19 | 1993-08-10 | Eastman Kodak Company | Thinning of imaging device processed wafers |
US5321301A (en) | 1992-04-08 | 1994-06-14 | Nec Corporation | Semiconductor device |
JPH05299578A (en) | 1992-04-17 | 1993-11-12 | Rohm Co Ltd | Semiconductor device and manufacture thereof |
US5236118A (en) | 1992-05-12 | 1993-08-17 | The Regents Of The University Of California | Aligned wafer bonding |
US5427638A (en) | 1992-06-04 | 1995-06-27 | Alliedsignal Inc. | Low temperature reaction bonding |
DE69321430T2 (en) | 1992-07-08 | 1999-04-29 | Matsushita Electric Ind Co Ltd | Optical waveguide and its manufacturing process |
JPH06291587A (en) | 1992-07-08 | 1994-10-18 | Matsushita Electric Ind Co Ltd | Piezoelectric vibrator |
US5489554A (en) | 1992-07-21 | 1996-02-06 | Hughes Aircraft Company | Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer |
US5910669A (en) | 1992-07-24 | 1999-06-08 | Siliconix Incorporated | Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof |
JP3192000B2 (en) | 1992-08-25 | 2001-07-23 | キヤノン株式会社 | Semiconductor substrate and manufacturing method thereof |
JPH06112451A (en) | 1992-09-29 | 1994-04-22 | Nagano Denshi Kogyo Kk | Manufacture of soi substrate |
US5324687A (en) | 1992-10-16 | 1994-06-28 | General Electric Company | Method for thinning of integrated circuit chips for lightweight packaged electronic systems |
KR0137125B1 (en) | 1992-11-16 | 1998-06-15 | 모리시타 요이찌 | An optical wave guide device and a method for fabricating the same |
US5503704A (en) * | 1993-01-06 | 1996-04-02 | The Regents Of The University Of California | Nitrogen based low temperature direct bonding |
WO2004077537A1 (en) | 1993-01-18 | 2004-09-10 | Shinsuke Sakai | Method of fabrication of semiconductor substrate |
US5591678A (en) | 1993-01-19 | 1997-01-07 | He Holdings, Inc. | Process of manufacturing a microelectric device using a removable support substrate and etch-stop |
US5353498A (en) | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
JP2701709B2 (en) * | 1993-02-16 | 1998-01-21 | 株式会社デンソー | Method and apparatus for directly joining two materials |
US5349207A (en) | 1993-02-22 | 1994-09-20 | Texas Instruments Incorporated | Silicon carbide wafer bonded to a silicon wafer |
US5272104A (en) | 1993-03-11 | 1993-12-21 | Harris Corporation | Bonded wafer process incorporating diamond insulator |
US5516727A (en) | 1993-04-19 | 1996-05-14 | International Business Machines Corporation | Method for encapsulating light emitting diodes |
EP0695494B1 (en) | 1993-04-23 | 2001-02-14 | Irvine Sensors Corporation | Electronic module comprising a stack of ic chips |
DE69426789T2 (en) | 1993-04-28 | 2001-08-02 | Matsushita Electric Ind Co Ltd | Surface acoustic wave device and manufacturing method therefor |
US5737192A (en) | 1993-04-30 | 1998-04-07 | The United States Of America As Represented By The Secretary Of The Air Force | Density improvement in integration modules |
US5647932A (en) | 1993-05-18 | 1997-07-15 | Matsushita Electric Industrial Co., Ltd. | Method of processing a piezoelectric device |
JP2771423B2 (en) | 1993-05-20 | 1998-07-02 | 日本電気株式会社 | Bipolar transistor |
US5441591A (en) | 1993-06-07 | 1995-08-15 | The United States Of America As Represented By The Secretary Of The Navy | Silicon to sapphire bond |
JPH06350371A (en) | 1993-06-10 | 1994-12-22 | Matsushita Electric Ind Co Ltd | Manufacture of piezoelectric device |
JP2856030B2 (en) | 1993-06-29 | 1999-02-10 | 信越半導体株式会社 | Method for manufacturing bonded wafer |
US5659192A (en) * | 1993-06-30 | 1997-08-19 | Honeywell Inc. | SOI substrate fabrication |
US5376579A (en) | 1993-07-02 | 1994-12-27 | The United States Of America As Represented By The Secretary Of The Air Force | Schemes to form silicon-on-diamond structure |
JP3806151B2 (en) | 1993-07-13 | 2006-08-09 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for coupling first object to second object |
JP3644980B2 (en) | 1993-09-06 | 2005-05-11 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
US6004865A (en) * | 1993-09-06 | 1999-12-21 | Hitachi, Ltd. | Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator |
EP1178530A2 (en) | 1993-09-30 | 2002-02-06 | Kopin Corporation | Three-dimensional processor using transferred thin film circuits |
JPH07193294A (en) | 1993-11-01 | 1995-07-28 | Matsushita Electric Ind Co Ltd | Electronic component and its manufacture |
EP0657900B1 (en) | 1993-12-06 | 1998-03-25 | Matsushita Electric Industrial Co., Ltd. | Hybrid magnetic structure and method for producing the same |
US5460659A (en) | 1993-12-10 | 1995-10-24 | Spectrolab, Inc. | Concentrating photovoltaic module and fabrication method |
US5413955A (en) | 1993-12-21 | 1995-05-09 | Delco Electronics Corporation | Method of bonding silicon wafers at temperatures below 500 degrees centigrade for sensor applications |
DE4400985C1 (en) | 1994-01-14 | 1995-05-11 | Siemens Ag | Method for producing a three-dimensional circuit arrangement |
TW289837B (en) | 1994-01-18 | 1996-11-01 | Hwelett Packard Co | |
FR2715502B1 (en) * | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Structure having cavities and method for producing such a structure. |
US5413952A (en) | 1994-02-02 | 1995-05-09 | Motorola, Inc. | Direct wafer bonded structure method of making |
JP3294934B2 (en) | 1994-03-11 | 2002-06-24 | キヤノン株式会社 | Method for manufacturing semiconductor substrate and semiconductor substrate |
US5380681A (en) | 1994-03-21 | 1995-01-10 | United Microelectronics Corporation | Three-dimensional multichip package and methods of fabricating |
US5362659A (en) | 1994-04-25 | 1994-11-08 | The United States Of America As Represented By The Secretary Of The Navy | Method for fabricating vertical bipolar junction transistors in silicon bonded to an insulator |
US5753529A (en) | 1994-05-05 | 1998-05-19 | Siliconix Incorporated | Surface mount and flip chip technology for total integrated circuit isolation |
US5627106A (en) | 1994-05-06 | 1997-05-06 | United Microelectronics Corporation | Trench method for three dimensional chip connecting during IC fabrication |
JPH0845699A (en) | 1994-05-24 | 1996-02-16 | Sony Corp | Plasma control method and plasma processing device |
US6326248B1 (en) * | 1994-06-02 | 2001-12-04 | Semiconductor Energy Laboratory Co., Ltd. | Process for fabricating semiconductor device |
US5517754A (en) | 1994-06-02 | 1996-05-21 | International Business Machines Corporation | Fabrication processes for monolithic electronic modules |
DE59510807D1 (en) | 1994-07-05 | 2003-11-20 | Infineon Technologies Ag | METHOD FOR PRODUCING A THREE-DIMENSIONAL CIRCUIT ARRANGEMENT |
US5880010A (en) | 1994-07-12 | 1999-03-09 | Sun Microsystems, Inc. | Ultrathin electronics |
KR960009074A (en) | 1994-08-29 | 1996-03-22 | 모리시다 요이치 | Semiconductor device and manufacturing method thereof |
DE4433833A1 (en) | 1994-09-22 | 1996-03-28 | Fraunhofer Ges Forschung | Method for producing a three-dimensional integrated circuit while achieving high system yields |
DE4433846C2 (en) | 1994-09-22 | 1999-06-02 | Fraunhofer Ges Forschung | Method of making a vertical integrated circuit structure |
DE4433845A1 (en) * | 1994-09-22 | 1996-03-28 | Fraunhofer Ges Forschung | Method of manufacturing a three-dimensional integrated circuit |
WO1996013060A1 (en) | 1994-10-24 | 1996-05-02 | Daimler-Benz Aktiengesellschaft | Method for directly connecting flat bodies and articles produced according to said method from said flat bodies |
JPH08195334A (en) * | 1994-11-17 | 1996-07-30 | Canon Inc | Method for bonding silicon substrate |
US5841197A (en) | 1994-11-18 | 1998-11-24 | Adamic, Jr.; Fred W. | Inverted dielectric isolation process |
US5534465A (en) | 1995-01-10 | 1996-07-09 | At&T Corp. | Method for making multichip circuits using active semiconductor substrates |
US5547896A (en) | 1995-02-13 | 1996-08-20 | Harris Corporation | Direct etch for thin film resistor using a hard mask |
NL1000100C2 (en) * | 1995-04-10 | 1996-10-11 | Pacques Bv | A settling device for a liquid, gas, and particulate material contains fluid, as well as a cleaning device and a method for cleaning waste water provided with this. |
US5673478A (en) | 1995-04-28 | 1997-10-07 | Texas Instruments Incorporated | Method of forming an electronic device having I/O reroute |
JP2679681B2 (en) | 1995-04-28 | 1997-11-19 | 日本電気株式会社 | Semiconductor device, package for semiconductor device, and manufacturing method thereof |
DE19516487C1 (en) | 1995-05-05 | 1996-07-25 | Fraunhofer Ges Forschung | Vertical integration process for microelectronic system |
JP3328102B2 (en) | 1995-05-08 | 2002-09-24 | 松下電器産業株式会社 | Surface acoustic wave device and method of manufacturing the same |
EP0742598B1 (en) | 1995-05-08 | 2000-08-02 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing a composite substrate and a piezoelectric device using the substrate |
US5915193A (en) | 1995-05-18 | 1999-06-22 | Tong; Qin-Yi | Method for the cleaning and direct bonding of solids |
US5661901A (en) | 1995-07-10 | 1997-09-02 | Micron Technology, Inc. | Method for mounting and electrically interconnecting semiconductor dice |
US5759753A (en) | 1995-07-19 | 1998-06-02 | Matsushita Electric Industrial Co., Ltd. | Piezoelectric device and method of manufacturing the same |
US5691248A (en) | 1995-07-26 | 1997-11-25 | International Business Machines Corporation | Methods for precise definition of integrated circuit chip edges |
TW374211B (en) | 1995-08-03 | 1999-11-11 | Ibm | Machine structures fabricated of multiple microstructure layers |
US5652436A (en) | 1995-08-14 | 1997-07-29 | Kobe Steel Usa Inc. | Smooth diamond based mesa structures |
US5653019A (en) | 1995-08-31 | 1997-08-05 | Regents Of The University Of California | Repairable chip bonding/interconnect process |
JPH0982588A (en) * | 1995-09-12 | 1997-03-28 | Denso Corp | Direct bonding method for nitride and direct bonded object |
US5669057A (en) * | 1995-10-03 | 1997-09-16 | Xerox Corporation | Reproduction machine having a tandem automatic document handler |
CN1132223C (en) | 1995-10-06 | 2003-12-24 | 佳能株式会社 | Semiconductor substrate and producing method thereof |
DE19543540C1 (en) | 1995-11-22 | 1996-11-21 | Siemens Ag | Vertically integrated semiconductor component |
US5567657A (en) | 1995-12-04 | 1996-10-22 | General Electric Company | Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers |
JP3250722B2 (en) | 1995-12-12 | 2002-01-28 | キヤノン株式会社 | Method and apparatus for manufacturing SOI substrate |
JP3250721B2 (en) * | 1995-12-12 | 2002-01-28 | キヤノン株式会社 | Method for manufacturing SOI substrate |
DE69718693T2 (en) | 1996-03-08 | 2003-11-27 | Matsushita Electric Ind Co Ltd | Electronic component and manufacturing process |
JPH09252100A (en) * | 1996-03-18 | 1997-09-22 | Shin Etsu Handotai Co Ltd | Manufacture of bonded wafer and the wafer manufactured by the method |
US5858876A (en) | 1996-04-01 | 1999-01-12 | Chartered Semiconductor Manufacturing, Ltd. | Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layer |
JPH09331049A (en) * | 1996-04-08 | 1997-12-22 | Canon Inc | Pasted soi substrate and its production |
US5760478A (en) | 1996-08-20 | 1998-06-02 | International Business Machines Corporation | Clock skew minimization system and method for integrated circuits |
JP2791429B2 (en) * | 1996-09-18 | 1998-08-27 | 工業技術院長 | Room-temperature bonding of silicon wafers |
US5783477A (en) | 1996-09-20 | 1998-07-21 | Hewlett-Packard Company | Method for bonding compounds semiconductor wafers to create an ohmic interface |
DE19639682A1 (en) | 1996-09-26 | 1998-04-02 | Fraunhofer Ges Forschung | Process for the permanent bonding of inorganic substrates |
US5807783A (en) | 1996-10-07 | 1998-09-15 | Harris Corporation | Surface mount die by handle replacement |
JPH10223495A (en) | 1997-02-04 | 1998-08-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device having flexible structure and manufacture thereof |
JP3765902B2 (en) | 1997-02-19 | 2006-04-12 | 株式会社半導体エネルギー研究所 | Manufacturing method of semiconductor device and manufacturing method of electronic device |
US5990562A (en) | 1997-02-25 | 1999-11-23 | International Business Machines Corporation | Semiconductor devices having backside probing capability |
JP3604026B2 (en) * | 1997-02-27 | 2004-12-22 | 三菱住友シリコン株式会社 | Manufacturing method of bonded silicon substrate |
US5929512A (en) | 1997-03-18 | 1999-07-27 | Jacobs; Richard L. | Urethane encapsulated integrated circuits and compositions therefor |
CA2233115C (en) | 1997-03-27 | 2002-03-12 | Canon Kabushiki Kaisha | Semiconductor substrate and method of manufacturing the same |
JPH10275752A (en) | 1997-03-28 | 1998-10-13 | Ube Ind Ltd | Laminated wafer, its manufacture and board |
US6284085B1 (en) * | 1997-04-03 | 2001-09-04 | The Board Of Trustees Of The Leland Stanford Junior University | Ultra precision and reliable bonding method |
US5915167A (en) | 1997-04-04 | 1999-06-22 | Elm Technology Corporation | Three dimensional structure memory |
US6551857B2 (en) | 1997-04-04 | 2003-04-22 | Elm Technology Corporation | Three dimensional structure integrated circuits |
US5889302A (en) | 1997-04-21 | 1999-03-30 | Advanced Micro Devices, Inc. | Multilayer floating gate field effect transistor structure for use in integrated circuit devices |
US5936280A (en) | 1997-04-21 | 1999-08-10 | Advanced Micro Devices, Inc. | Multilayer quadruple gate field effect transistor structure for use in integrated circuit devices |
JPH10294995A (en) | 1997-04-21 | 1998-11-04 | Matsushita Electric Ind Co Ltd | Dripproof ultrasonic wave transmitter |
US6270202B1 (en) | 1997-04-24 | 2001-08-07 | Matsushita Electric Industrial Co., Ltd. | Liquid jetting apparatus having a piezoelectric drive element directly bonded to a casing |
JP3920399B2 (en) | 1997-04-25 | 2007-05-30 | 株式会社東芝 | Multi-chip semiconductor device chip alignment method, and multi-chip semiconductor device manufacturing method and manufacturing apparatus |
US5877070A (en) | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
US6097096A (en) | 1997-07-11 | 2000-08-01 | Advanced Micro Devices | Metal attachment method and structure for attaching substrates at low temperatures |
EP0895282A3 (en) | 1997-07-30 | 2000-01-26 | Canon Kabushiki Kaisha | Method of preparing a SOI substrate by using a bonding process, and SOI substrate produced by the same |
EP1018153A1 (en) * | 1997-08-29 | 2000-07-12 | Sharon N. Farrens | In situ plasma wafer bonding method |
JP3324469B2 (en) * | 1997-09-26 | 2002-09-17 | 信越半導体株式会社 | Method for producing SOI wafer and SOI wafer produced by this method |
US5990472A (en) | 1997-09-29 | 1999-11-23 | Mcnc | Microelectronic radiation detectors for detecting and emitting radiation signals |
JP4439602B2 (en) | 1997-09-29 | 2010-03-24 | 株式会社東芝 | Manufacturing method of semiconductor device |
US5966622A (en) | 1997-10-08 | 1999-10-12 | Lucent Technologies Inc. | Process for bonding crystalline substrates with different crystal lattices |
SG71903A1 (en) * | 1998-01-30 | 2000-04-18 | Canon Kk | Process of reclamation of soi substrate and reproduced substrate |
JP4085459B2 (en) | 1998-03-02 | 2008-05-14 | セイコーエプソン株式会社 | Manufacturing method of three-dimensional device |
EP1062692A1 (en) * | 1998-03-09 | 2000-12-27 | Harris Corporation | Devices formable by low temperature direct bonding |
US6153495A (en) * | 1998-03-09 | 2000-11-28 | Intersil Corporation | Advanced methods for making semiconductor devices by low temperature direct bonding |
US6274892B1 (en) | 1998-03-09 | 2001-08-14 | Intersil Americas Inc. | Devices formable by low temperature direct bonding |
US5877516A (en) | 1998-03-20 | 1999-03-02 | The United States Of America As Represented By The Secretary Of The Army | Bonding of silicon carbide directly to a semiconductor substrate by using silicon to silicon bonding |
DE19813239C1 (en) | 1998-03-26 | 1999-12-23 | Fraunhofer Ges Forschung | Wiring method for manufacturing a vertical integrated circuit structure and vertical integrated circuit structure |
US6028365A (en) | 1998-03-30 | 2000-02-22 | Micron Technology, Inc. | Integrated circuit package and method of fabrication |
US5980770A (en) | 1998-04-16 | 1999-11-09 | Siemens Aktiengesellschaft | Removal of post-RIE polymer on Al/Cu metal line |
DE19818962A1 (en) * | 1998-04-28 | 1999-11-04 | Degussa | Method for connecting two solid bodies and the component produced in this way |
JP3697106B2 (en) | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | Method for manufacturing semiconductor substrate and method for manufacturing semiconductor thin film |
US6136691A (en) | 1998-05-26 | 2000-10-24 | Taiwan Semiconductor Manufacturing Corporation | In situ plasma clean for tungsten etching back |
US6316332B1 (en) | 1998-11-30 | 2001-11-13 | Lo Yu-Hwa | Method for joining wafers at a low temperature and low stress |
US6236141B1 (en) | 1998-12-14 | 2001-05-22 | Matsushita Electric Industrial Co., Ltd. | Surface acoustic wave element |
US6194323B1 (en) | 1998-12-16 | 2001-02-27 | Lucent Technologies Inc. | Deep sub-micron metal etch with in-situ hard mask etch |
TW389965B (en) | 1998-12-31 | 2000-05-11 | San Fu Chemical Co Ltd | Method for improving reliability of a gate oxide layer by NF3 annealing |
US6328796B1 (en) * | 1999-02-01 | 2001-12-11 | The United States Of America As Represented By The Secretary Of The Navy | Single-crystal material on non-single-crystalline substrate |
US6323108B1 (en) | 1999-07-27 | 2001-11-27 | The United States Of America As Represented By The Secretary Of The Navy | Fabrication ultra-thin bonded semiconductor layers |
US6242324B1 (en) * | 1999-08-10 | 2001-06-05 | The United States Of America As Represented By The Secretary Of The Navy | Method for fabricating singe crystal materials over CMOS devices |
US6255899B1 (en) | 1999-09-01 | 2001-07-03 | International Business Machines Corporation | Method and apparatus for increasing interchip communications rates |
KR100462980B1 (en) | 1999-09-13 | 2004-12-23 | 비쉐이 메저먼츠 그룹, 인코포레이티드 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
US6984571B1 (en) | 1999-10-01 | 2006-01-10 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6500694B1 (en) * | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6197663B1 (en) | 1999-12-07 | 2001-03-06 | Lucent Technologies Inc. | Process for fabricating integrated circuit devices having thin film transistors |
US6902987B1 (en) | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
GR1003602B (en) | 2000-02-29 | 2001-06-19 | Αλεξανδρος Γεωργακιλας | Procedure for the wafer scale intergration of gallium arsenide based optoelectronic devices with silicon based integrated circuits |
US6962835B2 (en) * | 2003-02-07 | 2005-11-08 | Ziptronix, Inc. | Method for room temperature metal direct bonding |
US7109092B2 (en) | 2003-05-19 | 2006-09-19 | Ziptronix, Inc. | Method of room temperature covalent bonding |
FR2884966B1 (en) * | 2005-04-22 | 2007-08-17 | Soitec Silicon On Insulator | METHOD OF BONDING TWO SLICES REALIZED IN MATERIALS SELECTED AMONG SEMICONDUCTOR MATERIALS |
US7485968B2 (en) | 2005-08-11 | 2009-02-03 | Ziptronix, Inc. | 3D IC method and device |
US8735219B2 (en) | 2012-08-30 | 2014-05-27 | Ziptronix, Inc. | Heterogeneous annealing method and device |
US9953941B2 (en) | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
US9496239B1 (en) | 2015-12-11 | 2016-11-15 | International Business Machines Corporation | Nitride-enriched oxide-to-oxide 3D wafer bonding |
US9852988B2 (en) | 2015-12-18 | 2017-12-26 | Invensas Bonding Technologies, Inc. | Increased contact alignment tolerance for direct bonding |
-
2000
- 2000-02-16 US US09/505,283 patent/US6902987B1/en not_active Expired - Lifetime
-
2001
- 2001-02-15 WO PCT/US2001/003683 patent/WO2001061743A1/en active Application Filing
- 2001-02-15 KR KR1020117015751A patent/KR101298859B1/en active IP Right Grant
- 2001-02-15 CA CA2399282A patent/CA2399282C/en not_active Expired - Fee Related
- 2001-02-15 AU AU2001241447A patent/AU2001241447A1/en not_active Abandoned
- 2001-02-15 KR KR1020097011631A patent/KR20090077981A/en not_active Application Discontinuation
- 2001-02-15 EP EP01912694A patent/EP1275142A4/en not_active Withdrawn
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- 2001-02-15 EP EP10185999A patent/EP2287896A2/en not_active Withdrawn
- 2001-02-15 KR KR1020027010561A patent/KR20020081328A/en not_active Application Discontinuation
-
2003
- 2003-06-13 US US10/460,418 patent/US7041178B2/en not_active Expired - Lifetime
-
2004
- 2004-01-23 US US10/762,318 patent/US7335572B2/en not_active Expired - Lifetime
- 2004-08-09 US US10/913,441 patent/US7387944B2/en not_active Expired - Lifetime
-
2007
- 2007-10-31 US US11/980,664 patent/US7807549B2/en not_active Expired - Fee Related
- 2007-10-31 US US11/980,415 patent/US7553744B2/en not_active Expired - Fee Related
-
2009
- 2009-06-29 US US12/493,957 patent/US8053329B2/en not_active Expired - Fee Related
-
2010
- 2010-03-09 US US12/720,368 patent/US7871898B2/en not_active Expired - Fee Related
- 2010-11-26 US US12/954,740 patent/US8153505B2/en not_active Expired - Lifetime
-
2011
- 2011-12-30 US US13/341,273 patent/US20120097638A1/en not_active Abandoned
-
2012
- 2012-05-08 JP JP2012107053A patent/JP5902030B2/en not_active Expired - Lifetime
-
2013
- 2013-07-08 JP JP2013143038A patent/JP5864481B2/en not_active Expired - Fee Related
-
2014
- 2014-03-04 US US14/197,070 patent/US9082627B2/en not_active Expired - Fee Related
- 2014-03-04 US US14/197,056 patent/US20140203407A1/en not_active Abandoned
-
2015
- 2015-06-29 US US14/754,111 patent/US9331149B2/en not_active Expired - Lifetime
- 2015-12-02 US US14/957,501 patent/US9391143B2/en not_active Expired - Lifetime
-
2016
- 2016-07-08 US US15/205,346 patent/US10312217B2/en not_active Expired - Fee Related
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