CA2459286A1 - Method for supporting sdh/sonet aps on ethernet - Google Patents
Method for supporting sdh/sonet aps on ethernet Download PDFInfo
- Publication number
- CA2459286A1 CA2459286A1 CA002459286A CA2459286A CA2459286A1 CA 2459286 A1 CA2459286 A1 CA 2459286A1 CA 002459286 A CA002459286 A CA 002459286A CA 2459286 A CA2459286 A CA 2459286A CA 2459286 A1 CA2459286 A1 CA 2459286A1
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- CA
- Canada
- Prior art keywords
- aps
- mac
- control
- ethernet
- hardware
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- RGNPBRKPHBKNKX-UHFFFAOYSA-N hexaflumuron Chemical compound C1=C(Cl)C(OC(F)(F)C(F)F)=C(Cl)C=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F RGNPBRKPHBKNKX-UHFFFAOYSA-N 0.000 title claims abstract 13
- 238000000034 method Methods 0.000 title claims 30
- 230000011664 signaling Effects 0.000 claims abstract 6
- 238000011084 recovery Methods 0.000 claims 6
- 230000002776 aggregation Effects 0.000 claims 2
- 238000004220 aggregation Methods 0.000 claims 2
- 230000000977 initiatory effect Effects 0.000 claims 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/28—Routing or path finding of packets in data switching networks using route fault recovery
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection (CSMA-CD)
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
- H04L12/462—LAN interconnection over a bridge based backbone
- H04L12/4625—Single bridge functionality, e.g. connection of two networks over a single bridge
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/22—Alternate routing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0057—Operations, administration and maintenance [OAM]
- H04J2203/006—Fault tolerance and recovery
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S370/00—Multiplex communications
- Y10S370/901—Wide area network
- Y10S370/902—Packet switching
- Y10S370/903—Osi compliant network
- Y10S370/907—Synchronous optical network, SONET
Abstract
An Ethernet MAC APS Control sublayer (305) is provided for supporting SDH/SONET APS standard functionality in Ethernet Networks. In accordance wit h one embodiment, an Ethernet MAC APS Control sublayer (305) is provided for processing Ethernet MAC APS Control frames (301B). The MAC APS Control sublayer (305) provides support for a MAC Client APS Controller to implement all of the SDH/SONET APS standard functionality. The MAC APS Control frame (301B) provides support for SDH/SONET K1/K2 APS signaling protocol on Ethern et networks. The near end APS Controller can use the MAC APS Control frames to communicate with the far end APS controller during switchover and other APS operational requests. The far end APS controller, in turn, can use the MAC A PS Control frames (301B) to communicate with the near end APS controller for switchover and other APS operational requests.
Claims (39)
1. A Media Access Control (MAC) hardware device for supporting MAC Automatic Protection Switching (APS) functionality, comprising:
a MAC APS Control sublayer for processing APS frames and maintaining APS
state; and a plurality of MAC sublayers for carrying out MAC operations.
a MAC APS Control sublayer for processing APS frames and maintaining APS
state; and a plurality of MAC sublayers for carrying out MAC operations.
2. The MAC hardware of claim 1, wherein the plurality of MAC sublayers further comprises a Link Aggregation sublayer.
3. The MAC hardware of claim 1, the plurality of MAC sublayers further comprises at least one MAC Control sublayer for generating control frames.
4. The MAC hardware of claim 1, wherein the MAC APS Control sublayer is located within a MAC.
5. The MAC hardware of claim 1, wherein a MAC Control Layer processes optional VLAN tags in control frames.
6. The MAC hardware of claim 1, wherein the MAC APS Control sublayer is implemented in the MAC hardware.
7. The MAC hardware of claim 1, wherein the MAC APS Control sublayer supports APS for logical links formed by a Link Aggregation sublayer.
8. The MAC hardware of claim 1, wherein the MAC APS Control sublayer supports APS for physical links.
9. The MAC hardware of claim 1, wherein the MAC APS Control sublayer supports APS for Network Layer paths.
10. The MAC hardware of claim 9, wherein the MAC sublayer can be implemented in at least one of an Ethernet Switch device and an Ethernet MAC device.
11. The MAC hardware of claim 1, wherein the MAC APS Control sublayer processes an Ethernet MAC control APS frame.
12. The MAC hardware of claim 1, wherein the MAC APS Control sublayer maintains an Ethernet MAC Control APS state.
13. The MAC hardware of claim 1, wherein a MAC APS Control Layer generates an interrupt when an APS frame is detected to invoke a MAC Client APS Controller.
14. The MAC hardware of claim 1, wherein a MAC APS Control Layer generates an interrupt when an APS state change is detected to invoke a MAC Client APS
Controller.
Controller.
15. The MAC hardware of claim 1, wherein the MAC APS Control sublayer interacts with an Ethernet MAC Client APS Controller.
16. An Ethernet PHY hardware device, comprising:
a decoder; and at least one physical sublayer, wherein one of the at least one physical sublayers generates an interrupt when a port/link failure is detected to invoke a MAC
Client APS
Controller.
a decoder; and at least one physical sublayer, wherein one of the at least one physical sublayers generates an interrupt when a port/link failure is detected to invoke a MAC
Client APS
Controller.
17. In a MAC APS hardware device, an Ethernet MAC APS Control Frame for supporting SDH/SONET APS Signalling Protocol, comprising:
a standard Ethernet frame Preamble field;
a standard Ethernet Start-of Frame Delimiter field;
a standard Ethernet Destination MAC address field;
a standard Ethernet Source MAC address field;
an optional standard Ethernet ULAN Tag field;
a standard Ethernet Type field;
a standard Ethernet MAC Control Opcode field;
a plurality of standard Ethernet MAC Control Parameters being opcode specific;
and a standard Ethernet Frame Check Sequence field.
a standard Ethernet frame Preamble field;
a standard Ethernet Start-of Frame Delimiter field;
a standard Ethernet Destination MAC address field;
a standard Ethernet Source MAC address field;
an optional standard Ethernet ULAN Tag field;
a standard Ethernet Type field;
a standard Ethernet MAC Control Opcode field;
a plurality of standard Ethernet MAC Control Parameters being opcode specific;
and a standard Ethernet Frame Check Sequence field.
18. The Ethernet MAC APS Control Frame of claim 17, wherein the Ethernet MAC
Control Opcode further comprises an ability to distinguish between a logical link failure, a physical Link failure, and a path failure.
Control Opcode further comprises an ability to distinguish between a logical link failure, a physical Link failure, and a path failure.
19. The Ethernet MAC APS Control Frame of claim 17, wherein the plurality of Ethernet MAC Control Parameters are further comprised of:
a K1 Word field containing an SDH/SONET K1 byte;
a K2 Word field containing an SDH/SONET K2 byte;
a Port ID field;
a Slot ID field;
a Chassis ID field;
a Bridge ID field;
a Node ID/IP field; and a Reserved field containing zero or more octets of zero value.
a K1 Word field containing an SDH/SONET K1 byte;
a K2 Word field containing an SDH/SONET K2 byte;
a Port ID field;
a Slot ID field;
a Chassis ID field;
a Bridge ID field;
a Node ID/IP field; and a Reserved field containing zero or more octets of zero value.
20. An Ethernet MAC Client, comprising:
at least one of a network layer protocol and a forwarding function for switches;
and at least one MAC Control Client APS Controller.
at least one of a network layer protocol and a forwarding function for switches;
and at least one MAC Control Client APS Controller.
21. A method of providing APS functionality on a MAC hardware and PHY
hardware, comprising:
detecting a failure along a first link on a near end network node;
a Physical Layer generating an interrupt when a port/ink failure is detected to invoke a MAC Client APS Controller; and switching to a second link to correct the failure.
hardware, comprising:
detecting a failure along a first link on a near end network node;
a Physical Layer generating an interrupt when a port/ink failure is detected to invoke a MAC Client APS Controller; and switching to a second link to correct the failure.
22. The method of claim 21, wherein the method executes within 50 ms to provide recovery functionality on an Ethernet protocol network.
23. A method of providing APS functionality on a MAC hardware, comprising:
a near end MAC APS Control sublayer receiving a MAC APS Control Frame containing an APS request from a MAC APS Control Frame buffer;
the near end MAC APS Control sublayer updating MAC APS state hardware registers to reflect receipt of the APS request;
the MAC APS hardware providing maskable interrupts for MAC APS Control Frames received;
the near end MAC APS Control sublayer generating interrupts to invoke the APS
Controller; and the APS Controller processing the APS request.
a near end MAC APS Control sublayer receiving a MAC APS Control Frame containing an APS request from a MAC APS Control Frame buffer;
the near end MAC APS Control sublayer updating MAC APS state hardware registers to reflect receipt of the APS request;
the MAC APS hardware providing maskable interrupts for MAC APS Control Frames received;
the near end MAC APS Control sublayer generating interrupts to invoke the APS
Controller; and the APS Controller processing the APS request.
24. The method of claim 23, wherein the APS request comprises at least one of a switchover request and an APS management request using APS K1/K2 signaling protocol.
25. The method of claim 23, further comprising at least one of manual and automatic switchover APS requests.
26. The method of claim 23, further comprising distinguishing between a logical failure, a physical failure, and a path failure.
27. The method of claim 23, wherein the method executes within 50 ms to provide recovery functionality.
28. A method of providing APS functionality on a MAC hardware device, comprising:
a near end MAC APS Control sublayer receiving APS Controller requests to be transmitted;
the MAC APS Control sublayer creating an APS Control frame with requested control parameters; and the near end MAC APS Control sublayer transmitting the MAC APS Control frame.
a near end MAC APS Control sublayer receiving APS Controller requests to be transmitted;
the MAC APS Control sublayer creating an APS Control frame with requested control parameters; and the near end MAC APS Control sublayer transmitting the MAC APS Control frame.
29. The method of claim 28, wherein the APS Controller requests comprise at least one of a switchover request and an APS management request using APS K1/K2 signaling protocol.
30. The method of claim 28, wherein the APS Controller requests comprise at least one of a manual and automatic switchover APS request.
31. The method of claim 28, wherein the method executes within 50 ms to provide recovery functionality.
32. A method of providing APS functionality on an Ethernet protocol network, comprising the steps of:
experiencing a failure along a first port/link;
generating an interrupt; and forwarding the interrupt to an APS controller, the APS controller initiating a switch from the first port/link to a second port/link.
experiencing a failure along a first port/link;
generating an interrupt; and forwarding the interrupt to an APS controller, the APS controller initiating a switch from the first port/link to a second port/link.
33. The method of claim 32, wherein the method executes within 50 ms to provide recovery functionality.
34. A method of providing APS functionality on an Ethernet protocol network, comprising the steps of:
receiving an APS Control frame with an APS request;
processing the APS Control frame APS request;
generating an interrupt; and forwarding the interrupt to an APS Controller, the APS Controller processing the APS request received.
receiving an APS Control frame with an APS request;
processing the APS Control frame APS request;
generating an interrupt; and forwarding the interrupt to an APS Controller, the APS Controller processing the APS request received.
35. The method of claim 34, wherein the method executes within 50 ms to provide recovery functionality.
36. The method of claim 34, wherein the method provides support for standard SDH/SONET APS functionality for linear, ring, and mesh topologies for Ethernet protocol networks using SDH/SONET K1/K2 bytes for SDH/SONET APS Signaling protocol.
37. A method of providing APS functionality on an Ethernet protocol network, comprising of steps of:
receiving an APS request from an APS Controller Client;
creating an APS Control Frame with the APS request; and transmitting the APS Control Frame.
receiving an APS request from an APS Controller Client;
creating an APS Control Frame with the APS request; and transmitting the APS Control Frame.
38. The method of claim 37, wherein the method executes within 50 ms to provide recovery functionality.
39. The method of claim 37, wherein the method provides support for standard SDH/SONET APS functionality for linear, ring, and mesh topologies for Ethernet protocol networks using SDH/SONET K1/K2 bytes for SDH/SONET APS Signaling protocol.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US31703501P | 2001-09-04 | 2001-09-04 | |
US60/317,035 | 2001-09-04 | ||
PCT/US2002/028112 WO2003021858A1 (en) | 2001-09-04 | 2002-09-04 | Method for supporting sdh/sonet aps on ethernet |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2459286A1 true CA2459286A1 (en) | 2003-03-13 |
CA2459286C CA2459286C (en) | 2010-07-20 |
Family
ID=23231823
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA2459286A Expired - Fee Related CA2459286C (en) | 2001-09-04 | 2002-09-04 | Method for supporting sdh/sonet aps on ethernet |
Country Status (8)
Country | Link |
---|---|
US (2) | US7394758B2 (en) |
EP (1) | EP1461890B1 (en) |
JP (1) | JP4212476B2 (en) |
CN (1) | CN100550715C (en) |
AT (1) | ATE418198T1 (en) |
CA (1) | CA2459286C (en) |
DE (1) | DE60230446D1 (en) |
WO (1) | WO2003021858A1 (en) |
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EP1461890B1 (en) | 2008-12-17 |
US20030043736A1 (en) | 2003-03-06 |
EP1461890A4 (en) | 2006-05-24 |
US20080259786A1 (en) | 2008-10-23 |
US7394758B2 (en) | 2008-07-01 |
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