CN100337327C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN100337327C
CN100337327C CNB200410011783XA CN200410011783A CN100337327C CN 100337327 C CN100337327 C CN 100337327C CN B200410011783X A CNB200410011783X A CN B200410011783XA CN 200410011783 A CN200410011783 A CN 200410011783A CN 100337327 C CN100337327 C CN 100337327C
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aforementioned
outside terminal
semiconductor device
circuit board
outside
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CN1606154A (zh
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青柳哲理
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Seiko Epson Corp
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Seiko Epson Corp
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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Abstract

一种半导体器件，包括半导体芯片(10)，搭载有半导体芯片(10)的布线基板(20)，设置在布线基板(20)上的多个外部端子(40)。多个外部端子(40)，包括至少一个第一外部端子(42)，两个以上的第二外部端子(44)、(45)、(46)、(47)。第一外部端子(42)，由焊料构成。第二外部端子(44)、(45)、(46)、(47)，包含焊料(50)和分散在焊料(50)中的由树脂构成的多个粒子(52)。在多个外部端子(40)中，与其它任何一对相比，相互远离配置的一对构成第二外部端子(44)、(45)、(46)、(47)。根据本发明可以缓和施加在半导体器件的外部端子上的应力。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法。
背景技术
在半导体器件安装在电路基板上的状态下，缓和施加在半导体器件的外部端子上的应力(热应力)是很重要的。外部端子由焊料球等构成，设置在半导体器件的电接合部(接合区)。在现有技术中，通过改变电接合部的平面形状避免向外部端子上的应力集中，但是，这种方法具有一定的局限性。
发明内容
本发明的目的是，缓和施加在半导体器件的外部端子上的应力。
(1)本发明的半导体器件，包含有：
半导体芯片，
搭载前述半导体芯片的布线基板，
设置在前述布线基板上的多个外部端子，
其中，前述多个外部端子包括至少一个第一外部端子，和两个以上(这里所的以上包括端点，即包括两个，下文相同)的第二外部端子，
前述第一外部端子由焊料构成，
前述第二外部端子，包含有焊料和在前述焊料中分散的由树脂构成的多个粒子，
前述多个外部端子中，与其它任何一对相比，相互远离配置的一对构成前述第二外部端子。根据本发明，在多个外部端子中，与其它任何一对相比，相互远离配置的一对构成前述第二外部端子。由于第二外部端子包含很多粒子，从而，可以缓和施加到第二外部端子上的应力。在多个外部端子中，由于布线基板的膨胀或收缩产生的应力，最多地施加到与其它任何一对相比相互远离配置的一对上。从而，通过将第二外部端子配置在该部分上，可以最有效地缓和应力。
(2)在这种半导体器件中，
在前述多个外部端子中，也可以令与其它任意一对相比相互远离配置的多对成为前述第二外部端子。
(3)在这种半导体器件中，
将前述多个外部端子的排列区域的外形构成四边形，
将前述第二外部端子配置在前述四边形的拐角部。这样，可以有效地缓和施加到四边形拐角部上的应力。
(4)本发明的半导体器件，包括：
包含第一布线基板以及正装于前述第一布线基板的第一半导体芯片的第一半导体器件，
包含第二布线基板以及倒装于前述第二布线基板的第二半导体芯片的第二半导体器件，
夹装在前述第一布线基板和前述第二布线基板之间，将两者电连接的多个外部端子，
其中，前述多个外部端子，包含至少一个第一外部端子和两个以上的第二外部端子，
前述第一外部端子由焊料构成，
前述第二外部端子，包含有焊料和在前述焊料中分散的由树脂构成的多个粒子，
在前述多个外部端子中，与其它任何一对相比相互远离配置的一对构成前述第二外部端子。根据本发明，在多个外部端子中，与其它任何一对相比，相互远离配置的一对构成前述第二外部端子。由于第二外部端子包含很多粒子，从而，可以缓和施加到第二外部端子上的应力。在多个外部端子中，由于布线基板的膨胀或收缩产生的应力，最多地施加到与其它任何一对相比相互远离配置的一对上。从而，通过将第二外部端子配置在该部分上，可以最有效地缓和应力。
(5)本发明的半导体器件，包括：多个第一半导体器件、第二半导体器件以及多个外部端子，
前述多个第一半导体器件分别包含第一布线基板以及正装于前述第一布线基板的第一半导体芯片，
前述第二半导体器件包含第二布线基板以及倒装于前述第二布线基板的第二半导体芯片，前述多个第一半导体器件以相互不重叠的方式搭载于第二半导体器件，
前述多个外部端子夹装在前述第一布线基板与前述第二布线基板之间，使前述第一布线基板和前述第二布线基板电连接并且由多组构成，其中各个前述第一半导体器件与前述多组中的一组对应，
前述多个外部端子，包含至少一个第一外部端子和两个以上的第二外部端子，
前述第一外部端子由焊料构成，
前述第二外部端子，包含有焊料和在前述焊料中分散的由树脂构成的多个粒子，
前述多个外部端子的各组的排列区域的外形呈长方形，
在至少一个组中，配置在前述长方形的对向的角部的区域的一对，成为前述第二外部端子。根据本发明，多个外部端子中，配置在排列区域的长方形的对向的拐角部的区域内的一对，成为第二外部端子。由于第二外部端子含有很多粒子，从而，可以缓和施加在第二外部端子上的应力。由布线基板的膨胀或收缩引起的应力最多地施加在多个外部端子中，配置在排列区域的长方形的对向拐角部区域上的一对上。从而，通过将第二外部端子配置在该部分上，可以有效地缓和应力。
(6)本发明的半导体器件，包括：多个第一半导体器件、第二半导体器件以及多个外部端子，
前述多个第一半导体器件分别含有第一布线基板以及正装于前述第一布线基板的第一半导体芯片，
前述第二半导体器件含有第二布线基板以及倒装于前述第二布线基板的第二半导体芯片、以相互不重叠的方式搭载有前述多个第一半导体器件的第二半导体器件，
夹装在前述第一布线基板与前述第二布线基板之间，将两者电连接的多组外部端子，其中各个前述第一半导体器件与前述多组中的一组对应，
其中，前述多个外部端子，包含至少一个第一外部端子和两个以上的第二外部端子，
前述第一外部端子由焊料构成，
前述第二外部端子，包含有焊料和在前述焊料中分散的由树脂构成的多个粒子，
前述多个外部端子的各组的排列区域的外形呈长方形，
在至少其中一组中，沿着前述长方形的各个短边的区域的端部配置的一对，成为前述第二外部端子。根据本发明，在多个外部端子中，沿着排列区域的长方形的短边的区域配置的一对成为第二外部端子。由于第二外部端子含有很多粒子，从而，可以缓和施加到第二外部端子上的应力。由布线基板的膨胀或收缩产生的应力容易施加到多个外部端子中，沿着排列区域的长方形的短边区域配置的一对上。从而，通过将第二外部端子配置在该部分上，可以有效地缓和应力。
(7)在这种半导体器件中，
前述第一半导体器件，可以进一步包括：
正装前述第一半导体芯片的第一布线基板，以及密封前述第一半导体芯片的树脂密封部。这样，在第一半导体器件具有树脂密封部的情况下，由于第一半导体器件和第二半导体器件之间的热膨胀率之差增大，所以更易于向外部端子上施加应力，因此，是更有效的。
(8)在这种半导体器件中，
前述第二半导体器件进一步包含有倒装前述第二半导体芯片的第二布线基板，
前述多个外部端子也可以排列在前述第二半导体芯片的外侧区域。
(9)在这种半导体器件中，
邻接前述第二外部端子的外部端子，可以和前述第二外部端子具有同样的结构。借此，可以更有效地缓和应力。
(10)在这种半导体器件中，
前述第二外部端子，进一步包含涂敷各个前述粒子的表面而构成的导体被膜。从而，由于用导体被膜涂敷粒子表面，所以，可以提高第二外部端子的电学特性。例如，即使多个粒子密集，导体被膜彼此接触，所以，在粒子之间流过电流，可以防止绝缘部分扩大。
(11)在这种半导体器件中，
也可以使前述粒子热固化。借此，由于在加热熔融第二外部端子时，粒子不会熔融(或者难以熔融)，所以，在加热熔融后，多个粒子也维持在分散状态。从而，加热熔融后，也可以缓和第二外部端子的应力。
(12)本发明的半导体器件的制造方法，
包括在搭载半导体芯片的布线基板上设置多个外部端子，
前述多个外部端子包括至少一个第一外部端子以及两个以上的第二外部端子，
用焊料形成前述第一外部端子，
通过在焊料中分散由树脂构成的多个粒子形成前述第二外部端子，
以比其它任何一对相互远离的配置的一对成为前述第二外部端子的方式，设置前述多个外部端子。根据本发明，以比其它任何一对相互远离配置的一对成为前述第二外部端子的方式，设置多个外部端子。由于第二外部端子包含有多个粒子，从而，可以缓和施加在第二外部端子上的应力。由布线基板的膨或收缩引起的应力，最多地施加在多个外部端子中，比其它任何一对相互远离地配置的一对上。从而，通过将第二外部端子配置在该部分上，可以有效地缓和应力。
附图说明
图1是本发明的第一种实施方式的半导体器件的平面图。
图2是图1的II-II线剖面图。
图3是图1的III-III线剖面图。
图4是图3的部分放大图。
图5是说明本发明的第一种实施方式的半导体器件的外部端子的制造方法的图示。
图6是本发明的第一种实施方式的变形例的半导体器件的平面图。
图7是本发明的第二种实施方式的半导体器件平面图。
图8是图7的VIII-VIII线的剖面图。
图9是本发明的第三种实施方式的半导体器件平面图。
图10是图9的X-X线剖面图。
图11是本发明的第四种实施方式的半导体器件平面图。
图12是表示安装本发明的实施方式的半导体器件的电路基板的图示。
图13是表示具有本发明的实施方式的半导体器件的电子设备的图示。
图14是表示具有本发明的实施方式的半导体器件的电子设备的图示。
具体实施方式
下面，参照附图说明本发明的实施方式。
(第一种实施方式)
图1是本发明的第一种实施方式的半导体器件的平面图，图2是图1的II-II线的剖面图，图3是图1的III-III线的剖面图。图4是图3的部分放大图。本实施方式的半导体器件，包含有半导体芯片10，布线基板20，多个外部端子40。
在半导体芯片10上形成集成电路(图中未示出)，形成电连接到集成电路上的多个电极12。多个电极12，可以形成在半导体器件10上的集成电路侧的面上。多个电极12，也可以形成在沿着半导体芯片10的表面的四个边或两个边的区域上。电极12具有焊盘(例如Al焊盘)。在将半导体芯片10倒装在布线基板20上的情况下，电极12可以进一步具有在焊盘上的凸起(例如，金凸起)。此外，在半导体芯片10的形成电极12的面上，形成钝化膜(图中未示出)。
如图2所示，布线基板20包括基体基板22，形成在基体基板22上的布线图形24。布线基板20也可以是半导体器件的插入机构。基体基板22大多是有机系树脂基板(例如，环氧系基板，聚酰亚胺基板)，但也可以是无机系基板(例如玻璃基板，陶瓷基板)，或者有机系和无机系的复合结构的基板(例如，玻璃环氧基板)。布线图形24，也可以形成在基体基板22的两个面上。布线图形24的一部分构成通孔26，以便将布线基板20的两面电导通。
如图2所示，半导体芯片10，也可以倒装(face down)到布线基板20上。更详细地说，半导体芯片10，其电极12的形成面与布线基板20对向。电极12和布线图形24的电接合，可以用各向异性的导电材料30进行。各向异性导电材料30，可以是各向异性导电薄膜或者各向异性导电胶中的任何一种，多个导电粒子32分散在粘结剂中。通过将导电粒子32介于电极12和布线图形24之间，可以达到两者之间的电接合。作为其它的电接合的形式，也可以采用导电树脂胶，金属接合(例如Au-Au接合，Au-Sn接合或者焊接接合)，利用绝缘树脂的收缩力等形式。在金属接合的情况下，也可以在半导体芯片10与布线基板20之间填充树脂(灌冲树脂)。
作为变形例，半导体芯片10也可以正装(face up)在布线基板20上。更详细地说，半导体芯片10，与电极12的形成面相反的面与布线基板20对向。电极12与布线图形24的电接合，可以利用金属丝进行。在这种情况下，优选地，半导体芯片10全部用树脂密封。
在基体基板22上，作为布线图形24的一部分，形成多个电接合部28。电接合部28可以是接合区(land)。在本实施方式中，在电接合部28上形成外部端子40。电接合部28，可以形成在与基体基板22上半导体芯片10的搭载面相反的面上，也可以形成在与基体基板22上半导体芯片10的搭载面相同的面(例如，半导体芯片10的外侧的区域)上。即，外部端子40，可以设置在与搭载半导体芯片10的面相反的面上，也可以设置在与半导体芯片10的搭载面相同的面(例如，半导体芯片10的外侧的区域)上。
外部端子40具有导电性。外部端子40，可以呈球状。所谓球状，并不必须是完全的球体，也可以是球体的一部分，或者呈块状。多个外部端子40，电连接到半导体芯片10上，可以排列成多行多列。多个外部端子40的排列区域48的外形，可以成四边形(例如正方形或长方形)。在布线基板20上至少配置三个以上(在大多数情况下n×n个(n为自然数))的外部端子。
如图1所示，多个外部端子40包括至少一个第一外部端子42，和两个以上(在图1中为四个)的第二外部端子44、45、46、47。第一外部端子42主成分由焊料构成。焊料可以是软焊料或硬焊料。第一外部端子42可以是公知的焊料球，也可以包含助焊剂等。在本实施方式中，在第一外部端子42内，不含有后面描述的由树脂构成的粒子。
如图4所示，第二外部端子44，包含有成为主成分的焊料50，以及分散在焊料50中的由树脂构成的多个粒子52。焊料50如已经说明过的，其组成没有特定的限制，例如，可以由锡(Sn)和其它金属化合物(例如银(Ag)及铜(Cu))构成。在焊料50中进一步可以混入助焊剂。第二外部端子44，可以是所谓树脂分散的焊料球。从而，借助多个粒子52，可以缓和施加到第二外部端子44上的应力。更详细地说，由于树脂比焊料50更柔软，所以，可以利用多个粒子52吸收或分散应力。此外，粒子52，由于分散多个，所以不容易造成与焊料50的不浸润。
粒子52的树脂成分没有特定的限制，例如，可以使用聚苯乙烯，二乙烯基苯等。粒子52也可以由热固化性树脂形成。在这种情况下，粒子52也可以是热固化的粒子(例如，是热固化完毕或进行一半以上的粒子)。这样，由于在加热熔融(例如软熔)第二外部端子44时，粒子52不会熔融(和不容易熔融)，所以，在加热熔融后，也可以保持多个粒子52的分散状态。从而，即使在加热熔融后也可以缓和第二外部端子44的应力。
在图4所示的粒子中，第二外部端子44，进一步包含在各个粒子52的表面上涂敷构成的导体被膜54。导体被膜54可以是金属被膜(例如铜(Cu))，例如，可以利用镀敷处理(例如电镀或化学镀敷)形成。从而，由于粒子52的表面被导电被膜54涂敷，所以，可以提高第二外部端子44的电学特性。例如，即使多个粒子52密集，由于导体被膜54彼此接触，所以在粒子52之间流过电流，可以防止绝缘部分的扩大。
其次，对多个外部端子40的排列进行说明。如图1所示，在多个外部端子40中，比其它任何一对都相互远离配置的一对成为第二外部端子44，45。即，在多个外部端子40的排列区域(用双点划线包围的区域)48的一个端部上，配置第二外部端子44，在另一个端部上配置第二外部端子45。同时，第二外部端子44、45之间的距离，比其它任何一对外部端子之间的距离都长。在排列区域48的外形成四边形的情况下，第二外部端子44、45配置在四边形的对向的拐角部区域上。换句话说，如图3所示，第二外部端子44、45配置在四边形的对角线上的两个端部上。此外，在一对第二外部端子44、45之外的剩下的外部端子的全部都是第一外部端子42。
在图1所示的例子中，在多个外部端子40中，与其它的任何一对相比相互远离配置的多对，构成第二外部端子44、45、46、47。更详细地说，第二外部端子44、45构成一对，第二外部端子46、47构成一对。第二外部端子46、47的距离，比其它任何一对外部端子间的距离都长，与第二外部端子44、45的距离相同。在排列区域48的外形是四边形的情况下，第二外部端子44、45、46、47，配置在四边形的全部拐角部的区域内。换句话说，如图3所示，第二外部端子44、45配置在四边形的一个对角线的两个端部上，第二外部端子46、47配置在四边形的另一个对角线上的两个端部上。此外，如图1所示，除一对第二外部端子44、45、46、47之外的剩余的外部端子全部是第一外部端子42。
将多个外部端子40向电接合部28上的配置方法，没有特定的限制，例如，在具有与图示的例子通孔26不同的贯通孔的情况下，可以通过从贯通孔进行吸引，吸附球状的外部端子40。可以在吸附第一外部端子42之后，吸附第二外部端子44、45、46、47。或者也可以反过来进行。
根据本实施方式，在多个外部端子40中，与其它任何一对相比，相互远离配置的一对(例如，四边形的排列区域的拐角部的区域)成为第二外部端子44、45。由布线基板20的膨胀或收缩引起的应力最多地施加在该部分上。从而，通过将第二外部端子44、45配置在该部分上，可以有效地缓和应力。
图5是说明本实施方式的第二外部端子的制造方法的图示。首先，在坩埚56内，将由树脂构成的多个粒子52混入到熔融的焊料50中。可以在混入前，使粒子52已经热固化。也可以在混入前利用导电被膜54涂敷粒子52的表面。作为涂敷方法，可以采用上述的镀敷处理。将加热熔融的液体状的焊料50从喷嘴58中滴下的同时，将其冷却。在这种情况下，将规定的方向、频率及振幅的振动传递给滴下的液体状焊料50。这样，在液体状的焊料流中间变细的同时，通过冷却保持固体状，可以将第二外部端子44形成球状。
图6是表示本实施方式的变形例的半导体器件的图示。在本变形例中，与第二外部端子44邻接的外部端子，与第二外部端子44具有相同的结构。即，邻接第二外部端子44的外部端子包含成为主成分的焊料，以及少量的分散在焊料中、由树脂构成的多个粒子。粒子可以用导体被膜涂敷。在具有多个邻接一个第二外部端子44的外部端子的情况下，其中的任何一个都具有和第二外部44相同的结构。在图6所示的例子中，相对于第二外部端子44在一行上相邻的外部端子60，相对于第二外部端子44在一列上相邻的外部端子62，以及相对于第二外部端子沿斜向方向相邻(一行相邻也一列相邻)的外部端子64，分别与第二外部端子44具有相同的结构。也可以是它们中的任何一个具有和第二外部端子44相同的结构。此外，如图6所示，邻接与第二外部端子44构成一对的第二外部端子45的外部端子，也是一样，邻接第二外部端子46、47的每一个的外部端子情况也一样。在图6所示的例子中，在排列区域48的拐角部区域上，各配置四个含有由树脂构成的粒子的外部端子(第二外部端子及与之具有同一结构的外部端子)。
本实施方式的半导体器件的制造方法，包括在搭载半导体芯片10的布线基板20上设置多个外部端子40的工序。多个外部端子40，包括第一外部端子42，第二外部端子44、45、46、47，它们的排列，可以采用已经说明过的内容，其效果也和已经说明过的一样。
(第二种实施方式)
图7是本发明的第二种实施方式的半导体器件的平面图，图8是图7的VIII-VIII线剖面图。此外，在本实施方式中，可以尽可能地采用第一种实施方式中说明过的内容(包括变形例)。
如图8所示，半导体器件(叠层型半导体器件)，具有第一及第二半导体器件70、80，上述多个外部端子40，以电接合上下半导体器件的方式夹装在两者之间。更详细地说，第一半导体器件70，具有半导体芯片72，搭载半导体芯片72的布线基板74，在布线基板74上，作为布线图形的一部分形成电接合部(例如接合区)78。半导体芯片72可以正装在布线基板74上。半导体芯片72用引线接合，全部用树脂密封部76密封。第二半导体器件80，具有半导体芯片82，搭载半导体芯片82的布线基板84，在布线基板84上作为布线图形的一部分形成电接合部(例如接合区)86。半导体芯片82可以倒装在布线基板84上。电接合部86可以形成在布线基板84的两面上。外部端子40，夹装在第一半导体器件70的电接合部78和第二半导体器件80的电接合部86之间。多个外部端子40排列在排列区域48内，也可以排列在半导体芯片82的外侧的区域内。多个外部端子40，具有至少一个第一外部端子42，两个以上(图7中四个)第二外部端子44、45、46、47。第一及第二外部端子的排列形式，可以采用第一种实施方式中说明的内容。在本实施方式中，可以缓和施加在叠层的多个半导体器件之间的外部端子上的应力。特别是，在第一半导体器件70具有树脂密封部76的情况下，由于第一半导体器件70与第二半导体器件80之间的热膨胀率之差变大，所以容易在外部端子上施加应力，所以采用本实施方式是很有效的。
在图8所示的例子中，在最下层的第二半导体器件80上，在与第一半导体器件70的相反面侧的电接合部86上设置外部端子40。从而，可以将叠层的多个半导体器件安装到电路基板上，其效果和已经描述过的一样。此外，在第一及第二半导体器件70、80之间，即，多个外部端子40的周围，利用灌冲材92进行树脂密封。
(第三种实施方式)
图9上本发明的第三种实施方式的半导体器件的平面图，图10是图9的X-X线剖面图。此外，在本实施方式中，可以尽可能地应用第一及第二种实施方式中说明的内容(包含变形例)。
半导体器件(叠层型半导体器件)，具有多个第一半导体器件100、110，和以相互不重叠的方式搭载各个第一半导体器件100、110的第二半导体器件80。第一半导体器件100、110分别设置在平面上不同的位置上。第一半导体器件100可以具有第一半导体芯片112，搭载第一半导体芯片112的布线基板114，第一半导体芯片112被树脂密封部116用树脂密封。第一半导体器件110，可以与第一半导体器件100具有相同的结构。
多个外部端子120(或多个外部端子130)，夹装在第一半导体器件100(或第一半导体器件110)与第二半导体器件80之间，将两者电连接。多个外部端子120、130，对应于各个第一半导体器件100、110，分割成多个组(在图9中为两组)。多个外部端子120，夹装在第一半导体器件100的电接合部108和第二半导体器件80的电接合部86之间，多个外部端子130，夹装在第一半导体器件110的电接合部118与第二半导体器件80的电接合的86之间。多个外部半导体器件120、130，具有至少一个第一外部端子122、132，和两个以上的第二外部端子124～127，134～137。如图9所示，也可以在各组的排列区域128、138的每一个上，设置第一及第二外部端子。第一及第二外端子的排列形式，可以应用第一种实施方式中说明的内容。
在图9所示的例子中，各排列区域128、138，呈长方形。同时，在至少一个(在图9中全部)组中，配置在长方形的对向的拐角部区域上的一对，成为第二外部端子124～127，134～137。其它详细情况，可以应用上述内容。
(第四种实施方式)
图11是本发明的第四种实施方式的半导体器件的平面图。此外，在本实施方式中，可以尽可能地应用第一～第三种实施方式说明的内容(包含变形例)。
半导体器件(叠层型半导体器件)，具有多个第一半导体器件100、110，以相互不重叠的方式分别搭载第一半导体器件100、110的第二半导体器件80。在本实施方式中，半导体器件具有分别对应于第一半导体器件100、110、分割成多个组的多个外部端子140、150。在本实施方式中，第一及第二外部的排列形式与第三种实施方式不同。
在图11所示的例子中，各组的排列区域148、158呈长方形。在其中的至少一组(在图11中全部)中，沿长方形的各个短边区域配置的一对，构成第二外部端子144、146、154、156。第二外部端子144、146(或第二外部端子154、156)，配置在排列区域148(和排列区域158)的端部(最外侧的区域)。当配置在沿着长方形短边的区域上的外部端子是多个的情况下，其中的一个或多个(例如全部)可以成为第二外部端子。一对第二外部端子144、146，可以排列在同一列(图11的纵向方向列)上，也可以排列在不同的列上。
在图12上表示出安装有上述本实施方式的半导体器件的电路基板1000。作为安装方法，将半导体器件的外部端子加热熔融(软熔)，将两者电接合。这样，对于安装时及其以后的热压，可以缓和半导体器件的外部端子上的应力。作为本实施方式的电子设备，在图13上表示出笔记本式个人计算机2000，在图14上表示出便携式电话3000。
本发明并不局限于上述实施方式，可以进行各种变形。例如，本发明包含与实施方式中说明的结构实质上相同的结构(例如，功能，方法及结果相同的结构，或者目的及结果相同的结构)。此外，本发明，包含置换在实施方式中说明的结构的非本质的部分的结构。此外，本发明包括与实施方式中说明的结构具有相同作用效果的结构，或者可以达到同一个目的的结构。此外，本发明包含在实施方式中说明的结构中附加公知技术的结构。

Claims (12)

1、一种半导体器件，包括：
半导体芯片，
搭载有前述半导体芯片的布线基板，
设置在前述布线基板上的多个外部端子，
其中，前述多个外部端子包括至少一个第一外部端子和两个以上的第二外部端子，
前述第一外部端子由焊料构成，
前述第二外部端子，包含有焊料和在前述焊料中分散的由树脂构成的多个粒子，
在前述多个外部端子中，与其它任何一对相比相互远离配置的一对成为前述第二外部端子。
2、如权利要求1所示的半导体器件，
在前述多个外部端子中，与其它任意一对相比相互远离配置的多对成为前述第二外部端子。
3、如权利要求1所示的半导体器件，
前述多个外部端子的排列区域的外形呈四边形，
前述第二外部端子配置在前述四边形的角部区域。
4、一种半导体器件，包括：
包含第一布线基板以及正装于前述第一布线基板的第一半导体芯片的第一半导体器件，
包含第二布线基板以及倒装于前述第二布线基板的第二半导体芯片的第二半导体器件，
夹装在前述第一布线基板和前述第二布线基板之间，将两者电连接的多个外部端子，
其中，前述多个外部端子，包含至少一个第一外部端子和两个以上的第二外部端子，
前述第一外部端子由焊料构成，
前述第二外部端子，包含有焊料和在前述焊料中分散的由树脂构成的多个粒子，
在前述多个外部端子中，与其它任何一对相比相互远离配置的一对构成前述第二外部端子。
5、一种半导体器件，包括：多个第一半导体器件、第二半导体器件以及多个外部端子，
前述多个第一半导体器件分别包含第一布线基板以及正装于前述第一布线基板的第一半导体芯片，
前述第二半导体器件包含第二布线基板以及倒装于前述第二布线基板的第二半导体芯片，前述多个第一半导体器件以相互不重叠的方式搭载于第二半导体器件，
前述多个外部端子夹装在前述第一布线基板与前述第二布线基板之间，使前述第一布线基板和前述第二布线基板电连接并且由多组构成，其中各个前述第一半导体器件与前述多组中的一组对应，
前述多个外部端子，包含至少一个第一外部端子和两个以上的第二外部端子，
前述第一外部端子由焊料构成，
前述第二外部端子，包含有焊料和在前述焊料中分散的由树脂构成的多个粒子，
前述多个外部端子的各组的排列区域的外形呈长方形，
在至少一个组中，配置在前述长方形的对向的角部的区域的一对，成为前述第二外部端子。
6、一种半导体器件，包括：多个第一半导体器件、第二半导体器件以及多个外部端子，
前述多个第一半导体器件分别含有第一布线基板以及正装于前述第一布线基板的第一半导体芯片，
前述第二半导体器件含有第二布线基板以及倒装于前述第二布线基板的第二半导体芯片、以相互不重叠的方式搭载有前述多个第一半导体器件的第二半导体器件，
夹装在前述第一布线基板与前述第二布线基板之间，将两者电连接的多组外部端子，其中各个前述第一半导体器件与前述多组中的一组对应，
其中，前述多个外部端子，包含至少一个第一外部端子和两个以上的第二外部端子，
前述第一外部端子由焊料构成，
前述第二外部端子，包含有焊料和在前述焊料中分散的由树脂构成的多个粒子，
前述多个外部端子的各组的排列区域的外形呈长方形，
在至少其中一组中，沿着前述长方形的各个短边的区域的端部配置的一对，成为前述第二外部端子。
7、如权利要求4至6中任一项所述的半导体器件，所述第一半导体器件还包括：密封前述第一半导体芯片的树脂密封部。
8、如权利要求4至6中任一项所述的半导体器件，前述多个外部端子排列在前述第二半导体芯片的外侧区域。
9、如权利要求1至6中任一项所述的半导体器件，
与前述第二外部端子邻接的外部端子，具有与前述第二外部端子同样的结构。
10、如权利要求1至6中任一项所述的半导体器件，
前述第二外部端子，还包含涂敷各个前述粒子的表面而构成的导体被膜。
11、如权利要求1至6中任一项所述的半导体器件，前述粒子被热固化。
12、一种半导体器件的制造方法，
包括在搭载有前述半导体芯片的布线基板上设置多个外部端子的工序，
前述多个外部端子包括至少一个第一外部端子和两个以上的第二外部端子，
用焊料形成前述第一外部端子，
通过在焊料中分散由树脂构成的多个粒子而形成前述第二外部端子，
以比其它任何一对相互远离配置的一对成为前述第二外部端子的方式，设置前述多个外部端子。
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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007069606A1 (ja) 2005-12-14 2007-06-21 Shinko Electric Industries Co., Ltd. チップ内蔵基板およびチップ内蔵基板の製造方法
JP2009246166A (ja) * 2008-03-31 2009-10-22 Fujitsu Ltd 電子部品パッケージおよび基板ユニット並びにプリント配線板およびその製造方法
JP2010147153A (ja) * 2008-12-17 2010-07-01 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
FR2943849B1 (fr) * 2009-03-31 2011-08-26 St Microelectronics Grenoble 2 Procede de realisation de boitiers semi-conducteurs et boitier semi-conducteur
US20110156240A1 (en) * 2009-12-31 2011-06-30 Stmicroelectronics Asia Pacific Pte. Ltd. Reliable large die fan-out wafer level package and method of manufacture
US8884422B2 (en) * 2009-12-31 2014-11-11 Stmicroelectronics Pte Ltd. Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture
US8502394B2 (en) * 2009-12-31 2013-08-06 Stmicroelectronics Pte Ltd. Multi-stacked semiconductor dice scale package structure and method of manufacturing same
US8436255B2 (en) * 2009-12-31 2013-05-07 Stmicroelectronics Pte Ltd. Fan-out wafer level package with polymeric layer for high reliability
US8466997B2 (en) * 2009-12-31 2013-06-18 Stmicroelectronics Pte Ltd. Fan-out wafer level package for an optical sensor and method of manufacture thereof
US8742603B2 (en) * 2010-05-20 2014-06-03 Qualcomm Incorporated Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
US8461676B2 (en) 2011-09-09 2013-06-11 Qualcomm Incorporated Soldering relief method and semiconductor device employing same
US9013037B2 (en) 2011-09-14 2015-04-21 Stmicroelectronics Pte Ltd. Semiconductor package with improved pillar bump process and structure
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8779601B2 (en) 2011-11-02 2014-07-15 Stmicroelectronics Pte Ltd Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
KR101403865B1 (ko) * 2011-12-16 2014-06-10 제일모직주식회사 이방성 도전 필름용 조성물, 이방성 도전 필름 및 반도체 장치
JP5993248B2 (ja) * 2012-08-27 2016-09-14 新光電気工業株式会社 電子部品内蔵基板及びその製造方法
US8963339B2 (en) 2012-10-08 2015-02-24 Qualcomm Incorporated Stacked multi-chip integrated circuit package
US9985007B2 (en) 2016-07-22 2018-05-29 Invensas Corporation Package on-package devices with multiple levels and methods therefor
WO2018098650A1 (zh) * 2016-11-30 2018-06-07 深圳修远电子科技有限公司 集成电路封装结构及方法
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10818602B2 (en) 2018-04-02 2020-10-27 Amkor Technology, Inc. Embedded ball land substrate, semiconductor package, and manufacturing methods
US11721657B2 (en) 2019-06-14 2023-08-08 Stmicroelectronics Pte Ltd Wafer level chip scale package having varying thicknesses
JP7234876B2 (ja) * 2019-09-20 2023-03-08 株式会社村田製作所 基板の接続構造
JP1686546S (zh) * 2020-05-13 2021-05-31

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223634A (ja) * 1999-01-28 2000-08-11 Hitachi Ltd 半導体装置
US6222265B1 (en) * 1997-03-10 2001-04-24 Micron Technology, Inc. Method of constructing stacked packages
US20020079568A1 (en) * 2000-12-27 2002-06-27 Yinon Degani Stacked module package

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3119230B2 (ja) * 1998-03-03 2000-12-18 日本電気株式会社 樹脂フィルムおよびこれを用いた電子部品の接続方法
JPH11254185A (ja) 1998-03-10 1999-09-21 Mitsui High Tec Inc フレックス接合材
KR20000057810A (ko) * 1999-01-28 2000-09-25 가나이 쓰토무 반도체 장치
JP3217041B2 (ja) 1999-04-15 2001-10-09 埼玉日本電気株式会社 電子部品の実装構造
TW415056B (en) * 1999-08-05 2000-12-11 Siliconware Precision Industries Co Ltd Multi-chip packaging structure
JP2001093329A (ja) 1999-09-20 2001-04-06 Sekisui Chem Co Ltd 半田メッキ高分子微球体及び接続構造体
TWI268581B (en) * 2002-01-25 2006-12-11 Advanced Semiconductor Eng Stack type flip-chip package including a substrate board, a first chip, a second chip, multiple conductive wire, an underfill, and a packaging material

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6222265B1 (en) * 1997-03-10 2001-04-24 Micron Technology, Inc. Method of constructing stacked packages
JP2000223634A (ja) * 1999-01-28 2000-08-11 Hitachi Ltd 半導体装置
US20020079568A1 (en) * 2000-12-27 2002-06-27 Yinon Degani Stacked module package

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