高压元件结构技术领域本发明涉及一种高压元件结构，特别是涉及一种可以抑制寄生电流(parasitical current)的高压元件结构。 High Pressure element structure FIELD The present invention relates to a high element structure, particularly to a parasitic current can be suppressed (parasitical current) high-voltage device structure. 背景技术近年来，随着移动电话等电子通讯产品的蓬勃发展，其所应用的液晶显示器(liquid crystal display; LCD)的驱动器显得格外的重要。 In recent years, with the rapid development of mobile phones and other electronic communication products, which it is applied LCD (liquid crystal display; LCD) drive is particularly important. 现今业界已开发出32伏特、0.18微米高压工艺技术的产品，以应用于可携式单芯片薄膜晶体管液晶显示器(thin film transistor liquid crystal display; TFT LCD)等领域， 这项技术的特点是可以为栅极驱动、源极驱动及控制器提供不同的电压，使其能够嵌入超高密度的静态随机存取存储器(static random access memory; SRAM)元件中，并制造出面积更小的芯片。 Today the industry has developed a 32 volt, 0.18-micron high-voltage process technology products, to apply to portable single-chip TFT-LCD (thin film transistor liquid crystal display; TFT LCD) and other areas, this technology is characterized for a gate driver, a source driver and a controller to provide different voltages, it can be embedded in ultra-high density static random access memory (static random access memory; SRAM) element, and producing a smaller chip area. 请参考图1,图1为现有高压元件结构IO的上视图。 Please refer to FIG. 1, FIG. 1 is a conventional high voltage element structure of the IO view. 如图1所示，高压元件结构IO形成于一P型基底(图未显示）中，包括一第一N型阱区12(如虛线所示区域)、 一第二N型阱区14(如虛线所示区域)、 一连接部分第一N型阱区12与第二N型阱区14的通道扩散区(channel diffusion) 16(如虛线所示区域)及一覆盖于通道扩散区16上方的多晶硅栅极18。 1, the high-pressure IO element structure formed in a P-type substrate (not shown), including 12 (shown as a dotted line area) of a first N-type well region, a second N-type well region 14 ( the area shown as dashed lines), a connecting portion of the first N-type well region 12 and the second N-type well region channel diffusion region (channel diffusion) 14 of 16 (the area shown as dashed lines) and a cover to channel diffusion region 16 above the polysilicon gate 18. 高压元件结构10还包括一源极扩散区20位于第一N型阱区12中、 一漏极扩散区22位于第二N 型阱区14中，以及浅沟隔离（shallow trench isolation )24位于P型基底(图未显示），用以将源极扩散区20、漏极扩散区22及通道扩散区16作良好的隔离。 High voltage element structure 10 further includes a source diffusion region 20 located between the first N-type well region 12, a drain diffusion region 22 in the second N-type well region 14, and a shallow trench isolation (shallow trench isolation) 24 is located in P type substrate (not shown) to the source diffusion region 20, the drain diffusion region 22 and the channel diffusion region 16 for good isolation. 其中，源极扩散区20、漏极扩散区22及多晶硅栅极18分别藉由接触插塞26、 28、 30、 32及34连接外部电路(图未显示）。 Wherein, the source diffusion region 20, the drain diffusion region 22 and the polysilicon gate contact plug 18 respectively by 26, 28, 30, 32 and 34 connected to an external circuit (not shown). 为了避免通道扩散区的角落产生漏电流的现象，根据现有技术，高压元件结构10经过改良，使得通道扩散区16的长度大于源极扩散区20及漏极扩散区22的长度。 In order to avoid the corner of the channel diffusion region leakage current phenomenon, according to the prior art, the high pressure element of improved structure 10, such that the length of the channel region 16 is larger than the diffusion source diffusion region 20 and the length of the drain diffusion region 22. 然而，现今元件的尺寸越缩越小，造成通道扩散区16长于源极扩散区20及漏极扩散区22的突出区域36及38具有高栅极电压的地方产生许多寄生电流(parasitical current),并造成不可预测的输出电流电压特性(IV characteristic)曲线。 Today, however, the size of elements of the more smaller and smaller, resulting in channel diffusion region 16 is longer than the protruding area of the source diffusion region 20 and the drain diffusion region 22, 36 and 38 places with a high gate voltage produces many parasitic current (parasitical current), and cause unpredictable output current-voltage characteristic (IV characteristic) curve. 发明内容有鉴于此，本发明的主要目的在于提供一种高压元件结构，以解决前述的问题。 SUMMARY OF THE INVENTION The main object of the present invention is to provide a high element structure to solve the aforementioned problems. 为达上述目的，根据本发明的优选实施例，本发明的高压元件结构设于一第一导电类型的一基底中，且高压元件结构包含具有第二导电类型的一第一阱区及一第二阱区位于基底中、具有一第一长度的一源极扩散区及一漏极扩散区分别位于第一阱区及第二阱区中以及具有一第二长度的一导体栅极层位于基底表面。 To achieve the above object, according to a preferred embodiment of the present invention, the structure of the present invention are high-voltage components provided on a substrate of a first conductivity type, and the high-voltage element structure comprises a first well region and a second conductivity type having a first Two well region located in the substrate having a source diffusion region and a drain diffusion region of a first length and are located in a first well region and a second well region of a second conductive gate layer having a length of substrate is located surface. 其中，第二长度大于第一长度，因此形成二突出区域于导体栅极层两侧。 Wherein the second length is greater than the first length, thus forming two protruding regions on both sides of the gate layer conductor. 本发明还包括一栅极氧化层位于导体栅极层所覆盖的基底表面、 一通道扩散区位于被导体栅极层所覆盖的基底中并位于部分第一阱区及第二阱区上方、至少一浅沟隔离位于基底中以隔离源极扩散区、漏极扩散区及通道扩散区以及二窗口分别位于各突出区域。 The present invention further includes a gate oxide layer on the gate layer conductor covered surface of the substrate, a diffusion region located in the channel is a gate conductor layer covered portion of the first substrate and positioned well above the well region and the second region, at least a shallow trench isolation located in the substrate to isolate the source diffusion region, a drain diffusion region and the channel diffusion region and two windows are located in each projection area. 其中，各窗口暴露出部分栅极氧化层。 Wherein each of the window to expose a portion of the gate oxide layer. 由于本发明形成二窗口于导体栅极层两侧突出的区域，故可有效地抑制寄生电流(parasitical current)的产生，并仍保有现有高压元件结构的长通道扩散区可避免通道扩散区的角落产生漏电流现象的优点，因此本发明非常有利于小尺寸的高压元件的制作。 Since the present invention is formed on the gate layer conductor projecting on both sides of the second window area, it is possible to effectively suppress parasitic current (parasitical current) generation, and still retains long channel diffusion regions existing high pressure passage member structure avoids diffusion region corner advantage of generating leakage current phenomenon, the present invention is very conducive to the production of small-sized high-voltage components. 为了进一步了解本发明的特征及技术内容，请参阅以下有关本发明的详细说明与附图。 In order to further understand the characteristics and technical contents of the present invention, please refer to the following detailed description of the present invention relating to the accompanying drawings. 然而附图仅供参考与辅助说明用，并非用来对本发明加以限制。 However, for your reference only and HELP, and it is not used to limit the present invention. 附图说明图1为现有高压元件结构的上视图。 Figure 1 is a view of a conventional high-voltage component structure. 图2为本发明的高压元件结构的上视图。 On the View high-voltage component structure in Figure 2 of the present invention. 图3为图2中沿切线AA，的剖面示意图。 Figure 3 is a cross-sectional schematic in Figure 2 along the tangent AA, of. 图4为图2中沿切线BB，的剖面示意图。 Figure 4 is a schematic cross-sectional view along the tangent 2 BB, the. 简单符号说明10 高压元件结构12 第一N型阱区14 第二N型阱区16 通道扩散区18 多晶硅栅极 20 源极扩散区22 漏极扩散区 24 浅沟隔离26 4矣触插塞 28 才妻触插塞30 接触插塞 32 接触插塞34 接触插塞 36 突出区域38 突出区域 50 高压元件结构52 第一阱区 54 第二阱区56 源极扩散区 58 漏极扩散区60 导体栅极层 62 通道扩散区64 突出区域 66 突出区域68 窗口 70 窗口72 接触插塞 74 接触插塞76 接触插塞 78 接触插塞80 接触插塞 82 浅沟隔离84 基底 86 栅极氧化层具体实施方式请参考图2，图2为本发明的高压元件结构50的上视图。 Simple Signs 10 high-voltage component structure 12 of the first N-type well region 14 of the second N-type well region 16-channel diffusion region 18 of the polysilicon gate 20 source diffusion region 22 of the drain diffusion region 24 shallow trench isolation 264 men touch the plug 28 Wife just touch the plug 30 contact plug 32 contact plug 34 contact plug 36 projecting regions 38 projecting regions 50 high-voltage component structure 52 of the first well region 54 of the second well region 56 of the source diffusion region 58 gate conductor drain diffusion region 60 electrode layer protruding region 66 64 62 channel diffusion region projecting window 70 window area 68 72 74 contact plug contact plug 76 contact plug 78 contact plug 80 contact plug 82 84 base 86 shallow trench isolation gate oxide layer DETAILED DESCRIPTION Refer to Figure 2, the high-voltage component structure Figure 2 is a top view of the invention 50. 如图2所示， 本发明的高压元件结构50设于一第一导电类型的一基底(图未显示）中，且该高压元件结构包含具有第二导电类型的一第一阱区52(如虛线所示区域)及一第二阱区54(如虛线所示区域)位于基底中、具有一第一长度L,的一源极扩散区56及一漏极扩散区58分别位于第一阱区52及第二阱区54中、具有一第二长度L2的一导体栅极层60位于基底表面、 一通道扩散区62(如虛线所示区域)位于被导体栅极层60所覆盖的基底中并位于部分第一阱区52及第二阱区54上方以及一栅极氧化层（图未显示)位于导体栅极层60所覆盖的基底表面。 2, the structure of the high-pressure device 50 of the present invention, a first conductivity type provided on a substrate (not shown), and the high-voltage element structure comprises a first well region of second conductivity type 52 (e.g. region shown in dashed lines) and a second well region 54 (shown in phantom area) located in the substrate, having a first length L, a source diffusion region 56 and a drain diffusion region 58 are located in the first well region 52 and the second well region 54 having a length L2 of a second conductive gate layer 60 is located in the substrate surface 62 (shown in phantom area) located in a channel diffusion region is covered by the gate conductor layer 60 The substrate and positioned above the first well region 52 and the second well region 54 and a portion of gate oxide layer (not shown) located on the gate conductor layer 60 covering the surface of the substrate. 其中，第一导电类型具有P型掺杂者，第二导电类型具有N型掺杂者， 以使高压元件结构50位于P型掺杂的基底中并具有N型掺杂的第一阱区52 与第二阱区54，或者第一导电类型具有N型掺杂者，第二导电类型具有P 型掺杂者，以使高压元件结构50位于N型掺杂的基底中并具有P型掺杂的第一阱区52与第二阱区54。 Wherein the first conductivity type having a P-type doped by the second conductivity type having an N-type dopant are, so that the structure of the high-pressure member 50 is located in the P-type doped N-type substrate and having a first doped well region 52 and a second well region 54, or a first conductivity type having an N-type doped by the second conductivity type having a P-type dopant are, so that the structure of the high-pressure member 50 is located in the N-type doped substrate and having a P-type doping The first well region 52 and the second well region 54. 导体栅极层60可由多晶硅(poly-silicon)或金属多晶硅化合物与多晶硅所结合的双层结构等等所构成。 The gate conductor layer 60 may be formed of polycrystalline silicon (poly-silicon) of polycrystalline silicon or metal compound bound double polysilicon structure, etc. of the composition. 上述第二长度L2大于第一长度L,，因此导体栅极层60的长度L2大于源极扩散区56及漏极扩散区58的长度L,，于是形成二突出区域64与66 于导体栅极层60两侧，且导体栅极层60两侧的突出区域64与66具有二窗口68与70以暴露出部分栅极氧化层。 Said first length is greater than the second length L2 and therefore the length L ,, L2 conductive gate layer 60 is greater than the length of the source diffusion region 56 and the drain diffusion region 58 is formed of two L ,, then projecting regions 64 and gate conductor 66 layer 60 on both sides, and both sides of the gate conductor layer 60 and the projecting region 64 a window 66 having two portions 68 and 70 to expose the gate oxide layer. 其中，本发明于定义出导体栅极层60 的时候，亦同时形成窗口68与70。 However, the present invention is to define a gate conductor layer 60 when the window 68 is also formed simultaneously with 70. 通道扩散区62的长度大于源极扩散区56及漏极扩散区58的长度，因此本发明可有效避免通道扩散区62的角落产生漏电流的现象。 Length of the channel diffusion region 62 is larger than the source diffusion region 56 and the drain diffusion zone length 58, the present invention can effectively avoid the corner of the channel diffusion region 62 of the leakage current phenomenon. 本发明的高压元件结构50还包括接触插塞72、 74、 76、 78及80分别位于源极扩散区56、漏极扩散区58及导体栅极层60的突出区域64上方以连接外部电路（图未显示）以及至少一浅沟隔离（shallow trench isolation)82位于基底中以隔离源极扩散区56、漏极扩散区58及通道扩散区62。 High voltage device structure of the present invention 50 further comprises a contact plug 72, 74, 76, 78 and 80 are located at the source diffusion region 56, the drain region 64 projecting upward diffusion region 58 and the gate conductor layer 60 is connected to an external circuit ( Figure not shown) and at least one shallow trench isolation (shallow trench isolation) 82 located in the substrate to isolate the source diffusion region 56, the drain diffusion region 58 and the channel diffusion region 62. 为了更清楚说明本发明的高压元件结构，请参考图3及图4，图3为图2中沿切线AA，的剖面示意图及图4为图2中沿切线BB，的剖面示意图。 In order to more clearly illustrate the structure of the present invention, a high pressure device, refer to FIG. 3 and FIG. 4, FIG. 2 FIG. 3 is a tangential AA, a cross-sectional schematic view of FIG. 2 and FIG. 4 is in tangential BB, cross-sectional schematic view. 如图3所示，本发明的高压元件结构50位于第一导电类型的基底84中，包含具有第二导电类型的第一阱区52及第二阱区54位于基底84中、源极扩散区56及漏极扩散区58分别位于第一阱区52及第二阱区54中、导体栅极层60位于基底84表面、通道扩散区62位于被导体栅极层60所覆盖的基底84 中并位于部分第一阱区52及第二阱区54上方、栅极氧化层86位于导体栅极层60与基底84表面之间以及浅沟隔离82位于基底84中以隔离源极扩散区56、漏极扩散区58及通道扩散区62。 As shown, the structure of the present invention, the high pressure element 50 of the first conductivity type on the third substrate 84 includes a first well region of the second conductivity type well region 52 and the second substrate 54 is 84, the source diffusion region 56 and the drain diffusion region 58 are located in a first well region 52 and the second well region 54, gate conductor layer 60 is located on the surface of the substrate 84, the channel diffusion region 62 are located in the gate conductor layer 60 covering the substrate 84 and Located portion of the first well region 52 and the second well region 54 above the gate oxide layer 86 is located between the gate conductor layer 60 and the substrate 84 surface and shallow trench isolation 82 is a substrate 84 to isolate the source diffusion region 56, the drain diffusion region 58 and the channel diffusion region 62. 如图4所示，导体栅极层60的突出区域64具有窗口68以暴露出部分栅极氧化层86。 4, the protruding region 64 of conductive gate layer 60 having a window 68 to expose a portion of the gate oxide layer 86. 其中，导体栅极层60覆盖于基底84中的通道扩散区62上方，且基底84中包括浅沟隔离82以形成隔离。 Wherein the gate conductor layer 60 covering the substrate 84 in the top of the channel diffusion region 62, and the substrate 84 including a shallow trench isolation 82 to form isolation. 相较于现有技术，由于本发明于导体栅极层两侧突出的区域形成二窗而能抑制寄生电流的产生，并能保有现有高压元件结构的长通道扩散区可避免通道扩散区的角落产生漏电流现象的优点，因此本发明非常有利于小尺寸的高压元件的制作。 Compared to the prior art, since the present invention is formed on both sides of the second window gate layer conductor protruding region can be suppressed while the generation of parasitic currents, and can maintain the existing long channel diffusion region to avoid the high pressure of the element structure of the channel diffusion region corner advantage of generating leakage current phenomenon, the present invention is very conducive to the production of small-sized high-voltage components. 以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。 The foregoing is only preferred embodiments of the present invention, any claim under this claimed invention made modifications and alterations, also belong to the scope of the invention.