CN100403551C - High-tension element structure - Google Patents
High-tension element structure Download PDFInfo
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- CN100403551C CN100403551C CNB2005100543155A CN200510054315A CN100403551C CN 100403551 C CN100403551 C CN 100403551C CN B2005100543155 A CNB2005100543155 A CN B2005100543155A CN 200510054315 A CN200510054315 A CN 200510054315A CN 100403551 C CN100403551 C CN 100403551C
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- element structure
- tension element
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- grid layer
- well region
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Abstract
The present invention relates to a high-voltage element structure arranged in a first current conducting type substrate, which comprises a first well area having a second current conducting type and a second well area positioned in a substrate, a source electrode diffusion area with a first length and a drain electrode diffusion area respectively positioned in the first well area and the second well area, and a conductor grid layer with a second length positioned on the surface of the substrate, wherein the second length is greater than the first length, and thus, two protruded areas are formed on both sides of the conductor grid layer. The present invention also comprises two windows respectively positioned on each of the protruded areas.
Description
Technical field
The present invention relates to a kind of high-tension element structure, particularly relate to a kind of high-tension element structure that can suppress parasite current (parasitical current).
Background technology
In recent years, flourish along with telecommunications products such as mobile phones, its applied LCD (liquid crystal display; LCD) seem especially important of driver.Industry has been developed the product of 32 volts, 0.18 micron high-pressure process technology now, to be applied to Portable single-chip Thin Film Transistor-LCD (thin film transistor liquid crystal display; TFT LCD) field such as, the characteristics of this technology are to provide different voltage for gate driving, source drive and controller, make its static RAM that can embed super-high density (static random access memory; SRAM) in the element, and produce the littler chip of area.
Please refer to Fig. 1, Fig. 1 is the top view of existing high-tension element structure 10.As shown in Figure 1, high-tension element structure 10 is formed in the P type substrate (figure does not show), comprises that one the one N type well region 12 (zone shown in dotted line), one the 2nd N type well region 14 (zone shown in dotted line), a junction divide the passage diffusion region (channel diffusion) 16 (zone shown in dotted line) and of a N type well region 12 and the 2nd N type well region 14 to be covered in the polysilicon gate 18 of 16 tops, passage diffusion region.High-tension element structure 10 comprises that also one source pole diffusion region 20 is arranged in a N type well region 12, a drain diffusion regions 22 is arranged in the 2nd N type well region 14, and shallow isolating trough (shallow trench isolation) 24 is positioned at P type substrate (figure show), in order to good isolation is made in source diffusion region 20, drain diffusion regions 22 and passage diffusion region 16.Wherein, source diffusion region 20, drain diffusion regions 22 and polysilicon gate 18 connect external circuit (figure does not show) by contact plunger 26,28,30,32 and 34 respectively.
Produce the phenomenon of leakage current for fear of the corner of passage diffusion region, according to prior art, high-tension element structure 10 is through improvement, makes the length of passage diffusion region 16 greater than the length of source diffusion region 20 and drain diffusion regions 22.Yet, size of component contracts littler and littler now, the place that the outburst area 36 and 38 that causes passage diffusion region 16 to be longer than source diffusion region 20 and drain diffusion regions 22 has high grid voltage produces many parasite currents (parasitical current), and causes uncertain output current voltage characteristic (I-V characteristic) curve.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of high-tension element structure, to solve aforesaid problem.
For reaching above-mentioned purpose, according to a preferred embodiment of the invention, high-tension element structure of the present invention is located in the substrate of one first conduction type, and high-tension element structure comprises one first well region and one second well region with second conduction type and is arranged in substrate, has the conductor grid layer that the one source pole diffusion region of one first length and a drain diffusion regions lay respectively at first well region and second well region and have one second length and be positioned at substrate surface.Wherein, therefore second length form two outburst areas in conductor grid layer both sides greater than first length.The present invention comprises that also substrate surface, a passage diffusion region that a grid oxic horizon is arranged in the conductor grid layer and is covered are arranged in the substrate that is covered by the conductor grid layer and are positioned at part first well region and second well region top, at least one shallow isolating trough are positioned at substrate and lay respectively at each outburst area to isolate source diffusion region, drain diffusion regions and passage diffusion region and two windows.Wherein, each window exposes the part of grid pole oxide layer.
Because the present invention forms two windows in the side-prominent zone of conductor grid layer two, so can suppress the generation of parasite current (parasitical current) effectively, and still possess the advantage that the corner generation leakage phenomenon of passage diffusion region can be avoided in the long-channel diffusion region that has high-tension element structure now, so the present invention is very beneficial for the making of undersized high voltage device.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 is the top view of existing high-tension element structure.
Fig. 2 is the top view of high-tension element structure of the present invention.
Fig. 3 is along the generalized section of tangent line AA ' among Fig. 2.
Fig. 4 is along the generalized section of tangent line BB ' among Fig. 2.
The simple symbol explanation
10 high-tension element structures 12 a N type well region
14 the 2nd N type well regions, 16 passage diffusion regions
18 polysilicon gates, 20 source diffusion region
22 drain diffusion regions, 24 shallow isolating trough
26 contact plungers, 28 contact plungers
30 contact plungers, 32 contact plungers
34 contact plungers, 36 outburst areas
38 outburst areas, 50 high-tension element structures
52 first well regions, 54 second well regions
56 source diffusion region, 58 drain diffusion regions
60 conductor grid layers, 62 passage diffusion regions
64 outburst areas, 66 outburst areas
68 windows, 70 windows
72 contact plungers, 74 contact plungers
76 contact plungers, 78 contact plungers
80 contact plungers, 82 shallow isolating trough
84 substrates, 86 grid oxic horizons
Embodiment
Please refer to Fig. 2, Fig. 2 is the top view of high-tension element structure 50 of the present invention.As shown in Figure 2, high-tension element structure 50 of the present invention is located in the substrate (figure show) of one first conduction type, and this high-tension element structure comprises one first well region 52 (zone shown in dotted line) and one second well region 54 (zone shown in dotted line) with second conduction type and is arranged in substrate, has one first length L
1An one source pole diffusion region 56 and a drain diffusion regions 58 lay respectively in first well region 52 and second well region 54, have one second length L
2A conductor grid layer 60 be arranged in substrate surface, a passage diffusion region 62 (zone shown in dotted line) and be positioned at the substrate that is covered by conductor grid layer 60 and be positioned at part first well region 52 and second well region, 54 tops and a grid oxic horizon (figure shows) are positioned at the substrate surface that conductor grid layer 60 is covered.Wherein, first conduction type has P type doping person, second conduction type has N type doping person, so that high-tension element structure 50 is arranged in the substrate of P type doping and has first well region 52 and second well region 54 that the N type mixes, perhaps first conduction type has N type doping person, second conduction type has P type doping person, so that high-tension element structure 50 is arranged in the substrate of N type doping and has first well region 52 and second well region 54 that the P type mixes.Double-decker that conductor grid layer 60 can be combined with polysilicon institute by polysilicon (poly-silicon) or metal multi-crystal silicification compound or the like constitute.
Above-mentioned second length L
2Greater than first length L
1, so the length L of conductor grid layer 60
2Length L greater than source diffusion region 56 and drain diffusion regions 58
1So, form two outburst areas 64 and 66 in conductor grid layer 60 both sides, and the outburst area 64 and 66 of conductor grid layer 60 both sides has two windows 68 and 70 to expose the part of grid pole oxide layer.Wherein, the present invention also forms window 68 and 70 simultaneously when defining conductor grid layer 60.The length of passage diffusion region 62 is greater than the length of source diffusion region 56 and drain diffusion regions 58, so the present invention can effectively avoid the corner of passage diffusion region 62 to produce the phenomenon of leakage current.
High-tension element structure 50 of the present invention comprises that also outburst area 64 tops that contact plunger 72,74,76,78 and 80 lays respectively at source diffusion region 56, drain diffusion regions 58 and conductor grid layer 60 are arranged in substrate to isolate source diffusion region 56, drain diffusion regions 58 and passage diffusion region 62 to connect external circuit (figure shows) and at least one shallow isolating trough (shallow trench isolation) 82.
In order more to clearly demonstrate high-tension element structure of the present invention, please refer to Fig. 3 and Fig. 4, Fig. 3 be among Fig. 2 along the generalized section of tangent line AA ' and Fig. 4 among Fig. 2 along the generalized section of tangent line BB '.As shown in Figure 3, high-tension element structure 50 of the present invention is arranged in the substrate 84 of first conduction type, comprises first well region 52 and second well region 54 with second conduction type and is arranged in substrate 84, source diffusion region 56 and drain diffusion regions 58 lay respectively in first well region 52 and second well region 54, conductor grid layer 60 is positioned at substrate 84 surfaces, passage diffusion region 62 is arranged in the substrate 84 that is covered by conductor grid layer 60 and is positioned at part first well region 52 and second well region, 54 tops, grid oxic horizon 86 between conductor grid layer 60 and substrate 84 surfaces and shallow isolating trough 82 be arranged in substrate 84 to isolate source diffusion region 56, drain diffusion regions 58 and passage diffusion region 62.
As shown in Figure 4, the outburst area 64 of conductor grid layer 60 has window 68 to expose part of grid pole oxide layer 86.Wherein, conductor grid layer 60 is covered in 62 tops, passage diffusion region in the substrate 84, and comprises in the substrate 84 that shallow isolating trough 82 is to form isolation.
Compared to prior art, because the present invention forms two windows in conductor grid layer two side-prominent zones, so can avoid protruding from the voltage effects that the conductor grid layer of passage diffusion region is caused effectively, and then can suppress the generation of parasite current, and can possess the advantage that the corner generation leakage phenomenon of passage diffusion region can be avoided in the long-channel diffusion region that has high-tension element structure now, so the present invention is very beneficial for the making of undersized high voltage device.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (16)
1. high-tension element structure, this high-tension element structure is located in the substrate of one first conduction type, and this high-tension element structure comprises:
Be arranged in one first well region with one second conduction type and one second well region of this substrate;
Lay respectively at an one source pole diffusion region with one first length and a drain diffusion regions in this first well region and this second well region;
Be positioned at the conductor grid layer with one second length of this substrate surface, wherein this second length is greater than this first length, to form two outburst areas in these conductor grid layer both sides;
One passage diffusion region is arranged in this substrate that is covered by this conductor grid layer; And
Two windows lay respectively in this conductor grid layer of these outburst areas,
Wherein this substrate surface of being covered of this conductor grid layer also comprises a grid oxic horizon, and described window exposes this grid oxic horizon of part.
2. high-tension element structure as claimed in claim 1, wherein this first conduction type has the doping of P type, and this second conduction type has the N type and mixes.
3. high-tension element structure as claimed in claim 1, wherein this first conduction type has the doping of N type, and this second conduction type has the P type and mixes.
4. high-tension element structure as claimed in claim 1, wherein this conductor grid layer is constituted by polysilicon.
5. high-tension element structure as claimed in claim 1, wherein this passage diffusion region is positioned at this first well region of part and this second well region top.
6. high-tension element structure as claimed in claim 1 also comprises a contact plunger, is positioned at these outburst area tops.
7. high-tension element structure as claimed in claim 1 also comprises at least one contact plunger, is positioned at this source diffusion region top.
8. high-tension element structure as claimed in claim 1 also comprises at least one contact plunger, is positioned at this drain diffusion regions top.
9. high-tension element structure as claimed in claim 1 also comprises at least one shallow isolating trough that is arranged in this substrate, to isolate this source diffusion region, this drain diffusion regions and this passage diffusion region.
10. high-tension element structure, this high-tension element structure is located in the substrate of one first conduction type, and this high-tension element structure comprises:
Be arranged in one first well region with one second conduction type and one second well region of this substrate;
Lay respectively at an one source pole diffusion region with one first length and a drain diffusion regions in this first well region and this second well region;
Be positioned at the conductor grid layer with one second length of this substrate surface, wherein this second length forms two outburst areas greater than this first length in these conductor grid layer both sides;
One grid oxic horizon is positioned at this substrate surface that this conductor grid layer is covered;
One passage diffusion region is arranged in this substrate that is covered by this conductor grid layer, and is positioned at this first well region of part and this second well region top;
Be arranged at least one shallow isolating trough of this substrate, to isolate this source diffusion region, this drain diffusion regions and this passage diffusion region; And
Two windows lay respectively in this conductor grid layer of these outburst areas, and these windows expose this grid oxic horizon of part respectively.
11. high-tension element structure as claimed in claim 10, wherein this first conduction type has the doping of P type, and this second conduction type has the N type and mixes.
12. high-tension element structure as claimed in claim 10, wherein this first conduction type has the doping of N type, and this second conduction type has the P type and mixes.
13. high-tension element structure as claimed in claim 10, wherein this conductor grid layer is constituted by polysilicon.
14. high-tension element structure as claimed in claim 10 also comprises a contact plunger, is positioned at these outburst area tops.
15. high-tension element structure as claimed in claim 10 also comprises at least one contact plunger, is positioned at this source diffusion region top.
16. high-tension element structure as claimed in claim 10 also comprises at least one contact plunger, is positioned at this drain diffusion regions top.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100543155A CN100403551C (en) | 2005-03-08 | 2005-03-08 | High-tension element structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100543155A CN100403551C (en) | 2005-03-08 | 2005-03-08 | High-tension element structure |
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| CN1832197A CN1832197A (en) | 2006-09-13 |
| CN100403551C true CN100403551C (en) | 2008-07-16 |
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| CNB2005100543155A Active CN100403551C (en) | 2005-03-08 | 2005-03-08 | High-tension element structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5973362A (en) * | 1997-04-21 | 1999-10-26 | Lg Semicon, Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6228663B1 (en) * | 1997-12-19 | 2001-05-08 | Advanced Micro Devices, Inc. | Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength |
| US6369422B1 (en) * | 2001-05-01 | 2002-04-09 | Atmel Corporation | Eeprom cell with asymmetric thin window |
-
2005
- 2005-03-08 CN CNB2005100543155A patent/CN100403551C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5973362A (en) * | 1997-04-21 | 1999-10-26 | Lg Semicon, Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6228663B1 (en) * | 1997-12-19 | 2001-05-08 | Advanced Micro Devices, Inc. | Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength |
| US6369422B1 (en) * | 2001-05-01 | 2002-04-09 | Atmel Corporation | Eeprom cell with asymmetric thin window |
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| Publication number | Publication date |
|---|---|
| CN1832197A (en) | 2006-09-13 |
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