CN100433322C - The encapsulation of integrated circuit chip without lead - Google Patents
The encapsulation of integrated circuit chip without lead Download PDFInfo
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- CN100433322C CN100433322C CNB2006101613978A CN200610161397A CN100433322C CN 100433322 C CN100433322 C CN 100433322C CN B2006101613978 A CNB2006101613978 A CN B2006101613978A CN 200610161397 A CN200610161397 A CN 200610161397A CN 100433322 C CN100433322 C CN 100433322C
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- integrated circuit
- chip
- substrate
- circuit chip
- bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
This invention relates to one integration circuit chip sealing without wireless, which comprises baseboard, integration circuit chip, several key wire and resin layers, wherein, the baseboard front and back surfaces are distributed with several connection wire and reverse connection wire; the integration circuit chip is set on front of baseboard with weld disc bonding through bonding line and positive wires with other end connected to metal hole; the reverse connection wire other end is as weld disc and the resin layer covers the baseboard front and integration circuit chip. The process method comprises steps of designing and processing mode, baseboard designing, integration circuit chip and baseboard adding, bonding integration circuit chip and baseboard.
Description
Technical field
The present invention relates to a kind of leadless integrated circuit Chip Packaging.
Background technology
Integrated circuit encapsulation is laid, fixes, seals, is protected the chip except plaing a part, and also provides current path with the circuit on the drive integrated circult chip, the signal on the distribution integrated circuit (IC) chip, and the heat that produces during with chip operation is taken away.Along with the increase of operating rate, add increasing sharply of low-work voltage and chip pin, electric capacity and inductance parasitic couplings effect increase sharply, and the uncared-for electric effect of some scripts has begun to influence the operate as normal of circuit in the encapsulation.Therefore the requirement of integrated circuit encapsulation is except satisfying basic being electrically connected the function, also wants to solve the problems of Signal Integrity that high frequency/high speed that the development because of the ic core chip technology proposes and number of pins increase cause.
Therefore, integrated circuit encapsulation is increasing to the influence of device performance, and the restriction that the performance of some integrated circuit is subjected to encapsulation technology and the restriction that is subjected to the ic core piece performance are much at one, and be even bigger.The integrated circuit encapsulation is the indivisible part of development of electronic devices, and it relates to multi-disciplinary technology such as material, electronics, heat, mechanics, chemistry, machinery and reliability, more and more receives the extensive attention and the concern of academia and industrial quarters.
The PLCC type that connects is drawn in DIP type, surface-pasted QFP type and Plastic Package side that integrated circuit package type commonly used at present has pin to insert, sees also Fig. 7～9.They all need lead frame, during making chip are placed on the lead frame, and the pad on the chip is connected to the front end of pin by the method for spun gold or aluminium wire bonding, links to each other with external circuit by pin then.DIP type pin 11 is long and thick, has both influenced the frequency characteristic of encapsulation back chip, is difficult for making the encapsulation miniaturization again.Continuous development along with integrated circuit technique, to the high frequency/raising of electrical characteristics such as high speed requirement and the increase of number of pins, the pin insert type develops into surface attaching type and the type of connecing 12,13 is drawn in the side, and the general weak point of their pin (line) also has frequency characteristic preferably.But because they all need lead frame, for guaranteeing the intensity and the globality of lead frame, each lead-in wire on the framework connects with same metal, must cut off the connecting line of the key that respectively goes between before encapsulation respectively more simultaneously.This needs special equipment on the one hand, increases processing step, and the consumption that can increase electric conducting material simultaneously will inevitably increase production cost.Recently, the BGA type integrated circuit encapsulation that pin is ball grid array occurs, seen also Figure 10.Though pin shortens greatly and has frequency characteristic preferably, the connection of spherical leg need have special equipment and corresponding process, can make production efficiency reduce cost up relatively equally.
Summary of the invention
The objective of the invention is to design a kind of leadless integrated circuit Chip Packaging that a kind of production technology is simple, cost is low and frequency characteristic is good, it is realized by following technical scheme:
Comprise substrate, integrated circuit (IC) chip, some bonding lines and capping layer, the obverse and reverse of wherein said substrate is furnished with some positive interconnection lines and anti-interconnection line respectively, integrated circuit (IC) chip places substrate front side, pad on it is by bonding line and positive interconnection line one end golden finger bonding, the other end of positive interconnection line is communicated with pairing anti-interconnection line one end by the metallization via hole, the other end of anti-interconnection line is a pad, and capping layer is sealed on substrate front side and the integrated circuit (IC) chip.
The pad of some anti-interconnection line one ends of some golden fingers of described substrate front side and substrate reverse side distributes in the form of a ring around the integrated circuit (IC) chip periphery.
Two or more independently integrated circuit (IC) chip tile on the described substrate.
The integrated circuit (IC) chip method for packing comprises the steps:
A) designing and producing of encapsulating mould comprises structural design and material selection.Its structure optimization disc structure, design casting groove on it, this groove preferably is arranged on the disc centre place, and be preferably designed to a rectangular recess, its bottom land is provided with out nib, is convenient to packaged integrated circuit (IC) chip is ejected, and goes out nib and preferentially is arranged on the bottom land center.The physical dimension of casting groove is determined according to the size of integrated circuit (IC) chip, the number of packaged chip, concrete packaging pin number.The material of mould should have not yielding, high temperature resistant and be convenient to the characteristics of the demoulding, preferably uses polytetrafluoroethylmaterial material.
B) designing and producing of substrate designed anti-interconnection line, connected pad that comprises positive positive interconnection line, connected golden finger and reverse side and the metallization via hole that is connected positive and negative interconnection line according to the distribution of the pad on the chip and the quantity of chip.
C) integrated circuit (IC) chip and substrate is bonding, and integrated circuit (IC) chip is pasted substrate front side, and puts into the heating furnace baking of nitrogen environment, 110～130 ℃ of heating-up temperatures, 15 to 25 minutes time.
D) bonding integrated circuit (IC) chip and substrate connect pad on the described chip and the golden finger on the substrate with bonding line.
E) the casting capping layer is put into described mould with the substrate that is connected with chip, pours the resin of fusion into mould again, scrape plane surface after being full of, and put into the heating furnace baking of nitrogen environment, 110～130 ℃ of heating-up temperatures, 25～35 minutes time, cool to normal temperature with the furnace and take out.
The invention has the beneficial effects as follows: do not need lead frame, do not need professional sealed in unit, technological process is simple and easy to realize low cost of manufacture; The encapsulation outline no-lead, thereby the encapsulation after chip can have better frequency characteristic, be applicable to the encapsulation of single chip or a plurality of chips.
Description of drawings
Fig. 1 encapsulating mould structural representation.
Fig. 2 substrate front side structure chart.
Fig. 3 substrate reverse side structure chart.
One of Fig. 4 structural representation of the present invention.
The A-A cross-sectional schematic of one of Fig. 5 structural representation of the present invention.
Two of Fig. 6 structural representation of the present invention.
The DIP type integrated circuit (IC) chip encapsulation that Fig. 7 pin inserts.
The encapsulation of the surface-pasted QFP type of Fig. 8 integrated circuit (IC) chip.
Fig. 9 draws the side PLCC type integrated circuit (IC) chip encapsulation that connects.
Figure 10 pin is the integrated circuit encapsulation of ball grid array.
Among the figure, 1 substrate, 2 bonding lines, 3 integrated circuit (IC) chip, 4 positive interconnection lines, 5 golden fingers, 6 metallic vias, the pad of 7 substrate reverse side, 8 anti-interconnection lines, 9 epoxy resin capping layers, 10 place chip center district, 11,12 pins, 13 outside line pass meet the place, 14 soldered balls, 20 capping moulds, 21 casting grooves, 22 go out nib.
Embodiment
The present invention will be further described below in conjunction with the drawings and specific embodiments.
At first design and produce encapsulating mould 20.Contrast Fig. 1, this mould is made of polytetrafluoroethylmaterial material, is disc-shaped structure, and heart position is provided with the casting groove 21 of a rectangle therein, and the bottom land center has one to go out nib 22.
Design and produce substrate 1 again, present embodiment is according to one 0.8 * 0.7mm
2The coding chip design.Fig. 2 is seen in the distribution of the positive interconnection line 4 of substrate front side, golden finger 5 and metallic vias 6, and Fig. 3 is seen in the distribution of the anti-interconnection line 8 of substrate reverse side, pad 7 and metallic vias 6.As seen from the figure, some pads 7 of Zheng Mian some golden fingers 5 and reverse side all are the chips of placing round the substrate front side center 3 and surround similar straight-flanked ring.
After completing, substrate 1 just can carry out the bonding of integrated circuit (IC) chip.Said chip is simultaneously brushed in the red gluing placement chip center district 10 that is attached to substrate front side, and put into the heating furnace baking of nitrogen environment, heating and temperature control is at 110 ℃, 15 minutes time.
Take out from stove the baking back, carries out the bonding of integrated circuit (IC) chip and substrate.Connect pad on the chip with aluminium wire (bonding line a 2) end, an end connects the golden finger 5 on the substrate, sees also Fig. 4, Fig. 5.After all pads on the chip and all golden fingers 5 on the substrate all connect one to one, just can carry out the casting of capping layer 9.At this moment, the above-mentioned substrate that connects chip is put into the casting groove 21 of encapsulating mould 20, again the epoxy resin of fusion is poured in this groove, after being full of this groove, the epoxy tree scrapes plane surface, and the heating furnace baking of putting into nitrogen environment, 110～130 ℃ of heating-up temperatures, 25～35 minutes time, cooling to normal temperature with the furnace takes out, the push rod of depanning (not drawing) is from going out of encapsulating mould 20 bottoms (bottom of the groove 21 of promptly casting) extend into casting groove 21 nib 22 in, integrated circuit (IC) chip encapsulation is ejected this Chip Packaging this moment structure as shown in Figure 4.
Encapsulating mould 20 in the present embodiment is same as the previously described embodiments, substrate 1 (not drawing) similar to the aforementioned embodiment.Chip is 1.2 * 1.0mm
2Decoding chip simultaneously brushes red glue with it, sticks on substrate and places in the chip center district 10, puts it into baking in the heating furnace of nitrogen environment again, and heating and temperature control is at 120 ℃, 20 minutes time.
Take out from stove the baking back, and bonding integrated circuit (IC) chip 3 and substrate 1 promptly use spun gold (bonding line a 2) end to connect pad on the decoding chip again, and an end connects the golden finger 5 on the substrate, sees also Fig. 4, Fig. 5.All pads on the chip connect one by one with all golden fingers 5 on the substrate are all corresponding, carry out the casting of capping layer 9 after having connected.At this moment, the above-mentioned substrate that connects chip is put into the casting groove 21 of encapsulating mould 20, again the epoxy resin of fusion is poured in the groove 21, after being full of this groove, the epoxy tree scrapes plane surface, and the heating furnace baking of putting into nitrogen environment, 120 ℃ of heating-up temperatures, 30 minutes time, cooling to normal temperature with the furnace takes out, the push rod of depanning (not drawing) is from going out of encapsulating mould 20 bottoms (bottom of the groove 21 of promptly casting) extend into casting groove 21 nib 22 in, the integrated circuit (IC) chip encapsulation is ejected, and its Chip Packaging is structure as shown in Figure 4.
Encapsulating mould 20 in the present embodiment is substantially the same manner as Example 1, and just casting groove 21 wherein is more a little than the length among the embodiment 1.The design of substrate designs by the scheme of above-mentioned Code And Decode two chip blocks of tiling, and the anti-interconnection line of the positive interconnection line in its front and golden finger and reverse side and pad and positive and negative interconnection line and the via hole that metallizes etc. are connected and embodiment 1 identical (its positive and negative structure chart is not drawn).
The same with above-mentioned embodiment, the substrate of making is connected with red glue with chip, and it to put into heating furnace baking of nitrogen environment, heating and temperature control is at 130 ℃, 25 minutes time.
Substrate and chip after the baking take out from stove, again with both bondings.Connect pad on the chip with Herba Anoectochili roxburghii (bonding line a 2) end, an end connects the golden finger 5 on the substrate, sees also Fig. 5, Fig. 6.All golden fingers 5 of all pads on the chip 3 and substrate front side connect one to one, and just carry out the casting of capping layer 9 after having connected.At this moment, the above-mentioned substrate that connects chip is put into the casting groove 21 of encapsulating mould 20, again the epoxy resin of fusion is poured in this groove, after being full of this groove, the epoxy tree scrapes plane surface, and the heating furnace baking of putting into nitrogen environment, 130 ℃ of heating-up temperatures, 35 minutes time, cooling to normal temperature with the furnace takes out, the push rod of depanning (not drawing) is from going out of encapsulating mould 20 bottoms (bottom of the groove 21 of promptly casting) extend into casting groove 21 nib 22 in, integrated circuit (IC) chip encapsulation is ejected this Chip Packaging this moment structure as shown in Figure 6.
The foregoing description is only for more abundant explanation technical scheme of the present invention, but the present invention is not limited to above-mentioned cited embodiment.
Claims (5)
1. a leadless integrated circuit chip packaging method is characterized in that comprising the steps:
1.1 designing and producing of encapsulating mould, this mould contains the casting groove, and bottom land is provided with out nib;
1.2 designing and producing of substrate, this substrate comprise the positive positive interconnection line and the anti-interconnection line and the connected pad of connected golden finger and reverse side, connect the metallization via hole of positive and negative interconnection line in addition;
1.3 integrated circuit (IC) chip and substrate is bonding, and integrated circuit (IC) chip is pasted substrate front side, and puts into the heating furnace baking of nitrogen environment, 110～130 ℃ of heating-up temperatures, 15 to 25 minutes time;
1.4 bonding integrated circuit (IC) chip and substrate are with pad on the described chip of bonding line bonding and the golden finger on the substrate;
1.5 the casting capping layer is put into described mould with the substrate that is connected with chip, pours the resin of fusion into mould again, scrape plane surface after being full of, and put into the heating furnace baking of nitrogen environment, 110～130 ℃ of heating-up temperatures, 25～35 minutes time, cool to normal temperature with the furnace and take out.
2. a kind of leadless integrated circuit chip packaging method according to claim 1 is characterized in that described encapsulating mould is a disc structure, and described casting groove places this disc centre position, is provided with out nib at the center of the bottom land of this groove.
3. a kind of leadless integrated circuit chip packaging method according to claim 2 is characterized in that described encapsulating mould makes with polytetrafluoroethylmaterial material.
4. a kind of leadless integrated circuit chip packaging method according to claim 3 is characterized in that integrated circuit (IC) chip puts into the heating furnace baking after the substrate front side with red gluing being attached to.
5. a kind of leadless integrated circuit chip packaging method according to claim 1 is characterized in that described resin is an epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101613978A CN100433322C (en) | 2006-12-25 | 2006-12-25 | The encapsulation of integrated circuit chip without lead |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101613978A CN100433322C (en) | 2006-12-25 | 2006-12-25 | The encapsulation of integrated circuit chip without lead |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1996583A CN1996583A (en) | 2007-07-11 |
| CN100433322C true CN100433322C (en) | 2008-11-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006101613978A Expired - Fee Related CN100433322C (en) | 2006-12-25 | 2006-12-25 | The encapsulation of integrated circuit chip without lead |
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Citations (12)
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| US6069407A (en) * | 1998-11-18 | 2000-05-30 | Vlsi Technology, Inc. | BGA package using PCB and tape in a die-up configuration |
| CN2401992Y (en) * | 1999-10-19 | 2000-10-18 | 胜开科技股份有限公司 | Plastic package structure for light sensed chip package |
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| US20020149102A1 (en) * | 2000-11-15 | 2002-10-17 | Conexant Systems, Inc. | Structure and method for fabrication of a leadless multi-die carrier |
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| CN1499614A (en) * | 2002-11-07 | 2004-05-26 | 矽统科技股份有限公司 | Base plate for encapsulating semiconductor and semiconductor device |
| US6882057B2 (en) * | 2003-06-25 | 2005-04-19 | Via Technologies, Inc. | Quad flat no-lead chip carrier |
| US6960824B1 (en) * | 2000-11-15 | 2005-11-01 | Skyworks Solutions, Inc. | Structure and method for fabrication of a leadless chip carrier |
| CN201000885Y (en) * | 2006-12-25 | 2008-01-02 | 南通大学 | Lead wire-free integrated circuit chip encapsulation |
-
2006
- 2006-12-25 CN CNB2006101613978A patent/CN100433322C/en not_active Expired - Fee Related
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640048A (en) * | 1994-07-11 | 1997-06-17 | Sun Microsystems, Inc. | Ball grid array package for a integrated circuit |
| CN1152797A (en) * | 1995-11-08 | 1997-06-25 | 富士通株式会社 | Elements with resin shell capsulation and making method |
| US6069407A (en) * | 1998-11-18 | 2000-05-30 | Vlsi Technology, Inc. | BGA package using PCB and tape in a die-up configuration |
| US6191477B1 (en) * | 1999-02-17 | 2001-02-20 | Conexant Systems, Inc. | Leadless chip carrier design and structure |
| US6921972B1 (en) * | 1999-02-17 | 2005-07-26 | Skyworks Solutions, Inc. | Leadless chip carrier design and structure |
| CN2401992Y (en) * | 1999-10-19 | 2000-10-18 | 胜开科技股份有限公司 | Plastic package structure for light sensed chip package |
| US6611055B1 (en) * | 2000-11-15 | 2003-08-26 | Skyworks Solutions, Inc. | Leadless flip chip carrier design and structure |
| US20020149102A1 (en) * | 2000-11-15 | 2002-10-17 | Conexant Systems, Inc. | Structure and method for fabrication of a leadless multi-die carrier |
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| CN1499614A (en) * | 2002-11-07 | 2004-05-26 | 矽统科技股份有限公司 | Base plate for encapsulating semiconductor and semiconductor device |
| US6882057B2 (en) * | 2003-06-25 | 2005-04-19 | Via Technologies, Inc. | Quad flat no-lead chip carrier |
| CN201000885Y (en) * | 2006-12-25 | 2008-01-02 | 南通大学 | Lead wire-free integrated circuit chip encapsulation |
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| Publication number | Publication date |
|---|---|
| CN1996583A (en) | 2007-07-11 |
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Assignee: Zhuhai Huajing Microelectronics Co., Ltd. Assignor: Nantong University Contract record no.: 2010440000673 Denomination of invention: The encapsulation of integrated circuit chip without lead Granted publication date: 20081112 License type: Exclusive License Open date: 20070711 Record date: 20100608 |
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