CN100435300C - Chip packing and IC module assembling mode - Google Patents
Chip packing and IC module assembling mode Download PDFInfo
- Publication number
- CN100435300C CN100435300C CNB2005101056359A CN200510105635A CN100435300C CN 100435300 C CN100435300 C CN 100435300C CN B2005101056359 A CNB2005101056359 A CN B2005101056359A CN 200510105635 A CN200510105635 A CN 200510105635A CN 100435300 C CN100435300 C CN 100435300C
- Authority
- CN
- China
- Prior art keywords
- wafer
- mode
- grinding
- metal
- glue material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
A method uses for wafer encapsulation and IC module assembly. The forming of metal raised block on wafer is to print electric metal grease on I/O joint of wafer in type of armor plate print and dry to metal raised block. The coated macromolecule glue is to coat encapsulation glue on the wafer surface of metal raised block in type of print and dry. Rubbing the solidified glue of the wafer surface until showing up the surface of metal raised block or reaching to the wanted thickness of glue and cut the CMOS chip into grain. The surface of grain SMT sticks to antenna or base plank. By this method, it produces a lot of CMOS chips with high quality in low cost.
Description
Technical field
The present invention relates to a kind ofly become circuit (IC:IntegratedCircuit) (for example: REID (RFID:Radio Frequency Identification), light-emitting diode (LED:Light-emitting diode), diode DIODE etc.) to form the encapsulation pattern of wafer scale with mode of printing at granule, low pin manifold, finish the component products that becomes surface mount (SMT) after grinding and cutting, be assembled on antenna or the substrate in the SMT mode again.
Background technology
The IC of granule and low pin number is for example: RFID, LED, field effect transistor MOSFET or DIODE etc., because IC is small-sized, make that the amounts of particles on wafer is a lot, so conventional package with particle unit, the efficient of production capacity quantity is not high, because want one one encapsulation, if 30K crystal grain is arranged with a wafer, the particle that encapsulates on the wafer will expend very many time, wafer-class encapsulation is to finish encapsulation on wafer, after the wafer cutting is exactly complete encapsulation IC, for granule IC, the production efficiency of wafer-class encapsulation is very high, because be to be production unit with the chip, general wafer-class encapsulation is the device fabrication with nearly semiconductor technology, for example: metal sputtering, photoetching process, the macromolecule coating, tin shot technology etc., though with the chip is unit, but the cost of manufacture of unit chip also is very high, because process equipment needs the cost of investment of great number.
At RFID or LED is among the typical granule IC, its encapsulation and packaging efficiency are the key factors of decision product cost, if with existing conventional package and assembling flow path, as depicted in figs. 1 and 2, all be individual particle encapsulation and assembling mode, Fig. 1 will form the IC module in solid brilliant bonding wire mode after the cutting of IC wafer grinding again, again the IC module is assembled on antenna or the substrate and forms finished product, its volume production apparatus expensive, production capacity efficient is very low, price is relatively very high, and can't make the thin type product.That is to say that the mode described in Fig. 1 is to finish product through each following step:
Prepare a wafer (seeing 1):
Brilliant Gu (seeing 2);
Grinding wafers (seeing 3);
Routing (seeing 4); And
Encapsulation (seeing 5).
If do the thin type product, must adopt as shown in Figure 2 flow process-flip-chip package mode as IC Card, RFID, the mode of this flow process is to form metal coupling on wafer, in the flip-chip mode IC is assembled into module or directly is engaged to antenna or the substrate metal projection again after the grinding and cutting, near wafer-class encapsulation.The habitual mode of this kind is to finish the product that desire forms through following step:
Prepare a wafer (seeing 1 ');
Gu crystalline substance (sees 2 ';
Grinding wafers (seeing 3 ');
Coating one deck silverskin (seeing 4 '); And
Flip-chip (seeing 5 ').
But this kind mode can only be used as the flip-chip completed knocked down products can not be used as general paster (SMD) product; Problem that flip-chip process is run into and flow process one same production efficiency are low, and the equipment price costliness makes production unit cost very high, can't popularize in a large number.
Summary of the invention
For solving the above problems, the invention provides a kind of wafer-class encapsulation mode of novelty.
The object of the invention is the IC characteristic with this class, adopts very cheap wafer-class encapsulation mode, promptly forms available SMD product after finishing grinding and cutting again, with general SMD equipment can the mass efficient rate being assembled on antenna or the substrate.
By encapsulation of the present invention and IC assembling, the present invention can utilize simple mode and cheap cost to finish the product that desire forms.
The objective of the invention is directly to form required chip by the wafer-class encapsulation pattern.
For reaching above-mentioned purpose, the invention provides a kind of wafer package mode, comprising:
Form metal coupling on the wafer: the mode with the steel plate printing, a conductive metal paste is printed on the I/O contact (pad) of wafer, dry more afterwards baking forms metal coupling;
Macromolecule glue material coating: the packaging adhesive material of wafer scale is coated the wafer surface of metal coupling with mode of printing, and dry again baking forms;
The surface grinding of glue material: the grinding wafers surface has covered the glue material of curing, and is exposed or reach required glue material thickness up to metal lug surface;
The end points printing: end points is element particle and antenna or substrate junction chalaza;
Brilliant back-grinding and cutting: brilliant back-grinding to required thickness, is cut into wafer the graininess assembly again and finishes packaging technology;
The formed graininess assembly surface in cutting back is adhered to antenna or substrate.
Described conductive metal paste is by copper cream, and silver paste is chosen any one kind of them in the tin cream.
Described end points is silver paste or tin cream.
The mode with low price that can be a large amount of by the present invention produces high-quality chip, and cost-effective expenditure that can be a large amount of also can be taken the high-quality of product into account simultaneously.
Description of drawings
Fig. 1 is the flow chart of first kind of existing packaged type;
Fig. 2 is the flow chart of first kind of existing packaged type;
Fig. 3 is a flow chart of the present invention.
The primary clustering symbol description:
1 prepares a wafer 2 solid crystalline substances
3 grinding wafers, 4 routings
A wafer is prepared in 5 encapsulation 1 '
2 ' solid brilliant 3 ' grinding wafers
4 ' coating one deck silverskin, 5 ' flip-chip
10 ' wafer, 11 metal couplings
The 30 glue material surface grindings of 20 glue materials
40 end points print 50 brilliant back-grinding and cuttings
60 particle SMT surface mount are to antenna or substrate
Embodiment
The present invention be directed to the low pin of granule and count IC, RFID for example, LED, Diode etc. form the encapsulation pattern of wafer scale with mode of printing, but finish grind and cutting after promptly be the subassembly product of SMT, be assembled on antenna or the substrate in the SMT mode again, its flow process as shown in Figure 3:
In the mode of steel plate printing, with copper cream, silver paste, or paste solder printing is on the I/O of wafer 10 contact (pad), and dry more afterwards baking forms metal coupling 11.
The coating of macromolecule glue material;
The packaging adhesive material 20 of wafer scale is coated the wafer surface of metal coupling 11 with mode of printing, and dry again baking forms.
Glue material surface grinding 30;
End points is assembly particle and antenna or substrate junction chalaza, normally silver paste or tin cream.
Brilliant back-grinding and cut 50;
With the thickness of brilliant back-grinding, again wafer is cut into the graininess assembly and finish packaging technology to institute palpus.
The formed graininess assembly surface in cutting back is adhered to antenna or substrate 60.
The foregoing description only is used to illustrate the present invention, but not is used to limit the present invention.
Claims (3)
1. a wafer package mode is characterized in that, comprising:
Form metal coupling on the wafer: the mode with the steel plate printing, a conductive metal paste is printed on the I/O contact of wafer, dry more afterwards baking forms metal coupling;
Macromolecule glue material coating: the packaging adhesive material of wafer scale is coated the wafer surface of metal coupling with mode of printing, and dry again baking forms;
The surface grinding of glue material: the grinding wafers surface has covered the glue material of curing, and is exposed or reach required glue material thickness up to metal lug surface;
The end points printing: end points is element particle and antenna or substrate junction chalaza;
Brilliant back-grinding and cutting: brilliant back-grinding to required thickness, is cut into wafer the graininess assembly again and finishes packaging technology;
The formed graininess assembly surface in cutting back is adhered to antenna or substrate.
2. wafer package mode as claimed in claim 1 is characterized in that, described conductive metal paste is by copper cream, and silver paste is chosen any one kind of them in the tin cream.
3. wafer package mode according to claim 1 is characterized in that, described end points is silver paste or tin cream.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101056359A CN100435300C (en) | 2005-09-28 | 2005-09-28 | Chip packing and IC module assembling mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101056359A CN100435300C (en) | 2005-09-28 | 2005-09-28 | Chip packing and IC module assembling mode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1941303A CN1941303A (en) | 2007-04-04 |
| CN100435300C true CN100435300C (en) | 2008-11-19 |
Family
ID=37959313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101056359A Active CN100435300C (en) | 2005-09-28 | 2005-09-28 | Chip packing and IC module assembling mode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100435300C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103441082B (en) * | 2013-08-12 | 2016-06-08 | 王功杰 | A kind of brand-new technique of integrated circuit packaging |
| CN104091865A (en) * | 2014-07-25 | 2014-10-08 | 胡溢文 | Method for preparing horizontal flip-chip |
| CN104091866B (en) * | 2014-07-25 | 2017-02-15 | 胡溢文 | Method for preparing LED lamp filament of horizontal flip-chip |
| CN113451158A (en) * | 2021-04-25 | 2021-09-28 | 福建天电光电有限公司 | Flip chip package structure and manufacturing process thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060373A (en) * | 1998-07-10 | 2000-05-09 | Citizen Watch Co., Ltd. | Method for manufacturing a flip chip semiconductor device |
| CN1307362A (en) * | 2000-01-25 | 2001-08-08 | 陈怡铭 | Semiconductor chip package and its packaging method |
| US6420244B2 (en) * | 2000-02-21 | 2002-07-16 | Advanced Semiconductor Engineering, Inc. | Method of making wafer level chip scale package |
| US6476501B1 (en) * | 1999-04-09 | 2002-11-05 | Oki Electric Industry Co., Ltd. | Semiconductor device, manufacturing method for semiconductor device and mounting method for the same |
-
2005
- 2005-09-28 CN CNB2005101056359A patent/CN100435300C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060373A (en) * | 1998-07-10 | 2000-05-09 | Citizen Watch Co., Ltd. | Method for manufacturing a flip chip semiconductor device |
| US6476501B1 (en) * | 1999-04-09 | 2002-11-05 | Oki Electric Industry Co., Ltd. | Semiconductor device, manufacturing method for semiconductor device and mounting method for the same |
| CN1307362A (en) * | 2000-01-25 | 2001-08-08 | 陈怡铭 | Semiconductor chip package and its packaging method |
| US6420244B2 (en) * | 2000-02-21 | 2002-07-16 | Advanced Semiconductor Engineering, Inc. | Method of making wafer level chip scale package |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1941303A (en) | 2007-04-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7273768B2 (en) | Wafer-level package and IC module assembly method for the wafer-level package | |
| US8030769B2 (en) | Grooving bumped wafer pre-underfill system | |
| CN102148179B (en) | Using method of bonding film | |
| US9997485B2 (en) | Bonding structure and method | |
| CN102222657B (en) | Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof | |
| US7838391B2 (en) | Ultra thin bumped wafer with under-film | |
| US20150221624A1 (en) | Semiconductor device including independent film layer for embedding and/or spacing semiconductor die | |
| WO2008141273A1 (en) | Systems and methods for post-circuitization assembly | |
| CN100435300C (en) | Chip packing and IC module assembling mode | |
| US7678610B2 (en) | Semiconductor chip package and method of manufacture | |
| CN101160596B (en) | Method of producing electronic apparatus | |
| CN101562138B (en) | Method for producing semiconductor packaging part | |
| US8809984B2 (en) | Substrate connection type module structure | |
| US20060057763A1 (en) | Method of forming a surface mountable IC and its assembly | |
| CN116936377A (en) | Board-level fan-out packaging method | |
| CN104701196A (en) | Method for manufacturing semiconductor package | |
| CN108431933A (en) | Electronic component and its manufacturing method and electronic part making | |
| TWI313500B (en) | ||
| US20140035165A1 (en) | Pierced Substrate on Chip Module Structure | |
| CN100477140C (en) | Packing component of semiconductor and preparing method thereof | |
| CN201425939Y (en) | Flip chip IC package structure | |
| US9780059B2 (en) | Bonding structure and method | |
| KR100499328B1 (en) | Flip Chip Packaging Method using Dam | |
| TW201117437A (en) | Method for packaging light-emitting diode | |
| CN100378977C (en) | Semiconductor device without chip carrier and its preparing process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |