CN100437831C - Shifting register reducing bias voltage effect - Google Patents
Shifting register reducing bias voltage effect Download PDFInfo
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- CN100437831C CN100437831C CNB2006101543871A CN200610154387A CN100437831C CN 100437831 C CN100437831 C CN 100437831C CN B2006101543871 A CNB2006101543871 A CN B2006101543871A CN 200610154387 A CN200610154387 A CN 200610154387A CN 100437831 C CN100437831 C CN 100437831C
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Abstract
The related shift register comprises multilevel registers, every of which includes an output circuit to output a first drive signal, a first switch circuit to draw the circuit to a low potential before the drive signal, and a second switch circuit for signal receiving. Wherein, the first circuit applies potential of the input signal to hold charge in its parasitic capacitor and keep opening before the drive signal.
Description
Technical field
The present invention relates to a kind of shift register, refer in particular to a kind of inner electric charge of retaining of transistor that utilizes and reduce bias effect (Stress) and the shift register that reduces AC signal coupling effect (AC coupling).
Background technology
Function advanced person's display gradually becomes the valuable feature of consumption electronic product now, and wherein LCD has become the display that various electronic equipments such as mobile phone, PDA(Personal Digital Assistant), digital camera, computer screen or the widespread use of laptop screen institute have the high-resolution color screen gradually.
Shift register (shift register) is the important structure in the driving circuit of display panels, it is in order to driving display circuits at different levels in the display panels, so the circuit design of shift register has decisive influence to the usefulness of display panels.
See also Fig. 1, Fig. 1 is the circuit structure diagram of single-stage shift register 11 in the LCD of prior art.This shift register 11 comprises a plurality of transistors 16,17,18,19,20,21, to control output signal OUTPUT1 according to clock signal C 1, C3 and input signal INPUT.See also Fig. 2, Fig. 2 is the signal timing diagram of each node in the shift register 11.When clock signal C3 was noble potential, transistor 20 was opened, and this moment, node P2 presented V
DDCurrent potential (noble potential), impel transistor 17 and 19 to be opened simultaneously, and the current potential of the grid (gate) (being node P1) of transistor 16 and source electrode (source) be pulled to V
SS(electronegative potential).
Though the shift register 11 of prior art can be pulled to V with the grid of transistor 16 and the current potential of source electrode rapidly
SS, but need be provided with direct voltage source V
DD, and its transistor 18 and the 20 long-time direct voltage source V that receive
DDAlso can cause the generation of bias effect (Stress), however now in the LCD shift register design all towards direct voltage source V need not be set
DDDirection develop, to reduce manufacturing cost and to improve product usefulness.Therefore, must propose a kind of direct voltage source V to be set
DDAnd the shift register with stable performance is to overcome the defective of prior art.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of inner electric charge of retaining of transistor that utilizes to reduce bias effect and the shift register that reduces the AC signal coupling effect.
According to above-mentioned purpose of the present invention, the invention provides a kind of shift register, it comprises multi-level register.Each grade register comprises output circuit, first commutation circuit and second commutation circuit.This output circuit comprises the first transistor in order to receive first clock signal and to export first drive signal, transistor seconds when not exporting this first drive signal at this first transistor, and this first transistor is pulled to electronegative potential.This first commutation circuit comprises the 3rd transistor and electrically connects in order to receive this transistor seconds of second drive signal, the 4th transistor AND gate, when not exporting this first drive signal at this first transistor, this first transistor is pulled to electronegative potential.This second commutation circuit comprises the 5th transistor in order to receiving inputted signal.Wherein the 3rd transistor by its endophyte electric capacity and the current potential that utilizes input signal to retain electric charge in this stray capacitance, make this transistor seconds and the 4th transistorized grid potential remain on noble potential for a long time, this transistor seconds and the 4th transistor are in the state that is opened when this first transistor is not exported this first drive signal.
Wherein this input signal can adopt different clock signals or drive signal, and direct voltage source need not additionally be set.
According to above-mentioned purpose of the present invention, the present invention also provides a kind of shift register, and it comprises: output circuit (36), and it comprises: the first transistor (T2), in order to receive first clock signal and to export first drive signal; Transistor seconds (T6) when not exporting this first drive signal at this first transistor, is pulled to electronegative potential with the output end voltage of this first transistor; First commutation circuit (52), it comprises: the 3rd transistor (T1), in order to receive second drive signal; The 4th transistor (T5), itself and this transistor seconds electrically connects, and when not exporting this first drive signal at this first transistor, the control end voltage of this first transistor is pulled to electronegative potential; The 5th transistor (T8) is in order to receive first input signal to control this transistor seconds and the 4th transistorized on off state; Second commutation circuit (34), it comprises: the 6th transistor (T3), in order to receive second input signal; Wherein this second and the 4th transistor by its endophyte electric capacity and the current potential that utilizes this second input signal to retain electric charge in this stray capacitance, make this transistor seconds and the 4th transistorized grid potential remain on noble potential for a long time, this transistor seconds and the 4th transistor are in the state that is opened when this first transistor is not exported this first drive signal.
According to above-mentioned purpose of the present invention, the present invention also provides a kind of control circuit to be applied in the LCD, it comprises: shift register, it has multi-level register, form with series connection connects, and the output signal of this grade register is the drive signal as next stage, and each grade register comprises: output circuit (36), it comprises: the first transistor (T2), in order to receive first clock signal and to export first drive signal; Transistor seconds (T6) when not exporting this first drive signal at this first transistor, is pulled to electronegative potential with the output end voltage of this first transistor; First commutation circuit (32), it comprises: the 3rd transistor (T1), in order to receive second drive signal; The 4th transistor (T5), itself and this transistor seconds electrically connects, and when not exporting this first drive signal at this first transistor, the control end voltage of this first transistor is pulled to electronegative potential; Second commutation circuit (34), it comprises: the 5th transistor (T3), in order to receiving inputted signal; Wherein this second and the 4th transistor by its endophyte electric capacity and the current potential that utilizes this input signal to retain electric charge in this stray capacitance, make this transistor seconds and the 4th transistorized grid potential remain on noble potential for a long time, this transistor seconds and the 4th transistor are in the state that is opened when this first transistor is not exported this first drive signal.
Shift register of the present invention utilizes the retention electric charge of transistor endophyte electric capacity to make special transistor remain on open mode for a long time, not only can reduce the bias effect of shift register internal transistor, also can improve the AC signal coupling effect of the drive signal that shift register exports.And shift register of the present invention need not be provided with extra direct voltage source, can reduce manufacturing cost and improve product usefulness.
Description of drawings
Fig. 1 is the circuit structure diagram of the single-stage shift register of prior art.
Fig. 2 is the signal timing diagram of this each node of shift register among Fig. 1.
Fig. 3 is the functional block diagram of a LCD.
Fig. 4 is the circuit structure diagram of single-stage shift register of the present invention.
Fig. 5 is the signal timing diagram of this each node of shift register among Fig. 4.
Fig. 6 is the circuit structure diagram of another embodiment of single-stage shift register of the present invention.
Fig. 7 is the signal timing diagram of each node of this shift register among Fig. 6.
Fig. 8 is the circuit structure diagram of another embodiment of shift register of Fig. 6.
Fig. 9 is the signal timing diagram of each node of this shift register among Fig. 8.
Figure 10 is the shift register circuit structure diagram of an embodiment again of Fig. 6.
Figure 11 is the signal timing diagram of each node of this shift register among Figure 10.
Figure 12 is the circuit structure diagram of the another embodiment of shift register of Fig. 6.
Figure 13 is the signal timing diagram of each node of this shift register among Figure 12.
The clock signal figure of each node that Figure 14 a and 14b compare for the present invention and prior art.
[main element label declaration]
100 LCD, 112 display panels
114 gate drivers, 116 source electrode drivers
120 pixel cells, 122 transistors
30,50 shift registers, 32,52 first commutation circuits
34 second commutation circuits, 36 output circuits
T401-T422 transistor CK first clock signal
XCK second clock signal N+1, N, N-1 drive signal
P, Q, R node C
dEquivalent capacity
Embodiment
See also Fig. 3, Fig. 3 is the functional block diagram of LCD 100.LCD 100 comprises display panels 112, gate drivers (gate driver) 114 and source electrode driver (sourcedriver) 116.Display panels 112 comprises a plurality of pixels, and each pixel comprises three and represents the trichromatic pixel cell of RGB (RGB) 120 to constitute respectively.Gate drivers 114 output scanning signals make the transistor 122 of each row open in regular turn, and the pixel cell 120 of data-signal to a permutation that 116 outputs of source electrode driver simultaneously are corresponding makes it be charged to required separately voltage, to show different GTGs.After same row charging finishes, the sweep signal that gate drivers 114 just will be listed as is closed, then gate drivers 114 again the output scanning signal transistor 122 of next column is opened, the pixel cell 120 by 116 pairs of next columns of source electrode driver discharges and recharges again.So go down in regular turn, all charge up to all pixel cells 120 of display panels 112 and finish, accent is since the first row charging again.In the design of present display panels, be shift register (shift register) in the control circuit equivalence of gate drivers 114, its purpose promptly every a fixed intervals output scanning signal to display panels 112.
See also Fig. 4, Fig. 4 is the circuit structure diagram of single-stage shift register 30 of the present invention.Shift register 30 is to be applied in the LCD to realize the control circuit of above-mentioned gate drivers.Shift register 30 comprises first commutation circuit 32, second commutation circuit 34 and output circuit 36.First commutation circuit 32 comprises transistor T 1 and T5, and second commutation circuit 34 comprises transistor T 3 and T4, and output circuit 36 comprises transistor T 2, T6 and T7.The grid of transistor T 1 and drain electrode (drain) receive the drive signal N-1 of N-1 level, and the source electrode of transistor T 1 is connected to node Q.The grid of transistor T 5 is connected to node P, and the drain electrode of transistor T 5 is connected to node Q, and the source electrode of transistor T 5 is connected to electronegative potential V
SSThe grid of transistor T 3 and drain electrode receiving inputted signal INPUT, input signal INPUT can be the drive signal N+1 of the first clock signal C K, second clock signal XCK or N+1 level, and the source electrode of transistor T 3 is connected to node P.The grid of transistor T 4 receives the drive signal N-1 of N-1 level, and the drain electrode of transistor T 4 is connected to node P, and the source electrode of transistor T 4 is connected to electronegative potential V
SSThe grid of transistor T 2 is connected to node Q, and the drain electrode of transistor T 2 receives the first clock signal C K, and the source electrode of transistor T 2 is in order to export the drive signal N of N level.The grid of transistor T 6 is connected to node P, and the drain electrode of transistor T 6 is connected to the source electrode of transistor T 2, and the source electrode of transistor T 6 is connected to electronegative potential V
SSThe grid of transistor T 7 is connected to the source electrode of transistor T 2, and the drain electrode of transistor T 7 is connected to node P, and the source electrode of transistor T 7 is connected to electronegative potential V
SS
See also Fig. 5, Fig. 5 is the signal timing diagram of each node of shift register 30.Because originally promptly having stray capacitance among transistor T 5 and the T6 (is C
Gs), this means at node P and electronegative potential V
SSBetween can be considered and connecting an equivalent capacity C
dSo after shift register 30 comes into operation (i.e. energising back), node P can constantly retain electric charge in this equivalence capacitor C
dIn, so node P can remain under the state of noble potential always.Because node P remains on noble potential always, transistor T 5 just can remain on the state that is opened with T6 always, makes the grid of transistor T 2 and source potential be pulled to electronegative potential V
SSTherefore, the input signal INPUT that the grid of transistor T 3 and drain electrode are received can be the drive signal N+1 of the first clock signal C K, second clock signal XCK or N+1 level, all can make node P remain on noble potential always.Yet when input signal INPUT adopts the first clock signal C K or drive signal N+1, and the drive signal N of N level is when being required to be noble potential, for the source electrode that keeps transistor T 2 is the state of noble potential, so need utilize transistor T 7 that node P is pulled to electronegative potential V
SS, also be about to transistor T 5 and close with T6 so that the source electrode of transistor T 2 keeps the state of noble potential.Otherwise, when input signal INPUT adopts second clock signal XCK, then utilize transistor T 4 that node P is pulled to electronegative potential V
SS
See also Fig. 6, Fig. 6 is the circuit structure diagram of another embodiment of single-stage shift register of the present invention.The structural similarity of the structure of shift register 50 and aforementioned shift register 30, difference are that its first commutation circuit 52 also includes transistor T 8 and T9.In shift register 50, the grid of transistor T 8 is connected to node P, and the drain electrode of transistor T 8 receives second clock signal XCK, and the source electrode of transistor T 8 is connected to node R.The grid of transistor T 9 receives the drive signal N-1 of N-1 level, and the drain electrode of transistor T 9 is connected to node R, and the source electrode of transistor T 9 is connected to electronegative potential V
SSThe grid of transistor T 5 and T6 then changes into and is connected to node R.Simultaneously, the grid of transistor T 3 and the signal that received of drain electrode change the drive signal N of N level into.
See also Fig. 7, Fig. 7 is the signal timing diagram of each node of shift register 50 among Fig. 6.The equivalent capacity C of this moment
dBe existing stray capacitance in the transistor T 8.Because node P can pass through equivalent capacity C
dThe electric charge of being retained and remain on the state of noble potential makes transistor T 8 remain on the state of opening, and node R just can be synchronous with second clock signal XCK, with the on off state of oxide-semiconductor control transistors T5 and T6, and the grid of synchro control transistor T 2 and source potential.Yet, when drive signal N-1 is noble potential, utilize transistor T 4 and T9 to equivalent capacitor C
dDischarge, transistor T 8 is closed.
See also Fig. 8, Fig. 8 is the circuit structure diagram of single-stage shift register 50 another embodiment.The difference of this embodiment and Fig. 6 is that the drain electrode of transistor T 8 changes the reception first clock signal C K into.See also Fig. 9, Fig. 9 is the signal timing diagram of each node of shift register 50 among Fig. 8.The equivalent capacity C of this moment
dBe existing stray capacitance in the transistor T 8.Because node P can pass through equivalent capacity C
dThe electric charge of being retained and remain on the state of noble potential makes transistor T 8 remain on the state of opening, and node R just can be synchronous with the first clock signal C K, with the on off state of oxide-semiconductor control transistors T5 and T6, and the grid of synchro control transistor T 2 and source potential.Yet, when drive signal N-1 is noble potential, utilize transistor T 4 and T9 to equivalent capacitor C
dDischarge, transistor T 8 is closed.
See also Figure 10, Figure 10 is single-stage shift register 50 circuit structure diagram of an embodiment again.The difference of this embodiment and Fig. 7 is that the drain electrode of transistor T 8 changes into and receives second clock signal XCK, and the signal that received of the grid of transistor T 3 and drain electrode changes the drive signal N+1 of N+1 level into.See also Figure 11, Figure 11 is the signal timing diagram of each node of shift register 50 among Figure 10.Because node P can pass through equivalent capacity C
dThe electric charge of being retained and remain on the state of noble potential makes transistor T 8 remain on the state of opening, and node R just can be synchronous with second clock signal XCK, with the on off state of oxide-semiconductor control transistors T5 and T6, and the grid of synchro control transistor T 2 and source potential.Yet, when drive signal N-1 is noble potential, utilize transistor T 4 and T9 to equivalent capacitor C
dDischarge, transistor T 8 is closed.
See also Figure 12, Figure 12 is the circuit structure diagram of single-stage shift register 50 another embodiment.The difference of this embodiment and Figure 10 is that the drain electrode of transistor T 8 changes the reception first clock signal XCK into.See also Figure 13, Figure 13 is the signal timing diagram of each node of shift register 50 among Figure 12.Because node P can pass through equivalent capacity C
dThe electric charge of being retained and remain on the state of noble potential makes transistor T 8 remain on the state of opening, and node R just can be synchronous with the first clock signal C K, with the on off state of oxide-semiconductor control transistors T5 and T6, and the grid of synchro control transistor T 2 and source potential.Yet, when drive signal N-1 is noble potential, utilize transistor T 4 and T9 to equivalent capacitor C
dDischarge, transistor T 8 is closed.
Utilize existing stray capacitance in the transistor to reach the purpose of retaining electric charge though it should be noted that the present invention, yet can also reach identical effect by extra electric capacity, the demand of its visual practical application is selected the embodiment of this electric capacity.
See also Figure 14 a and Figure 14 b, Figure 14 a is the clock signal figure of each node of prior art, and Figure 14 b then is the clock signal figure of each node of the present invention.Comparison diagram 14a and Figure 14 b can obviously find: use circuit structure of the present invention, the AC signal coupling effect of the N level drive signal N that its shift register is exported is obviously improved, and node P can remain on the state of noble potential by the retention electric charge of electric capacity.
Compared to prior art, shift register of the present invention utilizes the inner retention of transistor electric charge envoy to put the state that P remains on noble potential, not only can reduce the bias effect of internal transistor, also can improve the AC signal coupling effect of the N level drive signal N that shift register exports.And shift register of the present invention need not be provided with extra direct voltage source V
DD, can reduce manufacturing cost and improve product usefulness.
The above person only is a better embodiment of the present invention, and those skilled in the art help the equivalence of doing according to spirit of the present invention and modify or variation, all are covered by in the appended claim scope.
Claims (10)
1. shift register, it comprises:
Output circuit (36), it comprises:
The first transistor (T2) is in order to receive first clock signal and to export first drive signal;
Transistor seconds (T6) when not exporting this first drive signal at this first transistor, is pulled to electronegative potential with the output end voltage of this first transistor;
First commutation circuit (32), it comprises:
The 3rd transistor (T1) is in order to receive second drive signal;
The 4th transistor (T5), itself and this transistor seconds electrically connects, and when not exporting this first drive signal at this first transistor, the control end voltage of this first transistor is pulled to electronegative potential;
Second commutation circuit (34), it comprises:
The 5th transistor (T3) is in order to receiving inputted signal;
Wherein this second and the 4th transistor by its endophyte electric capacity and the current potential that utilizes this input signal to retain electric charge in this stray capacitance, make this transistor seconds and the 4th transistorized grid potential remain on noble potential for a long time, this transistor seconds and the 4th transistor are in the state that is opened when this first transistor is not exported this first drive signal.
2. shift register according to claim 1, wherein this electronegative potential is V
SSCurrent potential.
3. shift register according to claim 1, wherein this output circuit also comprises the 6th transistor (T7), when exporting this first drive signal at this first transistor, this transistor seconds and the 4th transistor is closed.
4. shift register according to claim 1, it is to be applied to LCD.
5. shift register, it comprises:
Output circuit (36), it comprises:
The first transistor (T2) is in order to receive first clock signal and to export first drive signal;
Transistor seconds (T6) when not exporting this first drive signal at this first transistor, is pulled to electronegative potential with the output end voltage of this first transistor;
First commutation circuit (52), it comprises:
The 3rd transistor (T1) is in order to receive second drive signal;
The 4th transistor (T5), itself and this transistor seconds electrically connects, and when not exporting this first drive signal at this first transistor, the control end voltage of this first transistor is pulled to electronegative potential;
The 5th transistor (T8) is in order to receive first input signal to control this transistor seconds and the 4th transistorized on off state;
Second commutation circuit (34), it comprises:
The 6th transistor (T3) is in order to receive second input signal;
Wherein the 5th transistor by its endophyte electric capacity and the current potential that utilizes this second input signal to retain electric charge in this stray capacitance, control this transistor seconds and the 4th transistorized on off state, and the grid of this first transistor of synchro control and source potential.
6. shift register according to claim 5, wherein this second commutation circuit also comprises the 7th transistor (T4), in order to when this second drive signal is noble potential, the 5th transistor is closed.
7. shift register according to claim 5, wherein this electronegative potential is V
SSCurrent potential.
8. control circuit that is applied in the LCD, it comprises:
Shift register, it has multi-level register, and with the form connection of series connection, the output signal of each grade register is the drive signal as next stage, and each grade register comprises:
Output circuit (36), it comprises:
The first transistor (T2) is in order to receive first clock signal and to export first drive signal;
Transistor seconds (T6) when not exporting this first drive signal at this first transistor, is pulled to electronegative potential with the output end voltage of this first transistor;
First commutation circuit (32), it comprises:
The 3rd transistor (T1) is in order to receive second drive signal;
The 4th transistor (T5), itself and this transistor seconds electrically connects, and when not exporting this first drive signal at this first transistor, the control end voltage of this first transistor is pulled to electronegative potential;
Second commutation circuit (34), it comprises:
The 5th transistor (T3) is in order to receiving inputted signal;
Wherein this second and the 4th transistor by its endophyte electric capacity and the current potential that utilizes this input signal to retain electric charge in this stray capacitance, make this transistor seconds and the 4th transistorized grid potential remain on noble potential for a long time, this transistor seconds and the 4th transistor are in the state that is opened when this first transistor is not exported this first drive signal.
9. control circuit according to claim 8, wherein this electronegative potential is V
SSCurrent potential.
10. control circuit according to claim 8, wherein this output circuit also comprises the 6th transistor (T7), when exporting this first drive signal at this first transistor, this transistor seconds and the 4th transistor is closed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101543871A CN100437831C (en) | 2006-09-25 | 2006-09-25 | Shifting register reducing bias voltage effect |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101543871A CN100437831C (en) | 2006-09-25 | 2006-09-25 | Shifting register reducing bias voltage effect |
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| CN1929031A CN1929031A (en) | 2007-03-14 |
| CN100437831C true CN100437831C (en) | 2008-11-26 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101042937B (en) * | 2007-04-24 | 2010-10-13 | 友达光电股份有限公司 | Displacement register capable of reducing voltage bias effective voltage, control circuit and liquid crystal display |
| CN101339809B (en) * | 2007-07-02 | 2011-01-05 | 上海天马微电子有限公司 | Shift register and LCD using the same |
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| JP2001282169A (en) * | 2000-03-31 | 2001-10-12 | Casio Comput Co Ltd | Shift register and electronic device |
| US6373456B1 (en) * | 1998-07-13 | 2002-04-16 | Kabushiki Kaisha Advanced Display | Liquid crystal display |
| CN1366284A (en) * | 2001-01-17 | 2002-08-28 | 卡西欧计算机株式会社 | Circuit |
| CN1684362A (en) * | 2004-04-15 | 2005-10-19 | 三菱电机株式会社 | Drive circuit with offset compensation function, and liquid crystal display apparatus employing the same |
| JP2006071672A (en) * | 2004-08-31 | 2006-03-16 | Sharp Corp | Display apparatus and its driving method |
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2006
- 2006-09-25 CN CNB2006101543871A patent/CN100437831C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6373456B1 (en) * | 1998-07-13 | 2002-04-16 | Kabushiki Kaisha Advanced Display | Liquid crystal display |
| JP2001282169A (en) * | 2000-03-31 | 2001-10-12 | Casio Comput Co Ltd | Shift register and electronic device |
| CN1366284A (en) * | 2001-01-17 | 2002-08-28 | 卡西欧计算机株式会社 | Circuit |
| CN1684362A (en) * | 2004-04-15 | 2005-10-19 | 三菱电机株式会社 | Drive circuit with offset compensation function, and liquid crystal display apparatus employing the same |
| JP2006071672A (en) * | 2004-08-31 | 2006-03-16 | Sharp Corp | Display apparatus and its driving method |
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