CN100440469C - Method of making a semiconductor chip packaging structure with a metal containment wall and a solder terminal - Google Patents

Method of making a semiconductor chip packaging structure with a metal containment wall and a solder terminal Download PDF

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Publication number
CN100440469C
CN100440469C CNB2006101032946A CN200610103294A CN100440469C CN 100440469 C CN100440469 C CN 100440469C CN B2006101032946 A CNB2006101032946 A CN B2006101032946A CN 200610103294 A CN200610103294 A CN 200610103294A CN 100440469 C CN100440469 C CN 100440469C
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China
Prior art keywords
metal substrate
metallic walls
semiconductor chip
welding ends
coiling
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CNB2006101032946A
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Chinese (zh)
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CN1925123A (en
Inventor
林文强
王家忠
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Yuqiao Semiconductor Co Ltd
Bridge Semiconductor Corp
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Yuqiao Semiconductor Co Ltd
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Priority claimed from US11/216,783 external-priority patent/US7419851B2/en
Application filed by Yuqiao Semiconductor Co Ltd filed Critical Yuqiao Semiconductor Co Ltd
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Publication of CN100440469C publication Critical patent/CN100440469C/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/05553—Shape in top view being rectangular
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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Abstract

A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a metal containment wall and a solder layer in which the metal containment wall includes a cavity and the solder terminal contacts the metal containment wall in the cavity, mechanically attaching a semiconductor chip to the routing line, forming a connection joint that electrically connects the routing line and the pad, etching the metal base to reduce contact area between the metal base and the routing line and between the metal base and the metal containment wall, and providing a solder terminal that includes the solder layer.

Description

The manufacture method of the semiconductor chip package of welding ends tool metallic walls
Technical field
The present invention is the manufacture method of semiconductor chip-packaging structure, refers to the semiconductor chip package of welding ends tool metallic walls and the manufacture method of this semiconductor chip package especially.
Background technology
Semiconductor chip has the pin (pads) of I/O at present, and this pin must be connected to circuit external, so that realize the part of functions of electronic system.The media of this connection mainly is with plain conductor array (as a lead frame) or is that an auxiliary circuit (supportcircuit) is as substrate (substrate), though the media of this connection can be connected directly to circuit operation panel (as motherboard).Have a lot of interconnection techniques to be widely used at present, include routing engage (wire bonding), winding engage automatically (tape automated bonding, TAB) and chip bonding technology such as (flip-chip bonding).
At following one deck Assemble Duration, this semiconductor chip package is to be connected to other circuit such as printed circuit board (PCB) (PCB) or motherboard continuously.Different semiconductor die package is used different modes in following one deck combination.For example, (ball gridarray BGA), comprises a solder ball array to ball form array structure dress, and (land gridarray LGA) comprises a metal pin array, the vestige of this metal pin array received tin on printed circuit board (PCB) and the planar lattice array structure is adorned.
Ball form array structure dress mainly contains the metallic element surface that the tin ball is melted in the nickel end, so the tin ball is the contact jaw of following one deck combination.When tin ball and this metallic element surface isolation, this ball form array structure dress becomes and can't contact or invalid.
Traditional tin ball contact technique, its purpose is to allow the tin ball to be fused to the metallic element surface easily.For example, the thin layer of continuous electric nickel plating and gold allows the tin ball can fuse easily on the metallic element surface in a level and smooth and flat partially surface on metallic element surface, but the problem that can not avoid the tin ball to separate.
Traditional tin ball contact technique also fuses on the contact insulator, and for example BT resin (the triazine span comes pi, Bismaleimide triazine epoxy) is to the tin ball, though strengthen the Mechanical Contact of this tin ball.Yet there is identical problem easily by this resin isolation in this tin ball with aforesaid metallic element surface.
Have different restrictions and developing stage at present efficient semiconductor chip-packaging structure, so demand urgently on semiconductor chip package, developing and have more economy, trustworthiness, manufacturability, diversity, and provide the welding ends of superior machinery of tool and characteristic electron, and utilize to connect the technology that engages, make it advantage applicable to the known applications scope.
Summary of the invention
Main purpose of the present invention is, the semiconductor chip package of a welding ends tool metallic walls is provided, and the structure dress of a low cost, high economy and high-reliability is provided.
Another object of the present invention is to, the method for the manufacturing semiconductor chip package of a convenience and economy is provided.
Generally speaking, the invention provides the semiconductor chip, comprise that the conductive trace and of semiconductor chip, a tool coiling, metallic walls and the welding ends of a tool conductive connecting pin can make the connecting portion that has electrical connection between this coiling and conductive connecting pin.This metallic walls comprises a hole, the metallic walls in this welding ends and this hole contact and with this coiling isolation.
The present invention also provides the method for this semiconductor chip package of manufacturing, comprise a metal substrate, a coiling, a metallic walls and a weld layer, wherein, this metallic walls has a hole, the interior metallic walls of this welding ends and hole is contacted, and make this semiconductor chip be connected to this route, and forming one can make between this coiling and conductive connecting pin and have the connecting portion that is electrically connected, then, this metal substrate of etching reduces the contact area between this metal substrate and coiling and metal substrate and metallic walls, and the welding ends that a tool weld layer is provided.
According to content of the present invention, this semiconductor chip package has and first vertical direction of a horizontal direction quadrature and the second relative vertical direction, this semiconductor chip package comprises the semiconductor chip on corresponding first plane of tool and second plane, wherein first plane of this semiconductor chip comprises a conductive connecting pin, one conductive trace comprises coiling, metallic walls and welding ends, horizontal expansion between this metallic walls and welding ends wherein should wind the line, this metallic walls comprises a hole, and has a fixed thickness, this metallic walls is electric conductor unique in this semiconductor chip package and contacts with this welding ends, metallic walls in this welding ends and this hole contacts, a junction can make between this coiling and conductive connecting pin has electrical connection, the sealing agent contacts with this semiconductor chip, and an insulated substrate contacts with this coiling and metallic walls.This semiconductor chip is embedded in the sealing agent, this metallic walls is embedded in this insulated substrate, and from the first direction vertical extent of this welding ends and from the second direction vertical extent of coiling, this hole extends in this insulated substrate, this welding ends extends in the insulated substrate but is not covered on the second direction of this welding ends by other material of this semiconductor chip package, it is in the surf zone of this hole that whole welding ends extends in this insulated substrate, is not covered in the first direction of this welding ends by this metallic walls.
This semiconductor chip is that one chip is embedded in the sealing agent, perhaps is embedded in the sealing agent for the multicore sheet.Second direction is faced in the face of second plane of first direction and this semiconductor chip in first plane of this semiconductor chip, perhaps is that first direction is faced in the face of second plane of second direction and this semiconductor chip in first plane of this semiconductor chip.This semiconductor chip is from this coiling, metallic walls, welding ends and insulated substrate toward the first direction vertical extent.This semiconductor chip is also from this conductive trace toward the first direction vertical extent.In addition, any semiconductor chip is embedded in the sealing agent to from this conductive trace toward the first direction vertical extent.
This coiling is from this metallic walls and welding ends horizontal expansion, and towards this semiconductor chip.This coiling is for reaching from this semiconductor chip toward the second direction vertical extent toward the first direction vertical extent from this metallic walls and welding ends.This coiling is extended inside and outside this semiconductor chip edge, or is placed in outside this semiconductor chip edge.This coiling also be smooth and with second plane parallel of this semiconductor chip.This coiling contacts with this metallic walls, but does not integrate with this metallic walls, perhaps should coiling isolate with this metallic walls.And this coiling is between this metallic walls and any semiconductor chip that is embedded in sealant, and has the conductive path of a tool electric power between this welding ends and any semiconductor chip that is embedded in sealant.The conductive path of the tool electric power by comprising coiling between any semiconductor chip that is embedded in sealant and this metallic walls and welding ends has and is electrically connected.
This metallic walls is embedded in this insulated substrate.This metallic walls from this welding ends toward the first direction vertical extent, and can be, and can be placed in this semiconductor chip edge or outside its edge from this semiconductor chip, coiling, connecting portion and sealant toward the second direction vertical extent.This metallic walls is electric conductor unique in this semiconductor chip package and contacts with this welding ends, and revolves three-sixth turn transverse to the integral solder end periphery that extends to this insulated substrate.This metallic walls has a bowl-type, on its vertical plane, have a U font and be parallel to first direction and second direction, its transverse plane be a circle, a rectangle or a square and with first direction and second direction quadrature, and in the opening part of this hole.The thickness of this metallic walls than the thin thickness of coiling, and is single metal such as nickel side by side, and comprises that the continuous single surface of a tool is used for defining this hole.This metallic walls only contacts with this coiling, welding ends and insulated substrate, perhaps only contacts with a metal column, this welding ends and insulated substrate.
This most height of this metallic walls of hole extend past and diameter, and can be covered in first direction and in a lateral direction by this metallic walls, and comprise an opening towards second direction, this hole is a spill.
This welding ends extends in this hole is inner and outside, perhaps can be placed in this hole.This welding ends is from this semiconductor chip, coiling, connecting portion and sealant toward the second direction vertical extent, and is placed in this semiconductor chip edge or outside the edge.For example: this welding ends extends in this hole is inner and outside, and from this metallic walls and insulated substrate toward the second direction vertical extent, and be covered in second direction by metallic walls.This welding ends fills up this hole.In addition, the part that this welding ends extends in this insulation base is in this hole, and only contacts with this metallic walls, and inside in first direction and horizontal direction by metal confinement.And be in this hole between all contacting between this welding ends and metallic walls.
This connecting portion is to have electrical connection extending between this coiling and the conductive connecting pin and make between this coiling and the conductive connecting pin.This connecting portion is plated metal, electroless-plating metal, tin material, conduction adhesive agent or bonding wire.
The sealing agent covers this semiconductor chip, coiling, metallic walls, welding ends, connecting portion and insulated substrate on first direction, and can isolate with this metallic walls and welding ends.
This insulated substrate can from this semiconductor chip, coiling, connecting portion and sealant toward the second direction vertical extent, and be covered in this semiconductor chip on second direction, and can isolate with this welding ends from this metallic walls and the past first direction vertical extent of welding ends.This insulated substrate can revolve three-sixth turn transverse to this metallic walls periphery.And this insulated substrate can be transversely arranged in a plane towards second direction with this metallic walls, this welding ends is placed in this hole, and it is transversely arranged in this plane towards second direction, perhaps this welding ends extends in hole is inner and outside, and from this past second direction vertical extent in plane towards second direction.
This conductive trace comprises a metal column, this metal column contacts with this coiling and metallic walls, and makes to have between this coiling and metallic walls and be electrically connected, but does not integrate with this coiling and metallic walls, and this coiling and this metallic walls are isolated, and from this metal column horizontal expansion.
This metal column is from metallic walls and welding ends toward the first direction vertical extent, from this semiconductor chip, coiling, connecting portion and sealant toward the second direction vertical extent, and can be placed in the edge of this semiconductor chip or outside the edge.This metal column is covered in first direction and is covered in second direction by this metallic walls and welding ends by coiling.The thickness of this metal column side by side thickness than coiling is thicker, and is a single metal such as a copper.This metal column is a taper shape, and its diameter is for continuing reduction simultaneously when this metallic walls is extended toward second direction.And this metal column comprises first plane and second plane towards second direction towards first direction, the surface area on second plane of this metallic walls is less than the surface area on first plane of this metallic walls, and the surface area on first plane of this metallic walls surface area than second plane of this metallic walls at least is big by 20%.
This semiconductor chip package comprises the insulated substrate that contacts with sealant with semiconductor chip, and this insulated substrate is from this semiconductor chip toward the second direction vertical extent.
This semiconductor chip package is contained in the conductive path of the tool electric power between this conductive connecting pin and welding ends, and this conductive path needs coiling, metallic walls and connecting portion.And this winds the line level coiling is provided between this conductive connecting pin and welding ends, but vertical coiling is not provided, and this metallic walls is not provide coiling between this welding ends and other electric conductor.
This semiconductor chip package is first a level structure dress, is single-chip or many chip packagings.
The others according to the present invention, a kind of method of making semiconductor chip package comprises that (1) provides a metal substrate, one coiling, one metallic walls and a weld layer, wherein this metal substrate comprises first plane and the second relative plane, first plane of this metal substrate is towards first direction, second plane of this metal substrate is towards second direction, this metallic walls extends in the metal substrate, extend towards first plane of this metal substrate from second plane of this metal substrate, and comprise a hole, first plane towards this metal substrate extends in this metal substrate this hole from second plane of this metal substrate, and comprise an opening towards second direction, metallic walls in this weld layer and this hole contacts, (2) mechanically connecting this semiconductor chip winds the line to this, wherein this semiconductor chip comprises a conductive connecting pin, (3) then forming one makes between this coiling and conductive connecting pin and has the connecting portion that is electrically connected, (4) utilize a kind of wet chemical etch mode that this metal substrate is carried out etching, therefore reduce the contact area between this metal substrate and this winding department and this metal substrate and metallic walls, and (5) provide a welding ends, this welding ends in this hole the metallic walls contact and comprise this weld layer.
This method comprises and forms coiling and wind the line and form on metal substrate by depositing this.For example: this method comprises that forming one electroplates and be shielded from this metal substrate, and this platings shielding comprises an opening makes this metal substrate have part to expose, and passes opening that this plating shields then with the expose portion of this wire winded electroplating in this metal substrate.
It is to form on metal substrate by depositing this metallic walls that this method comprises the formation metallic walls.For example: this method comprises that forming a plating is shielded from the metal substrate, and this plating shielding has an opening makes this metal substrate have part to expose, and the opening that passes then in this plating shielding is plated on this metal substrate exposed portions with this metallic walls.
This method comprises that to form this metallic walls be to form a via by this metal substrate of etching, and first plane from second plane of this metal substrate towards this metal substrate extends in this metal substrate, makes this metallic walls deposition then and enters this via.For example: this via is a perforation, pass this metal substrate, and this coiling is exposed, this metallic walls is passed this metal substrate, contact with this coiling, and utilize wet chemical etch that this metal substrate is carried out etching, and can eliminate between this metal substrate and winding department, this metal substrate and winding department and this metal substrate and metallic walls.Perhaps this via has a recess, this recess extends in this metal substrate but does not penetrate, and isolate with first plane of this metal substrate and coiling, this metallic walls extends in this metal substrate but does not penetrate and isolate with first plane and the coiling of this metal substrate, this metal substrate of etching utilizes wet chemical etch, and form a metal column from the not etched part of this metal substrate, and the not etched part of this metal substrate is defined by metallic walls, and this metal column contacts with this coiling and metallic walls.
It is to form on this metallic walls by depositing this weld layer that this method comprises the formation weld layer.Similarly, forming this weld layer only contacts this weld layer with this metallic walls.
The method of this formation welding ends is by forming this weld layer, perhaps forming this weld layer and form welding ends then.For example: form this welding ends and comprise that deposit solder paste is in metallic walls, this tin cream is refluxed form this weld layer and welding ends, perhaps deposit this tin cream in metallic walls, this tin cream is refluxed form this weld layer, then deposit a soldering tin material on weld layer, form this welding ends and this soldering tin material and this weld layer are refluxed.
This method comprises the formation metallic walls and weld layer is to form this via by this metal substrate of etching, deposits this metallic walls then on this metal substrate and in this via, then deposits this weld layer on this metallic walls.For example: form this metallic walls and weld layer according to priority and comprise: this metal substrate of first etching forms this via, this metallic walls is plated on the expose portion of this metal substrate and in this via, tin cream is deposited on this metallic walls, this tin cream is refluxed form this weld layer.And, forming this via and metallic walls according to priority comprises: form ostiolate being shielded from this metal substrate, make this metal substrate have part to expose, this metal substrate of opening etching that then passes this shielding forms this via, the opening that passes this shielding then is plated on this metal substrate exposed portions with this metallic walls and in this via, and remove this shielding, perhaps form an ostiolate etch shield on metal substrate, make this metal substrate have part to expose, and this metal substrate of opening etching that passes this etch shield forms this via, then remove this etch shield, forming an ostiolate plating then is shielded from this metal substrate, make this metal substrate have part to expose and this via is exposed, the opening that then passes this plating shielding with this metallic walls be plated on this metal substrate expose portion and with this via in, and remove this platings and shield.In addition, form this weld layer according to priority and comprise: pass this ostiolate shielding (this via is provided an etch shield and provides a plating shielding to this metallic walls) this tin cream is deposited on this metallic walls, this tin cream is refluxed, remove this shielding then; Perhaps remove this shielding, this tin cream is deposited on this metallic walls, and this tin cream is refluxed.Similarly, forming this weld layer according to priority comprises: pass this ostiolate plating shielding (being in the shielding of the plating on the metallic walls and after the etch shield of this via is removed) this tin cream is deposited on this metallic walls, this tin cream is refluxed, and remove this plating shielding; Perhaps remove this plating shielding, this tin cream is deposited on this metal column, and this tin cream is refluxed.
This method comprises this semiconductor chip of connection and winds the line to this, and an insulation adhesive agent is placed between this semiconductor chip and metal substrate, makes this adhesive agent sclerosis then.
This method comprises the formation connecting portion, is by this connecting portion is plated between this coiling and conductive connecting pin.For example: this connecting portion uses modes such as plating or electroless-plating to be plated between this coiling and the conductive connecting pin.Perhaps the method for this formation connecting portion is not had between this coiling and conductive connecting pin a non-solid-state material deposition, makes this non-solid-state material sclerosis then.For example: this tin cream can be deposited between this coiling and conductive connecting pin, and by refluxing and sclerosis, maybe this conduction adhesive agent can be placed between this coiling and conductive connecting pin, is hardened then then.The method of this formation connecting portion is to engage by routing to form.
It is to utilize the wet chemical etch mode that this method comprises this metal substrate of etching, this coiling is exposed, and remove in conductive connecting pin and the intramarginal metal substrate of semiconductor chip.For example: utilize this metal substrate of wet chemical etch mode etching to remove the contact area of this metal substrate and winding department and this metal substrate and this metallic walls, and can remove this metal substrate, perhaps utilize wet chemical etch to this metal substrate etching, and form a metal column from the not etched part of this metal substrate, the not etched part of this metal substrate is by this metallic walls definition, this metal column contacts with this coiling and metallic walls, and make the connection that has electric power between this coiling and metallic walls, and remove most metal substrate.And utilize wet chemical etch that the coiling tool that this metal substrate etching makes this coiling and other contact with metal substrate is isolated electrically, and make this conductive connecting pin and isolate electrically in other conductive connecting pin tool of semiconductor chip.For example: the method that forms connecting portion is to engage by routing, utilizes the wet chemical etch mode to this metal substrate etching then, this coiling and other coiling tool is isolated electrically, and this conductive connecting pin and other conductive connecting pin tool are isolated electrically.The method that perhaps forms connecting portion is a plating bus for electroplating and utilizing this metal substrate, utilize the wet chemical etch mode to this metal substrate etching then, this coiling and other coiling tool are isolated electrically, and this conductive connecting pin and other conductive connecting pin tool are isolated electrically.Perhaps the method for this metal substrate of etching is utilized wet chemical etch, and this coiling and other coiling tool are isolated electrically, forms this connecting portion by electroless-plating then, still can isolate electrically with other conductive connecting pin tool in this this conductive connecting pin.
This method forms coiling before comprising this metallic walls of formation, and perhaps this coiling and metallic walls side by side are formed, and perhaps forms back this coiling of formation in this metallic walls.
This method forms this metallic walls before being contained in and forming this weld layer.
Form metallic walls before this method is contained in this semiconductor chip and this metal substrate and coiling are connected, perhaps be connected the back with this metal substrate and coiling and form metallic walls in this semiconductor chip.
Form weld layer before this method is contained in this semiconductor chip and this metal substrate and coiling are connected, perhaps be connected the back with this metal substrate and coiling and form weld layer in this semiconductor chip.
This method forms this weld layer before being contained in and forming this welding ends, and perhaps forming this weld layer is this welding ends.
This method is to form this connecting portion before utilizing wet chemical etch to this metal substrate etching, perhaps forms this connecting portion after utilizing this metal substrate of wet chemical etch mode etching.
This method is contained in and connects this semiconductor chip to this metal substrate and preceding this welding ends that forms of coiling, perhaps connects this semiconductor chip to this metal substrate and coiling back and forms this welding ends.
This method forms this welding ends before being contained in and forming this connecting portion, perhaps forms this welding ends after forming this connecting portion.
Form this welding ends before this method is contained in and utilizes wet chemical etch to this metal substrate etching, perhaps after utilizing wet chemical etch, form this welding ends this metal substrate etching.
This method comprises this metallic walls of formation, forms this weld layer then, connects this semiconductor chip then to this metal substrate, coiling, metallic walls and weld layer, and utilizes wet chemical etch to this metal substrate etching then.
This method comprises this metallic walls of formation, connects this semiconductor chip then to this metal substrate, coiling and metallic walls, then forms this weld layer, and utilizes wet chemical etch to this metal substrate etching.
This method comprises and connects this semiconductor chip to this metal substrate and coiling, forms this metallic walls then, then forms this weld layer, and utilizes wet chemical etch to this metal substrate etching.
This method is contained in and connects this semiconductor chip to this metal substrate and coiling, forms sealant, and the sealing agent contacts with this semiconductor chip, and covers this semiconductor chip on first direction.The sealing agent is to form by the metaideophone forming process or by sclerosis.
This method is contained in and forms after the sealing agent, form insulated substrate, this insulated substrate contacts with this coiling, metallic walls and weld layer, and cover this coiling, metallic walls and weld layer on second direction, remove the insulated substrate of a part then, so that this insulated substrate no longer covers this weld layer on second direction.
This method comprises the metal substrate that (1) provides the first relative plane of a tool and second plane, wherein, first plane of this metal substrate is towards first direction, second plane of this metal substrate is towards second direction, (2) forming one then winds the line on first plane of this metal substrate, wherein should coiling with first plane contact of this metal substrate and with second planar isolated of this metal substrate, (3) then utilize first wet chemical etch that this metal substrate etching is formed a via in metal substrate, first plane toward this metal substrate extends in this metal substrate this via from second plane of this metal substrate, (4) then form a metallic walls on this metal substrate, wherein the metal substrate in this metallic walls and this via contacts, and from second plane of this metal substrate first plane toward this metal substrate extends in this metal substrate, and comprise a hole, first plane toward this metal substrate extends in this metal substrate this hole from second plane of this metal substrate, and be covered on the first direction by metallic walls, and comprise an opening towards second direction, (5) form a weld layer and contact with metallic walls in this hole, and isolate with this coiling, (6) mechanically connect the semiconductor chip to this metal substrate and coiling, wherein, this semiconductor chip comprises a conductive connecting pin, (7) form a junction, and make between this coiling and conductive connecting pin and be electrically connected, (8) then utilizing second wet chemical etch is to connect this semiconductor chip after this metallic walls and coiling and form this metallic walls and weld layer to this metal substrate etching, therefore reduce the contact area between this metal substrate and winding department and this metallic walls and metal substrate, and (9) provide a welding ends, metallic walls in this welding ends and this hole contacts, and comprises this weld layer.
This method comprises that (1) provides a metal substrate, this metal substrate comprises the first relative plane and second plane, wherein, first plane of this metal substrate towards second plane of first direction and this metal substrate towards second direction with respect to second direction, (2) formation one winds the line in first plane of this metal substrate then, wherein should coiling with first plane contact of this metal substrate and with second planar isolated of this metal substrate, (3) utilize first wet chemical etch that this metal substrate is carried out etching, therefore in this metal substrate, form a via, first plane toward this metal substrate extends in this metal substrate this via from second plane of this metal substrate, (4) form a metallic walls on this metal substrate, wherein, metal substrate in this metallic walls and this via contacts, and from second plane of this metal substrate first plane toward this metal substrate extends in this metal substrate, and comprise a hole, first plane towards this metal substrate extends in this metal substrate this hole from second plane of this metal substrate, and be covered on the first direction by this metallic walls, and comprise an opening towards second direction, (5) form a tin and connect layer, metallic walls in this weld layer and this hole contacts, isolate with this coiling, (6) connect this semiconductor chip to this metal substrate and coiling, wherein this semiconductor chip comprises a conductive connecting pin, (7) form a junction, this connecting portion makes to have between this coiling and this conductive connecting pin and is electrically connected, (8) forming a sealant is to connect this semiconductor chip to this metal substrate and coiling, wherein, the sealing agent contacts with this semiconductor chip, and from this semiconductor chip, metal substrate and coiling are toward the first direction vertical extent, this metal substrate is from this semiconductor chip and the past second direction vertical extent of coiling, (9) utilizing second wet chemical etch that this metal substrate is carried out etching is to form this metallic walls, after weld layer and the sealant, therefore reduce the contact area between this metal substrate and winding department and this metal substrate and metallic walls, (10) form an insulated substrate, this insulated substrate and this coiling, metallic walls and weld layer contact, and cover this coiling, metallic walls and weld layer are on second direction, be to utilize after this second wet chemical etch carries out etching to this metal substrate, (11) removing a part of insulated substrate makes this insulated substrate no longer cover this weld layer on second direction, and (12) provide a welding ends, and this welding ends contacts with metallic walls in hole and comprises this weld layer.
This method comprises and forms this metallic walls and weld layer in regular turn, be this metallic walls to be plated in this via by this metallic walls being plated on this metal substrate and passing an opening of electroplating shielding, and make this tin cream be deposited on this metallic walls, this tin cream is refluxed form this weld layer.
This method comprises by forming this weld layer and forms this welding ends, be after utilizing second wet chemical etch that this metal substrate is carried out etching perhaps, this soldering tin material and this weld layer are refluxed together and form this welding ends by a soldering tin material is deposited on this weld layer.
This method comprises that connecting this semiconductor chip to this metallic walls and coiling (if this metallic walls and weld layer are formed) is to place between this semiconductor chip and metal substrate by the adhesive agent that should insulate, and makes this adhesive agent sclerosis then.
This method comprises that utilizing first wet chemical etch that this metal substrate is carried out etching forms this via, this via is a perforation, extend through this metal substrate, and this coiling is exposed, then utilize second wet chemical etch that this metal substrate is carried out etching, remove the contact area between this metal substrate and winding department and this metal substrate and metallic walls, and remove this metal substrate, perhaps utilize first wet chemical etch that this metal substrate is carried out etching and form this via, this via is a recess, and extend in this metal substrate, do not pass this metal substrate, then utilize second wet chemical etch, and form a metal column from the not etched part of this metal substrate to this metal substrate etching, this metal column makes being connected of tool electric power between this coiling and metallic walls, and removes most metal substrate.
This method comprise the insulated substrate that removes this part be by grind, laser disappears molten, plasma etching or mode such as photoetch.This method comprises the insulated substrate that removes this part from whole insulated substrates in addition, the insulated substrate of this part is meant and covers this metallic walls and the insulated substrate of weld layer on second direction, and make this metallic walls and weld layer be exposed to second direction, but this coiling is exposed.For example: this method comprises utilizes lapping mode to grind this insulated substrate, but do not grind this metallic walls and weld layer, grind this insulated substrate, metallic walls and weld layer then, laterally be arranged in one up to this insulated substrate and this metallic walls and weld layer and on the plane of second direction, promptly stop to grind, and this metallic walls and weld layer are exposed.And after stopping grinding, this welding ends is made of this weld layer, and can be on this plane by transversely arranged, perhaps this method comprises that a soldering tin material is deposited on this weld layer, this soldering tin material and weld layer refluxed together and form this welding ends, this welding ends from this metallic walls and insulated substrate toward the second direction vertical extent.
This method comprises that utilizing first wet chemical etch that this metal substrate is carried out etching forms this via, form this metallic walls then, then form this weld layer, connected this semiconductor chip afterwards to this metal substrate, coiling, metallic walls and weld layer, then form the sealing agent, utilize second wet chemical etch that metal substrate is carried out etching then, then form insulated substrate, and the insulated substrate that removes part at last.
This method comprises that utilizing first wet chemical etch that this metal substrate is carried out etching forms this via, form this metallic walls then, then connect this semiconductor chip to this metal substrate, coiling and metallic walls, form the sealing agent then, then form this weld layer, utilize second wet chemical etch that metal substrate is carried out etching then, then form insulated substrate, remove the insulated substrate of part at last.
This method comprises that this semiconductor chip of connection is to this metal substrate and coiling metallic walls, form the sealing agent then, then utilize first wet chemical etch that this metal substrate is carried out etching and form this via, form this metallic walls then, then form this weld layer, utilize second wet chemical etch that metal substrate is carried out etching then, then form insulated substrate, remove the insulated substrate of part at last.
Benefit of the present invention is the manufactured easily and tool economy of this semiconductor chip package.Another is in the contact area of etched preceding this metal substrate of reduction of this metal substrate and metallic walls well the present invention, therefore strengthens mechanical support and protects this coiling.Another benefit is that this metal column more can improve consistency and reduce manufacturing time and cost than being formed by plating or electroless-plating by etching formation.Another benefit is that this welding ends can extend to this metallic walls and more surpass in contacting with the high pressure border of this semiconductor chip package in a transverse plane in this insulated substrate, because of the high pressure border of this transverse plane is one towards the main plane of the exposure of second direction, therefore can reduces the tin material and separate and improve reliability.Another benefit is that this connecting portion is formed by various material and processing manufacturing, therefore can utilize the interconnection technique of maturation to be of value to manufacturing and to improve manufacture method.Another benefit is that this semiconductor chip package does not comprise that routing engages or the automatic wire bonds of winding, though this processing to be tool flexible can with other technical compatibility.Another benefit is that this semiconductor chip package utilizes K cryogenic treatment manufactured, can reduce pressure and promote reliability.The present invention has more benefits except that above-mentioned, and is manufactured as the processing procedure of the good control of this semiconductor chip package utilization, easily built to place circuit board, lead frame and winding manufacturing.Still have other benefit to close, utilize the semiconductor chip of compatible made such as copper and do not have necessity product of lead environment for this semiconductor chip package.
Feature of the present invention and advantage will be further described in the execution mode preferred embodiment of passing the imperial examinations at the provincial level, and can more specifically understand the present invention.
Description of drawings
Fig. 1 a is the generalized section of semiconductor chip structure of the present invention.
Fig. 1 b is the schematic top plan view of semiconductor chip structure of the present invention.
Fig. 1 c is the elevational schematic view of semiconductor chip structure of the present invention.
Fig. 2 a is the generalized section of metal substrate structure of the present invention.
Fig. 2 b is the schematic top plan view of metal substrate structure of the present invention.
Fig. 2 c is the elevational schematic view of metal substrate structure of the present invention.
Fig. 3 a is the generalized section of photoresist layer of the present invention and metal substrate structure.
Fig. 3 b is the schematic top plan view of photoresist layer of the present invention and metal substrate structure.
Fig. 3 c is the elevational schematic view of photoresist layer of the present invention and metal substrate structure.
Fig. 4 a is the generalized section of the metal substrate structure of tool recess of the present invention.
Fig. 4 b is the schematic top plan view of the metal substrate structure of tool recess of the present invention.
Fig. 4 c is the elevational schematic view of the metal substrate structure of tool recess of the present invention.
Fig. 5 a is formed at the generalized section of metal substrate structure for metallic walls of the present invention.
Fig. 5 b is formed at the schematic top plan view of metal substrate structure for metallic walls of the present invention.
Fig. 5 c is formed at the elevational schematic view of metal substrate structure for metallic walls of the present invention.
Fig. 6 a is covered in the generalized section of the second photoresist layer structure for template of the present invention.
Fig. 6 b is covered in the schematic top plan view of the second photoresist layer structure for template of the present invention.
Fig. 6 c is covered in the elevational schematic view of the second photoresist layer structure for template of the present invention.
Fig. 7 a is deposited on the generalized section of metallic walls structure for tin cream of the present invention.
Fig. 7 b is deposited on the schematic top plan view of metallic walls structure for tin cream of the present invention.
Fig. 7 c is deposited on the elevational schematic view of metallic walls structure for tin cream of the present invention.
Fig. 8 a removes the generalized section of structure after the template for the present invention.
Fig. 8 b removes the schematic top plan view of structure after the template for the present invention.
Fig. 8 c removes the elevational schematic view of structure after the template for the present invention.
Fig. 9 a forms the generalized section of structure behind the weld layer for tin cream of the present invention.
Fig. 9 b forms the schematic top plan view of structure behind the weld layer for tin cream of the present invention.
Fig. 9 c forms the elevational schematic view of structure behind the weld layer for tin cream of the present invention.
Figure 10 a peels off the generalized section of back structure for the present invention's first photoresist layer and second photoresist layer.
Figure 10 b peels off the schematic top plan view of back structure for the present invention's first photoresist layer and second photoresist layer.
Figure 10 c peels off the elevational schematic view of back structure for the present invention's first photoresist layer and second photoresist layer.
Figure 11 a is formed at the generalized section of structure behind the metal substrate for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
Figure 11 b is formed at the schematic top plan view of structure behind the metal substrate for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
Figure 11 c is formed at the elevational schematic view of structure behind the metal substrate for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
The generalized section of structure when Figure 12 a invests metal substrate for the present invention's coiling.
The schematic top plan view of structure when Figure 12 b invests metal substrate for the present invention's coiling.
The elevational schematic view of structure when Figure 12 c invests metal substrate for the present invention's coiling.
Figure 13 a peels off the generalized section of back structure for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
Figure 13 b peels off the schematic top plan view of back structure for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
Figure 13 c peels off the elevational schematic view of back structure for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
The generalized section of structure when Figure 14 a is shielded from metal substrate and coiling for the present invention's welding.
The schematic top plan view of structure when Figure 14 b is shielded from metal substrate and coiling for the present invention's welding.
The elevational schematic view of structure when Figure 14 c is shielded from metal substrate and coiling for the present invention's welding.
Figure 15 a forms the generalized section of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 15 b forms the schematic top plan view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 15 c forms the elevational schematic view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 16 a is formed at the generalized section of coiling back structure for plating contact of the present invention.
Figure 16 b is formed at the schematic top plan view of coiling back structure for plating contact of the present invention.
Figure 16 c is formed at the elevational schematic view of coiling back structure for plating contact of the present invention.
Figure 17 a peels off the generalized section of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 17 b peels off the schematic top plan view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 17 c peels off the elevational schematic view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 18 a is formed at the generalized section of welding shielding back structure for adhesive agent of the present invention.
Figure 18 b is formed at the schematic top plan view of welding shielding back structure for adhesive agent of the present invention.
Figure 18 c is formed at the elevational schematic view of welding shielding back structure for adhesive agent of the present invention.
Figure 19 a is the generalized section of tool semiconductor chip structure of the present invention.
Figure 19 b is the schematic top plan view of tool semiconductor chip structure of the present invention.
Figure 19 c is the elevational schematic view of tool semiconductor chip structure of the present invention.
The generalized section of structure when Figure 20 a invests conductive connecting pin and plating contact for connecting portion of the present invention.
The schematic top plan view of structure when Figure 20 b invests conductive connecting pin and plating contact for connecting portion of the present invention.
The elevational schematic view of structure when Figure 20 c invests conductive connecting pin and plating contact for connecting portion of the present invention.
Figure 21 a is the generalized section of tool sealant structure of the present invention.
Figure 21 b is the schematic top plan view of tool sealant structure of the present invention.
Figure 21 c is the elevational schematic view of tool sealant structure of the present invention.
Figure 22 a forms the generalized section of back structure on metal substrate for metal column of the present invention.
Figure 22 b forms the schematic top plan view of back structure on metal substrate for metal column of the present invention.
Figure 22 c forms the elevational schematic view of back structure on metal substrate for metal column of the present invention.
Figure 23 a forms the generalized section of back structure for insulated substrate of the present invention.
Figure 23 b forms the schematic top plan view of back structure for insulated substrate of the present invention.
Figure 23 c forms the elevational schematic view of back structure for insulated substrate of the present invention.
Figure 24 a removes the generalized section of back structure for insulated substrate of the present invention.
Figure 24 b removes the schematic top plan view of back structure for insulated substrate of the present invention.
Figure 24 c removes the elevational schematic view of back structure for insulated substrate of the present invention.
Figure 25 a forms the generalized section of back structure for tin ball of the present invention.
Figure 25 b forms the schematic top plan view of back structure for tin ball of the present invention.
Figure 25 c forms the elevational schematic view of back structure for tin ball of the present invention.
Figure 26 a forms the generalized section of back structure for welding ends of the present invention.
Figure 26 b forms the schematic top plan view of back structure for welding ends of the present invention.
Figure 26 c forms the elevational schematic view of back structure for welding ends of the present invention.
Figure 27 a is the generalized section of semiconductor chip package structure of the present invention.
Figure 27 b is the schematic top plan view of semiconductor chip package structure of the present invention.
Figure 27 c is the elevational schematic view of semiconductor chip package structure of the present invention.
Figure 28 a is the generalized section of semiconductor chip structure of the present invention.
Figure 28 b is the schematic top plan view of semiconductor chip structure of the present invention.
Figure 28 c is the elevational schematic view of semiconductor chip structure of the present invention.
Figure 29 a is the generalized section of metal substrate structure of the present invention.
Figure 29 b is the schematic top plan view of metal substrate structure of the present invention.
Figure 29 c is the elevational schematic view of metal substrate structure of the present invention.
Figure 30 a is the generalized section of photoresist layer of the present invention and metal substrate structure.
Figure 30 b is the schematic top plan view of photoresist layer of the present invention and metal substrate structure.
Figure 30 c is the elevational schematic view of photoresist layer of the present invention and metal substrate structure.
Figure 31 a is the generalized section of the metal substrate structure of tool recess of the present invention.
Figure 31 b is the schematic top plan view of the metal substrate structure of tool recess of the present invention.
Figure 31 c is the elevational schematic view of the metal substrate structure of tool recess of the present invention.
Figure 32 a is the generalized section of the metal substrate structure of tool metallic walls of the present invention.
Figure 32 b is the schematic top plan view of the metal substrate structure of tool metallic walls of the present invention.
Figure 32 c is the elevational schematic view of the metal substrate structure of tool metallic walls of the present invention.
Figure 33 a peels off the generalized section of back structure for the present invention's first photoresist layer and second photoresist layer.
Figure 33 b peels off the schematic top plan view of back structure for the present invention's first photoresist layer and second photoresist layer.
Figure 33 c peels off the elevational schematic view of back structure for the present invention's first photoresist layer and second photoresist layer.
Figure 34 a is formed at the generalized section of structure behind the metal substrate for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
Figure 34 b is formed at the schematic top plan view of structure behind the metal substrate for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
Figure 34 c is formed at the elevational schematic view of structure behind the metal substrate for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
The generalized section of structure when Figure 35 a invests metal substrate for the present invention's coiling.
The schematic top plan view of structure when Figure 35 b invests metal substrate for the present invention's coiling.
The elevational schematic view of structure when Figure 35 c invests metal substrate for the present invention's coiling.
Figure 36 a peels off the generalized section of back structure for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
Figure 36 b peels off the schematic top plan view of back structure for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
Figure 36 c peels off the elevational schematic view of back structure for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
The generalized section of structure when Figure 37 a is shielded from metal substrate and coiling for the present invention's welding.
The schematic top plan view of structure when Figure 37 b is shielded from metal substrate and coiling for the present invention's welding.
The elevational schematic view of structure when Figure 37 c is shielded from metal substrate and coiling for the present invention's welding.
Figure 38 a forms the generalized section of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 38 b forms the schematic top plan view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 38 c forms the elevational schematic view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 39 a is formed at the generalized section of coiling back structure for plating contact of the present invention.
Figure 39 b is formed at the schematic top plan view of coiling back structure for plating contact of the present invention.
Figure 39 c is formed at the elevational schematic view of coiling back structure for plating contact of the present invention.
Figure 40 a peels off the generalized section of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 40 b peels off the schematic top plan view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 40 c peels off the elevational schematic view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 41 a is formed at the generalized section of welding shielding back structure for adhesive agent of the present invention.
Figure 41 b is formed at the schematic top plan view of welding shielding back structure for adhesive agent of the present invention.
Figure 41 c is formed at the elevational schematic view of welding shielding back structure for adhesive agent of the present invention.
Figure 42 a is the generalized section of tool semiconductor chip structure of the present invention.
Figure 42 b is the schematic top plan view of tool semiconductor chip structure of the present invention.
Figure 42 c is the elevational schematic view of tool semiconductor chip structure of the present invention.
The generalized section of structure when Figure 43 a invests conductive connecting pin and plating contact for connecting portion of the present invention.
The schematic top plan view of structure when Figure 43 b invests conductive connecting pin and plating contact for connecting portion of the present invention.
The elevational schematic view of structure when Figure 43 c invests conductive connecting pin and plating contact for connecting portion of the present invention.
Figure 44 a is the generalized section of tool sealant structure of the present invention.
Figure 44 b is the schematic top plan view of tool sealant structure of the present invention.
Figure 44 c is the elevational schematic view of tool sealant structure of the present invention.
Figure 45 a is covered in the generalized section of metal substrate structure for template of the present invention.
Figure 45 b is covered in the schematic top plan view of metal substrate structure for template of the present invention.
Figure 45 c is covered in the elevational schematic view of metal substrate structure for template of the present invention.
Figure 46 a is deposited on the generalized section of metallic walls structure for tin cream of the present invention.
Figure 46 b is deposited on the schematic top plan view of metallic walls structure for tin cream of the present invention.
Figure 46 c is deposited on the elevational schematic view of metallic walls structure for tin cream of the present invention.
Figure 47 a removes the generalized section of structure after the template for the present invention.
Figure 47 b removes the schematic top plan view of structure after the template for the present invention.
Figure 47 c removes the elevational schematic view of structure after the template for the present invention.
Figure 48 a forms the generalized section of structure behind the weld layer for tin cream of the present invention.
Figure 48 b forms the schematic top plan view of structure behind the weld layer for tin cream of the present invention.
Figure 48 c forms the elevational schematic view of structure behind the weld layer for tin cream of the present invention.
Figure 49 a forms the generalized section of back structure on metal substrate for metal column of the present invention.
Figure 49 b forms the schematic top plan view of back structure on metal substrate for metal column of the present invention.
Figure 49 c forms the elevational schematic view of back structure on metal substrate for metal column of the present invention.
Figure 50 a forms the generalized section of back structure for insulated substrate of the present invention.
Figure 50 b forms the schematic top plan view of back structure for insulated substrate of the present invention.
Figure 50 c forms the elevational schematic view of back structure for insulated substrate of the present invention.
Figure 51 a removes the generalized section of back structure for SI semi-insulation substrate of the present invention.
Figure 51 b removes the schematic top plan view of back structure for SI semi-insulation substrate of the present invention.
Figure 51 c removes the elevational schematic view of back structure for SI semi-insulation substrate of the present invention.
Figure 52 a forms the generalized section of back structure for tin ball of the present invention.
Figure 52 b forms the schematic top plan view of back structure for tin ball of the present invention.
Figure 52 c forms the elevational schematic view of back structure for tin ball of the present invention.
Figure 53 a forms the generalized section of back structure for welding ends of the present invention.
Figure 53 b forms the schematic top plan view of back structure for welding ends of the present invention.
Figure 53 c forms the elevational schematic view of back structure for welding ends of the present invention.
Figure 54 a is the generalized section of semiconductor chip package structure of the present invention.
Figure 54 b is the schematic top plan view of semiconductor chip package structure of the present invention.
Figure 54 c is the elevational schematic view of semiconductor chip package structure of the present invention.
Figure 55 a is the generalized section of semiconductor chip structure of the present invention.
Figure 55 b is the schematic top plan view of semiconductor chip structure of the present invention.
Figure 55 c is the elevational schematic view of semiconductor chip structure of the present invention.
Figure 56 a is the generalized section of metal substrate structure of the present invention.
Figure 56 b is the schematic top plan view of metal substrate structure of the present invention.
Figure 56 c is the elevational schematic view of metal substrate structure of the present invention.
Figure 57 a is the generalized section of photoresist layer of the present invention and metal substrate structure.
Figure 57 b is the schematic top plan view of photoresist layer of the present invention and metal substrate structure.
Figure 57 c is the elevational schematic view of photoresist layer of the present invention and metal substrate structure.
The generalized section of structure when Figure 58 a invests metal substrate for the present invention's coiling.
The schematic top plan view of structure when Figure 58 b invests metal substrate for the present invention's coiling.
The elevational schematic view of structure when Figure 58 c invests metal substrate for the present invention's coiling.
Figure 59 a peels off the generalized section of back structure for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
Figure 59 b peels off the schematic top plan view of back structure for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
Figure 59 c peels off the elevational schematic view of back structure for the present invention's the 3rd photoresist layer and the 4th photoresist layer.
The generalized section of structure when Figure 60 a is shielded from metal substrate and coiling for the present invention's welding.
The schematic top plan view of structure when Figure 60 b is shielded from metal substrate and coiling for the present invention's welding.
The elevational schematic view of structure when Figure 60 c is shielded from metal substrate and coiling for the present invention's welding.
Figure 61 a forms the generalized section of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 61 b forms the schematic top plan view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 61 c forms the elevational schematic view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 62 a is formed at the generalized section of coiling back structure for plating contact of the present invention.
Figure 62 b is formed at the schematic top plan view of coiling back structure for plating contact of the present invention.
Figure 62 c is formed at the elevational schematic view of coiling back structure for plating contact of the present invention.
Figure 63 a peels off the generalized section of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 63 b peels off the schematic top plan view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 63 c peels off the elevational schematic view of back structure for the present invention's the 5th photoresist layer and the 6th photoresist layer.
Figure 64 a is formed at the generalized section of welding shielding back structure for adhesive agent of the present invention.
Figure 64 b is formed at the schematic top plan view of welding shielding back structure for adhesive agent of the present invention.
Figure 64 c is formed at the elevational schematic view of welding shielding back structure for adhesive agent of the present invention.
Figure 65 a is the generalized section of tool semiconductor chip structure of the present invention.
Figure 65 b is the schematic top plan view of tool semiconductor chip structure of the present invention.
Figure 65 c is the elevational schematic view of tool semiconductor chip structure of the present invention.
The generalized section of structure when Figure 66 a invests conductive connecting pin and plating contact for connecting portion of the present invention.
The schematic top plan view of structure when Figure 66 b invests conductive connecting pin and plating contact for connecting portion of the present invention.
The elevational schematic view of structure when Figure 66 c invests conductive connecting pin and plating contact for connecting portion of the present invention.
Figure 67 a is the generalized section of tool sealant structure of the present invention.
Figure 67 b is the schematic top plan view of tool sealant structure of the present invention.
Figure 67 c is the elevational schematic view of tool sealant structure of the present invention.
Figure 68 a is formed at the generalized section of metal substrate structure for the present invention's second photoresist layer.
Figure 68 b is formed at the schematic top plan view of metal substrate structure for the present invention's second photoresist layer.
Figure 68 c is formed at the elevational schematic view of metal substrate structure for the present invention's second photoresist layer.
Figure 69 a is the generalized section of tool notch configuration of the present invention.
Figure 69 b is the schematic top plan view of tool notch configuration of the present invention.
Figure 69 c is the elevational schematic view of tool notch configuration of the present invention.
Figure 70 a is the generalized section of tool metallic walls structure of the present invention.
Figure 70 b is the schematic top plan view of tool metallic walls structure of the present invention.
Figure 70 c is the elevational schematic view of tool metallic walls structure of the present invention.
Figure 71 a is covered in the generalized section of the second photoresist layer structure for template of the present invention.
Figure 71 b is covered in the schematic top plan view of the second photoresist layer structure for template of the present invention.
Figure 71 c is covered in the elevational schematic view of the second photoresist layer structure for template of the present invention.
Figure 72 a is deposited on the generalized section of metallic walls structure for tin cream of the present invention.
Figure 72 b is deposited on the schematic top plan view of metallic walls structure for tin cream of the present invention.
Figure 72 c is deposited on the elevational schematic view of metallic walls structure for tin cream of the present invention.
Figure 73 a removes the generalized section of structure after the template for the present invention.
Figure 73 b removes the schematic top plan view of structure after the template for the present invention.
Figure 73 c removes the elevational schematic view of structure after the template for the present invention.
Figure 74 a forms the generalized section of structure behind the weld layer for tin cream of the present invention.
Figure 74 b forms the schematic top plan view of structure behind the weld layer for tin cream of the present invention.
Figure 74 c forms the elevational schematic view of structure behind the weld layer for tin cream of the present invention.
Figure 75 a peels off the generalized section of back structure for the present invention's second photoresist layer.
Figure 75 b peels off the schematic top plan view of back structure for the present invention's second photoresist layer.
Figure 75 c peels off the elevational schematic view of back structure for the present invention's second photoresist layer.
Figure 76 a removes the generalized section of back structure for metal substrate of the present invention.
Figure 76 b removes the schematic top plan view of back structure for metal substrate of the present invention.
Figure 76 c removes the elevational schematic view of back structure for metal substrate of the present invention.
Figure 77 a forms the generalized section of back structure for insulated substrate of the present invention.
Figure 77 b forms the schematic top plan view of back structure for insulated substrate of the present invention.
Figure 77 c forms the elevational schematic view of back structure for insulated substrate of the present invention.
Figure 78 a removes the generalized section of back structure for SI semi-insulation substrate of the present invention.
Figure 78 b removes the schematic top plan view of back structure for SI semi-insulation substrate of the present invention.
Figure 78 c removes the elevational schematic view of back structure for SI semi-insulation substrate of the present invention.
Figure 79 a forms the generalized section of back structure for tin ball of the present invention.
Figure 79 b forms the schematic top plan view of back structure for tin ball of the present invention.
Figure 79 c forms the elevational schematic view of back structure for tin ball of the present invention.
Figure 80 a forms the generalized section of back structure for welding ends of the present invention.
Figure 80 b forms the schematic top plan view of back structure for welding ends of the present invention.
Figure 80 c forms the elevational schematic view of back structure for welding ends of the present invention.
Figure 81 a is the generalized section of semiconductor chip package structure of the present invention.
Figure 81 b is the schematic top plan view of semiconductor chip package structure of the present invention.
Figure 81 c is the elevational schematic view of semiconductor chip package structure of the present invention.
Figure 82 a is the generalized section of the semiconductor chip package of fourth embodiment of the invention.
Figure 82 b is the schematic top plan view of the semiconductor chip package of fourth embodiment of the invention.
Figure 82 c is the elevational schematic view of the semiconductor chip package of fourth embodiment of the invention.
Figure 83 a is the generalized section of the semiconductor chip package of fifth embodiment of the invention.
Figure 83 b is the schematic top plan view of the semiconductor chip package of fifth embodiment of the invention.
Figure 83 c is the elevational schematic view of the semiconductor chip package of fifth embodiment of the invention.
Figure 84 a is the generalized section of the semiconductor chip package of sixth embodiment of the invention.
Figure 84 b is the schematic top plan view of the semiconductor chip package of sixth embodiment of the invention.
Figure 84 c is the elevational schematic view of the semiconductor chip package of sixth embodiment of the invention.
Figure 85 a is the generalized section of the semiconductor chip package of seventh embodiment of the invention.
Figure 85 b is the schematic top plan view of the semiconductor chip package of seventh embodiment of the invention.
Figure 85 c is the elevational schematic view of the semiconductor chip package of seventh embodiment of the invention.
Figure 86 a is the generalized section of the semiconductor chip package of eighth embodiment of the invention.
Figure 86 b is the schematic top plan view of the semiconductor chip package of eighth embodiment of the invention.
Figure 86 c is the elevational schematic view of the semiconductor chip package of eighth embodiment of the invention.
Figure 87 a is the generalized section of the semiconductor chip package of ninth embodiment of the invention.
Figure 87 b is the schematic top plan view of the semiconductor chip package of ninth embodiment of the invention.
Figure 87 c is the elevational schematic view of the semiconductor chip package of ninth embodiment of the invention.
Figure 88 a is the generalized section of the semiconductor chip package of tenth embodiment of the invention.
Figure 88 b is the schematic top plan view of the semiconductor chip package of tenth embodiment of the invention.
Figure 88 c is the elevational schematic view of the semiconductor chip package of tenth embodiment of the invention.
Figure 89 a is the generalized section of the semiconductor chip package of eleventh embodiment of the invention.
Figure 89 b is the schematic top plan view of the semiconductor chip package of eleventh embodiment of the invention.
Figure 89 c is the elevational schematic view of the semiconductor chip package of eleventh embodiment of the invention.
Figure 90 a is the generalized section of the semiconductor chip package of twelveth embodiment of the invention.
Figure 90 b is the schematic top plan view of the semiconductor chip package of twelveth embodiment of the invention.
Figure 90 c is the elevational schematic view of the semiconductor chip package of twelveth embodiment of the invention.
Figure 91 a is the generalized section of the semiconductor chip package of thriteenth embodiment of the invention.
Figure 91 b is the schematic top plan view of the semiconductor chip package of thriteenth embodiment of the invention.
Figure 91 c is the elevational schematic view of the semiconductor chip package of thriteenth embodiment of the invention.
Figure 92 a is the generalized section of the semiconductor chip package of fourteenth embodiment of the invention.
Figure 92 b is the schematic top plan view of the semiconductor chip package of fourteenth embodiment of the invention.
Figure 92 c is the elevational schematic view of the semiconductor chip package of fourteenth embodiment of the invention.
Figure 93 a is the generalized section of the semiconductor chip package of fifteenth embodiment of the invention.
Figure 93 b is the schematic top plan view of the semiconductor chip package of fifteenth embodiment of the invention.
Figure 93 c is the elevational schematic view of the semiconductor chip package of fifteenth embodiment of the invention.
Figure 94 is the structural representation of the metal column of sixteenth embodiment of the invention.
Figure 95 is the structural representation of the metal column of seventeenth embodiment of the invention.
Figure 96 is the structural representation of the metal column of eighteenth embodiment of the invention.
Figure 97 is the structural representation of the metal column of nineteenth embodiment of the invention.
Figure 98 is the structural representation of the metal column of twentieth embodiment of the invention.
Embodiment
Fig. 1 a to Figure 27 c is for making first embodiment of semiconductor chip package method, and wherein Fig. 1 a to Figure 27 a is that generalized section, Fig. 1 b to Figure 27 b are that schematic top plan view, Fig. 1 c to Figure 27 c are elevational schematic view.
See also shown in Fig. 1 a, Fig. 1 b and Fig. 1 c, be semiconductor chip structure generalized section of the present invention, semiconductor chip structure schematic top plan view of the present invention and semiconductor chip structure elevational schematic view of the present invention.As shown in the figure: the present invention is a kind of semiconductor chip package of welding ends tool metallic walls, and wherein this semiconductor chip 110 is an integrated circuit, and be connected by a plurality of transistors, circuit, connecting portion and with other form (not shown).This semiconductor chip 110 comprises corresponding first plane 112 and second plane 114, the thickness that this first plane 112 and second plane are 114 is 150 microns, and this first plane 112 is for active surface (active surface) and comprise a conductive connecting pin 116 and a passivation layer 118 (passivation layer).
In fact, the arrangement that is in line of this conductive connecting pin 116 and this passivation layer 118, the surface that makes this first plane 112 is smooth.This conductive connecting pin 116 extends on the passivation layer 118, perhaps is embedded in this passivation layer 118, and this conductive connecting pin 116 provides a junction point to be connected with these semiconductor chip 110 circuit external.Therefore, this conductive connecting pin 116 is an I/O pin or one power supply/ground connection pin.The length of this conductive connecting pin 116 and width respectively are 100 microns.
This conductive connecting pin 116 has an aluminium base, and it is by soaking this semiconductor chip 110 under room temperature in the 0.05M phosphoric acid 1 minute, utilizing distilled water to clean then that this conductive connecting pin 116 is cleaned.This conductive connecting pin 116 is considered as a superficial layer with aluminium base, and perhaps this conductive connecting pin 116 comprises a superficial layer, and this superficial layer covers this aluminium base, and contacts with this superficial layer according to the character of this connecting portion.In first embodiment, this connecting portion is a metallic gold routing (a gold wire bond).Therefore this conductive connecting pin 116 can not be regarded as holding this connecting portion, and perhaps on this aluminium base, this conductive connecting pin 116 can be chromium layer/copper layer/gold layer to this conductive connecting pin 116 by at least one above metal level storehouse, or is that titanium layer/nickel dam/gold layer is on this aluminium base.Wherein, this chromium layer or titanium layer provide this aluminium base one barrier (abarrier) and be furnished with an adhesive agent between upper metal layers and this aluminium bases.It is by utilizing a shielding to carry out evaporation (evaporation), electroplating complicated relatively processing such as (electroplating) or spraying plating (sputtering) that yet this metal level storehouse tool optionally is deposited.Perhaps, this conductive connecting pin 116 also can as this semiconductor chip 110 being soaked in a zinc solution, deposit a zinc layer on this aluminium base by forming a nickel surface layer on this aluminium base, and its method is zinc impregnation (zincation).Further, above-mentioned this zinc solution comprises the NaOH (NaOH) of 150 gram/litres, the zinc oxide (ZnO) of 25 gram/litres and the natrium nitrosum (NaNO of 1 gram/litre 3), can reduce the resolution ratio of this aluminium base just as tartaric acid.Afterwards, this nickel surface layer be electroless deposition in this aluminium base through zinc impregnation, a kind of suitable electroless nickel plating solution be in Celsius 85 the degree under Enthone EnplateNI-424.
This semiconductor chip 110 comprises at least one above conductive connecting pin on first plane 112, but only indicates single conductive connecting pin 116 among the figure, in order to illustrate and to illustrate conveniently.In addition, this semiconductor chip 110 has followed other semiconductor chip by independent, and this semiconductor chip all invests on the wafer originally.
See also shown in Fig. 2 a, Fig. 2 b and Fig. 2 c, be metal substrate structural profile schematic diagram of the present invention, metal substrate structure schematic top plan view of the present invention and metal substrate elevational schematic view of the present invention.As shown in the figure: this metal substrate 120 comprises the corresponding first main plane 122 and the second main plane 124.This metal substrate 120 (Metal base) is a metal copper plate, and its thickness is 150 microns.
See also shown in Fig. 3 a, Fig. 3 b and Fig. 3 c, be photoresist layer of the present invention and metal substrate structural profile schematic diagram, photoresist layer of the present invention and metal substrate structure schematic top plan view and photoresist layer of the present invention and metal substrate structure elevational schematic view.As shown in the figure: this first photoresist layer 126 (photoresist layer) and second photoresist layer 128 are formed on this metal substrate 120.This first photoresist layer 126 and second photoresist layer 128 are to be deposited by a kind of dry type film lamination treatment (a dry film lamination), and simultaneously with this first photoresist layer 126 and second photoresist layer 128 respectively the underground heat roll extrusion be printed on this first main plane 122 and the second main plane 124.One light shield (A reticle) (not shown) is positioned near this second photoresist layer 128.Afterwards, it is by optionally making this light shield of light transmission that this second photoresist layer 128 is printed on pattern, and uses a developer solution (a developer) that photoresistance is partly removed, and makes this photoresistance partly for soluble by light, dries (hardbaking) then.This second photoresist layer 128 comprises an opening, and the diameter of this opening is 250 microns, and this second main plane 124 is exposed, and this first photoresist layer 126 is not printed on pattern.The thickness of this first photoresist layer 126 and second photoresist layer 128 is 25 microns, is meant respectively to begin to count from this first main plane 122 and the second main plane 124.
See also shown in Fig. 4 a, Fig. 4 b and Fig. 4 c, be the elevational schematic view of the metal substrate structure of the schematic top plan view of the metal substrate structure of the generalized section of the metal substrate structure of tool recess of the present invention, tool recess of the present invention and tool recess of the present invention.As shown in the figure: this recess 130 is formed on this metal substrate 120.The formation of this recess 130 is by the rotating vane type chemical etching of a kind of back of the body limit (a back-side wet chemical etch), makes the expose portion on this second main plane 124 carry out etching, and utilizes this second photoresist layer 128 to be its etch shield.Because this first photoresist layer 126 can be protected the one side of this metal substrate 120; for example: a bottom nozzle (not shown) can spray this wet chemical etch solution on this metal substrate 120; when a top jet nozzle (not shown) is not used, or overall structure when being dipped in the wet chemical etch solution and this second photoresist layer front-end protection is provided.This wet chemical etch solution has the copper of high selectivity, and dark to these 80 microns of metal substrate 120 etchings.This recess 130 is a blind hole (a blind via), and extends in this metal substrate 120 from this second main plane 124, second main plane, but does not penetrate this metal substrate 120.The diameter of this recess 130 on this second main plane 124, second plane is 300 microns, and this recess 130 is 80 microns with respect to the degree of depth on this second main plane 124, second plane, with the spacing on the first main plane 122, first plane be 70 microns.
Wherein, a kind of suitable wet chemical etch solution is the ammoniacal liquor of alkalescence.In order to make this recess 130 have appropriate diameter, and the desirable etching period that this metal substrate 120 is exposed to this chemical etching liquor must be set up through repetition test.
See also shown in Fig. 5 a, Fig. 5 b and Fig. 5 c, for metallic walls of the present invention is formed at metal substrate structural profile schematic diagram, metallic walls of the present invention is formed at metal substrate structure schematic top plan view and metallic walls of the present invention is formed at metal substrate structure elevational schematic view.As shown in the figure: this metallic walls 132 is formed in the recess 130 of this metal substrate 120, and answers with the profile phase of this recess 130.This metallic walls 132 covers these recesses 130 in downward direction, and is deposited in this recess 130 but non-this recess 130 that fills up.And this metallic walls 132 is electrically connected with this metal substrate 120, but non-and this metal substrate 120 integrate.
This metallic walls 132 is plated on the gold (not shown) that layer is formed of this nickel dam by a nickel dam and that is plated on this metal substrate 120.This nickel dam is sandwiched in this metal substrate 120 and contacts with golden interlayer and with this metal substrate 120 and gold layer, and should contact with this nickel dam by the gold layer, and isolates with this metal substrate 120.Therefore this nickel dam is covered by this gold layer, and should be exposed by the gold layer.The thickness of this metallic walls 132 is 10.1 microns.Especially, the thickness of this nickel dam is 10 microns, and the thickness of this gold layer is 0.1 micron.In order to illustrate conveniently, this nickel dam and gold layer are only drawn simple layer in figure.
The formation of this metallic walls 132 utilizes this first photoresist layer 126 and second photoresist layer 128 for electroplating shielding, and the electroplating of going forward side by side is handled.Therefore, this metallic walls 132 is formed.At the beginning, one plating bus (a plating bus) (not shown) is connected to this metal substrate 120, be used for this plating bus from the electric current that external power source produced, and this metal substrate 120 is dipped in an electrolytic nickel electroplating solution (an electrolytic nickel plating solution), this solution is as the Technic Techni Nickel " S " under in room temperature.At last, this nickel dam is plated on recess 130 expose portions of this metal substrate 120.Yet continue to carry out the nickel electroplating processes and arrive needed thickness up to this nickel dam.Afterwards overall structure is shifted out from this electrolytic nickel electroplating solution, be dipped in electrolysis gold electroplating solution again, this solution is as the TechnicOrotemp under in room temperature, electric current by the external power source gained is used for this plating bus simultaneously, this gold layer is plated on the nickel dam, arrive needed thickness and continue to carry out the gold plating up to this gold layer, yet overall structure is shifted out and utilize distilled water flushing from electrolysis gold electroplating solution, remove pollutant.
The shape of this metallic walls 132 is bowl-shape, and its vertical plane is a U font, and with upward to parallel with downward direction, and it is in the circle that is shaped as of the transverse plane on the second main plane 124, the second main plane, and with upward to and the downward direction quadrature.The height of this metallic walls 132 is 80 microns, with the diameter on this second main plane 124 be 300 microns, the thickness of this metallic walls 132 is 10.1 microns.But this metallic walls 132 has small varied in thickness.Can be thicker such as this metallic walls 132 than near the thickness this second main plane 124, because near the turnover rate of the electrolytic solution this second main plane 124 is higher.This metallic walls 132 is made up of continuous single nickel dam and continuous single gold layer.This metallic walls 132 has a hole 134, and this hole 134 is isolated with this metal substrate 120, and extends in this recess 130.This hole 134 extends to this metallic walls 132, and through these metallic walls 132 most height and diameters, this hole 134 is covered in upward to reaching horizontal direction by this metallic walls 132, and comprise an opening 136, this opening is towards following direction, and forms a concave surface, the shape in hole, hole.
See also shown in Fig. 6 a, Fig. 6 b and Fig. 6 c, for template of the present invention is covered in the structural profile schematic diagram of second photoresist layer, template of the present invention is covered in the structure schematic top plan view of second photoresist layer and the structure elevational schematic view that template of the present invention is covered in second photoresist layer.As shown in the figure: the thickness of this template 138 is 80 microns, and comprises an opening (anopening), and the diameter of its opening is 200 microns, this template 138 with in opening, metallic walls 132 and the hole 134 of this second photoresist layer 128 by vertical arrangement.
In order to illustrate and illustrate convenience, this metal substrate 120 is plotted on this template 138, and is maintained fixed the convenient and preceding figure of direction relatively, though overall architecture direction mountain peak, and this gravity will help this template 138 to be covered on this second photoresist layer 128.
See also shown in Fig. 7 a, Fig. 7 b and Fig. 7 c, for tin cream of the present invention is deposited on the structural profile schematic diagram of metallic walls, tin cream of the present invention is deposited on the structure schematic top plan view of metallic walls and the structure elevational schematic view that tin cream of the present invention is deposited on metallic walls.As shown in the figure: the tin material particle that this tin cream 140 comprises Powdered titanium-Yin-copper is mixed in the organic resin solvent that sticks, and it comprises a flux.This tin cream 140 utilizes mould printing that it is deposited on this metallic walls 132.In mould printing is handled, one squeezer (squeegee) (not shown) pushes this tin cream 140 along the surface of this template 138 with respect to this metal substrate 120, the opening by this second photoresist layer 128 and the opening of template 138 clamp-on on this metallic walls 132 and this hole 134 in.This tin cream 140 can form Any shape under room temperature, so this tin cream 140 fills up this hole 134, in the opening of this second photoresist layer 128 and in the opening of this template 1388.Yet this tin cream 140 separates with this metal substrate 120.Yet this tin cream 140 is isolated with this metal substrate 120.
In order to illustrate conveniently, this metal substrate 120 is drawn on the top of this tin cream 140, and is maintained fixed direction in order to compare with preceding figure, though overall structure is reversed the deposition that gravity can help this tin cream 140.
See also shown in Fig. 8 a, Fig. 8 b and Fig. 8 c, remove structure elevational schematic view after structure schematic top plan view after the template and the present invention remove template for the present invention removes structural profile schematic diagram, the present invention after the template.As shown in the figure: be the schematic diagram after this template 138 is removed from this second photoresist layer 128.
In order to illustrate conveniently, this metal substrate 120 is drawn on the top of this tin cream 140, and is maintained fixed direction in order to compare with preceding figure, though overall structure is reversed, when this template 138 was removed, this tin cream 140 helped to be covered on this structure by gravity.
See also shown in Fig. 9 a, Fig. 9 b and Fig. 9 c, form structure elevational schematic view after structure schematic top plan view behind the weld layer and tin cream of the present invention form weld layer for tin cream of the present invention forms structural profile schematic diagram, tin cream of the present invention behind the weld layer.As shown in the figure: this weld layer 142 (solder layer) contacts and is electrically connected with this metallic walls 132, but non-and this metallic walls 132 integrate, and isolates with this metal substrate 120.And this weld layer 142 fills up this hole 134, and its thickness is 30 microns, with respect to the downward direction of this metal substrate 120, metallic walls 132 and hole 134.
This weld layer 142 is formed by these tin cream 140 backflows.At the beginning, overall structure is heated to about 260 degree, heating causes cosolvent and the tin material particle in this metallic walls 132 and this tin cream 140 in tin cream 140 to produce reaction, and the tin material particle in this metallic walls 132 and this tin cream 140 removes oxide, this tin material particle is melted, and make this tin material particle combination, and will evaporate in the organic resin in this tin cream 140, so the littler and generation tin material backflow than its original size of this tin cream 140.The gold layer of this metallic walls 132 provides a wetted surface (a wettable surface) in order to make the tin material that the tin material refluxes and decomposition has been melted in addition, so 132 of this metallic walls are made of nickel dam and gold layer by the biplate metal level, the nickel dam that is changed by unitary piece of metal is constituted.And this second photoresist layer 128 limits this tin material and is back to this metallic walls 132, and prevents that this tin material from touching this metal substrate 120.Afterwards, stop the tin material particle cooled and solidified that to heat and will be melted, when hardening weld layer 142.
The diameter of this weld layer 142 is 280 microns, and vertically arranges with opening, metallic walls 132 and hole 134 in this second photoresist layer 128.
In order to illustrate conveniently, this metal substrate 120 is drawn on the top of this weld layer 142, and is maintained fixed direction in order to compare with preceding figure, though overall structure is reversed, when this weld layer 142 formed, this tin material was by gravity reflux.
See also shown in Figure 10 a, Figure 10 b and Figure 10 c, be structure schematic top plan view and of the present invention first photoresist layer and second photoresist layer the structure elevational schematic view peel off after of first photoresist layer of the present invention and second photoresist layer structural profile schematic diagram, first photoresist layer of the present invention and second photoresist layer after peeling off after peeling off.As shown in the figure: this first photoresist layer 126 and second photoresist layer 128 use a solvent that it is removed, the alkaline solution that this solvent closes for temperature, its pH value is 9, is being suitable for during to copper, nickel and tin when photoresist, so this metal substrate 120, metallic walls 132 or tin metal layer 142 are not removed.
See also shown in Figure 11 a, Figure 11 b and Figure 11 c, be formed at structure elevational schematic view after structure schematic top plan view behind the metal substrate and the 3rd photoresist layer of the present invention and the 4th photoresist layer are formed at metal substrate for the 3rd photoresist layer of the present invention and the 4th photoresist layer are formed at structural profile schematic diagram, the 3rd photoresist layer of the present invention and the 4th photoresist layer behind the metal substrate.As shown in the figure: the 3rd photoresist layer 144 and the 4th photoresist layer 146 utilize the dry type film lamination treatment that the 3rd photoresist layer 144 and the hot respectively roll extrusion of the 4th photoresist layer 146 are printed on the first main plane 122 and the second main plane 124.One light shield (A reticle) (not shown) be positioned over the 3rd photoresist layer 144 near.Afterwards, the 3rd photoresist layer 144 is printed on pattern by optionally making this light shield of light transmission, and uses a developer solution (adeveloper) that photoresistance is partly removed, and makes this photoresistance partly for soluble by light, dries (hard baking) then.So the 3rd photoresist layer 144 has an opening, and this first main plane 122, first main plane is exposed, and the 4th photoresist layer 146 is not printed on pattern.The thickness of the 3rd photoresist layer 144 and the 4th photoresist layer 146 is 50 microns, and respectively from this first first main plane 122, main plane and the second main plane 124, the second main plane begin to calculate.
See also shown in Figure 12 a, Figure 12 b and Figure 12 c structure elevational schematic view when the structural profile schematic diagram when investing metal substrate for coiling of the present invention, the structure schematic top plan view when coiling of the present invention invests metal substrate and coiling of the present invention invest metal substrate.As shown in the figure: this coiling 150 is formed on the first main plane 122 of this metal substrate 120, and isolates with this second main plane 124, metallic walls 132 and weld layer 142.This coiling 150 is made up of the copper layer that a nickel dam and that is plated on this metal substrate 120 is plated on nickel metal layer, this nickel dam contacts and is sandwiched between this metal substrate 120 and the copper layer with this metal substrate 120, and this copper layer contacts with this nickel dam, and isolates with this metal substrate 120.Therefore, this nickel dam is covered by this copper layer, and this copper layer is exposed.The thickness of this coiling 150 is 30 microns.Especially, the thickness of this nickel dam is 5 microns, and the thickness of this copper layer is 25 microns.In order to illustrate conveniently, do not draw this nickel dam and copper layer among the figure, only draw single metal level.
This coiling 150 is used the 3rd photoresist layer 144 and the 4th photoresist layer 146 and carries out electroplating processes and form for electroplating shielding.At the beginning, one plating bus (not shown) is connected to this metal substrate 120, can be used for this plating bus from the electric current that external power source provided, and this metal substrate 120 is dipped in an electrolytic nickel electroplating solution, its solution is as the Technic Techni Nickel " S " under room temperature.Therefore this nickel dam plating (deposition or long) in the expose portion of this metal substrate 120, then continues to carry out the nickel electroplating processes and reaches needed thickness up to this nickel dam.Afterwards, total is shifted out and be dipped in a cathode copper electroplating solution from the electrolytic nickel electroplating solution, its solution is as the Sel-Rex CUBATH M under in room temperature TM, and estimated current can be used for this plating bus, makes this copper layer be plated on nickel dam, and the plating of lasting copper reaches needed thickness up to this copper layer.Overall structure shifts out from the cathode copper electroplating solution afterwards, and removes pollutant with the distilled water cleaning.
This coiling 150 is smooth plane, and it comprises a microscler winding portion 152 (elongated routing portion) and big circular portion 154 (enlargedcircular portion).This microscler winding portion 152 and big circular portion 154 adjoin each other and on same plane.The width of this microscler winding portion 152 is 100 microns, and the diameter of circular portion 154 is 300 microns greatly.And, this microscler winding portion 152 from these bigger circular portion 154 horizontal expansions, this metallic walls 132 and weld layer 142 vertically arranged with this bigger circular portion 154.
See also shown in Figure 13 a, Figure 13 b and Figure 13 c, be structure schematic top plan view and of the present invention three photoresist layer and four photoresist layer the structure elevational schematic view peel off after of the 3rd photoresist layer of the present invention and the 4th photoresist layer structural profile schematic diagram, the 3rd photoresist layer of the present invention and the 4th photoresist layer after peeling off after peeling off.As shown in the figure: the 3rd photoresist layer 144 and the 4th photoresist layer 146 utilize a solvent that it is removed, and this solvent is the alkaline solution that closes of temperature, and its pH value is 9, when photoresist suitable during to copper, nickel and tin material.So this metal substrate 120, metallic walls 132, weld layer 142 or wind the line 150 is not removed.
See also shown in Figure 14 a, Figure 14 b and Figure 14 c structure elevational schematic view when structure schematic top plan view when structural profile schematic diagram, the welding of the present invention when being shielded from metal substrate and coiling for welding of the present invention is shielded from metal substrate and coiling and welding of the present invention are shielded from metal substrate and coiling.As shown in the figure: this welding shielding 156 (Soldermask) are a liquid resin, are deposited on this metal substrate 120 and wind the line on 150.This liquid resin (liquid resin) solidifiable or sclerosis when relative low temperature afterwards, the scope of its relative temperature is between 100 is spent to Celsius 250, make this liquid resin form a solid-state insulating epoxy layer (solid insulative epoxy layer), the thickness of this solid-state insulating epoxy layer is 50 microns, and in this metal substrate 120 and 150 contacts that wind the line, and extend upward 20 microns from this coiling 150.
Afterwards, the upper part with this welding shielding 156 is to be removed by grinding.Especially, utilize a rotation diamond wheel (a rotating diamond sand wheel) and distilled water to be used for the front side of this welding shielding 156.At the beginning, this diamond wheel only grinds this welding shielding 156, when continuing to grind, makes these welding shielding 156 attenuation when down move on polished surface.This diamond wheel touches this and wound the line 150 o'clock then, therefore begins to grind this coiling 150, and when continuing to grind, this coiling 150 and welding shield 156 while attenuation downwards when move on polished surface.Before this coiling 150 and welding shielding 156 reach needed thickness and touch this metal substrate 120, stop to grind, then, pollutant is cleaned and removed to overall structure with distilled water.
After having ground, this coiling 150 and welding shielding 156 extend upward 25 microns from this metal substrate 120.Therefore this milled processed is to remove the upper section of the coiling 150 of 5 micron thickness, and the upper section of the welding of 25 micron thickness shielding 156.
In this stage, this welding shielding 156 connects and contacts with this coiling 150, and covers the side, edge of this coiling 150.Yet, this welding shielding 156 no longer be covered in this coiling 150 in upward to.Therefore this coiling 150 and welding shielding 156 all are exposed.And, this coiling 150 and welding shielding 156 by transversely arranged on the plane that makes progress one day.Therefore, the horizontal surface that is exposed comprises this coiling 150 and welding shielding 156, and towards the top.
See also shown in Figure 15 a, Figure 15 b and Figure 15 c, be structure schematic top plan view and of the present invention five photoresist layer and six photoresist layer the structure elevational schematic view form after of the 5th photoresist layer of the present invention and the 6th photoresist layer structural profile schematic diagram, the 5th photoresist layer of the present invention and the 6th photoresist layer after forming after forming.As shown in the figure: the 5th photoresist layer 158 is formed in this coiling 150 and the welding shielding 156, and the 6th photoresist layer 160 is formed on this metal substrate 120, metallic walls 132 and the weld layer 142.The 5th photoresist layer 158 and the 6th photoresist layer 160 are deposited with the form of liquid state, and utilize the roll extrusion coating to be deposited on corresponding plane respectively.One light shield (A reticle) (not shown) be positioned over the 5th photoresist layer 158 near.Afterwards, the 6th photoresist layer 160 is printed on pattern, and optionally makes this light shield of light transmission, and uses a developer solution (a developer) that photoresistance is partly removed, and makes this photoresistance partly for soluble by light, dries (hardbaking) then.So the 5th photoresist layer 158 has an opening, this coiling 150 is exposed, and the 6th photoresist layer 160 is not printed on pattern.The thickness of the 5th photoresist layer 158 and the 6th photoresist layer 160 is 50 microns, and begins to calculate from this coiling 150 and metal substrate 120 respectively.
See also shown in Figure 16 a, Figure 16 b and Figure 16 c, be formed at structure elevational schematic view after structure schematic top plan view after the coiling and plating contact of the present invention are formed at coiling for plating contact of the present invention is formed at structural profile schematic diagram, plating contact of the present invention after the coiling.As shown in the figure: this plating contact 162 (Plated contact) contacts and is electrically connected with this coiling 150, but non-and this coiling 150 integrate, and with these metal substrate 120 isolation.This plating contact 162 is plated on the gold layer of nickel dam by a nickel coating and that is plated on this coiling 150, and this nickel dam contact with this coiling 150 and gold layer, and is sandwiched between this coiling 150 and golden layer, and should contact with this nickel dam by the gold layer, and with these 150 isolation that wind the line.Therefore, this nickel dam is covered by this gold layer, and should be exposed by the gold layer.The thickness of this plating contact 162 is 3.5 microns, and especially, the thickness of this nickel dam is 3 microns, and thickness that should the gold layer is 0.5 micron.In order to illustrate conveniently, do not draw this nickel dam and gold layer among the figure, only draw single metal level.
This plating contact 162 the 5th photoresist layer 158 and the 6th photoresist layer 160 carry out electroplating processes for the plating shielding and are formed.At the beginning, one plating bus (not shown) is connected to this metal substrate 120, can be used for this plating bus from the electric current that external power source provided, and this metal substrate 120 is dipped in an electrolytic nickel electroplating solution, its solution is as the Technic Techni Nickel " S " under in room temperature.Therefore this nickel dam is plated on the expose portion of this coiling 150, continues to carry out the nickel plating and reaches needed thickness up to this nickel dam.Yet, total is shifted out and be dipped in electrolysis gold electroplating solution from the electrolytic nickel electroplating solution, and its solution is as the Technic Orotemp under in room temperature, and estimated current can be used for this plating bus, make this gold layer be plated on nickel dam, and lasting gold plating reach needed thickness up to this Gold plated Layer.Then overall structure is shifted out from the cathode copper electroplating solution, and remove pollutant with the distilled water cleaning.
See also shown in Figure 17 a, Figure 17 b and Figure 17 c, be structure schematic top plan view and of the present invention five photoresist layer and six photoresist layer the structure elevational schematic view peel off after of the 5th photoresist layer of the present invention and the 6th photoresist layer structural profile schematic diagram, the 5th photoresist layer of the present invention and the 6th photoresist layer after peeling off after peeling off.As shown in the figure: the 5th photoresist layer 158 and the 6th photoresist layer 160 use a solvent that it is removed, the alkaline solution that this solvent closes for temperature, its pH value is 9, when photoresist suitable during to copper, nickel, tin material and epoxy resin.So this metal substrate 120, metallic walls 132, weld layer 142, coiling 150, welding shielding 156 or plating contact 162 are not removed.
See also shown in Figure 18 a, Figure 18 b and Figure 18 c, be formed at structure elevational schematic view after structure schematic top plan view after the welding shielding and adhesive agent of the present invention are formed at the welding shielding for adhesive agent of the present invention is formed at structural profile schematic diagram, adhesive agent of the present invention after the welding shielding.As shown in the figure: this adhesive agent 164 (Adhesive) can comprise an organic surface protectant (an organic surface protectant); as HK 2000; this adhesive agent 164 is to be used in overall structure after the 5th photoresist layer 158 and the 6th photoresist layer 160 are removed, and reduces natural oxide and results from the copper laminar surface that is exposed.Being used for the semiconductor die package process of assembling uses this organic surface protectant in the insulation mount technology.
Then, one liquid resin such as polyamic acid (polyamic acid) utilize mould printing to make it be deposited on this welding shielding 156, when mould printing, one template (not shown) is placed in this coiling 150 and the welding shielding 156, one template opening (a stencil opening) forms a line with this metal substrate 120, and skew is arranged with this coiling 150, then, one squeezer (squeegee) (not shown) pushes this liquid resin and shields 156 directions along this template surface toward corresponding welding, pass this template opening, on this welding shielding 156, but not metal substrate 120, coiling 150 or plating contact 162.This liquid resin plastic type under room temperature is an Any shape.So, the welding shielding 156 that this liquid resin flows and covers a part, but still isolate with metal substrate 120, coiling 150 and plating contact 162.
See also shown in Figure 19 a, Figure 19 b and Figure 19 c, be the schematic top plan view of the generalized section of tool semiconductor chip structure of the present invention, tool semiconductor chip structure of the present invention and the elevational schematic view of tool semiconductor chip structure of the present invention.As shown in the figure: this adhesive agent 164 contacts with this semiconductor chip 110 and welding shielding 156, and in this semiconductor chip 110 and 156 extensions of welding shielding, but still isolate with this metal substrate 120, coiling 150 and plating contact 162.First plane 112 of this semiconductor chip 110 is towards last and away from this welding shielding 156 and be exposed; And second plane 114 of this semiconductor chip 110 is towards down, and towards this welding shielding 156, and covered by this adhesive agent 164.This semiconductor chip 110 is not in contact with one another with metal substrate 120, and this semiconductor chip 110 is not in contact with one another with coiling 150, and this semiconductor chip 110 is not in contact with one another with welding shielding 156.
This adhesive agent 164 is sandwiched in this semiconductor chip 110 and 156 of welding shieldings use relatively low pressure in acquisition head (pick-up head), this acquisition head is placed on the semiconductor chip 110 on the adhesive agent 164, need suppress this semiconductor chip 110 adhesive agent last 5 second, loosen this semiconductor chip 110 then.This acquisition head is heated in relative low temperature, be 150 degree as relative low temperature, and this adhesive agent 164 receives heat and reaches this semiconductor chip 110 from this acquisition head.Therefore this adhesive agent 164 is being close to that this semiconductor chip is aggregated especially, and form colloid but be not fully to be solidified, and this adhesive agent 164 is aggregated especially, and provides a soft mechanical engagement (a loose mechanical bond) in 156 of this semiconductor chip 110 and welding shieldings.
This semiconductor chip 110 is placed in relative position with metal substrate 120, so that this semiconductor chip 110 is placed in the edge of this adhesive agent 164, and this metallic walls 132, weld layer 142, coiling 150 and plating contact 162 are placed in outside the edge of this semiconductor chip 110.This semiconductor chip 110 and metal substrate 120 utilize an automated pattern recognition system (an automated pattern recognition system) to be arranged.
Afterwards, overall structure is placed on a baking oven, this adhesive agent 164 is hardened in relative low temperature fully, the scope of its relative low temperature is spent to 250 degree between 200, and form one and stick together insulate heat firmly and adjust aramid layer (adhesive insulative thermosettingpolyimide layer), it contacts with this semiconductor chip 110 and welding shielding 156, and is sandwiched in this semiconductor chip 110 and welds 156 of shieldings, and mechanically connects this semiconductor chip 110 and welding shielding 156.This adhesive agent 164 is 35 microns in the thickness of 156 of this semiconductor chip 110 and welding shieldings.
In this stage, this metal substrate 120 covers this semiconductor chip 110, coiling 150, welding shielding 156, plating contact 162 and adhesive agent 164, and from this semiconductor chip 110, coiling 150, welding shielding 156, plating contact 162 and adhesive agent 164 extend downwards, this metallic walls 132 is configured in outside the edge of this semiconductor chip, and from this semiconductor chip 110, coiling 150, welding shielding 156, plating contact 162 and adhesive agent 164 extend downwards, this weld layer 142 is configured in outside the edge of this semiconductor chip 110, and from this semiconductor chip 110, metallic walls 132, coiling 150, welding shielding 156, plating contact 162 and adhesive agent 164 extend downwards, this coiling 150 is placed in the downward direction of this semiconductor chip 110, and outside the edge of this semiconductor chip 110, and from this metallic walls 132 and 142 horizontal expansions of this weld layer, towards this semiconductor chip 110, and this adhesive agent 164 extends downwards from this semiconductor chip 110.And this semiconductor chip 110 still tool is isolated with this metal substrate 120, metallic walls 132, weld layer 142, coiling 150 and plating contact 162 electrically.
See also shown in Figure 20 a, Figure 20 b and Figure 20 c structure elevational schematic view when the structural profile schematic diagram when investing conductive connecting pin and plating contact for connecting portion of the present invention, the structure schematic top plan view when connecting portion of the present invention invests conductive connecting pin and plating contact and connecting portion of the present invention invest conductive connecting pin and plating contact.As shown in the figure: this connecting portion 166 is the routing of a metallic gold, its spherical being engaged on this conductive connecting pin 116, and its wedge bond is on this plating contact 162.Wherein this metal wire connects spherical contact and wedge contact, and the thickness of this routing is 25 microns.Therefore this connecting portion 166 contacts with this conductive connecting pin 116 and plating contact 162, and this conductive connecting pin 116 and plating contact 162 is electrically connected, 150 be connected so also can make this conductive connecting pin 116 can have electrically with this metal substrate 120, metallic walls 132, weld layer 142 and wind the line.And this connecting portion 166 is to reach to extend outside the edge in the edge of this semiconductor chip 110, and this semiconductor chip 110 extends upward 100 microns certainly, and isolates with this metal substrate 120, metallic walls 132, weld layer 142, coiling 150 and welding shielding 156.
See also shown in Figure 21 a, Figure 21 b and Figure 21 c, be the schematic top plan view of the generalized section of tool sealant structure of the present invention, tool sealant structure of the present invention and the elevational schematic view of tool sealant structure of the present invention.As shown in the figure: sealing agent 168 is to be deposited by metaideophone forming process (tran sfer molding), and this metaideophone forming process is most commonly used to the semiconductor chip construction method plastics structure is adorned.In general, this metaideophone forming process comprises that assembly forms an injection molded material (molding compound) in a sealed mould, this injection molded material be under the pressure that can be heat, plastic state with this injection molded material in also being sent to the die cavity of sealing for running channel (runners) and the cast gate (gates) that tree-shaped array is passed in material chamber (transfer pot) from center accumulator tank (centralreservoir).
The turnkey of metaideophone shaping preferably contains a preheater (preheater), a mould, a moulding press (press) and a hardening furnace (cure oven).This mould comprises a part of the upper die and a counterdie part, also can be described as (platens) or (halves) is used for defining this die cavity.This mould also comprises this material chamber, sprue gating and exhaust outlet (vents).This material chamber holds this injection molded material.This running channel and cast gate provide from this material chamber to the passage of die cavity.This cast gate is placed near this die cavity inlet, and is compressed and then controls the flowing velocity of this injection molded material when entering this die cavity and injection rate and make this injection molded material that is cured be displaced into this metaideophone easily and form when carrying out.This exhaust outlet is permitted restricted air and can be discharged, but this exhaust outlet is very little, and the injection molded material of only a few is passed through.
This injection molded material is the dull and stereotyped form that is at the beginning.This preheater uses the high-frequency energy to make this injection molded material be preheated to a temperature, and its temperature range is between 50 degree are spent to 100.The temperature of this preheating is lower than the temperature of metaideophone, so this injection molded material that is preheated is not in the state of a fluid.In addition, overall structure is placed in one of them die cavity, and this moulding press oil pressure ground running makes this mould driving fit and makes this die cavity driving fit by upper layer module and lower module location.This alignment pin (Guide pins) guarantees that this part of the upper die and part of the lower die driving fit place are just just in die parting line.In addition, this mould is heated to a metaideophone temperature, and the scope of its metaideophone temperature between 250 degree, is by inserting the electrons heat casket in this part of the upper die and part of the lower die between 150 degree.
Seal after this mould, this injection molded material that is preheated is that dull and stereotyped form is placed in this material chamber.A metaideophone striker (transfer plunger) pressurization is as for the injection molded material in this material chamber then.This pressure limit between 10 to 100kgf/cm 2And can set high more good more and do not have a problem of reliability.To be converted to fluid state in the injection molded material in expecting the chamber to heating of this mould and processing such as pressure that stress on this metaideophone striker.And the pressure that comes from this metaideophone striker is forced to make the metaideophone striker of this fluid enter this die cavity by this running channel and cast gate.This pressure is maintained at a fixing Best Times, can guarantee that this injection molded material fills up this die cavity.
This lower module contacts with this metal substrate 120, and can with these metal substrate 120 driving fits, and be right after with this metal substrate 120.Yet, 120 microns of this part of the upper die and this connecting portion 166 distances.Therefore the expose portion of this injection molded material and this semiconductor chip 110, coiling 150, welding shielding 156, plating contact 162, adhesive agent 164 and connecting portion 166 is contacted with in the die cavity.After it's 1 to 3 minute has been past the metaideophone temperature, this injection molded material polymerization and partly be hardened in the mould.
In case after having the injection molded material of part to be hardened, have enough elasticity and hardness, make it can resist the strength of extruding, make it can't remarkable and permanent distortion.This moulding press is opened mould, and this jemmy takes out the structure that is cast from this mould, and the injection molded material that lefts in invests on this structure that is cast, and this injection molded material that lefts in is cured and is organized and removes on this running channel and cast gate.This structure that is cast is loaded a casket box (magazine), and is placed in this hardening furnace 4 to 16 hours, and in one than the low a little temperature of metaideophone temperature in but than indoor temperature height this injection molded material is fully hardened.
This injection molded material is that the mixed sealing resin of more than one compositions adds various additive, and its main additive comprises curing agent, accelerator, inert filler, binding agent, incombustible agent, the agent that eliminates stress, colouring agent and release agent.The sealing resin provides a screen (a binder), this curing agent (curing agent) provides the polymerization (linear/cross-polymerization) of straight line/cross hairs, this accelerator improves this rate of polymerization, this inert filler increases heat conductivity, heat resistanceheat resistant impact and reduction thermal coefficient of expansion, resin runs off, shrink and remaining pressure, this links agent increases integrally-built adhesion, this incombustible agent reduces inflammability, this agent that eliminates stress reduces the crackle expansion, this colouring agent reduces photon energy and device visibility, and this release agent makes easily and shifts out from mould.
Sealing agent 168 contacts and covers with this semiconductor chip 110, coiling 150, welding shielding 156, plating contact 162, adhesive agent 164 and connecting portion 166.Sealing agent 168 contacts with first plane 112 and the external margin thereof of this semiconductor chip 110, but isolates with second plane 114 of this semiconductor chip 110.Sealing agent 168 is covered in this metal substrate 120, metallic walls 132 and welding ends 142, but isolates with this metal substrate 120, metallic walls 132 and welding ends 142.
Sealing agent 168 is a compressible solid-state passivation layer that sticks together, and it can provide the protection of environment, as moisture-proof, and to the protection of the particle of semiconductor chip 110 as to this mechanical support of 150 of winding the line.This semiconductor chip is embedded in the sealing agent 168.
Sealing agent 168 extends upward from this semiconductor chip 110, metal substrate 120, metallic walls 132, weld layer 142, coiling 150, welding shielding 156, plating contact 162, adhesive agent 164 and connecting portion 166, its thickness is 400 microns, and extends upward 120 microns from this connecting portion 166.
See also shown in Figure 22 a, Figure 22 b and Figure 22 c, be structural profile schematic diagram, of the present invention metal column structure schematic top plan view and of the present invention metal column the structure elevational schematic view in metal substrate on form after in metal substrate on form after of metal column of the present invention after forming on the metal substrate.As shown in the figure: this metal column 170 is the not etched part of this metal substrate 120, with this metallic walls 132 and wind the line and 150 contact, and be sandwiched in this metallic walls 132 and the coiling 150, and this metallic walls 132 is electrically connected with 150 of coilings, but not with this metallic walls 132 and wind the line and 150 integrate, and this metal column 170 is made up of copper.
This metal column 170 be formed be by a kind of wet chemical etch to these metal substrate 120 etchings, and utilize this metallic walls 132 and weld layer 142 to be its etch shield, and optionally protect this metal substrate 120.Therefore, this metal column 170 is made the not etched part of this metal substrate 120 according to this metallic walls 132 and is formed.
A kind ofly carry on the back limit rotating vane type chemical etching and be used to the second main plane 124, metallic walls 132 and welding ends 142 this metal substrate 120.Can spray this wet chemical etch solution on this metal substrate 120 as this bottom nozzle, when top jet nozzle is not used or overall structure be dipped in this wet chemical etch solution, sealing agent 168 provides front side protection.When copper is suitable for this wet chemical etch during to nickel, tin material, epoxy resin and injection molded material, so, when the nickel dam of 120 pairs of these metallic walls 132 of this metal substrate, weld layer 142, this coiling 150, welding shielding 156 and sealant 168, be suitable for this wet chemical etch.
This wet chemical etch passes completely through this metal substrate 120, therefore influences the design transfer of this metallic walls 132 on metal substrate 120.And make this coiling 150 and welding shielding 156 exposures, reduce but do not remove this metal substrate 120 shielding 156 contact area with metallic walls 132, coiling 150 and welding.Yet the nickel dam of this metallic walls 132, weld layer 142, coiling 150, welding shielding 156 or sealant 168 are not removed.And the nickel dam of this coiling 150 is copper layers of protecting this coiling 150 when chemical etching.So this coiling 150 is not removed.
This wet chemical etch also this metal substrate 120 of transverse cuts and causes this metal column 170 to inner inclination and increase height with respect to this metallic walls 132.One suitable angle of inclination between 45 degree between less than 90 degree, 75 degree according to appointment.
This metal column 170 contacts in big circular portion 154 with this coiling 150, but isolates with microscler winding portion 152, and extends downwards from this coiling 150.Therefore this metal column 170 has part to overlap with this coiling 150 in downward direction, yet this metal column 170 does not have this coiling 150 of covering in downward direction.
A kind of suitable wet chemical etch solution is provided by the ammoniacal liquor of alkalescence.Make this metal substrate 120 be exposed to the repetition test that desirable etching period in this chemical etching liquor must be repeatedly, for etching penetrates this metal substrate 120, and the metal column 170 that forms the tool ideal dimensions, but this metallic walls 132 is suffered erosion or avoid making this coiling 150 to be exposed in the chemical etching liquor.
This metal column 170 comprises corresponding first plane 172, second plane 174 and the conical surface 176 (tapered sidewalls), wherein, first plane 172 of this metal column 170 is established on the not etching part on the first main plane 122, the first main plane of this metal substrate 120, and second plane 174 of this metal column 170 is established in the not etching part of the recess 130 in this metal substrate 120.Therefore this first plane 172 is towards last, and this second plane 174 is towards following.This first plane 172 contacts with this coiling 150 and towards this coiling 150, and isolates with this metallic walls 132, and this second plane 174 contact with this metallic walls 132 and towards this metallic walls 132, but with these 150 isolation that wind the line.In addition, this first plane 172 is smooth, and with first plane 112 and second plane 114 of this semiconductor chip 110 and wind the line 150 parallelly, and this second plane 174 is along the profile of this metallic walls 132.This conical surface 176 and this first plane 172 and second plane, 174 adjacency, and towards these second plane, 174 past inner inclination.
This metal column 170 is a taper shape, and 174 height is 70 microns between first plane 172 and second plane for it, and when extend downwards on this first plane 172 (from this first plane 172 towards second plane 174), its diameter little by little dwindles.This first plane 172 is circular, and its diameter is 250 microns, and this second plane 174 also is circular, and its diameter is 200 microns.This first plane 172 and second plane 174 are vertically with metallic walls 132, weld layer 142 and big circular portion 154 etc. arranges.Therefore this second plane 174 is placed in the surf zone on this metallic walls 132, weld layer 142, big circular portion 154 and first plane 172.And the surf zone on this first plane 172 is than the surf zone big at least 20% on this second plane 174.
This metal column 170 is placed in outside the edge of this semiconductor chip 110, and be placed in this semiconductor chip 110, coiling 150, welding shielding 156, adhesive agent 164, connecting portion 166 and sealant 168, and extend upward from this metallic walls 132 and weld layer 142 in downward direction.And this semiconductor chip 110 is from this coiling 150, welding shielding 156, adhesive agent 164 and metal column 170 extend upward, this coiling is placed in this metallic walls 132, weld layer 142 and metal column 170 in upward to, and from this metallic walls 132, weld layer 142 and metal column 170 horizontal expansions, and towards this semiconductor chip 110, sealing agent 168 covers this semiconductor chip 110, metallic walls 132, weld layer 142, coiling 150, welding shielding 156, adhesive agent 164, connecting portion 166 and metal column 170, and from this semiconductor chip 110, metallic walls 132, weld layer 142, coiling 150, welding shielding 156, adhesive agent 164, connecting portion 166 and metal column 170 extend upward.
168 pairs of these coilings 150 of sealing agent and metal column 170 provide mechanical support, decrease in the mechanical tension on this adhesive agent 164, and be useful especially after this this metal column 170 of metal substrate 120 etched formation.Sealing agent 168 these coilings 150 of protection and metal column 170 are avoided mechanical damage when chemical etching and distilled water cleaning.For example: the physics strength that sealing agent 168 is absorbed in chemical etching and distilled water when cleaning, because of this semiconductor chip 110 is separated when chemical etching and the distilled water cleaning with this coiling 150.Therefore, sealing agent 168 increases the integrality of structure, and can be used more firmly in chemical etching and distilled water cleaning, and then boosts productivity.
This conductive trace 180 comprises metallic walls 132, weld layer 142, coiling 150, plating contact 162 and metal column 170.This conductive trace 180 is fit to provide the path of level and vertical direction between conductive connecting pin 116 and next level structure dress.
See also shown in Figure 23 a, Figure 23 b and Figure 23 c, be structure schematic top plan view and of the present invention insulated substrate the structure elevational schematic view form after of structural profile schematic diagram, the of the present invention insulated substrate of insulated substrate of the present invention after forming after forming.As shown in the figure: this insulated substrate 182 is the epoxy resin of a paste at the beginning, it comprises an epoxy resin, a curing agent, an accelerator and a filler, wherein this filler is an inert material, dissolve the quartz of shape as tripoli (silica) for powder, promote the consistency of heat conductivity, thermal-shock resistance (thermal shock resistance) and thermal coefficient of expansion.This epoxy paste (epoxy paste) is deposited on this metallic walls 132, weld layer 142, coiling 150, welding shielding 156 and the metal column 170; this epoxy paste is hardened down in relative low temperature and is formed a solid-state insulator that sticks together then; the scope of its relative low temperature between 100 degree to 250 degree, and the sealant (a protectiveseal) that can provide this coiling 150 and metal column 170 1 tools to protect.
This insulated substrate 182 contacts and covers this metallic walls 132, weld layer 142, coiling 150, welding shielding 156 and metal column 170 with this metallic walls 132, weld layer 142, coiling 150, welding shielding 156 and metal column 170, and extend downwards from this metallic walls 132, weld layer 142, coiling 150, welding shielding 156 and metal column 170, and cover this semiconductor chip 110, plating contact 162, connecting portion 166 and sealant 168, but isolate with this semiconductor chip 110, plating contact 162, connecting portion 166 and sealant 168.The thickness of this insulated substrate 182 is 200 microns.Therefore this insulated substrate 182 extends downwards from metallic walls 132, weld layer 142, coiling 150 and metal column 170, and makes this metallic walls 132, weld layer 142, coiling 150 and metal column 170 unexposed.
See also shown in Figure 24 a, Figure 24 b and Figure 24 c, be structure schematic top plan view and of the present invention insulated substrate the structure elevational schematic view remove after of structural profile schematic diagram, the of the present invention insulated substrate of insulated substrate of the present invention after removing after removing.As shown in the figure: this insulated substrate 182 be to be removed than lower part by Ginding process.Especially, a rotation diamond wheel and distilled water are used to the back side of this insulated substrate 182.At the beginning, this diamond wheel only grinds this insulated substrate 182, when continuing to grind, makes these insulated substrate 182 attenuation when upwards move on this polished surface.This diamond wheel contacts with this weld layer 142 then, grinds this weld layer 142 so open to make.When continuing to grind, when this insulated substrate 182 and weld layer 142 attenuation are simultaneously upwards moved on its polished surface.Yet this diamond wheel contacts this metallic walls 132, therefore opens to make and grinds this metallic walls 132.When continuing to grind, make this metallic walls 132, weld layer 142 and insulated substrate 182 attenuation when upwards moving on its polished surface.Continuing grinding reaches needed thickness and promptly stop grinding before touching this semiconductor chip 110, coiling 150, welding shielding 156, plating contact 162, adhesive agent 164, connecting portion 166, sealant 168 or metal column 170 up to this this metallic walls 132, weld layer 142 and insulated substrate 182, afterwards, pollutant is cleaned and removed to overall structure with distilled water.
After milled processed was intact, this metallic walls 132, weld layer 142 and insulated substrate 182 extended 70 microns downwards from this metal column 170.Therefore milled processed remove 10 micron thickness metallic walls 132 than lower part, the weld layer 142 that removes 40 micron thickness is than lower part, and removes 60 microns these insulated substrates 182 than lower part.
Behind said process, this semiconductor chip 110 still is embedded in the sealing agent 168, and this metal column 170 is embedded in this insulated substrate 182, and this coiling 150 and metal column 170 are not exposed yet, and this metallic walls 132 and weld layer are exposed.This insulated substrate 182 cover these semiconductor chips 110, plating contact 162, adhesive agent 164 and connecting portion 166 not with this semiconductor chip 110, plating contact 162, adhesive agent 164 and connecting portion 166, and extend downwards, but isolate with this semiconductor chip 110, plating contact 162, adhesive agent 164 and connecting portion 166 from this semiconductor chip 110, plating contact 162, adhesive agent 164 and connecting portion 166; And contact with this coiling 150, welding shielding 156 and metal column 170, and extend downwards from this coiling 150, welding shielding 156 and metal column 170, contact with this metallic walls 132 but with these weld layer 142 isolation.This insulated substrate 182 has part to overlap with this coiling 150, welding shielding 156, sealant 168 and metal column 170 in downward direction, yet this insulated substrate 182 no longer covers this coiling 150, welding shielding 156, sealant 168 or metal column 170 in downward direction.And this metallic walls 132, weld layer 142 and insulated substrate 182 laterally are arranged on the downward plane on one day mutually.Therefore this metallic walls 132, weld layer 142 and insulated substrate 182 are a horizontal plane that is exposed, and this plane is towards following.
See also shown in Figure 25 a, Figure 25 b and Figure 25 c, be structure schematic top plan view and of the present invention tin ball the structure elevational schematic view form after of structural profile schematic diagram, the of the present invention tin ball of tin ball of the present invention after forming after forming.As shown in the figure: originally this tin ball 184 is a no shot and is one spherical that its diameter is 300 microns, and this no shot is soaked in the flux, and provides this tin ball 184 to have the flow surface coating, and it does not have shot round this.With the overall structure reversing, make this weld layer 142 towards last, and this tin ball 184 is deposited on this weld layer 142 then.This tin ball 184 is attached on this weld layer 142 and built on the sand, because the flow surface coating of this tin ball 184.
In order to illustrate and illustrate that conveniently this tin ball 184 is plotted in this weld layer 142 belows, maintenance and the same direction of preceding figure though overall structure is put upside down, are attached to this weld layer on this tin ball 184 by gravity so that compare.
See also shown in Figure 26 a, Figure 26 b and Figure 26 c, be structure schematic top plan view and of the present invention welding ends the structure elevational schematic view form after of structural profile schematic diagram, the of the present invention welding ends of welding ends of the present invention after forming after forming.As shown in the figure: this welding ends 186 (Solder terminal) comprises this weld layer 142 and tin ball 184 and by this weld layer 142 and tin ball 184 and be formed.At first, this tin ball 184 places on this weld layer 142.Then, overall structure is heated to a temperature, and its temperature is about 260 degree.Heat the flux that causes on this tin ball 184 and produce reaction, and remove oxide, and this weld layer 142 and tin ball 184 are melted from this weld layer 142.Therefore making this weld layer 142 and tin ball 184 reflux into one is together melted the tin material mixture and is produced the backflow of tin material.And this insulated substrate 182 does not provide one can make this tin material backflow be easy to wet surface.So this tin material refluxes by this metallic walls 132 limitations.Afterwards, stop to heat and make the sclerosis of this tin material cooled and solidified of being melted form welding ends 186.In this method, this weld layer 142 and tin ball 184 are converted into welding ends 186.
Therefore this weld layer 142 and welding ends 186 are docile and obedient preface and are formed.This metallic walls 132 is plated on metal substrate 120, this tin cream 140 is deposited on the metallic walls 132 and forms this weld layer 142 when refluxing then, then this tin ball 184 is deposited on this weld layer 142, and this weld layer 142 and tin ball 184 are refluxed together and form this welding ends 186 then.
The diameter of this welding ends 186 is 400 microns, and its downward direction is 50 microns with respect to the thickness of metallic walls 132 and insulated substrate 182, and fills up this hole 134, and is arrangement vertically with this metallic walls 132, big circular portion 154 and metal column 170.
This welding ends 186 contacts and is electrically connected with it with this metallic walls 132, but non-and this metallic walls 132 integrate, and only contacts with metallic walls 132 in this metallic walls 132 and this hole 134.Therefore this welding ends 186 is isolated with this semiconductor chip 110, coiling 150, welding shielding 156, plating contact 162, adhesive agent 164, connecting portion 166, sealant 168, metal column 170 and insulated substrate 182, and extends downwards from this semiconductor chip 110, coiling 150, welding shielding 156, plating contact 162, adhesive agent 164, connecting portion 166, sealant 168, metal column 170 and insulated substrate 182.And this welding ends 186 is toward the inside and outside extension of these holes 134, and covers this metallic walls 132 and metal column 170 in downward direction, but is not covered in downward direction by any material of this semiconductor chip package.Similarly, integral parts that this welding ends 186 extends in these insulated substrates 182 only contact with this metallic walls 132, and by this metallic walls be covered in upward to, and in this hole 134.
This welding ends 186 provides a firm power contact to be connected with this metallic walls 132, and contact jaw is on external circuit.Help this welding ends 186 to extend to this metallic walls 132 in this insulated substrate 182, and can avoid opening 136 high pressure borders on a transverse plane with this contacts, this opens 136 is on the main exposed surface of this insulated substrate 182 and towards following direction, therefore can reduce the separation of tin material and promote reliability.
Via above-mentioned, this conductive trace 180 comprises metallic walls 132, coiling 150, plating contact 162, metal column 170 and welding ends 186.
In order to illustrate and illustrate that conveniently, this welding ends 186 is plotted in the below of this semiconductor chip, and keep and the comparison for convenience of preceding figure equidirectional,, when the formation of this welding ends 186, help the tin material to reflux by gravity though overall structure is put upside down.
See also shown in Figure 27 a, Figure 27 b and Figure 27 c, be semiconductor chip package generalized section of the present invention, semiconductor chip package schematic top plan view of the present invention and semiconductor chip package elevational schematic view of the present invention.As shown in the figure: comprise that through this semiconductor chip package 198 of said process semiconductor chip 110, metallic walls 132, coiling 150, welding shielding 156, plating contact 162, adhesive agent 164, connecting portion 166, sealant 168, metal column 170, insulated substrate 182 and welding ends 186 constitute.
This semiconductor chip 110 extends upward from this conductive trace 180, and with this insulated substrate 182 in upward to there being part to overlap, but not with this conductive trace 180 in upward to overlapping.Therefore this conductive trace 180 is placed in outside the edge of this semiconductor chip 110.This metallic walls 132 extends upward from this welding ends 186, and has fixed thickness, and only contacts with metal column 170, insulated substrate 182 and welding ends 186.This hole 134 is placed in this insulated substrate 182, and is filled up by this welding ends 186.It is by adhesive agent 164 that this coiling 150 mechanically is connected with this semiconductor chip 110, and to be electrically connected with this semiconductor chip 110 be by this connecting portion 166, and from this metallic walls 132, metal column 170 and welding ends 186 horizontal expansions, and towards semiconductor chip 110, this coiling 150 is smooth and is parallel to first plane 112 and second plane 114 of semiconductor chip 110.Sealing agent 168 cover these semiconductor chips 110, welding shielding 156, adhesive agent 164, connecting portion 166, conductive trace 180 and insulated substrate 182 in upward to.This metal column 170 by coiling 150 be covered in upward to, and be covered in downward direction by this metallic walls 132 and welding ends 186.Though this metal column 170 is not exposed, and having part to overlap in downward direction with this metallic walls 132, insulated substrate 182 and welding ends 186, this metal column 170 is not covered in downward direction by sealing agent 168, insulated substrate 182 or any insulation material in semiconductor die package.This insulated substrate 182 contacts with this metallic walls 132, coiling 150, welding shielding 156 and metal column 170, and extend upward, and extend downwards from semiconductor chip 110, coiling 150, welding shielding 156, connecting portion 166, sealant 168 and metal column 170 from metallic walls 132 and welding ends 186.
This metallic walls 132, metal column 170 and welding ends 186 are expanded downwards from this coiling 150, but do not cover this coiling 150 in downward direction.This metallic walls 132 is laterally revolved three-sixth turn in the integral part periphery in this welding ends 186 extends to this insulated substrate 182, and this insulated substrate 182 laterally revolves three-sixth turn around these metallic walls 132 peripheries.182 pairs of these semiconductor chip packages 198 of sealing agent 168 and insulated substrate provide mechanical support and environmental protection.
This connecting portion 166 provides the level coiling and vertically winds the line between conductive connecting pin 116 and external circuit, and horizontal output coiling (horizontal fan-out routing) this coiling 150 is provided is between conductive connecting pin 116 and external circuit, but do not provide vertical coiling, this metal column 170 and welding ends 186 provide vertical and wind the line between conductive connecting pin 116 and external circuit, but do not provide the level coiling, and this metallic walls 132 and plating contact 162 do not provide the level coiling or vertically wind the line between conductive connecting pin 116 and external circuit.Similarly, this metallic walls 132 does not provide and winds the line between welding ends 186 and any electric conductor.
This semiconductor chip package is a single-chip first a level structure dress.Therefore this semiconductor chip 110 unique chip that is this semiconductor chip package is embedded in the sealing agent 168.
This semiconductor chip package comprises other conductive trace, and is embedded in this welding shielding 156, sealant 168 and the insulated substrate 182, only draws a conductive trace 180 and make diagram and explanation conveniently in figure.Each conductive trace is isolated and tool electric power mutually.Each conductive trace all comprises metallic walls, coiling, plating contact, metal column and welding ends separately, and be electrically connected between the conductive connecting pin that makes this semiconductor chip 110 of the connecting portion by separately and conductive trace, and provide horizontal output coiling and vertical coiling to separately conductive connecting pin.And each conductive trace has a welding ends that protrudes downwards, and ball form array structure dress is provided.
This semiconductor chip 110 comprises conductive connecting pin, but isolates electrically with other part tool.Yet should corresponding coiling be plated on metal substrate at the beginning, and make between this coiling and other part by this metal substrate and to be electrically connected.And this connecting portion makes between this coiling and corresponding conductive connecting pin and is electrically connected, so this conductive connecting pin can be electrically connected with other part.Then, in case the etched formation metal column of this metal substrate, this coiling and other part tool are isolated electrically, so this conductive connecting pin and other part tool are isolated electrically.
So behind these metal substrate 120 etched formation metal columns, electroless plating bus or interlock circuit can be connected with conductive trace.
This Figure 28 a to Figure 54 c makes process second embodiment of this semiconductor chip package.In this second embodiment, after being formed on the sealing agent and being formed, this weld layer just forms.For the purpose of simplifying, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of this second embodiment is similar to first embodiment to have corresponding Ref. No., but assembly one hundred figure place assembly one hundred figure place " 1 " expression among the 1st embodiment among second embodiment with " 2 " expression, corresponding to semiconductor chip 110, coiling 250 is corresponding to the 150... etc. that winds the line as semiconductor chip 210.
See also shown in Figure 28 a, Figure 28 b and Figure 28 c, be semiconductor chip structure generalized section of the present invention, semiconductor chip structure schematic top plan view of the present invention and semiconductor chip structure elevational schematic view of the present invention.As shown in the figure: this semiconductor chip 210 comprises first plane 212 and second plane 214.This first plane 212 comprises conductive connecting pin 216 and passivation layer 218.
See also shown in Figure 29 a, Figure 29 b and Figure 29 c, be metal substrate structural profile schematic diagram of the present invention, metal substrate structure schematic top plan view of the present invention and metal substrate structure elevational schematic view of the present invention.As shown in the figure: this metal substrate 220 comprises first plane 222 and second plane 224.
See also shown in Figure 30 a, Figure 30 b and Figure 30 c, be the structure schematic top plan view of the structural profile schematic diagram of photoresist layer of the present invention and metal substrate, photoresist layer of the present invention and metal substrate and the structure elevational schematic view of photoresist layer of the present invention and metal substrate.As shown in the figure: this first photoresist layer 226 and second photoresist layer 228 are formed on this metal substrate 220.This second photoresist layer 228 comprises an opening and makes this second plane 224 local exposures, and this first photoresist layer 226 is not had a pattern.
See also shown in Figure 31 a, Figure 31 b and Figure 31 c, be the structure schematic top plan view of the structural profile schematic diagram of tool recess of the present invention, tool recess of the present invention and the structure elevational schematic view of tool recess of the present invention.As shown in the figure: this recess 230 is formed in this metal substrate 220.
See also shown in Figure 32 a, Figure 32 b and Figure 32 c, be the metal substrate structure schematic top plan view of the metal substrate structural profile schematic diagram of tool metallic walls of the present invention, tool metallic walls of the present invention and the metal substrate structure elevational schematic view of tool metallic walls of the present invention.As shown in the figure: this metallic walls 232 is formed on this metal substrate 220.
See also shown in Figure 33 a, Figure 33 b and Figure 33 c, be structure schematic top plan view and of the present invention first photoresist layer and second photoresist layer the structure elevational schematic view peel off after of first photoresist layer of the present invention and second photoresist layer structural profile schematic diagram, first photoresist layer of the present invention and second photoresist layer after peeling off after peeling off.As shown in the figure: the structural representation that is this metal substrate 220 and metallic walls 232 after first photoresist layer 226 and second photoresist layer 228 peel off.
See also shown in Figure 34 a, Figure 34 b and Figure 34 c, be formed at structure elevational schematic view after structure schematic top plan view behind the metal substrate and the 3rd photoresist layer of the present invention and the 4th photoresist layer are formed at metal substrate for the 3rd photoresist layer of the present invention and the 4th photoresist layer are formed at structural profile schematic diagram, the 3rd photoresist layer of the present invention and the 4th photoresist layer behind the metal substrate.As shown in the figure: the 3rd photoresist layer 244 and the 4th photoresist layer 246 are formed on the metal substrate 220.The 3rd photoresist layer 244 comprises an opening and makes the local expose portion of first plane, 222 tools of this metal substrate 220, and the 4th photoresist layer 246 does not have pattern.
See also shown in Figure 35 a, Figure 35 b and Figure 35 c structure elevational schematic view when the structural profile schematic diagram when investing metal substrate for coiling of the present invention, the structure schematic top plan view when coiling of the present invention invests metal substrate and coiling of the present invention invest metal substrate.As shown in the figure: this coiling 250 is by plating it to be plated on this metal substrate 220.
See also shown in Figure 36 a, Figure 36 b and Figure 36 c, be structure schematic top plan view and of the present invention three photoresist layer and four photoresist layer the structure elevational schematic view peel off after of the 3rd photoresist layer of the present invention and the 4th photoresist layer structural profile schematic diagram, the 3rd photoresist layer of the present invention and the 4th photoresist layer after peeling off after peeling off.As shown in the figure: for after the 3rd photoresist layer 244 and the 4th photoresist layer 246 peel off, this metal substrate 220, metallic walls 232 and 250 the structural representation of winding the line.
See also shown in Figure 37 a, Figure 37 b and Figure 37 c structure elevational schematic view when structure schematic top plan view when structural profile schematic diagram, the welding of the present invention when being shielded from metal substrate and coiling for welding of the present invention is shielded from metal substrate and coiling and welding of the present invention are shielded from metal substrate and coiling.As shown in the figure: this welding shielding 256 is formed on this metal substrate 220 and winds the line on 250.
See also shown in Figure 38 a, Figure 38 b and Figure 38 c, be structure schematic top plan view and of the present invention five photoresist layer and six photoresist layer the structure elevational schematic view form after of the 5th photoresist layer of the present invention and the 6th photoresist layer structural profile schematic diagram, the 5th photoresist layer of the present invention and the 6th photoresist layer after forming after forming.As shown in the figure: the 5th photoresist layer 258 and the 6th photoresist layer 260 are formed on this structure.Wherein the 5th photoresist layer 258 is formed in coiling 250 and the welding shielding 256, and the 6th photoresist layer 260 is formed on this metal substrate 220 and the metallic walls 232.The 5th photoresist layer 258 and the 6th photoresist layer 260 utilize a kind of dry type film lamination to impress respectively on corresponding plane.The 5th photoresist layer 258 comprises an opening and makes the local expose portion of these 250 tools that wind the line, and the 6th photoresist layer does not have pattern.
See also shown in Figure 39 a, Figure 39 b and Figure 39 c, be formed at structure elevational schematic view after structure schematic top plan view after the coiling and plating contact of the present invention are formed at coiling for plating contact of the present invention is formed at structural profile schematic diagram, plating contact of the present invention after the coiling.As shown in the figure: this plating contact 262 is to be plated in this coiling 250 by plating.
See also shown in Figure 40 a, Figure 40 b and Figure 40 c, be structure schematic top plan view and of the present invention five photoresist layer and six photoresist layer the structure elevational schematic view peel off after of the 5th photoresist layer of the present invention and the 6th photoresist layer structural profile schematic diagram, the 5th photoresist layer of the present invention and the 6th photoresist layer after peeling off after peeling off.As shown in the figure: be after the 5th photoresist layer 258 and the 6th photoresist layer 260 peel off, the structural representation of this metal substrate 220, metallic walls 232, coiling 250 and plating contact 262.
See also shown in Figure 41 a, Figure 41 b and Figure 41 c, be formed at structure elevational schematic view after structure schematic top plan view after the welding shielding and adhesive agent of the present invention are formed at the welding shielding for adhesive agent of the present invention is formed at structural profile schematic diagram, adhesive agent of the present invention after the welding shielding.As shown in the figure: this adhesive agent 264 is formed in this welding shielding 256.
See also shown in Figure 42 a, Figure 42 b and Figure 42 c, be the schematic top plan view of the generalized section of tool semiconductor chip structure of the present invention, tool semiconductor chip structure of the present invention and the elevational schematic view of tool semiconductor chip structure of the present invention.As shown in the figure: this semiconductor chip 210 is to be attached on the structure by this adhesive agent 264, and its structure comprises metal substrate 220, metallic walls 232, coiling 250, welding shielding 256 and plating contact 262.
See also shown in Figure 43 a, Figure 43 b and Figure 43 c structure elevational schematic view when the structural profile schematic diagram when investing conductive connecting pin and plating contact for connecting portion of the present invention, the structure schematic top plan view when connecting portion of the present invention invests conductive connecting pin and plating contact and connecting portion of the present invention invest conductive connecting pin and plating contact.As shown in the figure: this connecting portion 266 is formed on this conductive connecting pin 216 and the plating contact 262.
See also shown in Figure 44 a, Figure 44 b and Figure 44 c, be the schematic top plan view of the generalized section of tool sealant structure of the present invention, tool sealant structure of the present invention and the elevational schematic view of tool sealant structure of the present invention.As shown in the figure: sealing agent 268 is formed on semiconductor chip 210, coiling 250, welding shielding 256, plating contact 262, adhesive agent 264 and the connecting portion 266.
See also shown in Figure 45 a, Figure 45 b and Figure 45 c, for template of the present invention is covered in the structural profile schematic diagram of metal substrate, template of the present invention is covered in the structure schematic top plan view of metal substrate and the structure elevational schematic view that template of the present invention is covered in metal substrate.As shown in the figure: this template 238 is covered on this metal substrate 220.
See also shown in Figure 46 a, Figure 46 b and Figure 46 c, for tin cream of the present invention is deposited on the structural profile schematic diagram of metallic walls, tin cream of the present invention is deposited on the structure schematic top plan view of metallic walls and the structure elevational schematic view that tin cream of the present invention is deposited on metallic walls.As shown in the figure: this tin cream 240 is deposited on the metallic walls 232.
See also shown in Figure 47 a, Figure 47 b and Figure 47 c, be structural profile schematic diagram after the template, structure schematic top plan view and the structure elevational schematic view of removing after the template of removing after the template of the present invention of the present invention removed of the present invention.As shown in the figure: this template 238 removes from this metal substrate 220.
See also shown in Figure 48 a, Figure 48 b and Figure 48 c, form structure elevational schematic view after structure schematic top plan view behind the weld layer and tin cream of the present invention form weld layer for tin cream of the present invention forms structural profile schematic diagram, tin cream of the present invention behind the weld layer.As shown in the figure: this weld layer 242 is formed by this tin cream 240.This metallic walls 232 provides a wet surface that this tin material is flowed easily, yet this metal substrate 220 does not provide.Therefore this tin material only flows in this metallic walls 232.
See also shown in Figure 49 a, Figure 49 b and Figure 49 c, be structural profile schematic diagram, of the present invention metal column structure schematic top plan view and of the present invention metal column the structure elevational schematic view in metal substrate on form after in metal substrate on form after of metal column of the present invention after forming on the metal substrate.As shown in the figure: this metal column 270 is formed by this metal substrate 220.
See also shown in Figure 50 a, Figure 50 b and Figure 50 c, be structure schematic top plan view and of the present invention insulated substrate the structure elevational schematic view form after of structural profile schematic diagram, the of the present invention insulated substrate of insulated substrate of the present invention after forming after forming.As shown in the figure: this insulated substrate 282 is formed on metallic walls 232, weld layer 242, coiling 250, welding shielding 256 and the metal column 270.
See also shown in Figure 51 a, Figure 51 b and Figure 51 c, be structure schematic top plan view and of the present invention SI semi-insulation substrate the structure elevational schematic view remove after of structural profile schematic diagram, the of the present invention SI semi-insulation substrate of SI semi-insulation substrate of the present invention after removing after removing.As shown in the figure: be the structural representation after SI semi-insulation substrate 282 is removed.
See also shown in Figure 52 a, Figure 52 b and Figure 52 c, be structure schematic top plan view and of the present invention tin ball the structure elevational schematic view form after of structural profile schematic diagram, the of the present invention tin ball of tin ball of the present invention after forming after forming.As shown in the figure: this tin ball 284 is formed on the weld layer 242.
See also shown in Figure 53 a, Figure 53 b and Figure 53 c, be structure schematic top plan view and of the present invention welding ends the structure elevational schematic view form after of structural profile schematic diagram, the of the present invention welding ends of welding ends of the present invention after forming after forming.As shown in the figure: this welding ends 286 is formed by weld layer 242 and tin ball 284.
See also shown in Figure 54 a, Figure 54 b and Figure 54 c, be semiconductor chip package generalized section of the present invention, semiconductor chip package schematic top plan view of the present invention and semiconductor chip package elevational schematic view of the present invention.As shown in the figure: utilize a blade should weld shielding 256, sealant 268 and insulated substrate 282 and cut into semiconductor die package.This semiconductor chip package 298 comprises semiconductor chip 210, metallic walls 232, coiling 250, welding shielding 256, plating contact 262, adhesive agent 264, connecting portion 266, sealant 268, metal column 270, insulated substrate 282 and welding ends 286.
From Figure 55 a to Figure 81 c is the third embodiment of the present invention, is the manufacturing process of this semiconductor chip package.With preceding embodiment comparison this metallic walls and weld layer in the 3rd embodiment be after sealant forms, just to form, and remove metal column less.
See also shown in Figure 55 a, Figure 55 b and Figure 55 c, be semiconductor chip structure generalized section of the present invention, semiconductor chip structure schematic top plan view of the present invention and semiconductor chip structure elevational schematic view of the present invention.As shown in the figure: this semiconductor chip 310 comprises first plane 312 and second plane 314.This first plane 312 comprises conductive connecting pin 316 and passivation layer 318.
See also shown in Figure 56 a, Figure 56 b and Figure 56 c, be metal substrate structural profile schematic diagram of the present invention, metal substrate structure schematic top plan view of the present invention and metal substrate structure elevational schematic view of the present invention.As shown in the figure: this metal substrate 320 comprises first plane 322 and second plane 324.
See also shown in Figure 57 a, Figure 57 b and Figure 57 c, be the structure schematic top plan view of the structural profile schematic diagram of photoresist layer of the present invention and metal substrate, photoresist layer of the present invention and metal substrate and the structure elevational schematic view of photoresist layer of the present invention and metal substrate.As shown in the figure: the 3rd photoresist layer 344 and the 4th photoresist layer 346 are formed on this metal substrate 320.The 4th photoresist layer 346 comprises an opening and makes this first plane, 322 local exposures, and the 3rd photoresist layer 344 is not printed on pattern.
See also shown in Figure 58 a, Figure 58 b and Figure 58 c structure elevational schematic view when the structural profile schematic diagram when investing metal substrate for coiling of the present invention, the structure schematic top plan view when coiling of the present invention invests metal substrate and coiling of the present invention invest metal substrate.As shown in the figure: this coiling 350 is by plating it to be plated on this metal substrate 320.
See also shown in Figure 59 a, Figure 59 b and Figure 59 c, be structure schematic top plan view and of the present invention three photoresist layer and four photoresist layer the structure elevational schematic view peel off after of the 3rd photoresist layer of the present invention and the 4th photoresist layer structural profile schematic diagram, the 3rd photoresist layer of the present invention and the 4th photoresist layer after peeling off after peeling off.As shown in the figure: for after the 3rd photoresist layer 344 and the 4th photoresist layer 346 peel off, this metal substrate 320 and 350 the structural representation of winding the line.
See also shown in Figure 60 a, Figure 60 b and Figure 60 c structure elevational schematic view when structure schematic top plan view when structural profile schematic diagram, the welding of the present invention when being shielded from metal substrate and coiling for welding of the present invention is shielded from metal substrate and coiling and welding of the present invention are shielded from metal substrate and coiling.As shown in the figure: this welding shielding 356 is formed on this metal substrate 320 and winds the line on 350.
See also shown in Figure 61 a, Figure 61 b and Figure 61 c, be structure schematic top plan view and of the present invention five photoresist layer and six photoresist layer the structure elevational schematic view form after of the 5th photoresist layer of the present invention and the 6th photoresist layer structural profile schematic diagram, the 5th photoresist layer of the present invention and the 6th photoresist layer after forming after forming.As shown in the figure: the 5th photoresist layer 358 and the 6th photoresist layer 360 are formed on this structure.Wherein the 5th photoresist layer 358 is formed in coiling 350 and the welding shielding 356, and the 6th photoresist layer 360 is formed on this metal substrate 320.The 5th photoresist layer 358 comprises an opening and makes the local expose portion of these 350 tools that wind the line, and the 6th photoresist layer is not printed on pattern.
See also shown in Figure 62 a, Figure 62 b and Figure 62 c, be formed at structure elevational schematic view after structure schematic top plan view after the coiling and plating contact of the present invention are formed at coiling for plating contact of the present invention is formed at structural profile schematic diagram, plating contact of the present invention after the coiling.As shown in the figure: this plating contact 362 is to be plated in this coiling 350 by plating.
See also shown in Figure 63 a, Figure 63 b and Figure 63 c, be structure schematic top plan view and of the present invention five photoresist layer and six photoresist layer the structure elevational schematic view peel off after of the 5th photoresist layer of the present invention and the 6th photoresist layer structural profile schematic diagram, the 5th photoresist layer of the present invention and the 6th photoresist layer after peeling off after peeling off.As shown in the figure: be after the 5th photoresist layer 358 and the 6th photoresist layer 360 peel off, the structural representation of this metal substrate 320, coiling 350 and plating contact 362.
See also shown in Figure 64 a, Figure 64 b and Figure 64 c, be formed at structure elevational schematic view after structure schematic top plan view after the welding shielding and adhesive agent of the present invention are formed at the welding shielding for adhesive agent of the present invention is formed at structural profile schematic diagram, adhesive agent of the present invention after the welding shielding.As shown in the figure: this adhesive agent 364 is formed in this welding shielding 356.
See also shown in Figure 65 a, Figure 65 b and Figure 65 c, be the schematic top plan view of the generalized section of tool semiconductor chip structure of the present invention, tool semiconductor chip structure of the present invention and the elevational schematic view of tool semiconductor chip structure of the present invention.As shown in the figure: this semiconductor chip 310 is to be attached on the structure by this adhesive agent 364, and its structure comprises metal substrate 320, coiling 350, welding shielding 356 and plating contact 362.
See also shown in Figure 66 a, Figure 66 b and Figure 66 c structure elevational schematic view when the structural profile schematic diagram when investing conductive connecting pin and plating contact for connecting portion of the present invention, the structure schematic top plan view when connecting portion of the present invention invests conductive connecting pin and plating contact and connecting portion of the present invention invest conductive connecting pin and plating contact.As shown in the figure: this connecting portion 366 is formed on this conductive connecting pin 316 and the plating contact 362.
See also shown in Figure 67 a, Figure 67 b and Figure 67 c, be the schematic top plan view of the generalized section of tool sealant structure of the present invention, tool sealant structure of the present invention and the elevational schematic view of tool sealant structure of the present invention.As shown in the figure: sealing agent 368 is formed on semiconductor chip 310, coiling 350, welding shielding 356, plating contact 362, adhesive agent 364 and the connecting portion 366.
See also shown in Figure 68 a, Figure 68 b and Figure 68 c, for second photoresist layer of the present invention is formed at the structural profile schematic diagram of metal substrate, second photoresist layer of the present invention is formed at the structure schematic top plan view of metal substrate and the structure elevational schematic view that second photoresist layer of the present invention is formed at metal substrate.As shown in the figure: this 328 is formed on this metal substrate 320.This second photoresist layer 328 comprises an opening, and its opening diameter is 200 microns and makes this second plane, 324 local exposures.
See also shown in Figure 69 a, Figure 69 b and Figure 69 c, be the structure schematic top plan view of the structural profile schematic diagram of tool recess of the present invention, tool recess of the present invention and the structure elevational schematic view of tool recess of the present invention.As shown in the figure: this perforation 330 is for passing this metal substrate 320.This perforation 330 is carried out etching by chemical etching liquor to the second main plane, the 324 local expose portions of this metal substrate 320, and utilizes this second photoresist layer 328 to be its etch shield.This bottom nozzle sprays chemical etching liquor on metal substrate 320; when top jet nozzle is not used or overall architecture when being dipped in chemical etching liquor; and sealing agent 368 can be protected the front side, and this chemical etching liquor is the copper of high selectivity, and these metal substrate 320 etchings are penetrated.So this perforation 330 penetrates this metal substrate 320, it and exposes this coiling 350 between first plane 322 and second plane 324 of this metal substrate 320.The diameter of this perforation 330 on first plane 322 is 300 microns, and its degree of depth is 150 microns.Therefore, this perforation is 330 identical with the recess 130 formation methods of first embodiment, uses time except this chemical etching and grows and make these metal substrate 320 etchings penetrate.A kind of suitable chemical etching liquor is the ammoniacal liquor of alkalescence.Must repetition test with the desirable etching period that this metal substrate 320 is dipped in the chemical etching liquor, for the perforation 330 that forms the suitable diameter of tool.
See also shown in Figure 70 a, Figure 70 b and Figure 70 c, be the structure schematic top plan view of the structural profile schematic diagram of tool metallic walls of the present invention, tool metallic walls of the present invention and the structure elevational schematic view of tool metallic walls of the present invention.As shown in the figure: this metallic walls 332 is formed on this metal substrate 320 and winds the line on 350.This metallic walls 332 in recess 330 with being connected of this metal substrate 320 and the 350 tool electric power that wind the line, but non-integral and this metal substrate 320 and winding the line 350 engages.
See also shown in Figure 71 a, Figure 71 b and Figure 71 c, for template of the present invention is covered in the structural profile schematic diagram of second photoresist layer, template of the present invention is covered in the structure schematic top plan view of second photoresist layer and the structure elevational schematic view that template of the present invention is covered in second photoresist layer.As shown in the figure: this template 338 is covered on this second photoresist layer 328.
See also shown in Figure 72 a, Figure 72 b and Figure 72 c, for tin cream of the present invention is deposited on the structural profile schematic diagram of metallic walls, tin cream of the present invention is deposited on the structure schematic top plan view of metallic walls and the structure elevational schematic view that tin cream of the present invention is deposited on metallic walls.As shown in the figure: this tin cream 340 is deposited on the metallic walls 332.
See also shown in Figure 73 a, Figure 73 b and Figure 73 c, be structural profile schematic diagram after the template, structure schematic top plan view and the structure elevational schematic view of removing after the template of removing after the template of the present invention of the present invention removed of the present invention.As shown in the figure: this template 338 removes from this second photoresist layer 328.
See also shown in Figure 74 a, Figure 74 b and Figure 74 c, form structure elevational schematic view after structure schematic top plan view behind the weld layer and tin cream of the present invention form weld layer for tin cream of the present invention forms structural profile schematic diagram, tin cream of the present invention behind the weld layer.As shown in the figure: this weld layer 342 is formed by this tin cream 340.
See also shown in Figure 75 a, Figure 75 b and Figure 75 c, be structure schematic top plan view and of the present invention second photoresist layer the structure elevational schematic view peel off after of structural profile schematic diagram, of the present invention second photoresist layer of second photoresist layer of the present invention after peeling off after peeling off.As shown in the figure: be after second photoresist layer 328 peels off, the structural representation of this semiconductor chip 310, metal substrate 320, metallic walls 332, weld layer 342, coiling 350, plating contact 362, adhesive agent 364, connecting portion 366 and sealant 368.
See also shown in Figure 76 a, Figure 76 b and Figure 76 c, be structure schematic top plan view and of the present invention metal substrate the structure elevational schematic view remove after of structural profile schematic diagram, the of the present invention metal substrate of metal substrate of the present invention after removing after removing.As shown in the figure: this metal substrate 320 carries out etching by a kind of back of the body limit rotating vane type chemical etching liquor to this second main plane 324, metallic walls 332 and weld layer 342.As this bottom nozzle chemical etching liquor is sprayed on metal substrate 320; when top jet nozzle is not used or overall architecture when being dipped in chemical etching liquor; and sealing agent 368 can be protected the front side; when copper is suitable for this wet chemical etch during to nickel, tin material, epoxy resin and injection molded material; so, adopt this wet chemical etch when the nickel dam of 320 pairs of these metallic walls 332 of this metal substrate, weld layer 342, this coiling 350, welding shielding 356 and sealant 368.
This wet chemical etch is with this metal substrate etching and remove.So this wet chemical etch removes this metallic walls 332, coiling 350 and welding shielding 356 and 320 zones that contacted of this metal substrate.
Therefore, it is identical with the method for the metal substrate 120 etched formation metal columns 170 of first embodiment that this metal substrate 320 is removed, except long making these metal substrate 320 etchings remove of time used in this chemical etching.A kind of suitable chemical etching liquor is the ammoniacal liquor of alkalescence.Must repetition test with the desirable etching period that this metal substrate 320 is dipped in the chemical etching liquor, for removable this metal substrate 320 but do not make this metallic walls 332 and wind the line and 350 be exposed in the chemical etching liquor.
See also shown in Figure 77 a, Figure 77 b and Figure 77 c, be structure schematic top plan view and of the present invention insulated substrate the structure elevational schematic view form after of structural profile schematic diagram, the of the present invention insulated substrate of insulated substrate of the present invention after forming after forming.As shown in the figure: this insulated substrate 382 is formed in metallic walls 332, weld layer 342, coiling 350 and the welding shielding 356.
See also shown in Figure 78 a, Figure 78 b and Figure 78 c, be structure schematic top plan view and of the present invention SI semi-insulation substrate the structure elevational schematic view remove after of structural profile schematic diagram, the of the present invention SI semi-insulation substrate of SI semi-insulation substrate of the present invention after removing after removing.As shown in the figure: be the structural representation after SI semi-insulation substrate 382 is removed.
See also shown in Figure 79 a, Figure 79 b and Figure 79 c, be structure schematic top plan view and of the present invention tin ball the structure elevational schematic view form after of structural profile schematic diagram, the of the present invention tin ball of tin ball of the present invention after forming after forming.As shown in the figure: this tin ball 384 is formed on the weld layer 342.
See also shown in Figure 80 a, Figure 80 b and Figure 80 c, be structure schematic top plan view and of the present invention welding ends the structure elevational schematic view form after of structural profile schematic diagram, the of the present invention welding ends of welding ends of the present invention after forming after forming.As shown in the figure: this welding ends 386 is formed by weld layer 342 and tin ball 384.
See also shown in Figure 81 a, Figure 81 b and Figure 81 c, be semiconductor chip package generalized section of the present invention, semiconductor chip package schematic top plan view of the present invention and semiconductor chip package elevational schematic view of the present invention.As shown in the figure: 332 of this metallic walls engage with coiling 350, insulated substrate 382 and weld layer 386, and this semiconductor chip package does not have metal column.This semiconductor chip package 398 comprises semiconductor chip 310, metallic walls 332, coiling 350, welding shielding 356, plating contact 362, adhesive agent 364, connecting portion 366, sealant 368, insulated substrate 382 and welding ends 386.
See also shown in Figure 82 a, Figure 82 b and Figure 82 c, be the semiconductor chip package generalized section of the fourth embodiment of the present invention, the semiconductor chip package schematic top plan view of the fourth embodiment of the present invention and the semiconductor chip package elevational schematic view of the fourth embodiment of the present invention.As shown in the figure: in the 4th embodiment, this semiconductor chip is chip bonding.At first this connecting portion 466 is that a solder bump (a solder bump) is deposited on this conductive connecting pin 416, and this solder bump is a hemisphere, and its diameter is 100 microns.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the 4th embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 450 is corresponding to coiling 150... etc. as semiconductor chip 410.
This coiling 450 extending around this semiconductor chip 410.Therefore this microscler winding portion (with respect to assembly label 152 among first embodiment) extends.Further adjust the coiling 150 among first embodiment through plating formation.Therefore especially, the 3rd photoresist layer (with respect to the 3rd photoresist layer 144 of first embodiment) has pattern and forms one again and is opened in the coiling 450, and the coiling 150 of this coiling 450 to the first embodiment becomes longer.This plating contact (with respect to the plating contact 162 of first embodiment) is omitted.
First plane 412 of this semiconductor chip 410 faces down, and its second plane 412 is towards last, and this coiling 450 is to side extend past conductive connecting pin 416, this connecting portion 466 between conductive connecting pin 416 with wind the line between 450 and be in contact with it.Heat then and this connecting portion 466 is produced flow, stop to heat the pad that makes these connecting portion 466 cooled and solidified form a sclerosis and can be attached to this conductive connecting pin 416 and wind the line 450 and make this conductive connecting pin 416 and 450 electrical connections that wind the line.This connecting portion 466 has locality wetting but be unlikely and collapse, and this semiconductor chip 410 is isolated with this coiling 450.
Afterwards, this adhesive agent 464 is inserted between semiconductor chip 410 and the welding shielding 456, makes this adhesive agent 464 sclerosis then.So this adhesive agent 464 is sandwiched in semiconductor chip 410 and 456 of welding shieldings and shields 456 with this semiconductor chip 410 and welding and engages, and also engages with this connecting portion 466, does not contact with this conductive connecting pin 416.Therefore the adhesive agent 164 of this adhesive agent 464 and first embodiment is thicker.A kind of suitable adhesive agent is Namics U8443.
Sealing agent 468, metal column 470, insulated substrate 482 and welding ends 486 are formed.
This semiconductor chip package 498 comprises semiconductor chip 410, metallic walls 432, coiling 450, welding shielding 456, adhesive agent 464, connecting portion 466, sealant 468, metal column 470, insulated substrate 482 and welding ends 486.
See also shown in Figure 83 a, Figure 83 b and Figure 83 c, be the semiconductor chip package generalized section of the fifth embodiment of the present invention, the semiconductor chip package schematic top plan view of the fifth embodiment of the present invention and the semiconductor chip package elevational schematic view of the fifth embodiment of the present invention.As shown in the figure: in the 5th embodiment, this connecting portion forms through electroplating.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the 5th embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 550 is corresponding to coiling 150... etc. as semiconductor chip 510.
This conductive connecting pin 516 can hold the connecting portion of an electro-coppering, is by forming a nickel surface layer on this aluminium base.Be soaked in a zinc solution as this semiconductor chip 510, a zinc layer is deposited on the aluminium base.This method is zinc impregnation (zincation).This zinc solution comprises the NaOH of 150 gram/litres, the zinc oxide of 25 gram/litres and the natrium nitrosum of 1 gram/litre, can reduce the decomposition rate of this aluminium base just as tartaric acid.This nickel surface layer does not have the aluminium base that is deposited on through zinc impregnation electricly then.A kind of suitable electroless nickel plating solution is the Enthone Enplate NI-424 under 85 degree Celsius.
This coiling 550 is to be to reach outside the edge in the edge of this semiconductor chip 510 to extend.Therefore this microscler winding portion (execute with respect to first o'clock in the example microscler winding portion 152) becomes longer, be by for coiling among first embodiment by electroplating the processing procedure do adjustment slightly that forms.The 3rd photoresist layer (execute with respect to first o'clock in the example the 3rd photoresist layer 144) is printed on pattern and forms one again and is opened on coiling 550, makes the coiling 150 among this coiling 550 to the first embodiment become longer.
The etched formation one second dorsal part recess (not shown) of this metal substrate (execute with respect to first o'clock in the example metal substrate 120), this plating contact (execute with respect to first o'clock in the example plating contact 162) is deleted, and this adhesive agent 564 is deposited in this coiling 550 and the welding shielding 556.
This semiconductor chip 510 is by upside-down mounting, wherein this first plane 512 towards the below and this second plane 514 towards last, this adhesive agent 564 and this conductive connecting pin 516 and winding the line 550 contacts, and be sandwiched in this conductive connecting pin 516 and the coiling 550, and 550 contact mutually with coiling with this conductive connecting pin 516, in this conductive connecting pin 516 and 550 thickness of coiling is 5 microns, and this coiling 550 has the part overlapping with conductive connecting pin 516.Then, sealing agent 568 is formed, and this second dorsal part recess of the etched again conversion of this metal substrate is a slit (slot) (not shown) then, and this slit extension also penetrates this metal substrate, this welding shielding 556 is exposed, and be vertical arrangement with this conductive connecting pin 516.
Then, this perforation 565 (through-hole) is formed in this welding shielding 556 and the adhesive agent 564, and this conductive connecting pin 516 is exposed.When this welding shielding 556 and 564 pairs of these conductive connecting pins 516 of adhesive agent and wind the line and adopt suitable engraving method to form perforation 565 550 the time.In this embodiment, select a kind of a TEA CO for use 2The laser-induced thermal etching method.This laser is to point to this conductive connecting pin 516, and in these conductive connecting pin 516 vertical alignments and concentrate on this conductive connecting pin 516.This laser has a luminous point, and its size is 70 microns, and the length of this conductive connecting pin 516 and width are 100 microns.The coiling 550 of this conductive connecting pin 516 of this laser hits and part, this welding shielding 556 and adhesive agent 564 are to extend in the edge of this conductive connecting pin 516, and melt this welding shielding 556 and adhesive agent 564.This laser drills the welding shielding 556 and the adhesive agent 564 of this part, and removes the welding shielding 556 and the adhesive agent 564 of part.Yet the edge of the welding of part shielding 556 and this conductive connecting pin 516 of adhesive agent 564 extend pasts, but outside the scope that this laser can contact.Similarly, this coiling 550 can be protected the adhesive agent 564 of a part in laser-induced thermal etching, and this a part of adhesive agent 564 is sandwiched in this conductive connecting pin 516 and winds the line between 550 and be bonded with each other.This laser-induced thermal etching anisotropic is removed between 550 or excises so there is the adhesive agent 564 of fraction to be sandwiched in conductive connecting pin 516 and to wind the line.This is worn mouthfuls 565 and can excise slightly in the adhesive agent 564 of this conductive connecting pin 516 with 550 of coilings, because of the temperature of the angle of this laser beam, laser and plasma oxygen etc. tropism or chemical cleaning mode, make this diameter of wearing mouth 565 be a bit larger tham 70 microns.For convenience of description, there are a little cutting and expansion to be omitted.The formation of this recess 565 to this semiconductor chip 510 or the 550 generation infringements that wind the line, does not also extend to this semiconductor chip 510 inside then.
Utilize brief cleaning step to make this conductive connecting pin 516 then and wind the line removable oxide of 550 exposed portions and fragment.Be applied on the structure as a kind of brief plasma oxygen cleaning method, perhaps select a kind of brief chemical cleaning method of tool liquor potassic permanganate that utilizes to be applied on the structure.Above-mentioned cleaning method all can clean the conductive connecting pin 516 and 550 exposed portions that wind the line, and does not damage overall structure.
This connecting portion 566 is to be formed by plating, and at first this metal substrate is connected to a plating bus (not shown), and this plating bus uses external power source, and overall structure is dipped in a cathode copper electroplating solution, and its solution is as in the Sel-Rex of room temperature CUBATH M TMSo this connecting portion 566 is plated on this metal substrate exposed portions.Provide electric current to metal substrate from this plating bus in addition, so this metal substrate will provide electric current to coiling 550, this connecting portion 566 is plated on coiling 550 exposed portions in the perforation 565.In this stage at the beginning, be an insulator from this adhesive agent 564, and this conductive connecting pin 516 is not connected with plating bus, this connecting portion 566 is not plated on the conductive connecting pin 516, and isolates with this conductive connecting pin 516.Yet when continuing to carry out the copper plating, this connecting portion 566 continues to be plated in the coiling 550, and penetrates toward adhesive agent 564 extensions, contacts with this conductive connecting pin 516 at last.It is by this metal substrate, coiling 550 and connecting portion 566 that this conductive connecting pin 516 is connected to this plating bus, so these connecting portion 566 beginnings can be plated on the conductive connecting pin 516.Continue to carry out the copper plating and reach needed thickness up to this connecting portion 566.Then overall structure is shifted out from the cathode copper electroplating solution, and clean the removal pollutant with distilled water.
Then this insulating plug 569 (insulative plug) is formed on welding shielding 556 and the connecting portion 566, and is deposited in the slit, this metallic walls 570 then, and insulated substrate 582 and welding ends 586 are formed.
This semiconductor chip package 598 comprises semiconductor chip 510, metallic walls 532, coiling 550, welding shielding 556, adhesive agent 564, connecting portion 566, sealant 568, insulating plug 569, metal column 570, insulated substrate 582 and welding ends 586.
See also shown in Figure 84 a, Figure 84 b and Figure 84 c, be the semiconductor chip package generalized section of the sixth embodiment of the present invention, the semiconductor chip package schematic top plan view of the sixth embodiment of the present invention and the semiconductor chip package elevational schematic view of the sixth embodiment of the present invention.As shown in the figure: this connecting portion is an electroless-plating in the 6th embodiment.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the 6th embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 650 is corresponding to coiling 150... etc. as semiconductor chip 610.
This conductive connecting pin 616 comprises a nickel dam, identical with the conductive connecting pin 516 formation methods among the 5th embodiment, this coiling 650 is identical with coiling 550 formation methods among the 5th embodiment, this adhesive agent 664 is deposited on coiling 650 and welding shielding 656 and adhesive agent 564 among the 5th embodiment and is deposited on coiling 550 and welding to shield 556 formation methods identical, and this plating contact (with respect to the plating contact among first embodiment 162) is omitted.
This semiconductor chip 610 is by upside-down mounting, wherein this first plane 612 in the below and this second plane 614 in the top, this adhesive agent 664 is between this conductive connecting pin 616 and coiling 650, and 550 contact mutually with coiling with this conductive connecting pin 516, thickness therebetween is 5 microns, and this coiling 650 has part to overlap with conductive connecting pin 616.Then, sealing agent 668 is formed, then etched formation one metal column 670 of this metal substrate.Then, this perforation 656 is formed in this welding shielding 656 and the adhesive agent 664, and this conductive connecting pin 616 is exposed.This perforation 665 is identical with recess 565 formation methods among the 5th embodiment.
Then, this connecting portion 666 is to be formed by plating.Overall structure is dipped in an electrolytic nickel electroplating solution, its solution as in Celsius 85 the degree Enthone EnplateNI-424.The electrolytic nickel electroplating solution comprises nickelous sulfate (nickel-sulfate) and nickel chloride (nickel-chloride) preferably, and the pH value of its solution is approximately between 9.5 to 10.5.The electrolytic nickel electroplating solution of tool high concentration is accelerated rate of deposition (a faster plating rate), but reduces the stability of this solution.Chelating of tool some in this solution (chelating agents) or ligand (ligands) are according to the concentration of nickel and their chemical constitution, functional and equivalent.It is organic carboxylic acid (hydroxyorganic acids) that most chelating is used to electroless nickel plating solution, forms one or more water-soluble nickel annular compound thing.Above-mentioned compound reduces the free radical nickel ion concentration, therefore increases the stability of this solution, and possesses rate of deposition fast.In general, this complexing agent has high concentration, and reduces rate of deposition.When continuing to carry out electroless-plating, the pH value and the rate of deposition of this solution continue to successively decrease in addition, are injected into the accessory substance that reduces for nickel in this solution owing to hydroxyl ion.So this solution is cushioned and compensates the influence that is subjected to this hydroxyl ion.Sodium (sodium) salt that suitable reducing comprises monatomic (mono) or the organic acid of potassium (potassium) salt and binary (dibasic organic acids).At last, by above-mentioned process as can be known this electroless nickel plating solution can not deposit pure element nickel, because of reducing agent (reducing agent) as H 2PO 2To decompose naturally in the process of electroless-plating nickel.So in the above-mentioned process of learning electroless-plating nickel, the compound of this nickel is almost nickel but is not pure element nickel.
This conductive connecting pin 616 comprises a nickel surface layer that is exposed, so this conductive connecting pin 616 has haptoreaction with electroless nickel.And this welding shielding 656, adhesive agent 664 and sealant 668 do not have haptoreaction with this electroless nickel, electroplates shielding so must not use.This connecting portion 666 is plated on the conductive connecting pin 616, and with this conductive connecting pin 616 and in perforation 665 coiling 650 contact, and make this conductive connecting pin 616 and 650 electrical connections that in perforation 665, wind the line.Be about 10 microns when continuing to carry out the electroless nickel plating processing up to the thickness of this connecting portion 666.Overall architecture shifts out from electroless nickel plating solutions then, and cleans with distilled water.
Then, this insulated substrate 682 and welding ends 686 are formed.
This semiconductor chip package 698 comprises semiconductor chip 610, metallic walls 632, coiling 650, welding shielding 656, adhesive agent 664, connecting portion 666, sealant 668, metal column 670, insulated substrate 682 and welding ends 686.
See also shown in Figure 85 a, Figure 85 b and Figure 85 c, be the semiconductor chip package generalized section of the seventh embodiment of the present invention, the semiconductor chip package schematic top plan view of the seventh embodiment of the present invention and the semiconductor chip package elevational schematic view of the seventh embodiment of the present invention.As shown in the figure: in the 7th embodiment, this weld layer provides this welding ends.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the 7th embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 750 is corresponding to coiling 150... etc. as semiconductor chip 710.
This tin ball (with respect to the tin ball 184 among first embodiment) is omitted, so this weld layer (with respect to the weld layer among first embodiment 142) provides this welding ends 786.This welding ends 786 is placed in the hole 734, and this metallic walls 732, insulated substrate 782 and welding ends 786 laterally are arranged on the downward plane on one day mutually.Therefore a horizontal plane that exposes is towards down, and comprises metallic walls 732, insulated substrate 782 and welding ends 786.And each conductive trace comprises a transversely arranged welding ends one planar lattice array structure dress is provided.
This semiconductor chip package 798 comprises semiconductor chip 710, metallic walls 732, coiling 750, welding shielding 756, plating contact 762, adhesive agent 764, connecting portion 766, sealant 768, metal column 770, insulated substrate 782 and welding ends 786.
See also shown in Figure 86 a, Figure 86 b and Figure 86 c, be the semiconductor chip package generalized section of the eighth embodiment of the present invention, the semiconductor chip package schematic top plan view of the eighth embodiment of the present invention and the semiconductor chip package elevational schematic view of the eighth embodiment of the present invention.As shown in the figure: in the 8th embodiment, utilize laser disappear molten (laser ablation) this insulated substrate is partly removed.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the 6th embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 650 is corresponding to coiling 150... etc. as semiconductor chip 610.
This insulated substrate 882 is formed when not using filler (filler).So this metal substrate 882 is more responsive than the metal substrate among first embodiment 182 when laser-induced thermal etching.And milled processed is deleted, with tool TEA CO optionally 2The laser-induced thermal etching replacement also utilizes compound laser direct-writing head.Directed this weld layer of this laser (with respect to the weld layer 142 of first embodiment).The luminous point size of this laser is 100 microns.And this laser direct-writing head (laser direct writes) mutually skew overlap as yet, make the core of this laser scanning weld layer, its sweep diameter is 150 microns.In this method, this laser direct-writing head (laserdirect writes) is vertically to be arranged and concentrates on metallic walls 832, metal column 870 and the weld layer.So this laser light is hit this weld layer, and the part of etching insulated substrate 882 and weld layer overlapping, and molten this insulated substrate 882 that disappears.
This laser drills and removes the insulated substrate 882 of part.The insulated substrate 882 of a part extends and passes the edge of this weld layer then, but outside by the scope of laser hits.Therefore, this insulated substrate 882 still contacts with this weld layer and overlaps, but no longer is covered on this weld layer.
Then utilize brief cleaning step to make removable oxide of this weld layer exposed portions and fragment.Be applied on the structure as a kind of brief plasma oxygen cleaning method, perhaps select a kind of brief chemical cleaning method of tool liquor potassic permanganate that utilizes to be applied on the structure.Above-mentioned cleaning method all can clean the weld layer exposed portions, does not damage overall structure.
This opening 883 is formed on this insulated substrate 882, and extend perpendicularly to this insulated substrate 882 but do not penetrate this insulated substrate 882, and be placed in the edge of this semiconductor chip 810, and be arrangement vertically with metallic walls 832, metal column 870 and weld layer, this opening 883 exposes this weld layer, and separate with this metallic walls 832, coiling 850, welding shielding 856 and metal column 870, the diameter of this opening 883 is 150 microns.The formation of this opening 883 does not cause damage to weld layer or extends in this weld layer.
The diameter of this opening 883 has and is a bit larger tham 150 microns, owing to angle, laser temperature and the plasma oxygen of this laser beam etc. tropism or chemical cleaning method.For convenience of description, wherein having a little, expansion omits.
Then this welding ends 886 is formed.This welding ends 886 is in the inside of this this opening 883 and outside the extension, and fills up this opening 883, and extends downwards from this insulated substrate 882.Though the integral part that this welding ends 886 extends in this insulated substrate 882 is in the surf zone of this hole 834.
This semiconductor chip package 898 comprises semiconductor chip 810, metallic walls 832, coiling 850, welding shielding 856, plating contact 862, adhesive agent 864, connecting portion 866, sealant 868, metal column 870, insulated substrate 882 and welding ends 886.
See also shown in Figure 87 a, Figure 87 b and Figure 87 c, be the semiconductor chip package generalized section of the ninth embodiment of the present invention, the semiconductor chip package schematic top plan view of the ninth embodiment of the present invention and the semiconductor chip package elevational schematic view of the ninth embodiment of the present invention.As shown in the figure: in the 9th embodiment, utilize plasma etching that this insulated substrate is partly removed.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the 9th embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 950 is corresponding to coiling 150... etc. as semiconductor chip 910.
This insulated substrate 982 is formed when not using filler (filler).So this metal substrate 982 is more responsive and process of lapping is omitted than the metal substrate among first embodiment 182 when laser-induced thermal etching, further replaces and be applied in the structure with code-pattern back of the body limit formula plasma etching.When epoxy resin adopts plasma etching during to nickel and tin material, thus when 982 pairs of metallic walls 932 of this insulated substrate and welding ends 986 the employing plasma etching.This plasma etching can be from the thickness removable 80 microns than lower part of insulated substrate 982.So this metallic walls 932 and welding ends 986 extend from insulated substrate 982, and make this insulated substrate 982 downwards by recessed, with respect to metallic walls 932 and welding ends 956 in downward direction.And this insulated substrate 982 expands downwards from this metal column 970, and this metal column 970 is unexposed.
This semiconductor chip package 998 comprises semiconductor chip 910, metallic walls 932, coiling 950, welding shielding 956, plating contact 962, adhesive agent 964, connecting portion 966, sealant 968, metal column 970, insulated substrate 982 and welding ends 986.
See also shown in Figure 88 a, Figure 88 b and Figure 88 c, be the semiconductor chip package generalized section of the tenth embodiment of the present invention, the semiconductor chip package schematic top plan view of the tenth embodiment of the present invention and the semiconductor chip package elevational schematic view of the tenth embodiment of the present invention.As shown in the figure: in the tenth embodiment, do not have insulated substrate.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the tenth embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 1050 is corresponding to coiling 150... etc. as semiconductor chip 1010.
This insulated substrate (with respect to the insulated substrate among first embodiment 182) is deleted, so do not need to grind in present embodiment.
This semiconductor chip package 1098 comprises semiconductor chip 1010, metallic walls 1032, coiling 1050, welding shielding 1056, plating contact 1062, adhesive agent 1064, connecting portion 1066, sealant 1068, metal column 1070 and welding ends 1086.
See also shown in Figure 89 a, Figure 89 b and Figure 89 c, be the semiconductor chip package generalized section of the 11st embodiment of the present invention, the semiconductor chip package schematic top plan view of the 11st embodiment of the present invention and the semiconductor chip package elevational schematic view of the 11st embodiment of the present invention.As shown in the figure: in the 11 embodiment, this metallic walls is formed simultaneously with coiling.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the 11 embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 1150 is corresponding to coiling 150... etc. as semiconductor chip 1110.
This metallic walls 1132 and 1150 whiles that wound the line are formed in electroplating process, and the electroplating process of the formation metallic walls 132 among first embodiment is done to adjust a little.Especially, the same pattern that is printed on the 3rd photoresist layer (with respect to the 3rd resistance layer 144 among first embodiment) of this first photoresist layer (with respect to first photoresist layer 126 among first embodiment) forms coiling 1150.And this recess (with respect to the recess among first embodiment 130) is to form by the rotating vane type chemical etching of a kind of back of the body limit, do not use front side rotating vane type chemical etching (front-sidewet chemical etch), so this first photoresist layer (with respect to first photoresist layer 126 among first embodiment) tool makes optionally first plane of this metal substrate (with respect to the metal substrate among first embodiment 120) expose.For example, this bottom nozzle can spray wet chemical etch solution on metal substrate (with respect to the metal substrate among first embodiment 120), when this top jet nozzle is not used.Then this metallic walls 1132 and winding the line 1150 side by side is plated on the metal substrate respectively.So this metallic walls 1132 and the 1150 gold layer institute that all are plated on nickel dam by a nickel dam and that is plated on metal substrate that wind the line are formed.And the thickness of this nickel dam is 30 microns.In metallic walls 1132 and wind the line 1150 among both, this nickel dam is sandwiched in this metal substrate and golden interlayer, and is covered by the gold layer, and the thickness of this nickel dam is 30 microns, and should engage with this nickel dam by the gold layer, but isolates with this metal substrate, the surface of this gold layer is exposed, and its thickness is 0.1 micron.In addition, the 3rd photoresist layer and the 4th photoresist layer (with respect to the 3rd photoresist layer 144 among first embodiment and the 4th photoresist layer 146) are deleted in electroplating process formation coiling 1150.
This weld layer (with respect to the weld layer among first embodiment 142), welding shielding 1156, plating contact 1162 and adhesive agent 1164 are formed then, this semiconductor chip 1110 is installed on this adhesive agent 1164, and this connecting portion 1166, sealant 1168, metal column 1170, insulated substrate 1182 and welding ends 1186 are formed then.
This semiconductor chip package 1198 comprises semiconductor chip 1110, metallic walls 1132, coiling 1150, welding shielding 1156, plating contact 1162, adhesive agent 1164, connecting portion 1166, sealant 1168, metal column 1170, insulated substrate 1182 and welding ends 1186.
See also shown in Figure 90 a, Figure 90 b and Figure 90 c, be the semiconductor chip package generalized section of the 12nd embodiment of the present invention, the semiconductor chip package schematic top plan view of the 12nd embodiment of the present invention and the semiconductor chip package elevational schematic view of the 12nd embodiment of the present invention.As shown in the figure: in the 12 embodiment, this metallic walls and plating contact side by side are formed.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the 12 embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 1250 is corresponding to coiling 150... etc. as semiconductor chip 1210.
This metallic walls 1232 and plating contact 1262 side by side are formed in electroplating process, and the electroplating process that forms metallic walls 132 among first embodiment is done to adjust a little.Especially, after this coiling 1250 and welding shielding 1256 were formed, this first photoresist layer (with respect to first photoresist layer 126 among first embodiment) is the same with the 5th photoresist layer (with respect to the 5th photoresist layer 158 among first embodiment) to have pattern.Then, this recess (with respect to the recess among first embodiment 130) is to form by the rotating vane type chemical etching of a kind of back of the body limit, do not use front side rotating vane type chemical etching, so this first photoresist layer (with respect to first photoresist layer 126 among first embodiment) tool makes optionally the copper layer of this coiling 1250 expose.For example, this bottom nozzle can spray wet chemical etch solution on metal substrate (with respect to the metal substrate among first embodiment 120), when this top jet nozzle is not used.Then this metallic walls 1232 and plating contact 1262 side by side are plated on metal substrate respectively and wind the line on 1250.So this metallic walls 1232 and plating contact 1262 all are made up of the nickel dam of one 10 micron thickness and the gold layer of one 0.1 micron thickness.In addition, it is deleted that the 5th photoresist layer, the 6th photoresist layer (with respect to the 5th photoresist layer 158 among first embodiment and the 6th photoresist layer 160) form plating contact 1162 in electroplating process.
Then, this weld layer (with respect to the weld layer among first embodiment 142) and adhesive agent 1264 are formed, this semiconductor chip 1210 is installed on this adhesive agent 1264, and this connecting portion 1266, sealant 1268, metal column 1270, insulated substrate 1282 and welding ends 1286 are formed then.
This semiconductor chip package 1298 comprises semiconductor chip 1210, metallic walls 1232, coiling 1250, welding shielding 1256, plating contact 1262, adhesive agent 1264, connecting portion 1266, sealant 1268, metal column 1270, insulated substrate 1282 and welding ends 1286.
See also shown in Figure 91 a, Figure 91 b and Figure 91 c, be the semiconductor chip package generalized section of the 13rd embodiment of the present invention, the semiconductor chip package schematic top plan view of the 13rd embodiment of the present invention and the semiconductor chip package elevational schematic view of the 13rd embodiment of the present invention.As shown in the figure: in the 13 embodiment, this metallic walls, metal column and welding ends are configured in the edge of this semiconductor chip.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the 13 embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 1350 is corresponding to coiling 150... etc. as semiconductor chip 1310.
This coiling 1350 is to reach outside the edge to extend in the edge of this semiconductor chip, this metallic walls 1332, metal column 1370 and welding ends 1386 are configured in the periphery of this semiconductor chip 1310, are by recess among first embodiment 130 and 150 the electroplating process of winding the line are done to adjust a little.Especially, this second photoresist layer (with respect to second photoresist layer 128 among first embodiment) is printed on pattern, and changes the opening transverse to this recess (with respect to the recess among first embodiment 130), so this recess has been changed with respect to this recess 130.Then the 3rd photoresist layer (with respect to the 3rd photoresist layer 144 among first embodiment) is printed on pattern the opening that forms coiling 1350 is formed again.So this metallic walls 1332, metal column 1370 and welding ends 1386 are configured in the periphery of this semiconductor chip 1310.
This semiconductor chip package 1398 comprises semiconductor chip 1310, metallic walls 1332, coiling 1350, welding shielding 1356, plating contact 1362, adhesive agent 1364, connecting portion 1366, sealant 1368, insulated substrate 1382 and welding ends 1386.
See also shown in Figure 92 a, Figure 92 b and Figure 92 c, be the semiconductor chip package generalized section of the 14th embodiment of the present invention, the semiconductor chip package schematic top plan view of the 14th embodiment of the present invention and the semiconductor chip package elevational schematic view of the 14th embodiment of the present invention.As shown in the figure: in the 14 embodiment, this metal column is upside down.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the 14 embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 1450 is corresponding to coiling 150... etc. as semiconductor chip 1410.
The thickness of this metal substrate (with respect to the metal substrate among first embodiment 120) is 500 microns.This recess (with respect to the recess among first embodiment 130) and metallic walls 1432 are formed on the first main plane (with respect to the main plane 122 of first among first embodiment) of metal substrate, this weld layer (with respect to the weld layer among first embodiment 142) is formed on the metallic walls 1432, this coiling 1450 is formed on second plane (with respect to the main plane 124 of second among first embodiment) of metal substrate, and this welding shielding (with respect to the shielding of the welding among first embodiment 152) is deleted.
Then, this insulated substrate 1482 is placed on this coiling 1450 and the metal substrate, and the part of this insulated substrate is polymerisable and forms colloid (gel) then.
Then, overall structure is placed in a supporter similar to the metal substrate 120 of first embodiment, when this insulated substrate 1482 is colloid, this insulated substrate 1482 contacts and is sandwiched between this metal substrate and supporter and this coiling 1450 and supporter, these insulated substrate 1482 hardening then with this supporter.
Then, this metal column 1470 is formed, and this plating contact 1462 is formed then.
Come, this adhesive agent 1464 is placed on the insulated substrate 1482 again, and this semiconductor chip 1410 is placed on the adhesive agent 1464 then, then these adhesive agent 1464 hardening.This metal column 1470 is not configured in the below of this semiconductor chip 1410, upwards expands and surpass the thickness of this semiconductor chip 1410 on the contrary.And the thickness of this metal column 1470 is 420 microns.
Then, this connecting portion 1466 is formed, and sealing agent 1468 is formed subsequently.Sealing agent 1468 is similar to the insulated substrate 182 of first embodiment, and its thickness is 600 microns.So sealing agent 1468 is placed on this semiconductor chip 1410, coiling 1450, adhesive agent 1464, connecting portion 1466, metal column 1470 and the insulated substrate 1462, and sealing agent 1468 hardening.
Afterwards, sealing agent 1468 is ground, and this metallic walls 1432 and weld layer are exposed, and this welding ends 1486 is formed subsequently.
This semiconductor chip package 1498 comprises semiconductor chip 1410, metallic walls 1432, coiling 1450, plating contact 1462, adhesive agent 1464, connecting portion 1466, sealant 1468, metal column 1470, insulated substrate 1482 and welding ends 1486.
See also shown in Figure 93 a, Figure 93 b and Figure 93 c, be the semiconductor chip package generalized section of the 15th embodiment of the present invention, the semiconductor chip package schematic top plan view of the 15th embodiment of the present invention and the semiconductor chip package elevational schematic view of the 15th embodiment of the present invention.As shown in the figure: in the 15 embodiment, this semiconductor chip package is many chip packagings.For brief purpose, with first embodiment identical description is arranged, need not be repeated.Similarly, the assembly of the 15 embodiment is similar to first embodiment to have corresponding Ref. No., and corresponding to semiconductor chip 110, coiling 1550 is corresponding to coiling 150... etc. as semiconductor chip 1510.
This plating contact 1562 is extended, and the electroplating process that forms plating contact 162 among first embodiment is done to adjust a little.Especially, the 5th photoresist layer (with respect to the 5th photoresist layer 158 among first embodiment) has pattern, and the opening that forms plating contact 1562 is prolonged, so this plating contact 1562 becomes longer with respect to the plating contact 162 of first embodiment.
This semiconductor chip 1510 and this welding shield 1556 and are mechanical connection by this first adhesive agent 1564, and have by first connecting portion 1566 with this coiling 1550 and to be electrically connected.
Then, this second adhesive agent 1565 is configured on first semiconductor chip 1510, it is one to separate the silica gel of first semiconductor chip 1510 and second semiconductor chip 1511, this second semiconductor chip 1511 (it is the same with conductive connecting pin 1516 in first semiconductor chip 1510 to comprise conductive connecting pin 1517) is placed on this second adhesive agent 1565 then, this second adhesive agent 1565 is sandwiched between first semiconductor chip 1510 and second semiconductor chip 1511, then overall structure is put in the baking oven, make this second adhesive agent 1565 be formed solid-state insulation adhesion layer (solid adhesiveinsulative layer) by sclerosis down in relative low temperature, 1511 tool physical properties of this first semiconductor chip 1510 and second semiconductor chip are connected, the scope of its relative low temperature is between 150 degree are spent to 200, and this second adhesive agent 1565 is 100 microns between the thickness of 1511 of first semiconductor chip 1510 and second semiconductor chips, and this first semiconductor chip 1510 and second semiconductor chip 1511 are separated, and become vertically mutually to arrange.A kind of suitable separating agent (spacer paste) is Hysol QMI 500.
Then, this second semiconductor chip 1511 has by second connecting portion 1567 with coiling 1550 and is electrically connected, and 1550 has the same method that is electrically connected by second connecting portion 1566 with this first semiconductor chip 1510 with winding the line.
Afterwards, sealing agent 1568 is formed, its thickness is 700 microns, and sealing agent 1568 contacts and covers thereon with this first semiconductor chip 1510, second semiconductor chip 1511, coiling 1550, welding shielding 1556, plating contact 1562, first adhesive agent 1564, second adhesive agent 1565, first connecting portion 1566 and second connecting portion 1567.This metal column 1570, insulated substrate 1582 and welding ends 1582 are formed subsequently.
This semiconductor chip package is multicore sheet first a level structure dress (multi-chipfirst-level package).This first semiconductor chip 1510 and second semiconductor chip 1511 are embedded into sealing agent 1568.And this first conductive connecting pin 1516 and 1586 of welding endss not only comprise and need metallic walls 1532, coiling 1550, plating contact 1567 and metal column 1570 to constitute the conductive path of a tool electric power, and this second conductive connecting pin 1517 and 1586 of welding endss not only comprise and need the conductive path of metallic walls 1532, coiling 1550, plating contact 1567 and metal column 1570 formations one tool electric power in addition.Therefore this first semiconductor chip 1510 and second semiconductor chip 1511 all are embedded in sealing agent 1568, and the conductive path of the tool electric power that is constituted by this metallic walls 1532, coiling 1550, plating contact 1567 and metal column 1570 is with this welding ends 1568 and is electrically connected.
This semiconductor chip package 1598 comprises first semiconductor chip 1510, second semiconductor chip 1511, metallic walls 1532, coiling 1550, welding shielding 1556, plating contact 1562, first adhesive agent 1564, second adhesive agent 1565, first connecting portion 1566, second connecting portion 1567, sealant 1568, metal column 1570, insulated substrate 1582 and welding ends 1586.
See also shown in Figure 94, Figure 95, Figure 96, Figure 97 and Figure 98, be the metal column structural profile schematic diagram of the 16 to 20 embodiment of the present invention.As shown in the figure: when carrying out wet chemical etch, the metal column 1670,1770,1870,1970 and 2070 among the 16 to 20 embodiment stenosis gradually is narrow and cut this metallic walls, for example by increasing etching concentration or etching period.This metal column 1670,1770,1870,1970 and 2070 is also for taper, and when metal column extends downwards, its diameter will reduce constantly.In addition, each metal column comprises plane, a top (with respect to first plane 172 of this metal column 170 among first embodiment), plane, a below (with respect to second plane 174 of this metal column 170 among first embodiment), an and poppet surface (with respect to the poppet surface 176 of this metal column 170 among first embodiment), in between these, this lower, planar concentrated area is placed in the surface area on plane, top, and the surface area of this lower, planar is bigger by 20% than the surface area on top plane at least.
Semiconductor chip package in the above embodiments is the example for demonstrating only.Also having a lot of embodiment is what can consider, for example: should weld shielding, plating contact, metal column and insulated substrate deletion.In addition, the above embodiments application of can interosculating, for example: behind the sealant of second embodiment, form weld layer, and in forming metallic walls behind the sealant of the 3rd embodiment and weld layer can be used on other embodiment.Similarly, should reach in the connecting portion of the 5th and the 6th embodiment in the chip bonding of the 4th embodiment and be used among other embodiment through electroplating, except in the multi-chip semiconductor chip-packaging structure of the 15 embodiment, because this semiconductor chip can't be by upside-down mounting.Similarly, be used among other embodiment in the 7th embodiment.In the insulated substrate of the 8th and the 9th embodiment and in the tenth embodiment deleted insulated substrate similarly can be used among other embodiment.The metallic walls and the plating contact that are formed simultaneously among the metallic walls that is formed simultaneously in the 11 embodiment and coiling and the 12 embodiment similarly can be used among other embodiment.In the 13 and metallic walls, metal column and the welding ends of the 14 embodiment similarly can be used among other embodiment.Multi-chip semiconductor chip-packaging structure in the 15 embodiment is similarly in other embodiments available, except the 4th to the 6th embodiment, because this semiconductor chip can't be by upside-down mounting.In the the the 6th, the 7th, the 8th, the 9th and the metal column of the 12 embodiment similarly be used among first, second and the 4th to the 15 embodiment, but can not be used for the 3rd embodiment, because this metal column is deleted.The mutual mix and match of the above embodiments becomes other embodiment, can go up the consideration that reaches on the reliability with design and decide.
This metal substrate need not be removed in the border of this semiconductor chip, and for example: this a part of metal substrate extends in the border of semiconductor chip and separates in this metallic walls, still can be kept perfectly and provide a radiator (heat sink).
This metallic walls is various different materials, its material comprises the combination of copper, gold, nickel, palladium, titanium, scolding tin and above-mentioned material, this metallic walls is formed by variety of way, its mode comprises the combination of plating, electroless-plating, printing, backflow and aforesaid way, this metallic walls is single or multiple lift and has difformity and size, for example: the formation of this metallic walls can be by single mode as electroplating or tin cream deposition and anti-stream, or complex way is as electroplating during with anti-stream with the tin cream deposition.And this metallic walls comprises a hole, its hole is the monometallic face, this monometallic face is different moistening metal (wettable metals), it comprises gold, titanium and tin material, take place to reflux or during different nonwetting metal (non-wettablemetals) particularly in this tin material, anti-stream has taken place or do not take place particularly in this tin material.In addition, this hole has an opening, and its opening shape is circle, rectangle or square.
Before this coiling is deposited on metal substrate, be deposited between the metal substrate or after this coiling is deposited on metal substrate in this coiling; Before this plating contact is deposited on coiling, be deposited between the coiling or after this plating contact is deposited on coiling in this plating contact; In this semiconductor chip with before coiling is connected or in this semiconductor chip with wind the line be connected after; Be formed preceding or after the sealing agent is formed in the sealing agent; And in this connecting portion be formed preceding, between this connecting portion is formed or after this connecting portion is formed, this metallic walls is deposited on the metal substrate.For example, be formed with coiling, plating contact or connecting portion simultaneously, therefore improve and make productive rate through the electroplated metal wall energy.
Second photoresist layer 128 is to be formed preceding when this metallic walls is removed or after this second photoresist layer was to be formed when this metallic walls is removed, this weld layer was formed on the metallic walls.For example, this photoresist layer is present in this tin cream and deposits and reflux, and limit to this weld layer and be formed in the metallic walls, and this metal still is under the complete situation.
This coiling is different conducting metals, and it comprises the bond of copper, gold, nickel, silver, palladium, titanium, above-mentioned metal and the alloy of above-mentioned metal.The better combination of this coiling will be decided as the factor of design and reliability according to the essence of this connecting portion.And, from the above in, copper product is typical copper alloy, almost most of composition is copper but non-fine copper, as copper zirconium alloy (99.9% bronze medal), copper-Yin-phosphorus-magnesium (copper-silver-phosphorus-magnesium) (99.7% bronze medal) or copper-titanium-iron-phosphorus (copper-tin-iron-phosphorus) (99.7% bronze medal).This coiling can be input (fan-in) as output (fan-out).
This coiling is by multiple deposition technique it to be formed on the metal substrate, and its technology comprises electroplates and electroless-plating.In addition, this coiling is deposited on the metal substrate, and this coiling is single or multiple lift.For example: this coiling is the gold layer of one 10 micron thickness, or the nickel dam that can be one 9.5 micron thickness is plated on the gold layer of one 0.5 micron thickness and is plated on a copper base, to reduce cost; Or the nickel dam of one 9 micron thickness is plated on one 0.5 microns gold layer, is plated on one 0.5 microns titanium layer again and is plated on a copper base, to reduce cost and to avoid the gold copper that difficulty removes when copper plate is etched.Another example, this coiling are plated on the copper base by a non-copper layer (non-copperlayer) and a bronze medal layer is plated on the non-copper layer and constitutes.Suitable non-copper layer comprises nickel, gold, palladium and silver.When this coiling is formed, when copper is suitable for this copper base of wet chemical etch etching and makes this coiling exposure during to non-copper layer, but do not remove this copper layer and non-copper layer.This non-copper layer provides an etching to stop (etch stop), prevents that this wet chemical etch from removing copper plate.In the above description, this coiling and metal substrate are different metals (or metal material), it is similar to metal substrate though the coiling of tool multilayer comprises an individual layer, or is the individual layer (single layer of a multi-layermetal base) of a tool multiple layer metal substrate.
This coiling forms by the metal level that etching one invests metal substrate.For example, a photoresist layer can be formed on metal level, and this metal level utilizes this photoresist layer to be its etch shield when etched, and this photoresist layer is peeled off then; Or for a photoresist layer is formed on this metal level, optionally being plated on metal level and utilizing photoresist layer once the electroplated metal tool is that it electroplates shielding, this photoresist layer can be peeled off then, and make this metal level etched and use this through electroplated metal as etch shield, in this method, this coiling is formed, and it comprises the not etching part of this metal level and through electroplated metal.This coiling is formed by metal level, no matter whether this is etch shield through electroplated metal, this is attached to this coiling through electroplated metal.
This coiling can be electroplates (spot plated) near conductive connecting pin and make connecting portion and its compatibility.For example, the coiling of a bronze medal is and nickel point is electroplated, and silver makes itself and the connecting portion compatibility of a tool metal gold goal then, avoids frangible silver and copper two metals formation mixture.This metallic walls through a plating make its can with the welding ends compatibility, for example: the metal wall energy of a nickel and gold point are electroplated to make and are promoted the tin material to reflux.
This metal column can have different shape and size.For example: its top plane and lower, planar (with respect to first plane 172 and second plane 174 of the metal column of first embodiment) be circle, rectangle or square.In addition, the diameter on the plane, top of this metal column less than, be equal to or greater than the diameter of the lower, planar of this metal column.On plane above this metal column and be capped, its diameter is littler 100 microns than this metal ancient piece of jade, round, flat and with a hole in its centre outer boundary at least, and makes it form highdensity circuit easily as the big circular portion of the lower, planar of this metal column and this coiling.
Form and be connected about this metal substrate of the details etching of this metal column with this coiling, disclosed in the reference paper below: Application No. the 10/714th, propose by people such as Chuen Rong Leu on November 17th, 2003 for No. 794, its patent name " semiconductor chip package of the metal column that tool embeds ", Application No. the 10/994th, No. 604, propose by people such as Charles W.C Lin on November 22nd, 2004, its patent name " semiconductor chip package of tool reguline metal post " and Application No. the 10/994th, propose by people such as Charles W.C Lin on November 22nd, 2004 for No. 836, its patent name " tool is carved the semiconductor chip package of block contact jaw " is so reference data is as can be known thus for the details of this metal column.
The below of this welding ends can not be covered by the sealant of this semiconductor chip package, insulated substrate or other insulating material.For example: the following of this welding ends can be exposed, and perhaps the following of this welding ends can be covered by the outer insulating material of this semiconductor chip package, forms storehouse ground as a plurality of semiconductor chips and arranges.In each semiconductor chip package, the below of this welding ends is not covered by the sealant of this semiconductor chip package, insulated substrate or other insulating material.
This conductive trace energy tool signal, power supply or ground plane function are according to the purpose in conjunction with the semiconductor chip pin.
This semiconductor chip is vertical with main plane, this semiconductor chip is included in the conductive connecting pin of direction up and away from this coiling, perhaps this semiconductor chip can be by upside-down mounting, its main plane is in direction down and towards this coiling, for example: the main plane of direction utilizes routing to engage to this semiconductor chip with being positioned at up, and perhaps this semiconductor chip can the main plane of direction utilizes chip bonding with being positioned at down.And this semiconductor chip has being connected of electric power by various connecting portion with this winding department, no matter this semiconductor chip upright or by upside-down mounting.For example: the connecting portion of this semiconductor chip and a tin or the connecting portion of a gold medal are with chip bonding.For instance, one solder bump can be formed on the conductive connecting pin, this semiconductor chip can be by an acquisition head by upside-down mounting or be configured, this acquisition head is sandwiched in this conductive connecting pin and winding department for this solder bump, and making this solder bump be back to the connecting portion of a tin heating of the baking oven of one convection current, the connecting portion of this tin and this conductive connecting pin engage with winding the line.Other example can be formed on this conductive connecting pin as a gold medal projection, this coiling and a gold medal layer are formed, this semiconductor chip can be by an acquisition head by upside-down mounting or be configured, this acquisition head is sandwiched in this conductive connecting pin and winding department for this gold projection, energy heat application and pressure are also transmitted and are passed this semiconductor chip to this gold projection, and temperature, pressure and supersonic binding energy form a gold medal gold are connected (gold-gold interconnect, GGI), it is between the gold layer of golden projection and this coiling, and therefore the connecting portion of a gold medal engages with this conductive connecting pin and coiling.
This conductive connecting pin has multiple shape, and its shape comprises the flat rectangular convex.This conductive connecting pin is compatible with this connecting portion.
Multiple adhesive agent can connect this semiconductor chip to coiling.For example: this adhesive agent such as paste, interlayer or aqueously be applied to grid printing (screen-printing), rotation (spin-on) or spray (spray-on).This adhesive agent is that individual layer is applied to metal substrate or welding shielding, and contact with this semiconductor chip, or for individual layer is applied to this semiconductor chip, and with this metal substrate or weld to shield and contact.Similarly, this adhesive agent is a composite bed, has ground floor and is used in metal substrate or welding shielding, and the second layer is used for this semiconductor chip, and this ground floor and the second layer are in contact with one another then.This thermosetting adhesive agent forms liquid state and paste is suitable for as resin.Similarly, the thermoplasticity adhesive agent is suitable for as the thermoplastic pi film of the insulation of a tool 400 degree glass transition temperatures.The adhesive agent of silica gel shape also is suitable for.
The sealing agent utilizes various different technologies to form, and its technology comprises that printing and metaideophone are shaped.For example: sealing agent such as resin are printed on the semiconductor chip, and sclerosis forms a solid-state passivation layer that sticks together then.The sealing agent is the kind of above-mentioned adhesive agent.The sealing agent not necessarily contacts with this semiconductor chip in addition.For example: a sealing coating places this semiconductor chip after this semiconductor chip is connected to coiling, and the sealing agent can be formed on this sealing coating then.
This insulated substrate can be for hard or tool is flexible, and can be insulator such as winding, polyamide (polyimide), resin, silica gel, glass, aromatic polyamide (aramid) and the pottery (ceramic) that is formed multiple organic or inorganic by various insulation film or glass fibre.Organic insulator has low cost and high-insulativity, yet this inorganic insulator is important when higher calorific power consumption and suitable thermal coefficient of expansion.For example: originally this insulated substrate is an epoxy resin, and it comprises epoxy resin, curing agent, accelerator and filler, can side by side harden to form a solid-state insulating barrier that sticks together.This filler is an inert material such as tripoli (silica) (the Powdered quartz that dissolves), and it can improve heat conductivity, thermal shock and thermal coefficient of expansion.Organic reinforcing fiber can be used to as in epoxy resin, cyanate ester resin, pi, Teflon and the above-mentioned resins such as bond.This fiber comprises that aromatic polyamide, polynary ester (polyester), poly-ether-ether-ketone, pi, hot plastic type polyimides (polyetherimide) and polysulfones (polysulfone) are used.This reinforcing fiber is weave cotton cloth (woven fabric), glass cloth (woven glass), random microfiber glass, braiding quartzy (woven quartz), braid (woven), aromatic polyamide (aramid), nonwoven fabrics (non-woven fabric), nonwoven aromatic polyamide fibre (non-woven aramid fiber) or paper.Commercial available insulating material is as by W.L.Gore﹠amp; The SPEEDBOARD C preimpregnation material that Associates of Eau Claire makes is suitable.
This insulated substrate utilizes multiple mode to be formed, and its mode comprises that printing and metaideophone form.And this insulated substrate is connected to the preceding of this coiling or this semiconductor chip in this semiconductor chip and is formed after being connected to this coiling.
This insulated substrate utilizes various technology that it is removed than lower part, and its technology comprises grinding (comprising mechanical lapping and cmp), code-pattern laser disappears and melts and the code-pattern plasma etching.Similarly, this insulated substrate tool can select part to be removed under this metallic walls, metal column and weld layer and to utilize various different technologies, and wherein this technology comprises selective laser disappear molten, selectivity plasma etching and photoetch.
This insulated substrate and metallic walls are arranged along it towards the below flat transverse, and extend downwards from this coiling and metal column, and grind this insulated substrate but do not grind this weld layer, metal column or coiling, grind this insulated substrate and metallic walls then but do not grind this metal column or coiling, then stop to grind in arriving this metal column and coiling.This insulated substrate and weld layer are transversely arranged in down a plane, this insulated substrate extends downwards from this coiling and metal column, and grind this insulated substrate but do not grind this weld layer, metal column or coiling, grind this insulated substrate and welded plate then but do not grind this metal column or coiling, then before arriving this metal column or coiling, stop to grind.Similarly, this insulated substrate and metallic walls and weld layer are along its flat transverse arrangement down, and extend downwards from this coiling and metal column, and grind this insulated substrate but do not grind this metallic walls, weld layer, metal column or coiling, grind this insulated substrate, metallic walls and weld layer then but do not grind this metal column or coiling, then before arriving this metal column or coiling, stop to grind.
This connecting portion utilizes various different materials to form, its material comprises copper, gold, nickel, palladium, titanium, its alloy and bond thereof, and utilize various various process to form, its process comprises that plating, electroless-plating, ball bonding, routing engage, column engages (stud bumping), the reflow soldering of tin material, the conduction adhesive agent hardens and welding, and this connecting portion can have various difformities and size.According to the consideration of design with reliability, the shape of this connecting portion and composition are according to the composition of this coiling.And the details of the connecting portion of tool plating is in Application No. the 09/865th, proposed by Charles W.C.Lin May 24 calendar year 2001 for No. 367, its patent name is for being disclosed in " tool is electroplated the contact jaw of formation and the semiconductor chip package of connecting portion simultaneously ".And through the details of the connecting portion of electroless-plating in Application No. the 09/864th, proposed by Charles W.C.Lin May 24 calendar year 2001 for No. 555, its patent name is for being disclosed in " tool the contact jaw that forms of electroless-plating and the semiconductor chip package of connecting portion " simultaneously.The connecting portion that forms through ball bonding is proposed by Charles W.C.Lin May 24 calendar year 2001 in No. the 09/864th, 773, Application No., and its patent name is for being disclosed in " semiconductor chip of the connecting portion that the tool ball bonding forms ".The connecting portion that forms through scolding tin or conduction adhesive agent is proposed by Charles W.C.Lin August 10 calendar year 2001 in No. the 09/927th, 216, Application No., and its patent name is disclosed for " semiconductor chip of the connecting portion of tool sclerosis ".Connecting portion through welding is proposed by people such as Cheng-LienChiang in No. the 10/302nd, 642, Application No. on November 23rd, 2002, and its patent name is disclosed for " utilizing plasma etching to connect the method for conductive trace to semiconductor chip ".
After this connecting portion is formed, if this connecting portion is not connected with this conductive trace when this plating bus exists.This plating bus is not to be connected by mechanical type cutting, laser cutting, chemical etching and merging.Be not integrated into this semiconductor chip package if this plating bus is placed near this semiconductor chip package, when this semiconductor chip package separated with other semiconductor chip package, this plating bus was not connected then.If yet this plating bus has been integrated into this semiconductor chip package, or independently taken place, this photoetch (photolithography step) optionally is added into the circuit cutting about semiconductor chip package, and this semiconductor chip package is furnished with plating bus, when this circuit shortens this conductive trace in addition.And this plating bus is not to be connected by this metallic plate of etching.
One soldering tin material or tin ball can be placed on the weld layer by plating, printing or coating technique and carry out next level structure dress in need.This next level structure dress need not comprise the semiconductor chip package of tin material then, and for example: in planar lattice array structure dress, this soldering tin material is to provide rather than in the contact jaw of semiconductor chip package by panel.
Various cleaning way such as brief plasma oxygen cleaning way, or utilize the brief wet chemistry cleaning way of potassinm permanganate solution, can be applied in the structure of various various process, as before forming connecting portion, cleaning this conductive trace and conductive connecting pin immediately.
By in the specification of the present invention as can be known, it is to have between conductive path and this welding ends by a tool electric power to be electrically connected that any semiconductor chip is embedded in the sealing agent, the conductive path of this tool electric power comprises coiling and metallic walls, and its meaning is that this coiling and metallic walls connection are embedded in the welding ends of sealant and the conductive path of the tool electric power between any semiconductor chip.No matter be that single-chip is embedded in the sealing agent that (it is to have being connected of electric power between conductive path and this welding ends by a tool electric power that this semiconductor chip is embedded in the sealing agent, the conductive path of this tool electric power comprises coiling and metallic walls), or be embedded in the sealing agent (it is to have being connected of electric power between conductive path and this welding ends by a tool electric power that each semiconductor chip is embedded in the sealing agent, and whether the conductive path of this tool electric power comprises winds the line and metallic walls) for the multicore sheet.Also no matter the conductive path of this tool electric power comprise or need a junction and (or) plating contact is between this coiling and semiconductor chip.No matter whether the conductive path of this tool electric power comprises or needs one metal column between this coiling and metallic walls.No matter whether the conductive path of this tool electric power comprises or need be just like the passive composition assembly of capacitor or resistor.Also no matter whether this multicore sheet is electrically connected with this coiling by a plurality of connecting portions, these a plurality of connecting portions are to be in electrical connection by coiling.No matter this multicore sheet whether conductive path by different tool electric power has with this welding ends and is electrically connected the conductive path that (as the example of above-mentioned a plurality of connecting portions) need only each tool electric power and comprises this coiling and metallic walls.
By in the specification of the present invention as can be known, this metal column is to form by wet chemical etch, but is not once just to form metal column.For example: wet chemical etch formed this recess and can form this metal column lower, planar first time this, and this, wet chemical etch formed the plane, top and the poppet surface thereof of this metal column second time.This, wet chemical etch made this metal column form fully second time in this example.
By in the specification of the present invention as can be known, this metal column is the taper shape of tool poppet surface, its poppet surface next-door neighbour and spread over the top of this metal column and lower, planar between and to inner inclination, even this inner chamfer can change.For example this poppet surface can be to inner inclination, even the poppet surface of a part is to outer inclination, just the diameter on the big plane thereunder of the diameter on the plane, top of this metal column and this poppet surface almost slope inwardly in the plane inclination downwards from the plane, top of this metal column.
By in the specification of the present invention as can be known, this welding ends comprises this weld layer and contacts with metallic walls in this hole, no matter this welding ends comprises weld layer and other soldering tin material, or this welding ends is made up of this weld layer, no matter this welding ends extends and outside expansion toward this hole is inner, or be placed in this hole, no matter whether the whether contact of the metallic walls in hole outside of this weld layer contacts with this metallic walls regardless of this weld layer.
Can understand in specification of the present invention and learn that this weld layer may be changed even this welding ends comprises this weld layer.For example: the shape of this weld layer is being carried out chemical etching formation metal column, sclerosis formation insulated substrate, is being changed when grinding this weld layer expose portion and tin material backflow formation welding ends.Similarly, this tin material refluxes and can change the shape and the combination of this weld layer when forming welding ends, and may be mixed with this tin ball and weld layer, makes them no longer be separation that can be clear and definite.This welding ends comprises this weld layer in each embodiment.
Should " making progress " reach " downwards " vertical direction and disobey the location of this semiconductor chip package and decide, with clear and definite being expressed in the literary composition.For example, direction is vertically extended from this coiling toward " make progress " in the sealing agent, this metallic walls is vertically extended from this semiconductor chip toward " downwards " direction and this insulated substrate vertically extends from past " downwards " direction of sealing agent, regardless of this semiconductor chip package whether by upside-down mounting or be covered on the printed circuit board (PCB).Similarly, this coiling is laterally extended from this metallic walls, no matter this semiconductor chip package whether by upside-down mounting, rotate or cut apart.Therefore it is relative should " make progress " reach " downwards " direction, and with a horizontal direction quadrature, should " laterally arrange " surface and on same transverse plane or with making progress, reach downward direction.This semiconductor chip is drawn on this coiling, metallic walls, metal column, welding ends and the insulated substrate, and the sealing agent is drawn on and has on this semiconductor chip, coiling, metallic walls, metal column, welding ends and the insulated substrate on the single figure of being positioned everywhere, for scheme and figure between compare, though this semiconductor chip package and its composition can be by upside-down mounting in various manufacture processes.
The working forms of this semiconductor chip package can for single-chip structure dress or many chip packagings based in the designing for manufacturing.For example: this single-chip structure dress comprises the single-chip that can be made independently.Perhaps a plurality of semiconductor chips side by side are formed on the single welding shielding of a tool, on the metal substrate of sealant and insulated substrate, isolate mutually then, side by side form when this metal substrate of etching as: the recess in many chip packagings, this metallic walls side by side is plated on the recess of metal substrate then, then separating tin cream utilizes single template side by side to be placed in this corresponding metal wall, this tin cream formation weld layer that side by side refluxes then, and this coiling side by side is plated on the metal substrate, then this plating contact side by side is plated on corresponding coiling, the adhesive agent of the semiconductor chip package that separates out of the ordinary side by side is placed in the welding shielding, and this semiconductor chip side by side is placed on the corresponding adhesive agent, this adhesive agent is side by side hardened, this connecting portion is formed on corresponding plating contact and the conductive connecting pin then, then the sealing agent is formed, this metal substrate is etched and side by side form metal column, this insulated substrate is formed then, and this insulated substrate, metallic walls and weld layer are side by side ground, the space of tin cream separation side by side is placed on the corresponding weld layer then, and this weld layer and tin ball are side by side formed welding ends by backflow, and should welding shield, sealant and insulated substrate are cut, and therefore are divided into the independently semiconductor chip package of single-chip substrate of tool.
This semiconductor chip package has different structure dress forms when carrying out next level structure dress, for example: this conductive trace is formed, because of this semiconductor chip package is a kind of trellis array such as ball form array, post form array, planar lattice array or pin form array.
This semiconductor chip package is first a level structure dress, and its structure dress is adorned (as first embodiment to the, 14 embodiment) for the single-chip structure or is many chip packagings (as the 15 embodiment).And the first level structure of this multicore sheet dress can comprise semiconductor chip by storehouse and become vertical arrangement each other, or semiconductor chip is all on the same plane and becomes transversely arranged each other.
Manufacture method tool reliability and cost thereof in semiconductor chip package of the present invention are lower.Sealing agent and insulated substrate protect this semiconductor chip to suffer damage in processing procedure, and the shielding in this conductive trace one exhausted source is provided, and protect this semiconductor chip package not to be subjected to pollutant and unnecessary tin material refluxes in next level structure dress.The sealing agent can provide this conductive trace one mechanical support in the etched formation metal column of this metal substrate or when being removed.This metal wall energy is limited to this weld layer and welding ends when carrying out tin material reflux operation.This welding ends can extend to the metallic walls in this insulated substrate in addition, rather than this semiconductor chip package is contacted with the high pressure border of its transverse plane, its transverse plane is the main plane that is exposed downwards one day, therefore can reduce the separation of tin material and improve reliability.This juncture can be replaced with the coupling of metallurgical formula by mechanical coupling, guarantees that the joint of metallurgical formula has sufficient intensity.And this conductive trace can be for not using routing joint, the winding adhesive agent of joint, scolding tin or tool conductivity automatically in this semiconductor chip coupling, though process is adjustable, can adjust the technology that needs with mechanically reaching metallurgical formula.This process tool is multi-functional and permit that the perfect joining technique of various differences is applied to independently reaching in the method for improvement.And the suitable especially position of this metal column reduces the pressure when Yin Wendu is asymmetric to cause down one deck combination and influences yield and improve reliability in one deck combination down, and it has surpassed traditional ball form structure and has adorned.So semiconductor chip package of the present invention is compared characteristics such as can improving output, profit and usefulness with traditional structure packing technique.And semiconductor chip package of the present invention can with copper metal compatibility.
Above-mentioned only is embodiments of the invention, can not limit scope of the invention process with this; So, all according to simple equivalent variation and modification that the present invention did, all should still belong within the protection range of the present invention.

Claims (200)

1. the manufacture method of the semiconductor chip package of a welding ends tool metallic walls comprises at least:
A, one metal substrate is provided, one coiling, one metallic walls and a weld layer, wherein this metal substrate comprises corresponding first plane and second plane, first plane of this metal substrate is on first direction, second plane of this metal substrate is on second direction, and this second direction is opposite with first direction, this metallic walls is extended in this metal substrate toward its first plane by second plane of this metal substrate, and this metallic walls comprises a hole, this hole is extended in this metal substrate toward its first plane by second plane of this metal substrate, and comprising an opening towards second direction, this weld layer contacts with metallic walls in this hole;
B, mechanically connect the semiconductor chip and wind the line to this, wherein this semiconductor chip comprises a conductive connecting pin;
C, formation a junction, this connecting portion is electrically connected with this coiling and conductive connecting pin;
D, form a sealant connecting semiconductor chip to metal substrate and coiling back, utilize wet chemical etch this metal substrate etching; And
E, provide a welding ends, this welding ends contacts with metallic walls in this hole, and comprises this weld layer.
2. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the generation type of this coiling with this wire winded electroplating on this metal substrate.
3. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 2, it is characterized in that, the generation type of this coiling comprises that forming a plating is shielded from this metal substrate, wherein this plating shielding comprises an opening, and this opening exposes the metal substrate of a part; And with this wire winded electroplating in the expose portion of this metal substrate and pass the opening of this plating shielding.
4. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the generation type of this metallic walls is plated on this metal substrate this metallic walls.
5. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 4, it is characterized in that, the generation type of this metallic walls comprises that forming a plating is shielded from this metal substrate, wherein this plating shielding comprises an opening, and this opening exposes the metal substrate of a part; And this metallic walls is plated on the expose portion of this metal substrate, and pass the opening of this plating shielding.
6. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, the generation type of this metallic walls comprises that this metal substrate of etching forms a via, and this via is extended in this metal substrate toward its first direction by the second direction of this metal substrate; And this metallic walls is deposited in this via.
7. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 6 is characterized in that this via is a perforation, extends in this metal substrate and penetrates, and makes this coiling exposure; And this metallic walls extends in this metal substrate and penetrates, and contacts with this coiling.
8. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 7 is characterized in that, the etched contact area that makes between this metal substrate and winding department and this metal substrate and metallic walls that penetrates of this metal substrate is removed.
9. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 6, it is characterized in that, this via is a recess, and this recess extends in this metal substrate but do not penetrate, and isolates with first plane and the coiling of this metal substrate; And this metallic walls extends in this metal substrate but do not penetrate, and isolates with first plane and the coiling of this metal substrate.
10. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 9, it is characterized in that, the etched not etching part from this metal substrate of this metal substrate forms a metal column, the not etching part of this metal substrate is that this metal column contacts with this coiling and this metallic walls by this metallic walls definition.
11. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the generation type of this weld layer comprises is deposited on this metallic walls this weld layer.
12. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 11 is characterized in that, the generation type of this weld layer comprises that this weld layer only contacts with this metallic walls.
13. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 11 is characterized in that, the generation type of this weld layer comprises is deposited on this metallic walls a tin cream, and this tin cream is refluxed.
14. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this welding ends is this weld layer.
15. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, the generation type of this welding ends comprises is deposited on this weld layer a soldering tin material, and this soldering tin material is refluxed with weld layer.
16. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the formation method of this welding ends comprise the following steps at least and according to the order:
A, this tin cream is deposited on this metallic walls;
B, this tin cream is refluxed, therefore form this weld layer;
C, a soldering tin material is deposited on this weld layer; And
D, this soldering tin material and weld layer are refluxed together, therefore form this welding ends.
17. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the formation method of this metallic walls and weld layer comprise the following steps at least and according to the order:
A, this metal substrate of etching form a via;
B, this metallic walls is deposited on this metal substrate, and enters in this via; And
C, this weld layer is plated on this metallic walls.
18. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the formation method of this metallic walls and weld layer comprise the following steps at least and according to the order:
A, this metal substrate of etching also pass the opening of an etch shield, therefore form a via;
B, make this metallic walls be plated on the expose portion of this metal substrate, and pass an opening of electroplating shielding and enter in this via;
C, a tin cream is deposited on this metallic walls; And
D, this tin cream is refluxed, therefore form this weld layer.
19. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the formation method of this metallic walls and weld layer comprise the following steps at least and according to the order:
A, this metal substrate of etching form a via;
B, make this metallic walls be plated on the expose portion of this metal substrate, and pass an opening of electroplating shielding and enter in this via;
C, a tin cream is deposited on this metallic walls; And
D, this tin cream is refluxed, therefore form this weld layer.
20. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the formation method of this metallic walls and weld layer comprise the following steps at least and according to the order:
A, formation one are shielded from this metal substrate, and wherein this shielding comprises an opening, and the metal substrate of a part is exposed;
B, this metal substrate of etching also pass the opening of this shielding, therefore form a via;
C, make this metallic walls be plated on the expose portion of this metal substrate, and the opening that passes this shielding enter in this via;
D, a tin cream is deposited on this metallic walls; And
E, this tin cream is refluxed, therefore form this weld layer.
21. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the formation method of this metallic walls and weld layer comprise the following steps at least and according to the order:
A, formation one etch shield are in this metal substrate, and wherein this etch shield comprises an opening, and the metal substrate of a part is exposed;
B, this metal substrate of etching also pass the opening of this etch shield, therefore form a via;
C, formation one are electroplated and are shielded from this metal substrate, and wherein this plating shielding comprises an opening, and the metal substrate of a part and this via are exposed;
D, make this metallic walls be plated on the expose portion of this metal substrate, and the opening that passes this plating shielding enter in this via;
D, a tin cream is deposited on this metallic walls; And
E, this tin cream is refluxed, therefore form this weld layer.
22. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, this semiconductor chip and coiling ways of connecting comprise an adhesive agent are placed between this semiconductor chip and metal substrate, make this adhesive agent sclerosis then.
23. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the mode that this connecting portion forms comprises this connecting portion is plated between this coiling and conductive connecting pin.
24. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the mode that this connecting portion forms comprises utilizes electroless-plating that this connecting portion is plated between this coiling and conductive connecting pin.
25. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, the mode that this connecting portion forms comprises is deposited between this coiling and conductive connecting pin a non-solid-state material, and makes this non-solid-state material sclerosis.
26. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, the mode that this connecting portion forms comprises provides a routing between this coiling and conductive connecting pin.
27. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this metal substrate utilizes this wet chemical etch to carry out etching, and this coiling is exposed.
28. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this metal substrate utilizes this wet chemical etch to carry out etching, removes most metal substrate.
29. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this metal substrate utilizes this wet chemical etch to carry out etching, removes in the intramarginal metal substrate of this conductive connecting pin.
30. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this metal substrate utilizes this wet chemical etch to carry out etching, removes in the intramarginal metal substrate of this semiconductor chip.
31. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, this metal substrate utilizes this wet chemical etch to carry out etching, and the contact area between this metal substrate and winding department and this metal substrate and metallic walls is reduced but not removal fully.
32. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, this metal substrate utilizes this wet chemical etch to carry out etching, form a metal column from the not etching part of this metal substrate, the not etching part of this metal substrate is that this metal column makes this coiling be electrically connected with metallic walls by this metallic walls definition.
33. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, this metal substrate utilizes this wet chemical etch to carry out etching, and the contact area between this metal substrate and winding department and this metal substrate and metallic walls is removed fully.
34. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this metal substrate utilizes this wet chemical etch to carry out etching, and removes this metal substrate.
35. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, this metal substrate utilizes this wet chemical etch to carry out etching, and the coiling tool that this coiling and other are contacted with metal substrate is isolated electrically.
36. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, this metal substrate utilizes this wet chemical etch to carry out etching, and this conductive connecting pin and other conductive connecting pin tool on semiconductor chip is isolated electrically.
37. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that this metallic walls forms preceding formation at this weld layer.
38. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 37 metallic walls is characterized in that, forms this coiling before this metallic walls forms.
39. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 37 metallic walls is characterized in that, this metallic walls forms the back and forms this coiling.
40. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 37 metallic walls is characterized in that, this metallic walls side by side forms with this coiling.
41. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 37 metallic walls is characterized in that, this metallic walls is connecting the formation to this metal substrate and the coiling of this semiconductor chip.
42. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 37 metallic walls is characterized in that, this metallic walls forms connecting this semiconductor chip to this metal substrate and coiling back.
43. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 37 metallic walls is characterized in that, this weld layer is connecting the formation to this metal substrate and the coiling of this semiconductor chip.
44. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 37 metallic walls is characterized in that, this weld layer forms connecting this semiconductor chip to this metal substrate and coiling back.
45. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 37 metallic walls is characterized in that this weld layer forms preceding formation at this welding ends.
46. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 37 metallic walls is characterized in that this weld layer directly forms this welding ends.
47. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this connecting portion utilizes wet chemical etch to carry out forming before the etching at this metal substrate.
48. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this connecting portion utilizes wet chemical etch to carry out forming after the etching at this metal substrate.
49. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this welding ends forms to this metal substrate and coiling at this semiconductor chip of connection.
50. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this welding ends is connecting this semiconductor chip to this metal substrate and the formation of coiling back.
51. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that this welding ends forms preceding formation at this connecting portion.
52. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this welding ends forms the back at this connecting portion and forms.
53. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this welding ends utilizes wet chemical etch to carry out forming before the etching at this metal substrate.
54. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this welding ends utilizes wet chemical etch to carry out forming after the etching at this metal substrate.
55. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, further comprise and form this metallic walls, then form this weld layer, connect this semiconductor chip then to this metal substrate, coiling, metallic walls and weld layer, and utilize wet chemical etch that this metal substrate is carried out etching.
56. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, further comprise and form this metallic walls, then connect this semiconductor chip to this metal substrate, coiling and metallic walls, form this weld layer then, and utilize wet chemical etch that this metal substrate is carried out etching.
57. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, further comprise and connect this semiconductor chip to this metal substrate and coiling, then form this metallic walls, form this weld layer then, and utilize wet chemical etch that this metal substrate is carried out etching.
58. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1, it is characterized in that, further comprise formation one sealant, the sealing agent is to cover this semiconductor chip on first direction in this semiconductor chip of connection to this coiling back.
59. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 58 metallic walls, it is characterized in that, the sealing agent is formed the back and further forms an insulated substrate, and covering this metallic walls and weld layer on second direction, the insulated substrate that removes a part then makes this insulated substrate can't cover this weld layer on second direction.
60. the manufacture method of the semiconductor chip package of welding ends tool metallic walls according to claim 1 is characterized in that, this semiconductor chip package is the encapsulation of first level.
61. the manufacture method of the semiconductor chip package of a welding ends tool metallic walls comprises at least:
A, provide a metal substrate that comprises corresponding first plane and second plane, wherein first plane of this metal substrate is towards first direction, and second plane of this metal substrate is towards second direction, and this second direction is opposite with first direction;
B, form one and wind the line on first plane of metal substrate, wherein should coiling and first plane contact of this metal substrate, and with second planar isolated of this metal substrate;
C, utilize first wet chemical etch that this metal substrate is carried out etching, therefore form a via in this metal substrate, this via is extended in this metal substrate toward its first plane by second plane of this metal substrate;
D, formation one metallic walls are on this metal substrate, wherein, metal substrate in this metallic walls and this via contacts, this metallic walls is extended in this metal substrate toward its first plane by second plane of this metal substrate, and this metallic walls comprises a hole, this hole is extended in this metal substrate toward its first plane by second plane of this metal substrate, and is covered on the first direction by this metallic walls, and comprises an opening towards second direction;
E, form a weld layer, this weld layer contact with metallic walls in this hole, and with this isolation that winds the line;
F, mechanically connect the semiconductor chip to this metal substrate and coiling, wherein this semiconductor chip comprises a conductive connecting pin;
G, formation a junction, this connecting portion is electrically connected with this coiling and conductive connecting pin;
H, after connecting this semiconductor chip to this metal substrate and coiling back and forming a sealant and form this metallic walls and weld layer, utilize second wet chemical etch to this metal substrate etching; And
I, provide a welding ends, this welding ends contacts with metallic walls in this hole, and comprises this weld layer.
62. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls, it is characterized in that, the generation type of this coiling comprises that forming a plating is shielded from this metal substrate, wherein this plating shielding comprises an opening, and this opening exposes the metal substrate of a part; And the opening that passes this plating shielding is with the expose portion of this wire winded electroplating in this metal substrate.
63. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that, the formation method of this metallic walls and weld layer comprises the following steps and at least according to order:
A, pass an opening of electroplating shielding this metallic walls is plated on this metal substrate, and enter this via;
B, a tin cream is deposited on this metallic walls; And
C, this tin cream is refluxed, therefore form this weld layer.
64. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that this welding ends is this weld layer.
65. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls, it is characterized in that, after the mode that this welding ends forms is included in and utilizes second wet chemical etch that this metal substrate is carried out etching, one soldering tin material is deposited on this weld layer, this soldering tin material and weld layer are refluxed together, form this welding ends.
66. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls, it is characterized in that, this semiconductor chip and metal substrate and coiling ways of connecting comprise an adhesive agent are placed between this semiconductor chip and metal substrate, make this adhesive agent sclerosis then.
67. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that, the mode that this connecting portion forms comprises provides a routing between this coiling and conductive connecting pin.
68. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, and this coiling is exposed.
69. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 68 metallic walls, it is characterized in that, this metal substrate utilizes this first wet chemical etch to carry out etching and forms this via, this via is that a perforation and extension penetrate this metal substrate, and this coiling is exposed; And this metal substrate utilizes second wet chemical etch to carry out etching, removes the contact area between this metal substrate and winding department and this metal substrate and metallic walls.
70. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes this metal substrate.
71. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 68 metallic walls, it is characterized in that, this metal substrate utilizes this first wet chemical etch to carry out etching and forms this via, and this via is a recess and extends this metal substrate but do not penetrate; And this metal substrate utilizes second wet chemical etch to carry out etching, form a metal column from the not etching part of this metal substrate, the not etching part of this metal substrate is that this metal column contacts with this coiling and metallic walls by the definition of this metallic walls, and makes between this coiling and metallic walls and be electrically connected.
72. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 71 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes most metal substrate.
73. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 71 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes in the intramarginal metal substrate of this conductive connecting pin.
74. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 71 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes in the intramarginal metal substrate of this semiconductor chip.
75. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 68 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and the coiling tool that this coiling and other are contacted with metal substrate is isolated electrically.
76. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 68 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and this conductive connecting pin and other conductive connecting pin tool on semiconductor chip is isolated electrically.
77. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that, this metallic walls is connecting the formation to this metal substrate and the coiling of this semiconductor chip.
78. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that, this metallic walls forms connecting this semiconductor chip to this metal substrate and coiling back.
79. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that, this weld layer is connecting the formation to this metal substrate and the coiling of this semiconductor chip.
80. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that, this weld layer forms connecting this semiconductor chip to this metal substrate and coiling back.
81. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that this connecting portion utilizes second wet chemical etch to carry out forming before the etching at this metal substrate.
82. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that this connecting portion utilizes second wet chemical etch to carry out forming after the etching at this metal substrate.
83. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls, it is characterized in that, further comprise formation one sealant, the sealing agent is covered in this semiconductor chip at this semiconductor chip of connection on first direction to this metal substrate and coiling.
84. the manufacture method of the semiconductor chip package of 3 described welding ends tool metallic walls according to Claim 8, it is characterized in that, the sealing agent is formed the back and further forms an insulated substrate, this insulated substrate contacts with this coiling, metallic walls and weld layer, and covering this metallic walls and weld layer on second direction, the insulated substrate that removes a part then makes this insulated substrate can't cover this weld layer on second direction.
85. the manufacture method of the semiconductor chip package of 4 described welding ends tool metallic walls is characterized in that according to Claim 8, this insulated substrate that removes a part makes this metallic walls and weld layer expose in second direction, but this coiling is exposed.
86. the manufacture method of the semiconductor chip package of 5 described welding ends tool metallic walls is characterized in that according to Claim 8, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate.
87. the manufacture method of the semiconductor chip package of 6 described welding ends tool metallic walls according to Claim 8, it is characterized in that, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate, but do not grind this metallic walls and weld layer, then grind this insulated substrate, metallic walls and weld layer, laterally be arranged in one up to this insulated substrate, metallic walls and weld layer then and stop to grind during towards the plane of second direction, and this weld layer is exposed.
88. the manufacture method of the semiconductor chip package of 7 described welding ends tool metallic walls is characterized in that according to Claim 8, this weld layer directly forms this welding ends.
89. the manufacture method of the semiconductor chip package of 7 described welding ends tool metallic walls according to Claim 8, it is characterized in that, the mode that this welding ends forms is included in and makes a soldering tin material be deposited on this weld layer after this insulated substrate, metallic walls and welding ends are ground, and this soldering tin material is refluxed with weld layer form this welding ends.
90. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 61 metallic walls is characterized in that, this semiconductor chip package is the encapsulation of first level.
91. the manufacture method of the semiconductor chip package of a welding ends tool metallic walls comprises at least:
A, provide a metal substrate that comprises corresponding first plane and second plane, wherein first plane of this metal substrate is towards first direction, and second plane of this metal substrate is towards second direction, and this second direction is opposite with first direction;
B, form one and wind the line on first plane of metal substrate, wherein should coiling and first plane contact of this metal substrate, and with second planar isolated of this metal substrate;
C, utilize first wet chemical etch that this metal substrate is carried out etching, therefore form a via in metal substrate, this via is extended in this metal substrate toward its first plane by second plane of this metal substrate;
D, formation one metallic walls are on this metal substrate, wherein, metal substrate in this metallic walls and this via contacts, this metallic walls is extended in this metal substrate toward its first plane by second plane of this metal substrate, and this metallic walls comprises a hole, this hole is extended in this metal substrate toward its first plane by second plane of this metal substrate, and is covered on the first direction by this metallic walls, and comprises an opening towards second direction;
E, form a weld layer, this weld layer contact with metallic walls in this hole, and with this isolation that winds the line;
F, mechanically connect the semiconductor chip to this metal substrate and coiling, wherein this semiconductor chip comprises a conductive connecting pin;
G, formation a junction, this connecting portion is electrically connected with this coiling and conductive connecting pin;
H, form a sealant in connecting this semiconductor chip to this metal substrate and coiling back, wherein, the sealing agent contacts with this semiconductor chip, and vertically extend toward first direction from this semiconductor chip, metal substrate and coiling, and this metal substrate vertically extends toward second direction from this semiconductor chip and coiling;
I, after forming this metallic walls, weld layer and sealant, utilize second wet chemical etch to this metal substrate etching;
J, after this metal substrate utilizes second wet chemical etch to carry out etching, form an insulated substrate, this insulated substrate contacts with this coiling, metallic walls and weld layer, and covers this coiling, metallic walls and weld layer on second direction;
K, remove a part insulated substrate, make this insulated substrate can't cover this weld layer on second direction; And
L, provide a welding ends, this welding ends contacts with metallic walls in this hole, and comprises this weld layer.
92. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls, it is characterized in that, the generation type of this coiling comprises that forming a plating is shielded from this metal substrate, wherein this plating shielding comprises an opening, and this opening exposes the metal substrate of a part; And the opening that passes this plating shielding is with the expose portion of this wire winded electroplating in this metal substrate.
93. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that, the formation method of this metallic walls and weld layer comprises the following steps and at least according to order:
A, pass an opening of electroplating shielding this metallic walls is plated on this metal substrate, and enter this via;
B, a tin cream is deposited on this metallic walls; And
C, this tin cream is refluxed, therefore form this weld layer.
94. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that this welding ends is this weld layer.
95. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls, it is characterized in that, after the mode that this welding ends forms is included in and utilizes second wet chemical etch that this metal substrate is carried out etching, one soldering tin material is deposited on this weld layer, this soldering tin material and weld layer are refluxed together, form this welding ends.
96. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls, it is characterized in that, this semiconductor chip and metal substrate and coiling ways of connecting comprise an adhesive agent are placed between this semiconductor chip and metal substrate, make this adhesive agent sclerosis then.
97. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that, the mode that this connecting portion forms comprises provides a routing between this coiling and conductive connecting pin.
98. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, and this coiling is exposed.
99. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 98 metallic walls, it is characterized in that, this metal substrate utilizes this first wet chemical etch to carry out etching and forms this via, this via is that a perforation and extension penetrate this metal substrate, and this coiling is exposed; And this metal substrate utilizes second wet chemical etch to carry out etching, removes the contact area between this metal substrate and winding department and this metal substrate and metallic walls.
100. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 99 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes this metal substrate.
101. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 98 metallic walls, it is characterized in that, this metal substrate utilizes this first wet chemical etch to carry out etching and forms this via, and this via is a recess and extends this metal substrate but do not penetrate; And this metal substrate utilizes second wet chemical etch to carry out etching, form a metal column from the not etching part of this metal substrate, the not etching part of this metal substrate is that this metal column contacts with this coiling and metallic walls by the definition of this metallic walls, and makes between this coiling and metallic walls and be electrically connected.
102. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 101 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes most metal substrate.
103. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 101 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes in the intramarginal metal substrate of this conductive connecting pin.
104. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 101 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes in the intramarginal metal substrate of this semiconductor chip.
105. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 98 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and the coiling tool that this coiling and other are contacted with metal substrate is isolated electrically.
106. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 98 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and this conductive connecting pin and other conductive connecting pin tool on semiconductor chip is isolated electrically.
107. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that, this metallic walls is connecting the formation to this metal substrate and the coiling of this semiconductor chip.
108. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that, this metallic walls forms connecting this semiconductor chip to this metal substrate and coiling back.
109. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that, this weld layer is connecting the formation to this metal substrate and the coiling of this semiconductor chip.
110. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that, this weld layer forms connecting this semiconductor chip to this metal substrate and coiling back.
111. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that this connecting portion utilizes second wet chemical etch to carry out forming before the etching at this metal substrate.
112. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that this connecting portion utilizes second wet chemical etch to carry out forming after the etching at this metal substrate.
113. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that, the sealing agent utilizes the metaideophone forming process to form.
114. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that, this insulated substrate that removes a part makes this metallic walls and weld layer expose in second direction, but does not make this coiling exposure.
115. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 114 metallic walls is characterized in that, this insulated substrate that removes a part is to remove to cover this metallic walls and the insulated substrate of weld layer on second direction.
116. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 115 metallic walls is characterized in that, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate.
117. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 116 metallic walls, it is characterized in that, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate, but do not grind this metallic walls and weld layer, then grind this insulated substrate, metallic walls and weld layer, laterally be arranged in one up to this insulated substrate, metallic walls and weld layer then and stop to grind during towards the plane of second direction, and this metallic walls and weld layer are exposed.
118. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 117 metallic walls is characterized in that this weld layer directly forms this welding ends.
119. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 117 metallic walls, it is characterized in that, the mode that this welding ends forms is included in and makes a soldering tin material be deposited on this weld layer after this insulated substrate, metallic walls and welding ends are ground, and this soldering tin material is refluxed with weld layer form this welding ends.
120. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 91 metallic walls is characterized in that, this semiconductor chip package is the encapsulation of first level.
121. the manufacture method of the semiconductor chip package of a welding ends tool metallic walls comprises at least:
A, provide a metal substrate that comprises corresponding first plane and second plane, wherein first plane of this metal substrate is towards first direction, and second plane of this metal substrate is towards second direction, and this second direction is opposite with first direction;
B, form one and wind the line on first plane of metal substrate, wherein should coiling and first plane contact of this metal substrate, and with second planar isolated of this metal substrate;
C, utilize first wet chemical etch that this metal substrate is carried out etching, therefore form a via in this metal substrate, this via is extended in this metal substrate toward its first plane by second plane of this metal substrate;
D, formation one metallic walls are on this metal substrate, wherein, metal substrate in this metallic walls and this via contacts, this metallic walls is extended in this metal substrate toward its first plane by second plane of this metal substrate, and this metallic walls comprises a hole, this hole is extended in this metal substrate toward its first plane by second plane of this metal substrate, and is covered on the first direction by this metallic walls, and comprises an opening towards second direction;
E, form a weld layer, this weld layer contact with metallic walls in this hole, and with this isolation that winds the line;
F, mechanically connect the semiconductor chip to this metal substrate, coiling, metallic walls and weld layer, wherein this semiconductor chip comprises a conductive connecting pin;
G, formation a junction, this connecting portion is electrically connected with this coiling and conductive connecting pin;
H, to this metal substrate, coiling, metallic walls and welding ends, form a sealant in connecting this semiconductor chip, wherein, the sealing agent contacts with this semiconductor chip, and vertically extend toward first direction from this semiconductor chip, metal substrate, coiling, metallic walls and weld layer, and this metal substrate vertically extends toward second direction from this semiconductor chip and coiling;
I, after forming the sealing agent, utilize second wet chemical etch to this metal substrate etching, make this coiling exposure;
J, after this metal substrate utilizes second wet chemical etch to carry out etching, form an insulated substrate, this insulated substrate contacts with this coiling, metallic walls and weld layer, and covers this coiling, metallic walls and weld layer on second direction;
K, remove a part insulated substrate, make this insulated substrate can't cover this weld layer on second direction; And
L, provide a welding ends, this welding ends contacts with metallic walls in this hole, and comprises this weld layer.
122. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls, it is characterized in that, the generation type of this coiling comprises that forming a plating is shielded from this metal substrate, wherein this plating shielding comprises an opening, and this opening exposes the metal substrate of a part; And the opening that passes this plating shielding is with the expose portion of this wire winded electroplating in this metal substrate.
123. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls is characterized in that, the formation method of this metallic walls and weld layer comprises the following steps and at least according to order:
A, pass an opening of electroplating shielding this metallic walls is plated on this metal substrate, and enter this via;
B, a tin cream is deposited on this metallic walls; And
C, this tin cream is refluxed, therefore form this weld layer.
124. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls is characterized in that this welding ends is this weld layer.
125. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls, it is characterized in that, after the mode that this welding ends forms is included in and utilizes second wet chemical etch that this metal substrate is carried out etching, one soldering tin material is deposited on this weld layer, this soldering tin material and weld layer are refluxed together, form this welding ends.
126. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls, it is characterized in that, this metal substrate utilizes this first wet chemical etch to carry out etching and forms this via, this via is that a perforation and extension penetrate this metal substrate, and this coiling is exposed; And this metal substrate utilizes second wet chemical etch to carry out etching, removes the contact area between this metal substrate and winding department and this metal substrate and metallic walls.
127. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 126 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes this metal substrate.
128. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls, it is characterized in that, this metal substrate utilizes this first wet chemical etch to carry out etching and forms this via, and this via is a recess and extends this metal substrate but do not penetrate; And this metal substrate utilizes second wet chemical etch to carry out etching, form a metal column from the not etching part of this metal substrate, the not etching part of this metal substrate is that this metal column contacts with this coiling and metallic walls by the definition of this metallic walls, and makes between this coiling and metallic walls and be electrically connected.
129. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 128 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes most metal substrate.
130. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and the coiling tool that this coiling and other are contacted with metal substrate is isolated electrically.
131. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and this conductive connecting pin and other conductive connecting pin tool on semiconductor chip is isolated electrically.
132. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls is characterized in that this connecting portion utilizes second wet chemical etch to carry out forming before the etching at this metal substrate.
133. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls is characterized in that this connecting portion utilizes second wet chemical etch to carry out forming after the etching at this metal substrate.
134. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls is characterized in that, this insulated substrate that removes a part makes this metallic walls and weld layer expose in second direction, but does not make this coiling exposure.
135. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 134 metallic walls is characterized in that, this insulated substrate that removes a part is to remove to cover this metallic walls and the insulated substrate of weld layer on second direction.
136. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 135 metallic walls is characterized in that, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate.
137. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 136 metallic walls, it is characterized in that, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate, but do not grind this metallic walls and weld layer, then grind this insulated substrate, metallic walls and weld layer, laterally be arranged in one up to this insulated substrate, metallic walls and weld layer then and stop to grind during towards the plane of second direction, and this metallic walls and weld layer are exposed.
138. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 137 metallic walls is characterized in that this weld layer directly forms this welding ends.
139. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 137 metallic walls, it is characterized in that, the mode that this welding ends forms is included in and makes a soldering tin material be deposited on this weld layer after this insulated substrate, metallic walls and welding ends are ground, and this soldering tin material is refluxed with weld layer form this welding ends.
140. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 121 metallic walls is characterized in that, this semiconductor chip package is the encapsulation of first level.
141. the manufacture method of the semiconductor chip package of a welding ends tool metallic walls, comprise the following steps at least and according to the order:
A, provide a metal substrate that comprises corresponding first plane and second plane, wherein first plane of this metal substrate is towards first direction, and second plane of this metal substrate is towards second direction, and this second direction is opposite with first direction;
B, form one and wind the line on first plane of metal substrate, wherein should coiling and first plane contact of this metal substrate, and with second planar isolated of this metal substrate;
C, utilize first wet chemical etch that this metal substrate is carried out etching, therefore form a via in this metal substrate, this via is extended in this metal substrate toward its first plane by second plane of this metal substrate;
D, formation one metallic walls are on this metal substrate, wherein, metal substrate in this metallic walls and this via contacts, this metallic walls is extended in this metal substrate toward its first plane by second plane of this metal substrate, and this metallic walls comprises a hole, this hole is extended in this metal substrate toward its first plane by second plane of this metal substrate, and is covered on the first direction by this metallic walls, and comprises an opening towards second direction;
E, mechanically connect the semiconductor chip to this metal substrate, coiling and metallic walls, wherein this semiconductor chip comprises a conductive connecting pin;
F, formation a junction, this connecting portion is electrically connected with this coiling and conductive connecting pin;
G, to this metal substrate, coiling and metallic walls, form a sealant in connecting this semiconductor chip, wherein, the sealing agent contacts with this semiconductor chip, and vertically extend toward first direction from this semiconductor chip, metal substrate, coiling and metallic walls, and this metal substrate vertically extends toward second direction from this semiconductor chip and coiling;
H, after forming the sealing agent, form a weld layer, this weld layer contact with metallic walls in this hole, and with this isolation that winds the line;
I, after forming this weld layer, utilize second wet chemical etch to this metal substrate etching, make this coiling exposure;
J, after this metal substrate utilizes second wet chemical etch to carry out etching, form an insulated substrate, this insulated substrate contacts with this coiling, metallic walls and weld layer, and covers this coiling, metallic walls and weld layer on second direction;
K, remove a part insulated substrate, make this insulated substrate can't cover this weld layer on second direction; And
L, provide a welding ends, this welding ends contacts with metallic walls in this hole, and comprises this weld layer.
142. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls, it is characterized in that, the generation type of this coiling comprises that forming a plating is shielded from this metal substrate, wherein this plating shielding comprises an opening, and this opening exposes the metal substrate of a part; And the opening that passes this plating shielding is with the expose portion of this wire winded electroplating in this metal substrate.
143. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls is characterized in that, the formation method of this metallic walls and weld layer comprises the following steps and at least according to order:
A, pass an opening of electroplating shielding this metallic walls is plated on this metal substrate, and enter this via;
B, a tin cream is deposited on this metallic walls; And
C, this tin cream is refluxed, therefore form this weld layer.
144. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls is characterized in that this welding ends is this weld layer.
145. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls, it is characterized in that, after the mode that this welding ends forms is included in and utilizes second wet chemical etch that this metal substrate is carried out etching, one soldering tin material is deposited on this weld layer, this soldering tin material and weld layer are refluxed together, form this welding ends.
146. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls, it is characterized in that, this metal substrate utilizes this first wet chemical etch to carry out etching and forms this via, this via is that a perforation and extension penetrate this metal substrate, and this coiling is exposed; And this metal substrate utilizes second wet chemical etch to carry out etching, removes the contact area between this metal substrate and winding department and this metal substrate and metallic walls.
147. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 146 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes this metal substrate.
148. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls, it is characterized in that, this metal substrate utilizes this first wet chemical etch to carry out etching and forms this via, and this via is a recess and extends this metal substrate but do not penetrate; And this metal substrate utilizes second wet chemical etch to carry out etching, form a metal column from the not etching part of this metal substrate, the not etching part of this metal substrate is that this metal column contacts with this coiling and metallic walls by the definition of this metallic walls, and makes between this coiling and metallic walls and be electrically connected.
149. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 148 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes most metal substrate.
150. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and the coiling tool that this coiling and other are contacted with metal substrate is isolated electrically.
151. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and this conductive connecting pin and other conductive connecting pin tool on semiconductor chip is isolated electrically.
152. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls is characterized in that this connecting portion utilizes second wet chemical etch to carry out forming before the etching at this metal substrate.
153. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls is characterized in that this connecting portion utilizes second wet chemical etch to carry out forming after the etching at this metal substrate.
154. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls is characterized in that, this insulated substrate that removes a part makes this metallic walls and weld layer expose in second direction, but does not make this coiling exposure.
155. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 154 metallic walls is characterized in that, this insulated substrate that removes a part is to remove to cover this metallic walls and the insulated substrate of weld layer on second direction.
156. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 155 metallic walls is characterized in that, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate.
157. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 156 metallic walls, it is characterized in that, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate, but do not grind this metallic walls and weld layer, then grind this insulated substrate, metallic walls and weld layer, laterally be arranged in one up to this insulated substrate, metallic walls and weld layer then and stop to grind during towards the plane of second direction, and this metallic walls and weld layer are exposed.
158. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 157 metallic walls is characterized in that this weld layer directly forms this welding ends.
159. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 157 metallic walls, it is characterized in that, the mode that this welding ends forms is included in and makes a soldering tin material be deposited on this weld layer after this insulated substrate, metallic walls and welding ends are ground, and this soldering tin material is refluxed with weld layer form this welding ends.
160. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 141 metallic walls is characterized in that, this semiconductor chip package is the encapsulation of first level.
161. the manufacture method of the semiconductor chip package of a welding ends tool metallic walls, comprise the following steps at least and according to the order:
A, provide a metal substrate that comprises corresponding first plane and second plane, wherein first plane of this metal substrate is towards first direction, and second plane of this metal substrate is towards second direction, and this second direction is opposite with first direction;
B, form one and wind the line on first plane of metal substrate, wherein should coiling and first plane contact of this metal substrate, and with second planar isolated of this metal substrate;
C, mechanically connect the semiconductor chip to this metal substrate and coiling, wherein this semiconductor chip comprises a conductive connecting pin;
D, formation a junction, this connecting portion is electrically connected with this coiling and conductive connecting pin;
E, form a sealant in connecting this semiconductor chip to this metal substrate and coiling back, wherein, the sealing agent contacts with this semiconductor chip, and vertically extend toward first direction from this semiconductor chip, metal substrate and coiling, and this metal substrate vertically extends toward second direction from this semiconductor chip and coiling;
F, after forming sealant, utilize first wet chemical etch that this metal substrate is carried out etching, therefore in this metal substrate, form a via, this via is extended in this metal substrate toward its first plane by second plane of this metal substrate;
G, formation one metallic walls are on this metal substrate, wherein, metal substrate in this metallic walls and this via contacts, this metallic walls is extended in this metal substrate toward its first plane by second plane of this metal substrate, and this metallic walls comprises a hole, this hole is extended in this metal substrate toward its first plane by second plane of this metal substrate, and is covered on the first direction by this metallic walls, and comprises an opening towards second direction;
H, form a weld layer, this weld layer contact with metallic walls in this hole, and with this isolation that winds the line;
I, after forming this weld layer, utilize second wet chemical etch to this metal substrate etching, make this coiling exposure;
J, after this metal substrate utilizes second wet chemical etch to carry out etching, form an insulated substrate, this insulated substrate contacts with this coiling, metallic walls and weld layer, and covers this coiling, metallic walls and weld layer on second direction;
K, remove a part insulated substrate, make this insulated substrate can't cover this weld layer on second direction; And
L, provide a welding ends, this welding ends contacts with metallic walls in this hole, and comprises this weld layer.
162. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls, it is characterized in that, the generation type of this coiling comprises that forming a plating is shielded from this metal substrate, wherein this plating shielding comprises an opening, and this opening exposes the metal substrate of a part; And the opening that passes this plating shielding is with the expose portion of this wire winded electroplating in this metal substrate.
163. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls is characterized in that, the formation method of this metallic walls and weld layer comprises the following steps and at least according to order:
A, pass an opening of electroplating shielding this metallic walls is plated on this metal substrate, and enter this via;
B, a tin cream is deposited on this metallic walls; And
C, this tin cream is refluxed, therefore form this weld layer.
164. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls is characterized in that this welding ends is this weld layer.
165. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls, it is characterized in that, after the mode that this welding ends forms is included in and utilizes second wet chemical etch that this metal substrate is carried out etching, one soldering tin material is deposited on this weld layer, this soldering tin material and weld layer are refluxed together, form this welding ends.
166. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls, it is characterized in that, this metal substrate utilizes this first wet chemical etch to carry out etching and forms this via, this via is that a perforation and extension penetrate this metal substrate, and this coiling is exposed; And this metal substrate utilizes second wet chemical etch to carry out etching, removes the contact area between this metal substrate and winding department and this metal substrate and metallic walls.
167. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 166 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes this metal substrate.
168. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls, it is characterized in that, this metal substrate utilizes this first wet chemical etch to carry out etching and forms this via, and this via is a recess and extends this metal substrate but do not penetrate; And this metal substrate utilizes second wet chemical etch to carry out etching, form a metal column from the not etching part of this metal substrate, the not etching part of this metal substrate is that this metal column contacts with this coiling and metallic walls by the definition of this metallic walls, and makes between this coiling and metallic walls and be electrically connected.
169. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 168 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes most metal substrate.
170. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and the coiling tool that this coiling and other are contacted with metal substrate is isolated electrically.
171. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and this conductive connecting pin and other conductive connecting pin tool on semiconductor chip is isolated electrically.
172. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls is characterized in that this connecting portion utilizes second wet chemical etch to carry out forming before the etching at this metal substrate.
173. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls is characterized in that this connecting portion utilizes second wet chemical etch to carry out forming after the etching at this metal substrate.
174. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls is characterized in that, this insulated substrate that removes a part makes this metallic walls and weld layer expose in second direction, but does not make this coiling exposure.
175. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 174 metallic walls is characterized in that, this insulated substrate that removes a part is to remove to cover this metallic walls and the insulated substrate of weld layer on second direction.
176. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 175 metallic walls is characterized in that, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate.
177. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 176 metallic walls, it is characterized in that, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate, but do not grind this metallic walls and weld layer, then grind this insulated substrate, metallic walls and weld layer, laterally be arranged in one up to this insulated substrate, metallic walls and weld layer then and stop to grind during towards the plane of second direction, and this metallic walls and weld layer are exposed.
178. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 177 metallic walls is characterized in that this weld layer directly forms this welding ends.
179. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 178 metallic walls, it is characterized in that, the mode that this welding ends forms is included in and makes a soldering tin material be deposited on this weld layer after this insulated substrate, metallic walls and welding ends are ground, and this soldering tin material is refluxed with weld layer form this welding ends.
180. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 161 metallic walls is characterized in that, this semiconductor chip package is the encapsulation of first level.
181. the manufacture method of the semiconductor chip package of a welding ends tool metallic walls comprises at least:
A, provide a metal substrate that comprises corresponding first plane and second plane, wherein first plane of this metal substrate is towards first direction, and second plane of this metal substrate is towards second direction, and this second direction is opposite with first direction;
B, form one and wind the line on first plane of metal substrate, wherein should coiling and first plane contact of this metal substrate, and with second planar isolated of this metal substrate;
C, utilize first wet chemical etch that this metal substrate is carried out etching, therefore form a perforation in this metal substrate, first and second interplanar of this metal substrate is passed in this perforation, makes this coiling exposure;
D, formation one metallic walls are in this metal substrate and coiling, wherein, metal substrate in this metallic walls and this perforation and coiling contact, this metallic walls is extended first and second interplanar that penetrates this metal substrate, and this metallic walls comprises a hole, this hole is extended in this metal substrate toward its first plane by second plane of this metal substrate, and is covered on the first direction by this metallic walls, and comprises an opening towards second direction;
E, form a weld layer, this weld layer contact with metallic walls in this hole, and with this isolation that winds the line;
F, mechanically connect the semiconductor chip to this metal substrate and coiling, wherein this semiconductor chip comprises a conductive connecting pin;
G, formation a junction, this connecting portion is electrically connected with this coiling and conductive connecting pin;
H, form a sealant in connecting this semiconductor chip to this metal substrate and coiling back, wherein, the sealing agent contacts with this semiconductor chip, and vertically extend toward first direction from this semiconductor chip, metal substrate and coiling, and this metal substrate vertically extends toward second direction from this semiconductor chip and coiling;
I, after forming this metallic walls, weld layer and sealant, utilize second wet chemical etch to this metal substrate etching, therefore remove the contact area between this metal substrate and winding department and this metal substrate and metallic walls, and make this coiling exposure;
J, after this metal substrate utilizes second wet chemical etch to carry out etching, form an insulated substrate, this insulated substrate contacts with this coiling, metallic walls and weld layer, and covers this coiling, metallic walls and weld layer on second direction;
K, remove a part insulated substrate, make this insulated substrate can't cover this weld layer on second direction; And
L, provide a welding ends, this welding ends contacts with metallic walls in this hole, and comprises this weld layer.
182. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 181 metallic walls, it is characterized in that, the generation type of this coiling, metallic walls and welding ends comprises this wire winded electroplating on this metal substrate, again this metallic walls is plated on this metal substrate and coiling, one tin cream is deposited on the metallic walls, this tin cream is refluxed, therefore form this weld layer.
183. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 181 metallic walls is characterized in that this welding ends is this weld layer.
184. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 181 metallic walls, it is characterized in that, after the mode that this welding ends forms is included in and utilizes second wet chemical etch that this metal substrate is carried out etching, one soldering tin material is deposited on this weld layer, this soldering tin material and weld layer are refluxed together, form this welding ends.
185. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 181 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes this metal substrate.
186. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 181 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and the coiling tool that this coiling and other are contacted with metal substrate isolates electrically, and this conductive connecting pin and other conductive connecting pin tool on semiconductor chip is isolated electrically.
187. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 181 metallic walls, it is characterized in that, further comprise and form this metallic walls, then form this weld layer, connect this semiconductor chip then to this metal substrate, coiling, metallic walls and weld layer, and form the sealing agent.
188. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 181 metallic walls, it is characterized in that, further comprise and form this metallic walls, then connect this semiconductor chip to this metal substrate, coiling and metallic walls, form the sealing agent then, and form this weld layer.
189. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 181 metallic walls, it is characterized in that, further comprise and connect this semiconductor chip, then form the sealing agent to this metal substrate and coiling, form this metallic walls then, and form this weld layer.
190. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 181 metallic walls, it is characterized in that, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate, but do not grind this metallic walls and weld layer, then grind this insulated substrate, metallic walls and weld layer, laterally be arranged in one up to this insulated substrate, metallic walls and weld layer then and stop to grind during towards the plane of second direction, and this metallic walls and weld layer are exposed.
191. the manufacture method of the semiconductor chip package of a welding ends tool metallic walls comprises at least:
A, provide a metal substrate that comprises corresponding first plane and second plane, wherein first plane of this metal substrate is towards first direction, and second plane of this metal substrate is towards second direction, and this second direction is opposite with first direction;
B, form one and wind the line on first plane of metal substrate, wherein should coiling and first plane contact of this metal substrate, and with second planar isolated of this metal substrate;
C, utilize first wet chemical etch that this metal substrate is carried out etching, therefore in this metal substrate, form a recess, this recess is extended to toward its first plane in this metal substrate by second plane of this metal substrate but does not penetrate, and with second planar isolated of this metal substrate;
D, formation one metallic walls are in this metal substrate and coiling, wherein, metal substrate in this metallic walls and this recess contacts, this metallic walls is extended to toward its first plane in this metal substrate by second plane of this metal substrate but does not penetrate, and first planar isolated of this metallic walls and this metal substrate and comprise a hole, this hole is extended in this metal substrate toward its first plane by second plane of this metal substrate, and be covered on the first direction, and comprise an opening towards second direction by this metallic walls;
E, form a weld layer, this weld layer contact with metallic walls in this hole, and with this isolation that winds the line;
F, mechanically connect the semiconductor chip to this metal substrate and coiling, wherein this semiconductor chip comprises a conductive connecting pin;
G, formation a junction, this connecting portion is electrically connected with this coiling and conductive connecting pin;
H, form a sealant in connecting this semiconductor chip to this metal substrate and coiling back, wherein, the sealing agent contacts with this semiconductor chip, and vertically extend toward first direction from this semiconductor chip, metal substrate and coiling, and this metal substrate vertically extends toward second direction from this semiconductor chip and coiling;
I, after forming this metallic walls, weld layer and sealant, utilize second wet chemical etch to this metal substrate etching, and form a metal column from the not etching part of this metal substrate, the not etching part of this metal substrate is by this metallic walls definition, this metal column contacts with this coiling and metallic walls, and make between this coiling and metallic walls and be electrically connected, and isolate with this weld layer, make this coiling exposure;
J, after this metal substrate utilizes second wet chemical etch to carry out etching, form an insulated substrate, this insulated substrate contacts with this coiling, metallic walls, metal column and weld layer, and covers this coiling, metallic walls, metal column and weld layer on second direction;
K, remove a part insulated substrate, make this insulated substrate can't cover this weld layer on second direction; And
L, provide a welding ends, this welding ends contacts with metallic walls in this hole, and comprises this weld layer.
192. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 191 metallic walls, it is characterized in that, the generation type of this coiling, metallic walls and welding ends comprises this wire winded electroplating on this metal substrate, again this metallic walls is plated on this metal substrate and coiling, one tin cream is deposited on the metallic walls, this tin cream is refluxed, therefore form this weld layer.
193. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 191 metallic walls is characterized in that this welding ends is this weld layer.
194. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 191 metallic walls, it is characterized in that, after the mode that this welding ends forms is included in and utilizes second wet chemical etch that this metal substrate is carried out etching, one soldering tin material is deposited on this weld layer, this soldering tin material and weld layer are refluxed together, form this welding ends.
195. the manufacture method according to the semiconductor chip package of the described welding ends tool of claim 191 metallic walls is characterized in that this metal substrate utilizes this second wet chemical etch to carry out etching, removes most metal substrate.
196. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 191 metallic walls, it is characterized in that, this metal substrate utilizes second wet chemical etch to carry out etching, and the coiling tool that this coiling and other are contacted with metal substrate isolates electrically, and this conductive connecting pin and other conductive connecting pin tool on semiconductor chip is isolated electrically.
197. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 191 metallic walls, it is characterized in that, further comprise and form this metallic walls, then form this weld layer, connect this semiconductor chip then to this metal substrate, coiling, metallic walls and weld layer, and form the sealing agent.
198. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 191 metallic walls, it is characterized in that, further comprise and form this metallic walls, then connect this semiconductor chip to this metal substrate, coiling and metallic walls, form the sealing agent then, and form this weld layer.
199. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 191 metallic walls, it is characterized in that, further comprise and connect this semiconductor chip, then form the sealing agent to this metal substrate and coiling, form this metallic walls then, and form this weld layer.
200. manufacture method according to the semiconductor chip package of the described welding ends tool of claim 191 metallic walls, it is characterized in that, this insulated substrate that removes a part utilizes lapping mode to grind this insulated substrate, but do not grind this metallic walls and weld layer, then grind this insulated substrate, metallic walls and weld layer, laterally be arranged in one up to this insulated substrate, metallic walls and weld layer then and stop to grind during towards the plane of second direction, and this metallic walls and weld layer are exposed.
CNB2006101032946A 2005-08-31 2006-07-24 Method of making a semiconductor chip packaging structure with a metal containment wall and a solder terminal Expired - Fee Related CN100440469C (en)

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US10283471B1 (en) * 2017-11-06 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Micro-connection structure and manufacturing method thereof

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