CN100463186C - 用于半导体元件的电容器及其制造方法 - Google Patents

用于半导体元件的电容器及其制造方法 Download PDF

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CN100463186C
CN100463186C CNB2005101180892A CN200510118089A CN100463186C CN 100463186 C CN100463186 C CN 100463186C CN B2005101180892 A CNB2005101180892 A CN B2005101180892A CN 200510118089 A CN200510118089 A CN 200510118089A CN 100463186 C CN100463186 C CN 100463186C
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oxynitride film
film
capacitor
yttrium
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吴平源
金愚镇
吴勋静
尹孝根
尹孝燮
催佰一
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SK Hynix Inc
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Abstract

本发明公开一种用于半导体元件的电容器及该电容器的制造方法，所述电容器包括：形成在半导体衬底的预定下结构上的下电极；形成在下电极上具有低漏电流特性的氮氧化铝膜；形成在氮氧化铝膜上，且具有高于氮氧化铝膜的介电常数的氮氧化钇膜；及形成在氮氧化钇膜上的上电极。根据本发明，即使当半导体元件的集成度增加时，电容器的表面积会减少，但是藉由使用低漏电流特性的AlON膜和高电容特性的YON膜的双层膜，当作电容器的电介质膜，也可以得到具有高电容和低漏电流特性的电容器。

Description

用于半导体元件的电容器及其制造方法
技术领域
本发明涉及一种用于半导体元件的电容器及其制造方法，尤其是具有低漏电流特性和高电容的半导体元件的电容器，及其制造方法。
背景技术
一般而言，用于半导体元件的电容器应该具有高于预定值的电容，而且为了增加半导体元件的刷新时间，尤其是DRAM或类似元件，电容器已持续研究和发展，使具有更低的漏电流特性。
另一方面，随着半导体元件的集成性越高，被半导体元件各区所占用的表面积会逐渐减少。因此，用以形成半导体元件的电容器的表面积也会减少，使得难以获得足够的电容和低漏电流特性。
下面，将参考附图，详细说明用于半导体元件的现有技术电容器的问题，及其制造方法。
图1a到图1g为电容器的传统制造工艺的横截面图。参考这些图式，下面将说明用于半导体元件的现有技术电容器的问题，及其制造方法。
首先，如图1a所示，在其中已藉由元件隔离膜(未图示)界定有源区的半导体衬底(未图示)上，形成的预定下结构1上方，形成位线电极2结构和类似结构。
接着，如图1b所示，在上述结构的上部的整个表面上，沉积由氧化物膜或类似材料所制成的层间绝缘膜3，然后在层间绝缘膜3之上，形成当作阻挡层的氮化物膜4。
然后，如图1c所示，藉由光蚀刻工艺，蚀刻氮化物膜4和层间绝缘膜3，以形成接触孔。接触孔曝露下结构1的表面，尤其是连接到半导体衬底(未图示)的接面的栓塞(未图示)的表面，其对应位在位线电极2之间的储存节点。
接着，如图1d所示，在结果材料的整个表面上，沉积导电多晶硅，使接触孔被多晶硅埋入。然后，对结果材料执行平坦化工艺，直到曝露出氮化物膜4，于是在接触孔当中形成接触栓塞5。
其次，如图1e所示，在结构上部的整个表面上，沉积氧化物膜6，然后再藉由光蚀刻工艺，蚀刻预定区域的氧化物膜6，以曝露接触栓塞5的上部，及其周边部分的预定区域的氮化物膜4。要被蚀刻掉的氧化物膜6的区域，直接关系着要在后面形成的电容器的下电极表面积，而且考虑与相邻单胞的电容器的间隔距离，其要尽可能的宽。
然后，在结果材料的整个表面上，沉积多晶硅膜，之后，藉由化学机械抛光(CMP)或类似方法，自沉积的多晶硅膜移除沉积在氧化物膜6上方的部分。然后，选择性蚀刻和移除氧化物膜6剩余的部分，于是形成电容器下电极7，如图1f所示。
其次，如图1g所示，在结构的上部之上，沉积电介质膜8。至于电介质膜，其被形成氧化物膜-氮化物膜-氧化物膜的多重层(即，ONO膜)。然后，在结果材料上形成电容器上电极9，于是完成电容器的制作。
但是，包括使用现有技术的单一ONO膜的电介质膜8的电容器结构，无法满足要有足够的电容和低漏电流特性的要求。
因此，由电介质膜所形成的AlON(氮氧化铝)已被用以改善漏电流特性。但是，在此情形下，虽然其界面特性非常好，因此漏电流特性很好，但是由于低电容特性，所以不能满足最近电容器需要高电容的要求。
在此情形下，当半导体元件的集成度增加时，使用单一电介质膜的电容器，无法满足电容器应具有电容和漏电流特性。
发明内容
本发明的目的是要提供一种用于半导体元件的电容器，一种即使在小的放置表面积上，也还具有低漏电流特性和高电容的电容器，及其制造方法。
为了达成本发明上述的目的，本发明提供一种用于半导体元件的电容器，其包括：形成在半导体衬底的预定下结构上的下电极；形成在下电极上且具有低漏电流特性的第一电介质膜；形成在第一电介质膜上，且具有高于第一电介质膜的介电常数的第二电介质膜；及形成在第二电介质膜上的上电极。
第一电介质膜为AlON(氮氧化铝)膜，优选的厚度为50到150
Figure C200510118089D0005113515QIETU
。
第二电介质膜为YON(氮氧化钇)膜，优选的厚度为小于10
Figure C200510118089D0005113515QIETU
4。
下电极优选具有掺杂硅膜和未掺杂硅膜的双结构，而在第二电介质膜和上电极之间，优选包括当作阻挡层的TiN层。
此外，本发明还提供一种用于半导体元件的电容器的制造方法，其包括下列步骤：在半导体衬底的预定下结构上形成下电极；在下电极上，形成具有低漏电流特性的第一电介质膜；在第一电介质膜上，形成具有高于第一电介质膜的介电常数的第二电介质膜；及在第二电介质膜上形成上电极。
第一电介质膜为AlON(氮氧化铝)膜，优选的厚度为50到150
Figure C200510118089D0005113515QIETU
。
AlON膜可以藉由PECVD(等离子体增强式CVD)法沉积，其中沉积Al2O3时，使用(CH3)3Al当作来源材料，而使用H2O和NH3当作反应材料。
晶片温度宜为200到450℃，而沉积时的反应炉压力宜为0.1到1.0torr，以及H2O使用的流量宜为10到500sccm，而NH3使用的流量优选为10到500sccm。
本发明的制造方法优选还包括：在形成AlON膜之后，再执行N2O等离子体退火的步骤，以增加AlON膜的氮含量。
第二电介质膜是YON膜，优选的厚度为小于10
Figure C200510118089D0005113515QIETU
。YON膜可以藉由ALD(原子层沉积)法形成。
在使用ALD沉积时，优选地，当作来源气体的钇气体与当作反应材料的NH3气体和H2O气体，切换注入反应腔，而且在注入钇气体和NH3和H2O气体之间，提供惰性气体。
优选地，钇气体的注入时间、NH3和H2O气体的注入时间、和惰性气体的注入时间分别为0.1到10秒，NH3的流量为10到100sccm、H2O的流量为10到100sccm，而反应腔的温度则维持在250到350℃。
YON膜优选藉由ICE(离子化原子团束)沉积法形成。
本发明的制造方法优选还包括：在形成YON膜之后，再执行N2O等离子体退火的步骤，以增加YON膜的氮含量。
附图说明
藉由参考附图的优选实施例的详细说明，本发明上述的和其他的特征与优点将会变得更清楚，其中：
图1a到图1g为电容器的传统制造工艺的横截面图；及
图2a到图2h为说明根据本发明的一实施例，用于半导体元件的电容器的制造工艺横截面图。
附图标记说明
1 下结构             2 位线电极
3 层间绝缘膜         4 氮化物膜
5 接触栓塞           6 氧化物膜
7 下电极             8 电介质膜
9 上电极             101 下结构
102 位线电极         103 层间绝缘膜
104 氮化物膜         105 接触栓塞
106 氧化物膜         107 下电极
108 AlON膜           109 YON膜
110 阻挡层           111 上电极
具体实施方式
现在将参考本发明的实施例，详细说明本发明。实施例只是用以说明本发明，并非要局限本发明的范围。
图2a到图2h为说明根据本发明的一实施例，用于半导体元件的电容器的制造工艺横截面图。本发明将参考这些图式说明如下。
首先，如图2a所示，在其中已藉由元件隔离膜(未图示)形成有源区的半导体衬底(未图示)上，形成的预定下结构101上方，形成位线电极102结构和类似结构。接着，在结果材料的整个表面上，沉积由氧化物膜或类似材料所制成的层间绝缘膜102，然后在层间绝缘膜103之上，形成当作阻挡层的氮化物膜104。
然后，如图2b所示，藉由光蚀刻工艺，蚀刻氮化物膜104和层间绝缘膜103，以形成接触孔。接触孔A曝露下结构101的表面。尤其是连接到半导体衬底(未图示)的接面的栓塞(未图示)的表面，其对应位在位线电极102之间的储存节点。
接着，如图2c所示，在结果材料的整个表面上，沉积导电多晶硅，使接触孔A可被多晶硅埋入。然后，对结果材料执行平坦化工艺，直到曝露出氮化物膜104，于是在接触孔A当中形成接触栓塞105。
其次，如图2d所示，在结构上部的整个表面上，沉积氧化物膜106，然后再藉由光蚀刻工艺，蚀刻预定区域的氧化物膜106，以曝露接触栓塞105的上部，及其周边部分的预定区域的氮化物膜104。要被蚀刻掉的氧化物膜106的区域，直接关系着要在后面形成的电容器的下电极表面积，而且考虑与相邻单胞的电容器的间隔距离，其要尽可能的宽。氧化物膜106沉积的厚度为5,000到20,000
Figure C200510118089D0005113515QIETU
。
然后，在结果材料的整个表面上，沉积多晶硅膜，之后，藉由化学机械抛光(CMP)或类似方法，自沉积的多晶硅膜移除沉积在氧化物膜106上方的部分。然后，选择性蚀刻和移除氧化物膜106剩余的部分，于是形成电容器下电极107，如图2e所示。用以当作电容器下电极107的多晶硅膜，是在500到560℃的温度下，尤其是530℃，及在0.5到1.0torr的压力下，藉由沉积100到300
Figure C200510118089D0005113515QIETU
的掺杂硅膜，然后再沉积100到500
Figure C200510118089D0005113515QIETU
的未掺杂硅膜的两个沉积步骤所形成的。当沉积掺杂硅膜时，使用800到1,200sccm的SiH4和150到250sccm的PH3，而当沉积未掺杂硅膜时，使用800到1,200sccm的SiH4和0sccm的PH3。
其次，如图2f所示，在结果材料的上部之上，沉积具有致密的膜材料且造成低漏电流的AlON(氮氧化铝)膜108。因为AlON膜108因其致密的膜材料而展现良好的界面特性，所以可以抑制其和下电极107之间形成界面膜，于是可以抑制漏电流。此时，AlON膜108是使用PECVD(等离子体增强式CVD)法沉积。当使用PECVD法沉积时，晶片的温度为200到450℃，沉积时的反应炉压力为0.1到1.0torr，而且使用(CH3)3Al当作来源材料。在沉积Al2O3时，使用H2O和NH3当作反应材料。H2O使用的流量为10到500scmm，而NH3使用的流量为10到500scmm。AlON膜108要沉积的厚度为50到150
Figure C200510118089D0005113515QIETU
，而沉积时的RF功率为10到500W。此膜的厚度设定顾及介电常数和整个电介质膜的漏电流防止特性。若小于此范围，则漏电流防止特性会退化，但是若大于此范围，则介电常数会退化，因此不能展现足够的电容。
接着，对具有AlON膜108形成的结果材料执行退火工艺。在此退火工艺中，执行N2O等离子体退火，以增加AlON膜108的氮含量。此时，在快速热退火的情形下，N2O气体的流量为1到10slm，温度保持在700到850℃之间，而处理时间为60到180秒。因此，若氮的含量增加，则介电常数也会增加，而使膜材料变得更致密。
其次，如图2g所示，在AlON膜108的上部之上，沉积具有高介电常数的YON膜(氮氧化钇)109。因为YON膜109的介电常数约为25，因此具有很高的电容，所以其允许可以制成高电容电容器。就此点而言，YON膜109藉由ALD(原子层沉积法)形成，换言之，YON膜是藉由将当作来源气体的钇气体与当作反应材料的NH3气体和H2O气体，切换注入反应腔所沉积的，其中厚度为10
Figure C200510118089D0005113515QIETU
。在注入钇气体和NH3和H2O气体之间，提供惰性气体，如N2、Ar、He等，使各材料没有留下残留物。
在使用ALD沉积时，每个周期所沉积的薄膜都小于1
Figure C200510118089D0005113515QIETU
，一个周期由来源气体注入、惰性气体注入、及NH3和H2O气体注入所构成，而总厚度为10
Figure C200510118089D0005113515QIETU
的YON膜109则是藉由重复上述的周期所形成的。每一个反应材料的注入时间和惰性气体的注入时间分别为0.1到10秒。而且，当作反应气体的NH3的流量为10到100sccm，H2O的流量为10到100Ssccm，而反应腔的温度则维持在250到350℃。藉由重复上述周期而连续沉积的薄膜，在400到550℃的温度下，执行低温退火，以转变成单一膜。
在YON膜109的形成方面，可以采用ICE(离子化原子团束)沉积法。
如上的观察，在本发明中，藉由先在电容器下电极上形成AlON膜108，然后再在其上形成YON膜109所形成的双层结构电介质膜，可以减少电容器的漏电流和显著增加电容。换言之，因为先形成在下电极上的AlON膜108，因其致密的膜材料而展现良好的界面特性，所以可以抑制其和下电极107之间形成界面膜，于是可以抑制漏电流。此外，因为形成在AlON膜108上的YON膜109具有约为25的非常高的介电常数，所以其可以显著增加电容器的电容。因此，根据本发明的电容器的制造方法，藉由使用具有AlON膜108和YON膜109的双结构电介质膜，可以明显减少电容器的漏电流和显著增加电容器的电容。
再者，在使用藉由沉积在下电极上的YON膜当作单一电介质膜的案例中，此会在下电极的多晶硅和YON膜之间产生界面反应，而形成具有低介电常数的SiO2，于是造成YON膜的品质劣化。在本发明中，膜材料很致密的AlON膜108在YON膜109形成之前形成，于是可以抑制YON膜和下电极之间界面膜的形成，因此可以抑制YON膜109的品质劣化。
接着，对结果材料执行N2O等离子体退火，以增加YON膜109的氮含量。此时，在快速热退火的情形下，N2O气体的流量为1到10slm，温度保持在700到850℃之间，而处理时间为60到180秒。因此，若氮的含量增加，则介电常数也会增加，而使膜材料变得更致密。
其次，为了移除AlON膜108和YON膜109中的杂质，并保持增加的氮的含量，可以执行炉管真空N2退火。在炉管真空N2退火时，温度保持在500到650℃之间，而处理时间为5到60分钟。或者，可以执行快速热处理(RTP)，取代炉管真空N2退火。
接着，如图2h所示，在上述结构的整个表面上，沉积当作阻挡层110的TiN层，然后再在其上部的上沉积多晶硅，于是制成电容器上电极111。
如上述方法所形成的电容器，可用以当作DRAM的单胞电容器，及各种不同领域的半导体元件的电容器元件。
如上所述，根据本发明，即使当半导体元件的集成度增加时，电容器的表面积会减少，但是藉由使用低漏电流特性的AlON膜和高电容特性的YON膜的双层膜，当作电容器的电介质膜，也可以得到具有高电容和低漏电流特性的电容器。
此外，藉由透过分别增加具有低漏电流特性的AlON膜和具有高电容特性的YON膜中氮含量的额外工艺，改善电介质膜或类似材料的膜材料，及增加电容，本发明可以允许制造具有较高电容和较低漏电流特性的电容器。
本申请要求于2004年12月23日提交的韩国专利申请第2004-111387号的权益，引入其公开的全文作参照。

Claims (19)

1.一种用于半导体元件的电容器，包括：
在半导体衬底的预定下结构上由多晶硅形成的下电极；
形成在所述下电极上具有低漏电流特性的氮氧化铝膜；
形成在所述氮氧化铝膜上，且具有高于所述氮氧化铝膜的介电常数的氮氧化钇膜；及
形成在所述氮氧化钇膜上的上电极，
其中所述氮氧化铝膜防止所述氮氧化钇膜与所述下电极直接接触时引起的在所述下电极上形成的SiO2界面膜。
2.如权利要求1的电容器，其中所述氮氧化铝膜的厚度为50到150
Figure C200510118089C0002190243QIETU
。
3.如权利要求1的电容器，其中所述氮氧化钇膜的厚度小于10
Figure C200510118089C0002190244QIETU
。
4.如权利要求1的电容器，其中所述下电极具有掺杂硅膜和未掺杂硅膜的双结构。
5.如权利要求1的电容器，其中在所述氮氧化钇膜和所述上电极之间，包括当作阻挡层的氮化钛层。
6.一种用于半导体元件的电容器的制造方法，包括下列步骤：
在半导体衬底的预定下结构上由多晶硅形成下电极；
在所述下电极上，形成具有低漏电流特性的氮氧化铝膜；
在所述氮氧化铝膜上，形成具有高于所述氮氧化铝膜的介电常数的氮氧化钇膜；及
在所述氮氧化钇膜上形成上电极，
其中所述氮氧化铝膜防止所述氮氧化钇膜与所述下电极直接接触时引起的在所述下电极上形成的SiO2界面膜。
7.如权利要求6的方法，其中所述氮氧化铝膜的厚度为50到150。
8.如权利要求6的方法，其中所述氮氧化铝膜藉由使用等离子体增强式化学气相沉积法沉积。
9.如权利要求8的方法，其中沉积所述氮氧化铝膜时，使用(CH3)3Al当作来源材料，而使用H2O和NH3当作反应材料。
10.如权利要求9的方法，其中晶片温度为200到450℃，而沉积时的反应炉压力为0.1到1.0torr，以及H2O使用的流量为10到500sccm，而NH3使用的流量为10到500sccm。
11.如权利要求6的方法，还包括：在形成氮氧化铝膜之后，再执行N2O等离子体退火的步骤，以增加所述氮氧化铝膜的氮含量。
12.如权利要求6的方法，其中所述氮氧化钇膜的厚度小于10。
13.如权利要求6的方法，其中所述氮氧化钇膜使用原子层沉积法形成。
14.如权利要求13的方法，其中当作来源气体的钇气体与当作反应材料的NH3气体和H2O气体切换注入反应腔，而在注入钇气体和NH3和H2O气体之间，则提供惰性气体。
15.如权利要求14的方法，其中钇气体的注入时间、NH3和H2O气体的注入时间、和惰性气体的注入时间分别为0.1到10秒，NH3的流量为10到100sccm，H2O的流量为10到100sccm，而反应腔的温度则维持在250到350℃。
16.如权利要求6的方法，其中所述氮氧化钇膜使用离子化原子团束沉积法形成。
17.如权利要求6的方法，还包括：在形成氮氧化钇膜之后，再执行N2O等离子体退火的步骤，以增加所述氮氧化钇膜的氮含量。
18.如权利要求17的方法，还包括：在N2O等离子体退火之后，再执行炉管真空N2退火或快速热处理的步骤。
19.如权利要求6的方法，还包括：在形成氮氧化钇膜之后，再沉积当作阻挡层的氮化钛层的步骤。
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US7741671B2 (en) 2010-06-22
TW200623213A (en) 2006-07-01
KR20060072680A (ko) 2006-06-28
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