CN100477141C - 半导体封装器件及其制造和测试方法 - Google Patents

半导体封装器件及其制造和测试方法 Download PDF

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Publication number
CN100477141C
CN100477141C CNB028245296A CN02824529A CN100477141C CN 100477141 C CN100477141 C CN 100477141C CN B028245296 A CNB028245296 A CN B028245296A CN 02824529 A CN02824529 A CN 02824529A CN 100477141 C CN100477141 C CN 100477141C
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integrated circuit
pad
chip
packaging
substrate
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CN1602548A (zh
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马克·A.·吉伯
肖恩·M.·奥＇康纳
特兰特·A.·汤普森
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NXP USA Inc
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Freescale Semiconductor Inc
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种封装器件(10，100)具有在封装衬底(12，122)的一个腔(20，120)中并电耦接到该封装衬底的一个侧面(50，150)的一个集成电路(22，122)。一个第二集成电路(32，132)被安装到该封装器件的另一个侧面上，并且也电耦接到该侧面。第三或者更多的集成电路(38，138)可以被安装到所述第二集成电路上。在封装衬底的两个侧面都有可用于测试的焊盘(16，116，116)。在最后外封之前，可以对集成电路进行测试，从而降低制得的封装包含不能工作的集成电路的风险。

Description

半导体封装器件及其制造和测试方法
技术领域
本发明总体上涉及半导体封装器件，尤其涉及半导体封装器件的制造和测试方法。
背景技术
在封装集成电路时，越来越有必要允许在一个封装中封装多个芯片(die)。由于芯片的复杂性提高，这种多芯片封装的测试变得更加困难。另外，对于某些多芯片封装，多芯片封装中的一个或者多个芯片与该多芯片封装中其余的一个或者多个芯片之间的电屏蔽是很重要的。还希望允许在形成多芯片封装的制造工艺中进行返工(再加工)。因此，由于电路板技术的限制，希望有一种外形小的多芯片封装。
发明内容
本发明的一个目的是提供具有屏蔽的半导体封装器件。
本发明提供了一种形成封装器件的方法，包括：提供具有第一侧面和第二侧面并在第一侧面上有第一焊盘、在第二侧面上有第二焊盘的封装衬底；将第一集成电路置于所述第一侧面上，将第二集成电路置于所述第二侧面上，其中在第一集成电路和第二集成电路之间插入芯片连接材料；将所述第一集成电路电连接到所述第一焊盘，将所述第二集成电路电连接到所述第二焊盘；以及通过将测试探针施加于所述第一焊盘和第二焊盘来测试所述第一集成电路和第二集成电路，其中，所述第一焊盘中的至少一个焊盘与所有第二焊盘电屏蔽，并且其中，外封材料不上覆至少一个焊盘。
本发明还提供了一种形成封装器件的方法，包括：提供具有沿第一平面的第一表面和沿第二平面的第二表面的封装衬底，其中，所述封装衬底在所述第一平面和所述第二平面之间有一个腔，并且其中，所述封装衬底在所述第一表面上具有第一焊盘，在所述第二表面上具有第二焊盘；将第一集成电路置于所述腔中；将第二集成电路在所述腔外部与所述第一集成电路相邻地放置，使得在第一集成电路和第二集成电路之间插入芯片连接材料；在所述第一集成电路和所述第二集成电路上覆盖外封材料；将所述第一集成电路电连接到所述第一焊盘，将所述第二集成电路电连接到所述第二焊盘；以及通过将测试探针施加于所述第一焊盘和第二焊盘来测试所述第一集成电路和第二集成电路，其中，所述第一焊盘中的至少一个焊盘与所有第二焊盘电屏蔽，并且其中，所述外封材料不上覆至少一个焊盘。
本发明的一个技术效果是使半导体封装器件具有屏蔽。
附图说明
通过举例而非限制性的方式在附图中图解了本发明，附图中，相同的标记表示相同的部件。其中：
图1-12图解了根据本发明的一个实施例形成的封装器件的顺序的剖面图；
图13-23图解了根据本发明的另一个实施例形成的封装器件的顺序的剖面图。
本领域普通技术人员知道，图中的元件的图解方式是为了简明的目的，并不一定是按比例绘制的。例如，图中某些元件的尺度相对于其它的元件被放大了，以帮助理解本发明的各种实施例。
具体实施方式
利用用以接纳多个芯片中的至少一个的衬底的腔堆叠多个芯片允许使用外形小的封装器件。另外，用于测试目的的焊盘可以位于封装器件的不止一个侧面上。另外，多个芯片之间的层可以用来提供选定的芯片之间的电屏蔽。结合附图可以更好地理解本发明。
图1图解了根据本发明的一个实施例的具有一个腔20的封装器件10。封装器件10包括一个具有表面50和表面52的封装衬底12。注意，所述表面50构成第一平面，表面52构成第二平面。在顶部，衬底12包括一个或者多个接合指状物(bond finger)14和一个或多个焊盘16。在本发明的一个实施例中，焊盘16是导电的，可以用于多种目的。例如，焊盘16可以用来安装分立器件，可以用来接受用于测试目的的测试探针，或者可以用来接受导电互连(例如焊球)。图1图解了被施加到衬底12的表面52上的带状层(tape layer)18。在本发明的一个实施例中，衬底12包括电导体比如迹线(traces)和通孔(vias)，它们可以用来将一个或者多个芯片互连到外部触点(未示出)。
图2图解了封装器件10的一个实施例，其中，一种芯片连接材料24已经被放置在带状层18上，一个芯片22然后被放置到芯片连接材料24的顶部。本发明的另外的实施例可以不使用芯片连接材料24，而可以直接将芯片22连接到带状层18。带状层18被用作支持芯片22的支承件，或者(可选地)支持芯片连接材料24的支承件。带状层18可以也可以不在衬底12的整个表面52上延伸。
图3图解了封装器件10的一个实施例，其中，芯片22已经通过接合线(wire bond)被电连接到接合指状物14。本发明的另外的实施例可以使用任何数量的接合线26和接合指状物14。
图4图解了封装器件10的一个实施例，其中，已经在芯片22、接合线26和接合指状物14上覆盖了一种外封材料(encapsulatingmaterial)28。注意，外封材料28可以是任何类型的适合用于集成电路的材料，比如模制塑料或者液体淀积团块材料。
图5图解了封装器件10的一个实施例，其中，所述带状层18已经从衬底12的底面52被去除。
图6图解了封装器件10的一个实施例，其中，放置了芯片连接材料30以将芯片32连接到封装器件10。在一个实施例中，将芯片连接材料30放置在芯片连接材料24和芯片32之间。在另一种实施例中，当不使用芯片连接材料24时，将芯片连接材料30置于芯片22和芯片32之间。注意，在本发明的一个实施例中，在工艺的这个点，可以倒装封装器件10，从而底面52变为顶面52，顶面50变为底面50。但是，本发明的另外的实施例可以在制造过程中以任何方式对封装器件10定向。为了简明起见，在剩下的附图中，图示的封装器件10都是相同的取向。
图7图解了封装器件10的一个实施例，其中，已经通过接合线34将芯片32电连接到接合指状物14。本发明的另外的实施例可以使用任何数量的接合线34和接合指状物亚4。对于本发明的实施例，可以使用倒装晶片技术，芯片32可以没有接合线34，而可以通过表面52进行电连接。
图8图解了封装器件10的一个实施例，其中，放置了芯片连接材料36以将芯片38连接到芯片32。在一个实施例中，芯片连接材料36被放置在芯片32和芯片38之间。在另外的使用倒装晶片技术的实施例中，不使用芯片连接材料36，而使用已知的倒装晶片技术将芯片38直接电连接到芯片32。
图9图解了封装器件10的一个实施例，其中，芯片38已经用接合线42被电连接到接合指状物14，并且芯片38已经用接合线40被电连接到芯片32。本发明的另外的实施例可以使用任何数量的接合线40和42，以及任何数量的接合指状物14。对于本发明的使用倒装晶片技术的实施例，芯片38可以没有接合线42，而被直接电连接到芯片32。
图10图解了封装器件10的一个实施例，其中，图解了测试探针44，以说明一种对芯片22、32和38进行电测试的方式。注意，在本发明的另外的实施例中，测试探针44可以使用仅位于衬底12顶面50上、仅位于衬底12底面52上或者在衬底12顶面50和底面52上的一个或者多个的焊盘16。注意，在本发明的某些实施例中，允许测试探针44能够到达衬底12的顶面50和底面52有重要的好处。例如，这可以允许测试探针到达更多的焊盘16，从而允许在测试过程中使用更多的信号。另外，允许测试探针44到达衬底12的顶面50和底面52可以允许更容易接触各个芯片22、32和38。注意，当在一个封装中使用多个芯片时，测试所需的焊盘数量可能多得多。
图11图解了封装器件10的一个实施例，其中，已经覆盖了一种外封材料46，覆盖芯片38、芯片32和接合指状物14。注意，在本发明的另外的实施例中，可以在衬底12的更大的部分上覆盖外封材料46。例如，在本发明的某些实施例中，也可以覆盖外封材料46来覆盖焊盘16。无论焊盘16是否被外封材料46封住，焊盘16都可以用来将分立器件电耦合到一个或者多个芯片22、32和38。注意，外封材料46可以是任何类型的适合用于集成电路的材料，比如模制塑料或者液体淀积团块材料。
图12图解了封装器件10的一个实施例，其中，已经放置了导电互连48来覆盖表面50上的焊盘16。在本发明的一个实施例中，导电互连48可以是焊球。但是，在本发明的其他实施例中，导电互连48可以是以任何方式形成的任何类型的导电材料。注意，导电互连48是可选的。在本发明的某些实施例中，如果外封材料28与衬底12的顶面50齐平，则可以不需要导电互连48，可以直接实现到衬底12表面50上的焊盘16的电连接。注意，衬底12中的迹线和通孔(未示出)用来选择性地互连衬底12的各个部分。还要注意，芯片连接材料24、30和36可以是任何类型的合适的材料，比如胶粘带或者非固体粘合剂(例如胶水，环氧树脂)。芯片22、32或38可以是任何类型的集成电路、半导体器件或者其它类型的电活动衬底。本发明的另外的实施例可以具有任何数量的芯片22、32和38被封装到封装器件10中。例如，其它实施例可以在封装器件10中仅仅封装两个芯片。注意，芯片22、32的尺寸和长宽比可以变化，可以在芯片之间使用芯片隔离物(未图示)。注意，芯片22位于腔20内，芯片32和芯片38位于腔20之外。
图13图解了根据本发明的一个实施例具有腔120的封装器件100。封装器件100包括一个具有表面150和表面152的封装衬底112。注意，表面150构成第一平面，表面152构成第二平面。在顶部，衬底112包括一个或者多个接合指状物114和一个或者多个焊盘116。在本发明的一个实施例中，焊盘116是导电的，可以用于多种目的。例如，焊盘116可以用来安装分立器件，可以用来接受用于测试目的的测试探针，或者可以用来接受导电互连(例如焊球)。图13图解了一个层101，它是衬底112的一部分，其外表面是表面152。在本发明的一个实施例中，层101包括支承件119、一个或者多个接合指状物114以及一个或者多个焊盘116。本发明的另外的实施例可以不需要接合指状物114(例如在使用倒装芯片技术时)，在不需要到表面152的电连接时也可以不需要焊盘116。在本发明的一个实施例中，衬底112包括电导体比如迹线(traces)和通孔(vias)，它们可以用来将一个或者多个芯片互连到外部触点(未示出)。
图14图解了封装器件100的一个实施例，其中，一种芯片连接材料124已经被放置在支承件119上，一个芯片22然后被放置到芯片连接材料124的顶部。
图15图解了封装器件100的一个实施例，其中，芯片122已经通过接合线(wire bond)126被电连接到接合指状物114。本发明的另外的实施例可以使用任何数量的接合线126和接合指状物114。对于本发明的使用倒装芯片技术的实施例，芯片122可以没有接合线126，而可以用层101进行电连接。
图16图解了封装器件100的一个实施例，其中，已经在芯片122、接合线126和接合指状物114上覆盖了一种外封材料(encapsulatingmaterial)128。注意，外封材料128可以是任何类型的适合用于集成电路的材料，比如模制塑料或者液体淀积团块材料。
图17图解了封装器件100的一个实施例，其中，放置了芯片连接材料130以将芯片132连接到封装器件100。在一个实施例中，将芯片连接材料130放置在层101和芯片132之间。注意，在本发明的一个实施例中，在工艺的这个点，可以倒装封装器件100，从而底面152变为顶面152，顶面150变为底面150。但是，本发明的另外的实施例可以在制造过程中以任何方式对封装器件100定向。为了简明起见，在剩下的附图中，图示的封装器件100都是相同的取向。
图18图解了封装器件100的一个实施例，其中，已经通过接合线134将芯片132电连接到接合指状物114。本发明的另外的实施例可以使用任何数量的接合线134和接合指状物114。对于本发明的实施例，可以使用倒装晶片技术，芯片132可以没有接合线134，而可以通过表面152进行电连接。
图19图解了封装器件100的一个实施例，其中，放置了芯片连接材料136以将芯片138连接到芯片132。在一个实施例中，芯片连接材料136被放置在芯片132和芯片3丑8之间。在另外的使用倒装晶片技术的实施例中，不使用芯片连接材料136，而使用已知的倒装晶片技术将芯片138直接电连接到芯片132。
图20图解了封装器件100的一个实施例，其中，芯片138已经用接合线142被电连接到接合指状物114，并且芯片138已经用接合线140被电连接到芯片132。本发明的另外的实施例可以使用任何数量的接合线140和142，以及任何数量的接合指状物114。对于本发明的使用倒装晶片技术的实施例，芯片138可以没有接合线142，而被直接电连接到芯片132。
图21图解了封装器件100的一个实施例，其中，图解了测试探针144，以说明一种对芯片122、132和138进行电测试的方式。注意，在本发明的另外的实施例中，测试探针144可以使用仅位于衬底112顶面150上、仅位于衬底112底面152上或者衬底112顶面150和底面152上的一个或者多个的焊盘116。注意，在本发明的某些实施例中，允许测试探针144能够到达衬底112的顶面150和底面152有重要的好处。例如，这可以允许测试探针144到达更多的焊盘116，从而允许在测试过程中使用更多的信号。另外，允许测试探针144到达衬底112的顶面150和底面152可以允许更容易接触各个芯片122、132和丑38。注意，当在一个封装中使用多个芯片时，测试所需的焊盘116数量可能多得多。
图22图解了封装器件100的一个实施例，其中，已经覆盖了一种外封材料146，覆盖芯片138、芯片132和接合指状物114。注意，在本发明的另外的实施例中，可以在衬底112的更大的部分上覆盖外封材料146。例如，在本发明的某些实施例中，也可以覆盖外封材料146来覆盖焊盘116。无论焊盘116是否被外封材料146封住，焊盘116都可以用来将分立器件电耦合到一个或者多个芯片122、132和138。注意，外封材料146可以是任何类型的适合用于集成电路的材料，比如模制塑料或者液体淀积团块材料。
图23图解了封装器件100的一个实施例，其中，已经放置了导电互连148来覆盖表面150上的焊盘116。在本发明的一个实施例中，导电互连148可以是焊球。但是，在本发明的其他实施例中，导电互连148可以是以任何方式形成的任何类型的导电材料。注意，导电互连148是可选的。在本发明的某些实施例中，如果外封材料128与衬底112的顶面150齐平，则可以不需要导电互连148，可以直接实现到衬底112表面150上的焊盘116的电连接。注意，衬底112中的迹线和通孔(未示出)用来选择性地互连衬1底12的各个部分。还要注意，芯片连接材料124、130和136可以是任何类型的合适的材料，比如胶粘带或者非固体粘合剂(例如胶水，环氧树脂)。芯片122、132和138可以是任何类型的集成电路、半导体器件或者其它类型的电活动衬底。本发明的另外的实施例可以具有任何数量的芯片122、132或138被封装到封装器件100中。例如，其它实施例可以在封装器件100中仅仅封装两个芯片。注意，芯片122、132的尺寸和长宽比可以变化，可以在芯片之间使用芯片隔离物(未图示)。注意，芯片122位于腔120内，芯片132和芯片138位于腔120之外。
在前述说明书中，结合具体的实施例描述了本发明。但是，本领域的普通技术人员知道，可以在权利要求所述的本发明的范围之内进行各种修改和变化。例如，在制造封装器件10和100时，可以使用任何合适的芯片连接工艺、接合线工艺以及带状层工艺，在现有技术中有很多这样的工艺。相应地，前述说明和附图都应视为说明性的而非限制性的，所有这样的修改都应包括在本发明的范围之内。另外，结合具体实施例，描述了对问题的解决方案、好处以及其它优点。但是，对问题的解决方案、好处和优点，以及任何可以使任何优点、好处或者解决方案产生或者变得更为明显的因素都不是权利要求的关键的、必需的或者本质的特点或者要素。

Claims (5)

1.一种形成封装器件的方法，包括：
提供具有第一侧面和第二侧面并在第一侧面上有第一焊盘、在第二侧面上有第二焊盘的封装衬底；
将第一集成电路置于所述第一侧面上，将第二集成电路置于所述第二侧面上，其中在第一集成电路和第二集成电路之间插入芯片连接材料；
将所述第一集成电路电连接到所述第一焊盘，将所述第二集成电路电连接到所述第二焊盘；以及
通过将测试探针施加于所述第一焊盘和第二焊盘来测试所述第一集成电路和第二集成电路，
其中，所述第一焊盘中的至少一个焊盘与所有第二焊盘电屏蔽，并且其中，外封材料不上覆至少一个焊盘。
2.一种形成封装器件的方法，包括：
提供具有沿第一平面的第一表面和沿第二平面的第二表面的封装衬底，其中，所述封装衬底在所述第一平面和所述第二平面之间有一个腔，并且其中，所述封装衬底在所述第一表面上具有第一焊盘，在所述第二表面上具有第二焊盘；
将第一集成电路置于所述腔中；
将第二集成电路在所述腔外部与所述第一集成电路相邻地放置，使得在第一集成电路和第二集成电路之间插入芯片连接材料；
在所述第一集成电路和所述第二集成电路上覆盖外封材料；
将所述第一集成电路电连接到所述第一焊盘，将所述第二集成电路电连接到所述第二焊盘；以及
通过将测试探针施加于所述第一焊盘和第二焊盘来测试所述第一集成电路和第二集成电路，
其中，所述第一焊盘中的至少一个焊盘与所有第二焊盘电屏蔽，并且其中，所述外封材料不上覆至少一个焊盘。
3.如权利要求2所述的方法，其中，所述覆盖步骤包括：
在放置第二集成电路的步骤之前，将所述外封材料的第一部分覆盖到所述第一集成电路上；以及
将所述外封材料的第二部分覆盖到所述第二集成电路上。
4.如权利要求2所述的方法，其中，所述封装衬底还包括沿着所述衬底的第二平面的支承件。
5.如权利要求4所述的方法，还包括在放置所述第二集成电路之前去除所述支承件。
CNB028245296A 2001-11-08 2002-10-16 半导体封装器件及其制造和测试方法 Expired - Fee Related CN100477141C (zh)

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