CN100485635C - Device for real-time monitoring inside state of processor - Google Patents
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- CN100485635C CN100485635C CNB2006101184436A CN200610118443A CN100485635C CN 100485635 C CN100485635 C CN 100485635C CN B2006101184436 A CNB2006101184436 A CN B2006101184436A CN 200610118443 A CN200610118443 A CN 200610118443A CN 100485635 C CN100485635 C CN 100485635C
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Abstract
The invention discloses a device for detecting inner state of a micro processor in real time. During the design process of the micro processor, a plurality of partial monitors or a multi-level partial monitor and a global monitor are added, and the inner state information of the micro processor is serially output to a one-bit state-monitor output port with fixed cycle in circulating manner. The outer system is allocated with a signal-monitor collecting device which collects signal in the state-monitor output port of the micro processor, and is split-jointed into inner state information of the micro processor which has practical meanings through a shift memory, and is displayed on a front end PC machine finally. Small amount of hardware cost added in the design stage of the micro processor, real-time observability of the inner state of the micro processor under the situation of practical running mode of a chip is supported, and the shortcoming of measurable design technology of a traditional chip is compensated.
Description
Technical field
The present invention relates to a kind of device of real-time monitoring inside of processor.
Background technology
Along with the continuous development of microprocessor technology and microelectronic processing technique, microprocessor chip (the following stated chip all refers to microprocessor chip) scale and complexity improve constantly, and make the chip testing time increase considerably; Though the pin of Chip Packaging increases to some extent, the pin that is used for external testing reduces relatively, and the difficulty of test of chip internal logic constantly increases; Ang Gui testing apparatus makes testing cost be the index percent increase with the complexity of chip in addition.For this reason, people recognize the importance of design for Measurability (DFT:Design-For-Test) thought gradually, and the pattern that promptly adopts logical design to combine with Test Design is just considered the requirement of measurability when the designer carries out the chip logic design.Design for Measurability comprises controllability and observability two parts: controllability is research and describes the control action of the original input of chip to chip internal node logic; Observability is can observed possibility at the original output terminal of chip when describing the chip internal node and breaking down.Traditional design for Measurability comprises technology such as scan path design, built-in self-test design, boundary scan testing design.These technology have been brought into play important effect in the debugging of the initial stage of chip, but further increase along with debugging intensity, be difficult to cover all functions of entire chip from the reference mark that the original input end of chip adds, and whether design for Measurability successfully directly depends on the correctness and the completeness of substantive test circuit.Therefore, also there is certain defective in actual applications in traditional design for Measurability technology, remains further perfect.
In the later stage of chip debugging, for the dynamics of strengthening core built-in testing, microprocessor chip need enter the actual motion pattern, by the load operation system, moves various test procedures, comes all functions of quick overriding processor with this.In the chip operational process, chip debugging person wishes and can leave alone under the prerequisite of microprocessor work, by increasing a spot of hardware circuit, realize some key states of monitoring microprocessor internal primary scene in real time, judge with this whether chip is in normal condition.When chip ran into fault, the status information of microprocessor internal can help debugging person quick failure judgement zone and fault type, and then utilized traditional scan path to obtain more detailed failure message.Microprocessor internal information and traditional scan path information that chip debugging person obtains by monitoring relatively in real time, the correctness verification of two kinds of test circuits of realization.This shows that the real-time observability of microprocessor internal state has promptly remedied the defective of traditional measurability technology, guaranteed the correctness of traditional measurability circuit again.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of real-time monitoring microprocessor internal state device, when chip is in the actual motion pattern, supports the real-time observability to its internal state.
For solving the problems of the technologies described above, the device of real-time monitoring microprocessor internal state of the present invention adopts following technical scheme to realize: this device comprises the state monitor of microprocessor internal, the monitor signal collector in the external system and front end PC, wherein: in described microprocessor, add a plurality of or multistage means of local detectors and an overall monitor, described microprocessor internal status information is outputed on the monitoring state output port with fixed cycle circulation serial; Described monitor signal collector, acquired signal on the monitoring state output port of described microprocessor, and, be spliced into inside of processor information by shift register, finally be presented on the front end PC.
Adopt real-time monitoring microprocessor internal state device of the present invention, do not influence the duty of other circuit of microprocessor internal, the running status of its energy real-time follow-up microprocessor helps chip debugging person to judge in time whether microprocessor breaks down.When microprocessor runs into fault and comes to a halt, can also for chip debugging person the trouble spot field data is provided or from the trouble spot nearest field data, for fault analysis and location provide reliable guarantee.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the structured flowchart that the present invention monitors the microprocessor internal state device in real time;
Fig. 2 is the structured flowchart of means of local detectors among the present invention;
Fig. 3 is the structured flowchart of overall monitor among the present invention;
Fig. 4 is the state exchange synoptic diagram of overall monitor among the present invention;
Fig. 5 is the timing diagram of various clocks, counter and output signal in means of local detectors and the overall monitor among the present invention.
Embodiment
As shown in Figure 1, the device of real-time monitoring microprocessor internal state of the present invention is included in a plurality of or multistage means of local detectors and overall monitor that adds in the microprocessor, externally a monitor signal collector of configuration and a front end PC in the system.The microprocessor internal status information is outputed on the monitoring state output port with fixed cycle circulation serial, monitor signal collector of external system configuration, acquired signal on the monitoring state output port of microprocessor, and pass through shift register, be spliced into inside of processor information, finally be presented on the front end PC.
Needing the status information of monitoring is the output of a series of triggers of processor inside, they are distributed in different physical location in the chip, in order to reduce line and transmission delay, need carry out area dividing according to the physical location at these trigger places, monitoring state in a certain zone is collected with means of local detectors earlier, be pooled at last in the overall monitor.Quantity and distribution range according to monitoring state can be provided with multistage means of local detectors, and the monitoring state output of previous stage means of local detectors is imported as the state of back one-level means of local detectors.In order not influence the normal frequency of operation of chip, the stability of enhanced situation monitoring simultaneously, state selection that carry out all means of local detectors inside and the state transfer between the monitor all must adopt unified monitoring clock.Overall situation monitor utilizes external system work clock and microprocessor work clock to generate the monitoring clock, pass to all means of local detectors then, monitoring total cycle of clock is 4 external system work clock cycles, the width of high level is a processor work clock cycle, and low level width is three processor work clock cycles.The frequency relation of microprocessor work clock and external system work clock is adjustable, and the microprocessor work clock is 4 frequencys multiplication of external system work clock at least.
Describe the implementation method of means of local detectors among the present invention, overall monitor and monitor signal collector in detail below in conjunction with embodiment.
As shown in Figure 2, the input of means of local detectors comprises: a microprocessor work clock (GClk), a monitoring clock (localObsClk), and the internal state information that needs in the subrange to monitor (LocalState0, LocalState1 ..., LocalStatei), each status information be respectively N0, N1 ..., the Ni position.Means of local detectors is output as one local state monitor signal (localStateOut).Means of local detectors inside comprises: some synchronizer triggers, a local saturated counters (LocalCounterN) and a local MUX (LocalMux).
The part input signal of means of local detectors need carry out synchronous processing earlier, with GClk other input signals are deposited in the trigger, comprise localObsClk, LocalState0, LocalState1 ..., the LocalStatei signal, the signal after depositing be respectively localObsClk_t, LocalState0_t, LocalState1_t ..., the LocalStatei_t signal.
The local saturated counters (LocalCounterN) of means of local detectors inside, counting mode is as follows:
(1) with the GClk rising edge as trigger condition;
Local saturated counters is changed to " 0 " when (2) resetting;
(3) if localObsClk_t is " 1 ", then local saturated counters adds " 1 ";
(4) equal " N " if local saturated counters adds 1, then put local saturated counters and be " 0 ";
(5) " N " is the figure place sum that needs all status informations of monitoring, i.e. N=N0+N1+ ... + Ni.
The local sclector of means of local detectors inside (LocalMux), input end be respectively LocalState0_t, LocalState1_t ..., LocalStatei_t, and the order of agreement serial output is: LocalState0_t[0], LocalState0_t[1] ..., LocalState0_t[N0-1], LocalState1_t[0], LocalState1_t[1] ..., LocalState1_t[N1-1] ..., LocalStatei_t[0], LocalStatei_t[1] ..., LocalStatei_t[Ni-1].The working method of local MUX is as follows: with the value of local saturated counters as the selecting side, when being " 0 ", value selects LocalState0_t[0], select LocalState0_t[1 during for " 1 "], select LocalState1_t[0 during for " N0 "], select LocalState1_t[1 during for " N0+1 "] ..., select LocalStatei_t[Ni-1 during for " N0+N1+ ...+Ni-1 "].The output of local MUX is directly as the output (localStateOut) of means of local detectors, because the value of local saturated counters arrives circulation between " N-1 " in " 0 ", therefore local MUX can be the cycle with N, by about definite sequence, all internal state information that this monitor of circulation output is monitored.
Means of local detectors is placed on the place closer from the monitoring point usually, can multistage means of local detectors be set according to the needs of debugging, the state output (localStateOutj) of the means of local detectors of upper level is as the state input (LocalStatej) of next stage means of local detectors.Though LocalStatej has only one, its is actual to have comprised multidigit information (Nj position) of upper level monitoring, so should handle as Nj position information in the counting of next stage means of local detectors and multichannel are selected.Because localStateOutj is the circulation output of Nj position status information, can both must be the integral multiple of Nj so require the count cycle in the next stage monitor when guaranteeing that the next stage monitor is selected to export localStateOutj at every turn since the 0th.
As shown in Figure 3, the input of overall monitor comprises: the state output of a microprocessor reset signal (Reset_N), a microprocessor work clock (GClk), a system works clock (SynClk) and upper level means of local detectors (localStateOut0, localStateOut1 ..., localStateOutk).The output of overall situation monitor comprises: an area monitoring's clock (LocalObsClk) and a global state monitor signal (GlobalStateOut), this signal will be connected to output port as the total status monitoring signal of chip.The inside of overall situation monitor comprises: a plurality of synchronizer triggers, an overall finite state machine (GlobalFSM), an overall saturated counters (GlobalCounterM), a global state MUX (GlobalStateMux), an overall situation output MUX (GlobalOutMux).
The system works clock has synchronized relation for the clock that the chip exterior system carries out the state sampling with the microprocessor work clock, is the frequency difference, and both frequency relations are configurable, and the microprocessor work clock is at least 4 frequencys multiplication of system works clock.
The overall finite state machine (GlobalFSM) of overall situation monitor inside is used to control the generation of monitoring clock and the selection of monitoring state.Overall situation finite state machine comprises 7 different states, counts T0, T1, T2, T3, T4, T5, T6 respectively, state exchange with the rising edge of system works clock as trigger condition.The state exchange synoptic diagram is seen Fig. 4, and concrete conversion regime is as follows:
When (1) processor began to reset, the Reset_N signal was " 0 ", and next bat of overall finite state machine enters the T0 state;
(2) overall finite state machine is finished when initialize routine (SROM) loads when clapping the T0 state that is in, and when the SromOE_N signal became " 0 " from " 1 ", next bat of overall finite state machine entered the T1 state;
(3) overall finite state machine is in the T1 state when clapping, and keeps 4 system works after the clock period, and next bat of overall finite state machine enters the T2 state;
(4) overall finite state machine be in the T2 state when clapping, and keeps 4 system works after the clock period, or the T6 state keeps 1 system works after the clock period, and next bat of overall finite state machine enters the T3 state;
(5) overall finite state machine is in the T3 state when clapping, and keeps 1 system works after the clock period, and next bat of overall finite state machine enters the T4 state;
(6) overall finite state machine is in the T4 state when clapping, and keeps 1 system works after the clock period, and next bat of overall finite state machine enters the T5 state;
(7) overall finite state machine is in the T5 state when clapping, and keeps 1 system works after the clock period, and next bat of overall finite state machine enters the T6 state.
Overall situation monitor utilizes microprocessor work clock and overall finite state machine to produce the monitoring clock (LocalObsClk) that means of local detectors is used, and it is as follows specifically to generate step:
(1) generates the ObsClkSrc signal according to overall finite state machine: if overall finite state machine is in the T3 state, then be ObsClkSrc signal " 1 ", otherwise be " 0 ";
(2) with the microprocessor work clock ObsClkSrc signal is deposited in the trigger, formed the ObsClkSrc0 signal;
(3) with the microprocessor work clock ObsClkSrc0 signal is deposited in the trigger, formed the ObsClkSrc1 signal;
(4) with the microprocessor work clock ObsClkSrc1 signal is deposited in the trigger, formed the ObsClkSrc2 signal;
(5) use the non-of ObsClkSrc1 signal and last ObsClkSrc2 signal, form the ObsClk signal;
(6) with the microprocessor work clock ObsClk signal is deposited in the trigger, form the LocalObsClk signal, and be connected to output port.
Overall saturated counters (GlobalCounterM) in the overall situation monitor, its method of counting is as follows:
(1) overall saturated counters with the system works rising edge clock as trigger condition;
When (2) microprocessor resetted, overall saturated counters was changed to " 0 ";
(3) if overall finite state machine is in the T4 state, then overall saturated counters adds " 1 ";
(4) equal " M " if overall saturated counters adds 1, then overall saturated counters returns to " 0 ";
(5) M equals the status information figure place sum that the means of local detectors of all inputs is monitored, and be the integral multiple of any means of local detectors status information figure place of monitoring, suppose localStateOut0, localStateOut1 ..., status information figure place that localStateOutk monitored be respectively M0, M1 ..., Mk, M=M0+M1+ then ... + Mk, and M be M0, M1 ..., Mk integral multiple.
The inner global state selector switch (GlobalStateMux) that is provided with of overall situation monitor, input be respectively localStateOut0, localStateOut1 ..., localStateOutk.The order of agreement serial output is: the 0th monitoring state of localStateOut0, the 1st monitoring state of localStateOut0, localStateOut0 M0-1 monitoring state, the 0th monitoring state of localStateOut1, the 1st monitoring state of localStateOut1, localStateOut1 M1-1 monitoring state, the 0th monitoring state of localStateOutk, the 1st monitoring state of localStateOutk, localStateOutk Mk-1 monitoring state.The working method of overall situation MUX is as follows: with the value of overall saturated counters as the selecting side, the LocalStateOut0 that selects when arriving between " M0-1 " in " 0 " on duty, select LocalStateOut1 when arriving between " M0+M1-1 ", by that analogy at " M0 ".Because the value of overall saturated counters arrives circulation between " M-1 " in " 0 ", therefore overall MUX can be the cycle with M, by about definite sequence, and the internal state information that all means of local detectors of circulation output are monitored.
The inner overall outlet selector (GlobalOutMux) that is provided with of overall situation monitor, its output will be connected to output terminal as global state monitor signal (GlobalStateOut), and concrete forming process is as follows:
(1) if overall finite state machine is in the T1 state, then the global state monitor signal is " 0 " (keeping 4 system works clock period);
(2) if overall finite state machine is in the T2 state, then the global state monitor signal is " 1 " (keeping 4 system works clock period), the sign that 4 continuous " 0 " and 4 continuous " 1 " will begin to monitor as external system;
(3) if overall finite state machine is in the T3 state, then the global state monitor signal equals the output signal of global state Port Multiplier;
(5) if overall finite state machine is in T4, T5, T6 state, it is constant that then the global state monitor signal keeps last one value of clapping.
The monitor signal collector utilizes the external system work clock, M position status information in the monitoring state output port up-sampling of microprocessor chip circulation output, and order according to a preconcerted arrangement, these status informations are spliced into the microprocessor internal status signal with physical meaning, finally are presented on the front end PC by monitoring of software.The concrete operations mode of monitor signal collector is as follows:
(1) with the rising edge of system works clock as trigger condition;
(2) when microprocessor was finished initialize routine serial loading, the SromOE_N signal became " 0 " from " 1 ", and begin the monitoring state output port of microprocessor chip is sampled this moment;
(3) sampling find the monitoring state output signal by " 0 " and after changing to " 1 ", first monitoring state of 5 system works clock period samplings at interval, 4 follow-up monitoring states of system works clock period sampling at interval later on;
(4) state that comes out of sampling enters shift register, goes out the internal state signal of microprocessor then by the order restoring of agreement.
The content that real-time monitoring microprocessor internal state device of the present invention is monitored will be selected in the microprocessor architecture design phase.At first, can react the key signal of microprocessor running status from the angle Selection of debugging, and these signals have certain stability in certain hour, withdraw from situation etc. as current operational mode, nearest instruction fetch address, interrupt request, streamline obstruction or the cutout situation of suspension, register renaming situation, scoring plug steering order emission situation, access instruction formation situation, instruction.In addition, also will be according to the rule of the normal operation of microprocessor, increase a series of fault flag circuit, when the microprocessor operation is broken down, record trouble type and the reason that causes fault, carry out fault analysis and location after being convenient to, as instruction stream block overtime, the instruction stream cutout is overtime, instruction withdraw from overtime, Interrupt Process is overtime etc.In the chip operational process, whether debugging person's Real Time Observation fault flag is effective, in case illustrate that effectively microprocessor breaks down, the key state that observe microprocessor internal this moment again obtains more fully information, is used for fault analysis and location.
Fig. 5 has compiled the sequential relationship of various clocks, saturated counters and monitoring state output signal in means of local detectors among the present invention and the overall monitor.As seen from the figure, system works clock (SynClk) is 4 frequency divisions of microprocessor work clock (GClk), behind microprocessor serial initialize routine loaded, the SROM_N signal becomes " 0 " from " 1 ", overall situation finite state machine (GlobalFSM) begins to forward the T1 state to from the T0 state, keep 4 SynClk week after dates at the T1 state and transfer the T2 state to, keep 4 SynClk week after dates at the T2 state and transfer the T3 state again to, then cyclic transformation between T3, T4, T5, T6 one of four states later on, and all only keep 1 SynClk cycle at T3, T4, T5, T6 state.Overall situation monitor is when GlobalFSM is in the T3 state, produce monitoring clock source pulse (ObsClkSrc), and utilize GClk to carry out synchronously, produce monitoring clock source pulse 0 (ObsClkSrc0) for the first time synchronously, produce monitoring clock source pulse 1 (ObsClkSrc1) for the second time synchronously, produce monitoring clock source pulse 2 (ObsClkSrc2) for the third time synchronously, utilize ObsClkSrc1 and ObsClkSrc2 to extrude monitoring time clock (ObsClk) then, this signal just produces area monitoring's clock (LocalObsClk) through GClk synchronously again, outputs in all means of local detectors.
After means of local detectors is received area monitoring's clock, carry out synchronously with GClk once more, and with the trigger condition of the monitoring clock after synchronous as local saturated counters (LocalCounterN), local sclector is selected according to the count value of LocalCounterN, and outputs on area monitoring's state (LocalStateOut).When the value of LocalCounterN is " 0 ", select the 0th input state; When the value of LocalCounterN is " 1 ", select the 1st input state; By that analogy.
When overall finite state machine (GlobalFSM) process T4 state, overall saturated counters (GlobalCounterM) is carried out operation of saturated adding " 1 ".The global state selector switch is selected according to the count value of GlobalCounterM, and outputs on the state multichannel output signal (StateMuxOut).When the value of GlobalCounterM is " 0 ", select the 0th state of means of local detectors 0; When the value of GlobalCounterM is " 1 ", select the 1st state of means of local detectors 0; By that analogy.Overall situation outlet selector is selected according to the state of GlobalFSM, and outputs on the overall monitoring state output signal (GlobalStateOut).When GlobalFSM was in the T1 state, GlobalStateOut exported " 1 "; When GlobalFSM was in the T2 state, GlobalStateOut exported " 0 "; When GlobalFSM is in T3, T4, T5, T6 state, the value of GlobalStateOut output StateMuxOut.
Claims (7)
1, a kind of device of real-time monitoring microprocessor internal state, comprise the state monitor of microprocessor internal, the monitor signal collector in the external system, front end PC, it is characterized in that: in described microprocessor, add a plurality of or multistage means of local detectors and an overall monitor, described microprocessor internal status information is outputed on the monitoring state output port with fixed cycle circulation serial; Described monitor signal collector, acquired signal on the monitoring state output port of described microprocessor, and, be spliced into inside of processor information by shift register, finally be presented on the front end PC.
2, the device of real-time monitoring microprocessor internal state as claimed in claim 1 is characterized in that: described overall monitor produces the monitoring clock, sends all means of local detectors respectively to; Behind described microprocessor serial initialize routine loaded, described overall monitor utilizes external system work clock and microprocessor work clock to generate the monitoring clock, monitoring total cycle of clock is 4 external system work clock cycles, the width of high level is a processor work clock cycle, and low level width is three processor work clock cycles; The frequency relation of described microprocessor work clock and described external system work clock is adjustable, and the microprocessor work clock is 4 frequencys multiplication of external system work clock at least.
3, the device of real-time monitoring microprocessor internal state as claimed in claim 1, it is characterized in that: described means of local detectors adopts the monitoring clock, utilize MUX, each the microprocessor internal state that need monitor is selected in timesharing, and be the cycle with the total bit of the microprocessor internal state of required monitoring, output circulates; The microprocessor internal state of input is deposited a bat with described microprocessor work clock earlier, and then participates in the multichannel selection; Described means of local detectors is provided with a local saturated counters, the maximal value of counting is the total bit of the microprocessor internal state of the required monitoring of this means of local detectors, the counting condition is: when described microprocessor work rising edge clock, described monitoring clock value is " 1 "; The monitoring clock of input is earlier deposited a bat with described microprocessor work clock, and then as one of counting condition of described saturated counters; The monitoring clock of input is produced by described overall monitor, and is synchronous with the work clock of described microprocessor.
4, the device of real-time monitoring microprocessor internal state as claimed in claim 1, it is characterized in that: according to quantity, the physical distribution position of monitor signal, make up multistage means of local detectors, the monitoring state output of upper level means of local detectors is as the state input of next stage means of local detectors; In the monitoring state output of upper level means of local detectors, comprise the multidigit inside of processor, when the next stage means of local detectors is carried out the multichannel selection, should handle as multidigit information, and the total bit that requires the next stage means of local detectors to monitor is the integral multiple of the total bit of upper level means of local detectors monitoring.
5, the device of real-time monitoring microprocessor internal state as claimed in claim 1, it is characterized in that: described overall monitor is behind described microprocessor serial initialize routine loaded, the monitoring state that compiles all means of local detectors, utilize MUX and finite states machine control, each internal state information that each means of local detectors is monitored is exported in timesharing, and finally outputs on the port as the monitoring state of described microprocessor chip; The monitoring state of described means of local detectors comprises multidigit microprocessor internal state, when in described overall monitor, carrying out the multichannel selection, should handle as multidigit information, and to require the total bit of overall monitor monitors be the integral multiple of the total bit of all local monitor monitors; Described overall monitor is provided with a finite state machine, be in T0, T1, T2, T3, T4, T5, T6 state respectively, be in the T0 state when resetting, be in the T1 state behind the described microprocessor serial initialize routine loaded, carry out state exchange by the described external system work clock cycle later on; Described overall monitor also is provided with an overall saturated counters, the maximal value of counting is the total bit of the microprocessor internal state of the required monitoring of this overall situation monitor, the counting condition is: when described microprocessor work rising edge clock, described finite state machine is in the T4 state.
6, real-time monitoring microprocessor internal state device as claimed in claim 1, it is characterized in that: described monitor signal collector, behind described microprocessor serial initialize routine loaded, utilize described external system work clock rising edge that the monitoring state signal of processor chips output is sampled, external system and fixing monitoring state opening flag of processor chips agreement, after external system samples this sign, just every the internal state of four systems work clock sampling serial output, the information bit that samples is sent in the shift register, state output by agreement is spliced in proper order, finally is presented on the front end PC.
7, the device of real-time monitoring microprocessor internal state as claimed in claim 1 is characterized in that: the microprocessor internal state of monitoring comprises key state and a series of fault flag circuit state of microprocessor self in real time; The key state of described microprocessor self is meant the running status of each streamline platform, comprise current operational mode, nearest instruction fetch address, suspension interrupt request, streamline blocks or cutout situation, register renaming situation, scoring plug steering order emission situation, access instruction formation situation, instruction withdraw from situation; Described fault flag circuit is meant when the processor operation is broken down, utilize extra hardware logic record trouble type and the reason that causes fault, carry out fault analysis and location after being convenient to, comprise that instruction stream blocks stop overtime fault flag, instruction of overtime fault flag, instruction stream and withdraws from overtime fault flag and the overtime fault flag of Interrupt Process.
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| CN102141787B (en) * | 2010-01-29 | 2013-08-21 | 比亚迪股份有限公司 | Singlechip monitoring system and control method |
| CN102768335A (en) * | 2012-06-29 | 2012-11-07 | 福州瑞芯微电子有限公司 | Circuit and method for monitoring chip internal circuit signal |
| CN103809491A (en) * | 2014-01-26 | 2014-05-21 | 河南工业职业技术学院 | Method for single chip monitoring chip to monitor single chip |
| CN104484308B (en) * | 2014-11-18 | 2017-12-26 | 瑞昱半导体股份有限公司 | Control method applied to operator scheme finite state machine |
| CN108768768B (en) * | 2018-05-15 | 2020-12-01 | 苏州科达科技股份有限公司 | Blocking detection method and device for business system and storage medium |
| CN109032664B (en) * | 2018-07-04 | 2021-08-06 | 中国人民解放军国防科技大学 | Method and system for tracking queue full state of micro-architecture level queue in real time |
| CN109444716B (en) * | 2018-11-27 | 2021-08-10 | 中科曙光信息产业成都有限公司 | Scanning test structure with positioning function and method |
| CN110502279A (en) * | 2019-08-23 | 2019-11-26 | 中国人民解放军国防科技大学 | Intelligent adjustment method for emission queue based on markable instruction |
| CN112198471A (en) * | 2020-09-13 | 2021-01-08 | 南京宏泰半导体科技有限公司 | Real-time state detection device of efficient test system |
| CN112416687B (en) * | 2020-12-02 | 2022-07-12 | 海光信息技术股份有限公司 | Method and system for verifying access operation, verification device and storage medium |
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