CN100495701C - A three-dimensional wafer stacking structure with post-and-beam construction and method to stack three-dimensional wafer - Google Patents
A three-dimensional wafer stacking structure with post-and-beam construction and method to stack three-dimensional wafer Download PDFInfo
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- CN100495701C CN100495701C CNB2005101203964A CN200510120396A CN100495701C CN 100495701 C CN100495701 C CN 100495701C CN B2005101203964 A CNB2005101203964 A CN B2005101203964A CN 200510120396 A CN200510120396 A CN 200510120396A CN 100495701 C CN100495701 C CN 100495701C
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Abstract
The provided wafer static structure comprises: the first wafers with multiple metal support structures, and the second wafer on top of the first wafer. Wherein, the said support structure is set on chip position to extend from the silicon surface of the first chip to the second wafer base and form a support force for preventing the damage from vertical stress or shearing stress.
Description
Technical field
The present invention relates to the method for a kind of three-dimensional wafer-to-wafer stacking and three-dimensional wafer stacking, especially relate to a kind of three-dimensional wafer-to-wafer stacking of metal support structure and method of three-dimensional wafer stacking of between two silicon substrates, comprising.
Background technology
Along with the development of electronic manufacturing technology, increasing electronic product with portable, high functionality and compact be its developing goal.Yet, under such development trend, the circuit arrangement functional and that comprised of the electronic chip that electronic product is arranged in pairs or groups also will certainly get more and more and can become increasingly complex, and under the demand of chip area microminiaturization, although little shadow manufacturing process (lithographic process) of wafer manufacturing at present is still constantly toward 45nm, 32nm even smaller szie evolution; Yet, in any case, the great change of the following chip design result that will be inevitable.Therefore, a kind of technology of wafer stacking of prospective three-dimensional has begun progressively to develop.
See also Fig. 1, it is the schematic diagram of the known a kind of three-dimensional wafer-to-wafer stacking of explanation.As shown in fig. 1, this wafer-to-wafer stacking 100 ' comprises one first wafer 10 ', one second wafer 20 ' and one the 3rd wafer 30 '; Wherein said wafer 10 '-30 ' is made of a substrate 12 ', 22 ', 32 ' and one device layer; Wherein, finish piling up of wafer by a binder course (bonding layer) between the different wafer; Wherein, this first and second wafer 10 ', 20 ' the adjacent arrangement of device layer, thereby form the stacked structure of face-to-face (face to face), this second wafer and the 3rd wafer 20 ', 30 ' be then by a substrate and the adjacent arrangement of device layer, thereby form a stacked structure back to face (back to face).As shown in FIG., comprise most circuit arrangements 16 ', 26 ', 36 ' etc. on the device layer of described wafer 10 '-30 ', the circuit arrangement on the different chips is then realized the purpose of electrical connection mutually by signalling channel (signal vias) 15 '.
Although above-mentioned wafer-to-wafer stacking 100 ' can be looked the needs of chip design and repeatedly pile up a plurality of wafers, yet, under the situation of increasing wafer-to-wafer stacking and the circuit arrangement configuration that becomes increasingly complex, exist low dielectric (low-k) material that respectively installs in the layer possibly because the compression of stacked structure, the perhaps thermal stress that is produced during circuit operation and produce destruction, and then cause the damage of entire chip circuit.
Although as in the above-mentioned wafer-to-wafer stacking 100 ', it has the signalling channel structure that connects different chips, yet these signalling channels directly are not disposed on two rigid surfaces of described device layer, therefore can't produce the effect that supports to described device layer.Thereby this wafer-to-wafer stacking and can't avoid the dielectric materials stress in the device layer and the destruction of causing.
In sum, how making the low dielectric material layer in the wafer-to-wafer stacking can keep out deformation or the destruction that compression or thermal stress produce, has been the big problem that this area demands urgently overcoming.In view of this, in order to overcome the above-mentioned problem that meets with effectively, the present inventor has proposed a kind of three-dimensional wafer-to-wafer stacking with beam column construction.
Summary of the invention
First kind of scheme of the present invention proposed a kind of three-dimensional wafer (wafer) stacked structure, it comprises one first wafer, this first wafer has one first device layer and one first substrate, and wherein this first device layer has at least one chip (chip) and at least one dielectric materials; One second wafer is arranged on this first wafer, and this second wafer has one second device layer and one second substrate; And at least one metal support structure, this metal support structure is positioned on this chip position, this metal support structure vertical arrangement and extend to the lower surface of this second substrate from the upper surface of this first substrate wherein, and described metal support structure by column or beam shape vertical or horizontal support to be provided and to be formed, so that this dielectric materials avoids the destruction of stress by material with pyroconductivity character.
According to above-mentioned technical conceive, wherein this first and second adjacent arrangement of device layer is so that this first and second wafer forms a face-to-face stacked structure.
According to above-mentioned technical conceive, wherein this metal support structure is installed vertical alignment (vertically aligned) in the layer this first and second.
According to above-mentioned technical conceive, the wherein adjacent arrangement with second substrate of this first device layer is so that this first and second wafer forms a stacked structure back to face.
According to above-mentioned technical conceive, the wherein adjacent arrangement with second substrate of this first substrate is so that this first and second wafer forms a back-to-back stacked structure.
According to above-mentioned technical conceive, wherein this first and second substrate be selected from silicon substrate, comprise the silicon substrate of silicon dioxide and comprise nitrogen/Si oxide silicon substrate one of them.
According to above-mentioned technical conceive, wherein this metal support structure is arranged on arbitrary position on this chip.
According to above-mentioned technical conceive, wherein should the three-dimensional wafer-to-wafer stacking comprise a plurality of supporting constructions and be arranged in respectively on the diverse location on this circuit.
According to above-mentioned technical conceive, the arrangement position of wherein said supporting construction form arranged, annular arrangement and other symmetric arrays form one of them.
According to above-mentioned technical conceive, wherein this metal support structure be column and beam texture one of them, to provide vertically and horizontal support.
According to above-mentioned technical conceive, wherein this metal support structure is made up of the material of high thermoconductivity.
According to above-mentioned technical conceive, wherein this metal support structure also runs through this first and second substrate layer, the thermal energy transfer between this first and second wafer is arrived this wafer-to-wafer stacking outside.
According to above-mentioned technical conceive, wherein this dielectric materials is porous crack (porous) material.
Second kind of scheme of the present invention also proposes a kind of three-dimensional wafer-to-wafer stacking, and it comprises one first wafer, and this first wafer has one first device layer and one first substrate, and wherein this first device layer has at least one first circuit and at least one dielectric materials; One second wafer is arranged on this first wafer, and this second wafer has one second device layer and one second substrate, and wherein this second device layer has at least one second circuit; And at least one passage (via), it runs through this second substrate and makes this second circuit be electrically connected to this first device layer; Wherein, this first and second wafer comprises at least one metal support structure respectively, described metal support structure is built up on this first and second circuit position, and respectively from the past described direction vertical arrangement of installing layer of described substrate, and described metal support structure by column or beam shape vertical or horizontal support to be provided and to be formed, so that this dielectric materials avoids the destruction of stress by material with pyroconductivity character.
According to above-mentioned technical conceive, wherein this first and second substrate be selected from silicon substrate, comprise the silicon substrate of silicon dioxide and comprise nitrogen/Si oxide silicon substrate one of them.
According to above-mentioned technical conceive, wherein this first and second wafer is the wafer with live width manufacturing process.
According to above-mentioned technical conceive, wherein this second wafer is the wafer of low-res (high live width) manufacturing process.
According to above-mentioned technical conceive, wherein this second circuit comprises ESD protection circuit (ESD), passive component, drive circuit and power supply/earth shield (P/G shielding) circuit.
The third technical scheme of the present invention also proposes a kind of wafer-to-wafer stacking, it comprises one first wafer, and this first wafer has a device layer and a substrate, wherein, comprise at least one circuit and at least one dielectric materials in this device layer, and this substrate is in order to carry this device layer; One second wafer, this second wafer are arranged on this first wafer; An and supporting construction, be built in this circuit position between this first and second wafer, and from this substrate toward this second wafer vertical extent, and described supporting construction by column or beam shape vertical or horizontal support to be provided and to be formed, so that this dielectric materials avoids the destruction of stress by material with pyroconductivity character.
According to above-mentioned technical conceive, wherein this substrate be selected from silicon substrate, comprise the silicon substrate of silicon dioxide and comprise nitrogen/Si oxide silicon substrate one of them.
According to above-mentioned technical conceive, this first and second wafer wafer that is different live width manufacturing process wherein.
According to above-mentioned technical conceive, wherein this second wafer comprises a circuit layer.
According to above-mentioned technical conceive, wherein this circuit layer surface down so that this first and second wafer forms a face-to-face stacked structure.
According to above-mentioned technical conceive, wherein this supporting construction vertically runs through this device layer and this circuit layer.
According to above-mentioned technical conceive, wherein this circuit layer comprise ESD protection circuit, passive component, drive circuit and power supply/earth shield circuit one of them.
According to above-mentioned technical conceive, wherein this circuit layer surface down so that this first and second wafer forms the stacked structure back to face.
According to above-mentioned technical conceive, wherein this supporting construction be column and beam texture one of them, to provide vertically and horizontal support.
According to above-mentioned technical conceive, wherein this supporting construction is made up of the material of high thermoconductivity.
According to above-mentioned technical conceive, wherein this supporting construction also runs through this substrate, the thermal energy transfer between this first and second wafer is arrived this wafer-to-wafer stacking outside.
The 4th kind of technical scheme of the present invention proposes a kind of method of three-dimensional wafer stacking, and it comprises the following step: one first wafer (a) is provided; B provides one second wafer; (c) on this first wafer, form a supporting construction, described supporting construction by column or beam shape vertical or horizontal support to be provided and to be formed by material with pyroconductivity character; (d) on this second wafer, form a plurality of interface channels, so that the both sides up and down of this second wafer are electrically connected to each other; And (e) engage this first and second wafer, to finish this three-dimensional wafer-to-wafer stacking.
According to above-mentioned technical conceive, wherein in the step (c), this supporting construction be column and beam texture one of them.
According to above-mentioned technical conceive, wherein in step (d), utilize a ultraviolet ray (UV) laser means, carbon dioxide (CO2) gas laser method and a method for chemially etching one of them and form this interface channel.
According to above-mentioned technical conceive, wherein in step (e), also be included in and insert an electric conducting material in the part interface channel, so that the both sides up and down of this second wafer are electrically connected to each other.
According to above-mentioned technical conceive, wherein in step (e), also be included in and form an insulating barrier in this part interface channel, so that the circuit beyond this electric conducting material and this part interface channel produces insulation.
According to above-mentioned technical conceive, wherein in step (e), also be included in and form a wiring layer on this second wafer, so that the circuit on this second wafer is electrically connected mutually with this part passage.
The 5th kind of technical scheme of the present invention also proposes a kind of wafer-to-wafer stacking, and it comprises one first wafer, and this first wafer has a device layer and a substrate, comprise a circuit and a dielectric materials in this device layer, and this substrate is in order to carry this device layer; And one second wafer, it is arranged on this first wafer; An and stress protective device; it is built between this first and second wafer; and from this substrate toward this second wafer vertical extent; and described stress protective device by column or beam shape vertical or horizontal support to be provided and to be formed, so that this dielectric materials avoids the destruction of stress by material with pyroconductivity character.
The 6th kind of technical scheme of the present invention also proposes a kind of three-dimensional chip stacked structure, it comprises one first chip, and this first chip has a circuit layer and a substrate, wherein, this circuit layer comprises a circuit and a dielectric materials, and this substrate is in order to carry this circuit layer; And one second chip, it is arranged on this first chip; An and stress protective device; it is arranged between this first and second chip; and from this substrate toward this second chip vertical extent; and described stress protective device by column or beam shape vertical or horizontal support to be provided and to be formed, so that this dielectric materials avoids the destruction of stress by material with pyroconductivity character.
In sum, the invention provides a kind of three-dimensional wafer-to-wafer stacking of innovation.Compare with known three-dimensional wafer-to-wafer stacking, the three-dimensional wafer-to-wafer stacking that the application proposed is except comprising interface channel (via) with the circuit arrangement that connects the two plates top between different wafers, also on each chip position of wafer, at least one metal support structure is set, wherein, described metal support structure can the matrix kenel be arranged on the described chip, also can be arranged in each chip around or the optional position on.Can make the dielectric materials that respectively waits between the wafer by metal support structure proposed by the invention, avoid being subjected to the destruction of stress.
The present invention can illustrate by the preferred embodiment of following collocation accompanying drawing, can access more deep understanding to the present invention:
Description of drawings
Fig. 1 is the known a kind of wafer-to-wafer stacking figure of explanation;
Fig. 2 A is the wafer-to-wafer stacking figure of explanation the present invention first specific embodiment;
Fig. 2 B is the wafer-to-wafer stacking figure of explanation the present invention second specific embodiment;
Fig. 2 C is the wafer-to-wafer stacking figure of explanation the present invention the 3rd specific embodiment;
Fig. 2 D is the wafer-to-wafer stacking figure of explanation the present invention the 4th specific embodiment;
Fig. 3 A and Fig. 3 B are respectively the vertical view of this metal support structure configuration in the explanation wafer-to-wafer stacking of the present invention; And
Fig. 4 is the manufacturing flow chart of explanation wafer-to-wafer stacking of the present invention.
Wherein, description of reference numerals is as follows:
10 ', 20 ', 30 ' wafer, 13 ' knitting layer
12 ', 22 ', 32 ' substrate, 15 ' signalling channel
16 ', 26 ', 36 ' circuit arrangement S11-S30 manufacturing process step
10 first wafers, 20 second wafers
12 first substrates, 22 second substrates
14 first device layers, 24 second device layer
16,26 circuit arrangements, 18,28 low dielectric layers
15 signalling channels, 25 metal support structure
30 esd protection circuit 100-400 wafer-to-wafer stackings
Embodiment
Three-dimensional wafer-to-wafer stacking of the present invention utilizes layer by layer deposition or laser drill mode to form a metal support structure between two rigid surfaces (or substrate) on the wafer, to provide support the purpose of this structure sheaf, reaches the purpose of strengthening this low dielectric material layer.
See also Fig. 2 A-Fig. 2 D, it illustrates the various specific embodiment of three-dimensional wafer-to-wafer stacking of the present invention.Shown in Fig. 2 A, the three-dimensional wafer-to-wafer stacking 100 of the present invention's first specific embodiment is made of one first wafer 10 and one second wafer 20, (or being called back to the stacked structure of face (back to face or back to front)) arranged on wherein said first and second wafer 10,20 equal surfaces (face up) up, wherein, described first and second wafer 10,20 comprises first and second substrate layer 12,22 and one first and one second device layer 14,24 respectively.Described first and second device layer 14,24 comprise respectively a plurality of circuit arrangements 16,26 (described circuit arrangement is integrated into the kenel of integrated circuit (IC) chip usually) with and low dielectric layer 18,28, wherein this dielectric materials can be traditional dielectric materials, as silicon dioxide, or porous crack (porous) material etc.In addition, in order to make the circuit arrangement 16,26 on described first and second device layer 14,24 can carry out the signal transmission, between this first and second wafer 10,20, also comprise a signalling channel 15, to connect the circuit arrangement 16,26 on described first and second wafer.Except said structure, three-dimensional wafer-to-wafer stacking 100 of the present invention also comprises at least one metal support structure 25, so that described low dielectric material layer 18,28 avoids suffering the destruction of stress.
As shown in Fig. 2 A, this metal support structure 25 is arranged on the rigid surface (rigid surface) on the described circuit arrangement 16,26, or vertically extends (vertically extending) to the surface from the rigid surface of described first or second substrate 12,22.Described rigid surface refers to by the nitrogen Si oxide on silicon, silicon dioxide, the silicon substrate (as Si
3N
4On Si) surface of material such as, but rigid surface described here does not comprise on the described low dielectric material layer 18,28, for employed silicon dioxide of wiring purpose or silicon nitride surface.
As shown in Fig. 2 A, described metal support structure 25 mainly is contained in described first and second device layer in 14,24; Yet, in other preferred embodiment, this metal support structure 25 also can run through described first and second substrate 12,22, because of deformation its device layer 14,24 generation compression or shear stress is destroyed described low dielectric layer 18,28 to avoid described substrate 12,22.In addition, the specific embodiment of also having represented the arrangement configuration that this metal support structure 25 is different among Fig. 2 A: as arranging shown in the configuration (), it represents that this metal support structure 25 is utilized depositional mode, up deposition forms layer by layer; Arrange configuration (two) and then utilize the mode of boring, form this metal support structure 25 again behind the passage of formation metal support structure 25; As arrange shown in the configuration (three), be arranged in the same wafer, as the metal support structure 25 in second wafer 20, must arrange (vertical aligned) by vertical alignment, just can reach the low dielectric layer 28 of strengthening this second device layer 24, yet, in the present embodiment in the wafer-to-wafer stacking of face, the metal support structure 25 on the different chips then may not need vertical alignment.
Please continue to consult Fig. 2 B, the three-dimensional wafer-to-wafer stacking 200 of its explanation the present invention second specific embodiment.Compare with the three-dimensional wafer-to-wafer stacking 100 of aforesaid first specific embodiment, (being also referred to as face-to-face stacked structure) arranged on second wafer, 20 surfaces of this three-dimensional wafer-to-wafer stacking 200 (face down) downwards, except have the difference herein, the structure of described first and second wafer is formed with the three-dimensional wafer-to-wafer stacking 100 of first embodiment identical.As shown in Fig. 2 B, because described first and second installs layer 14,24 adjacent arrangement, not only can reduce the thickness of device layer, also can significantly shorten the transmission distance of this signalling channel 15.And on the arrangement configuration of this metal support structure 25, also embodiment implements with layer by layer deposition mode () or bore mode (two) as described above.It should be noted that in aspectant wafer-to-wafer stacking 200 metal support structure 25 on described first and second wafer 10,20 must be kept vertical arrangement, could provide the support structure effect to described first and second device layer 14,24 effectively.Therefore, planting metal support structure as (three) among Fig. 2 A arranges configuration and is not suitable in the present embodiment.
Please continue to consult Fig. 2 C, the three-dimensional wafer-to-wafer stacking 300 of its explanation the present invention the 3rd specific embodiment.As shown in Fig. 3 C, first and second wafer 10,20 of this three-dimensional wafer-to-wafer stacking 300 comprises members such as substrate 12 and 22, device layer 14 and 24, low dielectric layer 18 and 28, signalling channel 15 and metal support structure 25 equally; The main difference of present embodiment and aforesaid three-dimensional wafer-to-wafer stacking 100 or 200 embodiment is the adjacent arrangement of substrate of this first and second wafer 10,20, the wafer-to-wafer stacking of back-to-back to form (back to back).
Please continue to consult Fig. 2 D, the three-dimensional wafer-to-wafer stacking 400 of its explanation the present invention the 4th specific embodiment.As shown in FIG., this three-dimensional wafer-to-wafer stacking 400 comprises one first wafer 10 and one second wafer 20, and wherein, this first wafer 10 has a substrate 12 and a device layer 14, and 14 comprise an at least one circuit arrangement 16 and a low dielectric layer 18 in this device layer; This second wafer 20 then is stacked on this first wafer.This wafer-to-wafer stacking 400 is do not have the device layer on this second wafer 20 with the difference of aforesaid wafer-to-wafer stacking 100,200 or 300, thereby this second wafer 20 only is regarded as a blank wafer (dummy wafer) that protection or wiring effect be provided.In the device layer 14 of this first wafer 10, this metal support structure 25 is from a rigid surface toward these second wafer, 20 vertical extent.Same, this metal support structure 25 can form by the mode of boring or layer by layer deposition, and this metal support structure 25 can optionally run through this second wafer 20.
In aforementioned every specific embodiment, described second wafer can utilize with the identical resolution of this first wafer or than the manufacturing process of low-res and make.Such advantage makes specific core circuit; ESD protection circuit, passive component, drive circuit and power supply/earth shield circuit (as the circuit 30 of Fig. 2 D) etc. for example; can be placed on the different wafers, so that the circuit design of low manufacturing cost to be provided.
Please continue to consult Fig. 3 A and Fig. 3 B, it further specifies the vertical view of the allocation position of a plurality of metal support structure 25 on wafer.Shown in Fig. 2 A-Fig. 2 D, a plurality of metal structures are arranged in the arbitrary position on each circuit arrangement as the aforementioned; And for more effective support structure is provided, described a plurality of metal support structure also can be arranged in matrix pattern (as shown in Figure 3A) or ring-type pattern (shown in Fig. 3 B); Perhaps also can be arranged in other symmetrical type of array.In addition, in aforesaid every specific embodiment, this metal support structure 25 also can be arranged in the horizontal expansion structure of beam shape except vertical arrangement becomes column structure.In addition, this metal support structure 25 also can be made up of the metal material of high thermoconductivity, with the past wafer surface transmission of the thermal source that will be produced in this device layer or along the beam texture lateral transport.
See also Fig. 4, it is the manufacturing flow chart of explanation three-dimensional wafer-to-wafer stacking of the present invention.As shown in Figure 4, this three-dimensional wafer-to-wafer stacking is made up of one first wafer and one second wafer, and wherein said first wafer and this second wafer can be obtained by identical or different resolution manufacturing process respectively; Wherein this first wafer carries out the S11-S13 manufacturing process step as left side among the figure in regular turn; At first, in step S11, the substrate of one first wafer is provided, then, in step S12 and S13, this circuit arrangement layer of layer by layer deposition on this substrate, wherein, this circuit arrangement layer is made of a plurality of metal level, and this metal support structure also successively is formed in this circuit arrangement layer along with a plurality of metal levels.In addition, the manufacturing process step S21-S24 of this second wafer is then represented on Fig. 4 right side; At first in S21, one second wafer substrate is provided, then in step S22, utilize chemical etching or ultraviolet ray (UV) laser, boring manufacturing process such as carbon dioxide gas volumetric laser form a plurality of access openings, then, in step S23, on the hole wall of described access opening, form an insulating barrier, at last, in step S24, in described access opening, form a metal connecting line, so that on this second wafer, following both sides can be electrically connected each other, simultaneously, also can form a wiring layer on the same side of this second wafer, so that the purpose of the circuit arrangement of the same side to realize being electrically connected mutually.After described first and second wafer was finished, in step S30, the mode of utilizing wafer to engage made this second wafer stacking on this first wafer, to finish wafer-to-wafer stacking of the present invention.
Above-described, only in order to preferred embodiment of the present invention to be described, yet scope of the present invention should not be subject to this above-mentioned every embodiment.For example, three-dimensional wafer-to-wafer stacking of the present invention, the also extensible stacked structure that is applied to three-dimensional chip is to provide the chip stack structure that has the protection low dielectric material layer, reaches low manufacturing cost.Therefore, the present invention can be carried out various modifications and variation by those skilled in the art, yet it does not all break away from the claimed scope of claims.
Claims (32)
1, a kind of three-dimensional wafer-to-wafer stacking comprises:
One first wafer, it has one first device layer and one first substrate, and the wherein said first device layer has at least one chip and at least one dielectric materials;
One second wafer is arranged on described first wafer, and it has one second device layer and one second substrate; And
At least one metal support structure, it is positioned on the described chip position, wherein said metal support structure vertical arrangement and extend to the lower surface of described second substrate from the upper surface of described first substrate, and described metal support structure by column or beam shape vertical or horizontal support to be provided and to be formed by material with pyroconductivity character.
2, three-dimensional wafer-to-wafer stacking as claimed in claim 1, wherein said first device layer and the adjacent arrangement of the described second device layer are so that described first wafer and described second wafer form a face-to-face stacked structure.
3, three-dimensional wafer-to-wafer stacking as claimed in claim 2, wherein said metal support structure is installed vertical alignment in the layer at the described first device layer with described second.
4, three-dimensional wafer-to-wafer stacking as claimed in claim 1, the wherein said first device layer and the adjacent arrangement of described second substrate is so that described first wafer and described second wafer form a stacked structure back to face.
5, three-dimensional wafer-to-wafer stacking as claimed in claim 1, wherein said first substrate and the adjacent arrangement of described second substrate are so that described first wafer and described second wafer form a back-to-back stacked structure.
6, three-dimensional wafer-to-wafer stacking as claimed in claim 1, wherein said first substrate and described second substrate be silicon substrate, comprise the silicon substrate of silicon dioxide or comprise the silicon substrate of nitrogen/Si oxide.
7, three-dimensional wafer-to-wafer stacking as claimed in claim 1, wherein said metal support structure are arranged on arbitrary position on this chip.
8, three-dimensional wafer-to-wafer stacking as claimed in claim 1, it comprises a plurality of supporting constructions that are arranged in diverse location on the described chip respectively.
9, three-dimensional wafer-to-wafer stacking as claimed in claim 8, the arrangement position of wherein said supporting construction forms arranged, annular arrangement or other symmetric arrays form.
10, three-dimensional wafer-to-wafer stacking as claimed in claim 1, wherein said metal support structure also run through described first substrate and described second substrate, the thermal energy transfer between described first wafer and described second wafer is arrived the described wafer-to-wafer stacking outside.
11, three-dimensional wafer-to-wafer stacking as claimed in claim 1, wherein said dielectric materials is a mushy material.
12, a kind of three-dimensional wafer-to-wafer stacking comprises:
One first wafer, it has one first device layer and one first substrate, and the wherein said first device layer has one first circuit and at least one dielectric materials;
One second wafer is arranged on described first wafer, and it has one second device layer and one second substrate, and the wherein said second device layer has at least one second circuit; And
At least one passage, it runs through described second substrate and makes described second circuit be electrically connected to the described first device layer;
Wherein, described first wafer and described second wafer comprise at least one metal support structure respectively, described metal support structure is arranged on described first circuit and the described second circuit position, and the direction vertical arrangement from described substrate, and described metal support structure respectively toward described device layer by column or beam shape vertical or horizontal support to be provided and to be formed by material with pyroconductivity character.
13, as the three-dimensional wafer-to-wafer stacking of claim 12, wherein said first substrate and described second substrate be silicon substrate, comprise the silicon substrate of silicon dioxide or comprise the silicon substrate of nitrogen/Si oxide.
14, as the three-dimensional wafer-to-wafer stacking of claim 12, wherein said first wafer and described second wafer are the wafer with live width manufacturing process.
15, as the three-dimensional wafer-to-wafer stacking of claim 12, the wafer that wherein said first wafer and described second wafer are different live width manufacturing process.
16, as the three-dimensional wafer-to-wafer stacking of claim 12, wherein said second circuit comprises ESD protection circuit, passive component, drive circuit or power supply/earth shield circuit.
17, a kind of wafer-to-wafer stacking comprises:
One first wafer, it has:
One device layer comprises at least one circuit and at least one dielectric materials in the described device layer; And
One substrate is in order to carry described device layer;
One second wafer, it is arranged on described first wafer; And
One supporting construction, be built in described first and described second wafer between described circuit position, and from described substrate toward the described second wafer vertical extent, and described supporting construction by column or beam shape vertical or horizontal support to be provided and to be formed by material with pyroconductivity character.
18, as the wafer-to-wafer stacking of claim 17, wherein said substrate is silicon substrate, comprise the silicon substrate of silicon dioxide or comprise the silicon substrate of nitrogen/Si oxide.
19, as the wafer-to-wafer stacking of claim 17, the wafer that wherein said first wafer and described second wafer are different live width manufacturing process.
20, as the wafer-to-wafer stacking of claim 17, wherein said second wafer comprises a circuit layer.
21, as the wafer-to-wafer stacking of claim 20, wherein said circuit layer surface down so that described first wafer and described second wafer form a face-to-face stacked structure.
22, as the wafer-to-wafer stacking of claim 21, wherein said supporting construction vertically runs through described device layer and described circuit layer.
23, as the wafer-to-wafer stacking of claim 20, wherein said circuit layer comprises ESD protection circuit, passive component, drive circuit or power supply/earth shield circuit.
24, as the wafer-to-wafer stacking of claim 20, wherein said circuit layer surface down so that described first wafer and described second wafer form a stacked structure back to face.
25, as the wafer-to-wafer stacking of claim 17, wherein said supporting construction also runs through described substrate, the thermal energy transfer between described first wafer and described second wafer is arrived the described wafer-to-wafer stacking outside.
26, a kind of method of three-dimensional wafer stacking comprises:
One first wafer is provided;
One second wafer is provided;
On described first wafer, form a supporting construction, described supporting construction by column or beam shape vertical or horizontal support to be provided and to be formed by material with pyroconductivity character;
On described second wafer, form a plurality of interface channels, so that the both sides up and down of described second wafer are electrically connected to each other; And
Engage described first wafer and described second wafer, to finish described three-dimensional wafer-to-wafer stacking.
27,, wherein in the step that forms a plurality of interface channels, utilize a ultraviolet laser method, carbon dioxide laser means or a method for chemially etching and form described interface channel as the method for claim 26.
28,, wherein engage also to be included in the described interface channel of part in the step of described first wafer and described second wafer and insert an electric conducting material, so that the both sides up and down of described second wafer are electrically connected to each other as the method for claim 26.
29, as the method for claim 28, wherein engage also to be included in the step of described first wafer and described second wafer and form an insulating barrier in the described interface channel of part, so that producing, the circuit beyond the described interface channel of described electric conducting material and part insulate.
30,, wherein engage also to be included in the step of described first wafer and described second wafer and form a wiring layer on described second wafer, so that the circuit on described second wafer is electrically connected mutually with the described interface channel of part as the method for claim 26.
31, a kind of wafer-to-wafer stacking comprises:
One first wafer, it has:
One device layer comprises a circuit and a dielectric materials in the described device layer; And
One substrate is in order to carry described device layer; And
One second wafer, it is arranged on described first wafer; And
One stress protective device; its be built in described first and described second wafer between; and from described substrate toward the described second wafer vertical extent, and described stress protective device by column or beam shape vertical or horizontal support to be provided and to be formed by material with pyroconductivity character.
32, a kind of three-dimensional chip stacked structure comprises:
One first chip, it has:
One circuit layer, described circuit layer comprise a circuit and a dielectric materials; And
One substrate is in order to carry described circuit layer; And
One second chip, it is arranged on described first chip; And
One stress protective device; it is built between described first chip and described second chip; and from described substrate toward the described second chip vertical extent, and described stress protective device by column or beam shape vertical or horizontal support to be provided and to be formed by material with pyroconductivity character.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101203964A CN100495701C (en) | 2005-11-11 | 2005-11-11 | A three-dimensional wafer stacking structure with post-and-beam construction and method to stack three-dimensional wafer |
Applications Claiming Priority (1)
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| CNB2005101203964A CN100495701C (en) | 2005-11-11 | 2005-11-11 | A three-dimensional wafer stacking structure with post-and-beam construction and method to stack three-dimensional wafer |
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| CN100495701C true CN100495701C (en) | 2009-06-03 |
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| US20100091475A1 (en) * | 2008-10-15 | 2010-04-15 | Qualcomm Incorporated | Electrostatic Discharge (ESD) Shielding For Stacked ICs |
| TWI469312B (en) * | 2012-03-09 | 2015-01-11 | Ind Tech Res Inst | Chip stack structure and method of fabricating the same |
| US9257399B2 (en) * | 2013-10-17 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D integrated circuit and methods of forming the same |
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