CN100514676C - Strained channel mos device - Google Patents

Strained channel mos device Download PDF

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Publication number
CN100514676C
CN100514676C CNB2007101380239A CN200710138023A CN100514676C CN 100514676 C CN100514676 C CN 100514676C CN B2007101380239 A CNB2007101380239 A CN B2007101380239A CN 200710138023 A CN200710138023 A CN 200710138023A CN 100514676 C CN100514676 C CN 100514676C
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layer
mos device
semiconductor layer
channel mos
strain
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CN101118928A (en
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陈豪育
杨富量
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors

Abstract

A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper semiconductor region overlying the insulator region; patterning the upper semiconductor region and insulator region to form a MOS active region; forming an MOS device comprising a gate structure and a channel region on the MOS active region; and, carrying out an oxidation process to oxidize a portion of the upper semiconductor region to produce a strain in the channel region.

Description

Strained channel mos device
Technical field
The present invention relates to a kind of microelectronic integrated circuit semiconductor element and technology thereof, particularly relate to and a kind ofly have the strained-channel electric crystal that forms on the insulator-semiconductor base material of preferable charge carrier mobility, it utilizes a technology that does not contain brilliant step of heap of stone to form.
Background technology
The semi-conductor electricity crystal structure develops fast, utilizes the technology of electric charge carrier conducting in the admixture control cmos element raceway groove to suffer from bottleneck.Along with cmos element technology is contracted to nanoscale technology, the technology with silicon insulating barrier of complete exhaustion region and local exhaustion region can make MOSFETS act under the situation of low consumpting power.Yet the silicon insulating barrier can produce the charge mobility in self-conductance heating problems thereby the reduction electric crystal channel layer.
Mechanical stress has been played the part of important role on charge carrier mobility, and charge carrier mobility can influence many important parameters, as the switching of critical voltage (VT), saturated (I DSat) and the electric current (On/Off current) that switch switches of drive current.Cause the induction mechanical stress of MOSFET element channel ply strain and charge carrier mobility all to be considered to the acousto-optic scattering phenomenon influence that is produced in the entity technology of complexity.In general, the height of charge carrier mobility is to be directly proportional with the size of drive current.
For instance, prior art of heap of stone brilliant method that utilization lattice constant difference is provided causes the stress on the channel layer and forms strained-channel in order to cause.Yet caused degree of strain can be in follow-up Technology for Heating Processing, and as alleviating in the self-conductance heating effect, therefore the usefulness of element also reduce.The not only complicated and consumption cost of existing brilliant depositing operation of heap of stone more needs the step of multiple tracks just can finish.In addition, the method for utilizing the difference of lattice constant between two materials to produce stress on channel layer can cause the problem that connects face electric leakage (junction leakage), thereby has reduced the reliability and the performance of element.
When the elongation strain channel layer had improved electron mobility in the NMOS element, the hole mobility among the PMOS may be according to the elongation strain of differently strained intensity or compression strain and is improved or reduce.Therefore, the strain that imports various suitable degree on a wafer to the channel layer of PMOS and NMOS element is still a challenge to be overcome.
So, how on the semiconducter IC technology, to develop strained-channel SOI element of improvement and forming method thereof in order to the lift elements performance, and improve its technology, promptly become the target of pursuit.
Summary of the invention
Main purpose of the present invention is at strained-channel SOI element that an improvement is provided and forming method thereof, strained channel mos device and forming method thereof of an improvement particularly, not only overcome the shortcoming and the deficiency of prior art, and promoted element function and improved its technology.
According to above-mentioned purpose of the present invention, propose a kind of selectivity strain MOS element, as constitute one group of NMOS and PMOS selection of components strain PMOS element, and do not influence the strain in the NMOS element.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of strained channel mos device that the present invention proposes, it comprises: a MOS active region, and this MOS active region comprises: an end semiconductor layer; One insulating barrier is disposed on this end semiconductor layer; And a top semiconductor layer, be disposed on this insulating barrier; One MOS element is positioned on this MOS active region, and comprises a grid structure and a channel layer; And the top semiconductor layer of a part of oxidation, optionally in channel layer, form a strain, and the top semiconductor layer of this insulating barrier and this partial oxidation is combined into one and enlarges insulation layer, wherein the both sides of this expansion insulation layer be adjacent to this MOS element source/drain regions, and should enlarge insulation layer in forming the beak shape, and this expansion insulation layer forms concave surface curved surface up in the bottom of this top semiconductor layer in abutting connection with this source/drain regions.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid strained channel mos device, it more comprises the depressed area that is filled with a conductive material, wherein this depressed area is positioned at the two opposite sides that is adjacent to the MOS element in order to form source/drain regions.
Aforesaid strained channel mos device, it more comprises the source/drain regions with a conductive material and raising.
Aforesaid strained channel mos device, wherein said MOS active region are by the electrically insulated structures electric insulation of adjacency, and this electrically insulated structures is shallow trench isolation layer (STI) structure.
Aforesaid strained channel mos device, wherein said MOS improves on abutment surface the active region.
Aforesaid strained channel mos device, wherein said insulating barrier comprises a buried oxide.
Aforesaid strained channel mos device, the thickness of wherein said insulating barrier is approximately less than 20nm.
Aforesaid strained channel mos device, wherein said MOS element comprises a PMOS element, and with this NMOS element electric insulation of adjacency, wherein a NMOS element is formed on the NMOS active region.
Aforesaid strained channel mos device, wherein said strain are a compressive strain, and this compressive strain optionally results from the PMOS element channel layer, and this compressive strain does not influence the strain of this NMOS element region.
Aforesaid strained channel mos device, wherein said NMOS element is formed on the end semiconductor layer.
The present invention compared with prior art has tangible advantage and beneficial effect.As known from the above, in order to achieve the above object, in first embodiment, its method comprises provides the semiconductor base material, and wherein this semiconductor substrate has comprised end semiconductor layer, is disposed at the insulating barrier on this end semiconductor layer and has been disposed at top semiconductor layer on this insulating barrier; This top semiconductor layer of patterning and insulating barrier are in order to form the MOS active region; Form the MOS element on the MOS active region, and the MOS element comprises grid structure and channel layer; And carry out oxidation technology, with the top semiconductor layer oxidation of some in order on channel layer, to produce strain.
Via as can be known above-mentioned, the present invention's one selectivity strain MOS element, wherein this MOS element can be the selectivity strain PMOS element of being made up of one group of NMOS element and PMOS element, and it does not influence the strain on the NMOS element.Its formation method comprises provides semiconductor substrate, and wherein semiconductor substrate comprises end semiconductor layer, is disposed at the insulating barrier on this end semiconductor layer and is disposed at top semiconductor layer on this insulating barrier; This top semiconductor layer of patterning and insulating barrier are in order to form the MOS active region; Form the MOS element on the MOS active region, and the MOS element comprises grid structure and channel layer; And carry out oxidation technology, with the top semiconductor layer oxidation of some in order on channel layer, to produce strain.
By technique scheme, strained channel mos device of the present invention has following advantage at least: the invention discloses a kind of method that goes out optionally to form the compressive strain raceway groove on the PMOS element, wherein the compression in the PMOS element region does not influence the stress in the NMOS element region.At the channel layer generation strain of PMOS element and NMOS element, can obtain preferable level of strain control and charge carrier mobility by individually.In addition, though the method that forms channel layer according to the staggered crystalline substance of heap of stone of lattice constant is also often used in manufacture craft, the method that forms strained channel layer is not limited thereto.The present invention utilizes existing processes to form the method for a mechanical strain element channel layer, the productivity ratio that can reduce product cost, improve technological process and promote wafer.More can solve the shortcoming that connects the face electric leakage in the prior art, improve the overall efficiency of element whereby.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Figure 1A to Fig. 1 F is in the embodiments of the invention, and strained-channel SOI NMOS and PMOS element are at the side sectional view of each processing step.
Fig. 2 A to Fig. 2 C is in the another embodiment of the present invention, and strained-channel SOI NMOS and PMOS element are at the side sectional view of each processing step.
Fig. 3 is the schematic flow sheet of various embodiments of the present invention.
12: semiconductor substrate 12A: end semiconductor layer
12B: electric insulation layer 12C: top semiconductor layer
14A:PMOS element region 14B:NMOS element region
16A: shallow trench isolation layer 16B: shallow trench isolation layer
16C: shallow trench isolation layer 18A:PMOS element
18B:NMOS element 20A: depressed area
20B: depressed area 20AA: source area
20BB: drain region 22A: gate dielectric
22B: gate electrode layer 24A: lateral wall insulation clearance wall
24B: lateral wall insulation clearance wall 30: protection cover layer
32A:PMOS channel layer 32B:NMOS channel layer
301: step 303: step
305: step 307: step
309: step 311: step
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to foundation the specific embodiment of the present invention, structure, feature and effect thereof, describe in detail as after.
Though it is optionally to form compressive strain channel PMOS element that the present invention forms the mode of soi structure, and do not influence in abutting connection with the strain of NMOS element, but can utilize technology separately in the channel layer of adjacency NMOS element, to form an elongation strain in a selective manner yet.
See also the cutaway view of the base material part of insulator-semiconductor layer among Figure 1A.In the semiconductor substrate 12 (as silicon), electric insulation layer 12B is formed under the semiconductor substrate surface to define end semiconductor layer 12A and top semiconductor layer 12C.Wherein electric insulation layer 12B can be a buried oxide (buried oxide, BOX).Buried oxide 12B can be formed by existing method, as utilizes cloth to plant the degree of depth and the thickness of the size decision buried oxide 12B of energy.For example, the cloth oxonium ion of planting high-energy (200-1000keV) forms buried oxide to semiconductor substrate 12 and via a high-temperature annealing step (about 1200 degree are to 1350 degree).In addition, other existing methods also can be used to form insulating barrier 12B in this technical field.The thickness of buried oxide 12B can be between about 100 dust to 5000 dusts, even less than 200 dusts (20nm).The thickness of top semiconductor layer 12C is between about 50 dust to 2000 dusts.But the actual (real) thickness of buried oxide 12B and top semiconductor layer 12C should be looked the parameter value of actual components (electric crystal) size and element operation and decide.
Consult Figure 1A once more, semiconductor substrate 12 mixes by implanting ions and forms P doped region (P well) and N doped region (N well) in order to indivedual NMOS elements (electric crystal) and PMOS elements (electric crystal) of forming on two doped regions.
See also Figure 1B, utilize existing Patternized technique (as little shadow patterning and etching) to etch the thickness of top semiconductor layer 12C and buried oxide 12B in order on semiconductor substrate 12A, to form a PMOS element region 14A and a NOMS element region 14B.Wherein PMOS element region 14A is outwards outstanding by semiconductor substrate 12A, and NOMS element region 14B is in the same plane with semiconductor substrate 12A.
In an embodiment, the thickness of buried oxide 12B is less than 20nm.Select preferable buried oxide thickness, can not need follow-up selectivity building crystal to grow step on NMOS element region 14B can reach the purpose that ladder height is removed.In addition, in the middle of follow-up thermal oxidation process (being detailed later), the buried oxide 12B with preferred thickness can produce a high compression stress because of a large amount of the expansion (as swell increment percentage).
Consult Figure 1B once more, (Shallow Trench Isolation, STI) structure 16A, 16B and 16C utilize existing method to form and be adjacent to respectively NMOS element region and PMOS element region for electric insulation layer such as shallow trench isolation layer.For instance, hard mask layer is that patterning and the etching step that semiconductor substrate 12A goes up the sti trench groove that continuing is formed on the base material.Cloth is planted and is finished and after light shield removes, filled up the insulation material in the sti trench groove, as silicon dioxide.Be preferably on the surface of semiconductor substrate 12 an outstanding STI oxide layer, as shown in FIG., the upper surface of outstanding STI oxide layer be with PMOS active region 14A in the upper surface of buried oxide 12B after the etching be in same plane.
See also Fig. 1 C, PMOS element (electric crystal) 18A and NMOS element (electric crystal) 18B with grid structure utilize existing processes and material to form on PMOS element region 14A and NMOS element region 14B.These MOS elements include gate dielectric (gate dielectricportion) 22A, gate electrode layer (conductive gate electrode portion) 22B and lateral wall insulation clearance wall (sidewall insulator spacer) 24A and 24B.Though the lateral wall insulation clearance wall shown in the figure has the chamfering of a circular arc, also can be existing L type clearance wall or multilayer clearance wall.Before lateral wall insulation clearance wall 24A and 24B formation, on the semiconductor layer 12C of top, form one and utilize ring-type cloth to plant the light doping section that forms, and this light doping section is adjacent to gate electrode layer 22B.
See also Fig. 1 D, protection cover layer 30 is formed at NMOS element region 14B and goes up and be overlying on that on sti structure 16B and the 16C it to be avoided etched in follow-up dry etch process.Protection cover layer 30 can be the organic or inorganic material.After the dry-etching step finishes, be positioned at that the semiconductor substrate 12 of PMOS element 18A below is etched to be gone out a degree of depth and form depressed area 20A and 20B. Depressed area 20A and 20B are between PMOS element 18A both sides and sti structure 16A and 16B adjacent to PMOS element 18A.
See also Fig. 1 E, it illustrates the generalized section of the present invention's one important step.When with about 800 the degree to 900 the degree temperature finish a dry type (or wet type) oxidation technology after, the part top semiconductor layer 12C promptly oxidized.The zoneofoxidation of this part has comprised the external oxidation district (outerportion) of a preferential oxidation and the block that diffuses to buried oxide 12B.Therefore, on top semiconductor layer 12C (material can be silicon), can produce a compression.This compression has the lateral stress line that horizontal direction produced on finished surface.In oxidation technology, the zoneofoxidation of silicon semiconductor layer 12C part combines with buried oxide 12B with the expansion insulation layer, and this insulation layer forms a rostriform structure because of having comprised buried oxide 12B.Consult the buried oxide 12B and the top semiconductor layer 12C of the central adjacency of diagram, top semiconductor layer 12C forms an outstanding zone towards the buried oxide 12B direction of adjacency, that is to say, comprised that the silicon oxide layer 12C of buried oxide 12B has concave surface curved surface up in the bottom.
See also Fig. 1 F, utilize existing brilliant technology of heap of stone to deposit (growth) and form source area 20AA and drain region 20BB in order to fill depressed area 20A and 20B as the semiconductor material of silicon or as the strain semiconductor alloy of SiGe.Lattice constant can be used greater than the strained silicon alloy of semiconductor substrate (as silicon substrate 12A) and be filled among depressed area 20A and the 20B, increases the compression on the PMOS channel layer 32A whereby.After the depressed area filling finishes, can in brilliant technology of heap of stone or implanting ions technology, be added in order to reduce the resistance value of source electrode and drain electrode in the original place as the P admixture of this class of boron.
Utilizing semiconductor material or semiconducting alloy to be filled in depressed area 20A and 20B in order to after forming source area 20AA and drain region 20BB, protection cover layer 30 is removed.PMOS element 18A has a compressive strain channel layer 32A, and NMOS element 18B does not form the induction mechanical stress at its channel layer 32B.In addition, also can utilize technology separately in NMOS channel layer 32B, to produce a tensile stress.
' follow-up formation silicide is with in the technology that reduces the lip-deep contact resistance of source/drain, the material of surface region is a silicon, and the material at gate electrode top is a polysilicon.
See also Fig. 2 A, it illustrates another embodiment of the present invention.Before the shaping structures shown in Fig. 2 A, step is all identical with aforesaid the 1st embodiment with the numbering of element, no longer adds to give unnecessary details at this.
See also Fig. 2 B, the structure shown in the figure as first embodiment in Fig. 1 D, do not form the depressed area, make top semiconductor layer 12C (material can be silicon) oxidized and form the less semiconductor substrate 12C of a compression but carry out oxidation technology from the outside area BOB(beginning of block).Therefore, can with the source area of PMOS element 18A both sides adjacency and drain region on form a beak shape.
After oxidation technology, can form a leptosomatic semiconductor layer 12C, and the lateral stress of this semiconductor region 12C with horizontal direction, lateral stress channel layer 32A in PMOS element 18A goes up and produces a compression whereby.
See also Fig. 2 C, source area 34A and drain region 34B are formed at two opposition side limits on PMOS element 18A and the NMOS element 18B respectively.Source area 34A and drain region 34B can utilize the method for deposited semiconductor material or semiconducting alloy, are forming source area 34A and the drain region 34B with predetermined altitude (as 25 dust to 500 dusts) with lateral wall insulation clearance wall 24A and the adjacent place of 24B.
Source area 34A and drain region 34B can by the selectivity building crystal to grow (SelectiveEpitaxial Growth, SEG) technology and utilize silicon or silicon alloy (as sige alloy) in order to increase or to keep compression on the PMOS element channel layer 32A.Source electrode 34A and drain region 34B can mix with P admixture (as boron) in the original place and form, or carry out an implanting ions technology after source electrode 34A and drain region 34B moulding.In addition, PMOS element 18A can separate with source/drain regions on the NMOS element 18B and forms.Source/drain regions can be by semiconductor silicon or made less than the elongation strain semiconducting alloy of the silicon silicide of carbon (as be doped with) by lattice constant.This elongation strain semiconducting alloy can be by adding or being generated the admixture of a N type and formed by the original place.Existing metal silicide moulding process can be used to form a metal silicide on the source/drain regions surface, so that carry out the formation of follow-up contact.
Therefore, the present invention puies forward a kind of method that goes out optionally to form the compressive strain raceway groove on the PMOS element, and wherein the compression in the PMOS element region does not influence the stress in the NMOS element region.At the channel layer generation strain of PMOS element and NMOS element, can obtain preferable level of strain control and charge carrier mobility by individually.In addition, though the method that forms channel layer according to the staggered crystalline substance of heap of stone of lattice constant is also often used in manufacture craft, the method that forms strained channel layer is not limited thereto.The present invention utilizes existing processes to form the method for a mechanical strain element channel layer, the productivity ratio that can reduce product cost, improve technological process and promote wafer.More can solve the shortcoming that connects the face electric leakage in the prior art, improve the overall efficiency of element whereby.
See also Fig. 3, it illustrates the flow chart of various embodiment among the present invention.In step 301, provide a semiconductor substrate with insulating buried layer (as buried oxide).In step 303, form the NMOS and the PMOS active region of electric insulation, wherein the height of PMOS active region is raised, and has comprised the buried oxide district, bottom that extends on the finished surface.In step 305, the grid structure of NMOS and PMOS is formed on other active region.In step 307, the depressed area is formed in abutting connection with the source/drain regions on the arbitrary limit of PMOS grid structure.In step 309, utilize oxidation technology will be disposed at the top semiconductor layer oxidation of PMOS grid structure below, thereby form a compressive strain channel layer.In step 311, form a source/drain regions with high height, and be that conductive material is made.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.

Claims (10)

1. strained channel mos device is characterized in that comprising:
One MOS active region comprises:
One end semiconductor layer;
One insulating barrier is disposed on this end semiconductor layer; And
One top semiconductor layer is disposed on this insulating barrier;
One MOS element is positioned on this MOS active region, and comprises a grid structure and a channel layer; And
The top semiconductor layer of part oxidation, optionally in channel layer, form a strain, and the top semiconductor layer of this insulating barrier and this partial oxidation is combined into one and enlarges insulation layer, wherein the both sides of this expansion insulation layer are adjacent to the source/drain regions of this MOS element, and should enlarge insulation layer in forming the beak shape, and this expansion insulation layer forms concave surface curved surface up in the bottom of this top semiconductor layer in abutting connection with this source/drain regions.
2. strained channel mos device according to claim 1 is characterized in that more comprising the depressed area that is filled with a conductive material, and wherein this depressed area is positioned at the two opposite sides that is adjacent to the MOS element in order to form source/drain regions.
3. strained channel mos device according to claim 1 is characterized in that more comprising the source/drain regions with a conductive material and raising.
4. strained channel mos device according to claim 1 is characterized in that the electrically insulated structures electric insulation of wherein said MOS active region by adjacency, and this electrically insulated structures is a shallow trench isolation layer structure.
5. strained channel mos device according to claim 1 is characterized in that wherein said MOS active region improves on abutment surface.
6. strained channel mos device according to claim 1 is characterized in that wherein said insulating barrier comprises a buried oxide.
7. strained channel mos device according to claim 1, the thickness that it is characterized in that wherein said insulating barrier is less than 20nm.
8. strained channel mos device according to claim 1 is characterized in that wherein said MOS element comprises a PMOS element, and with this NMOS element electric insulation of adjacency, wherein a NMOS element is formed on the NMOS active region.
9. strained channel mos device according to claim 8 is characterized in that wherein said strain is a compressive strain, and this compressive strain optionally results from the PMOS element channel layer, and this compressive strain does not influence the strain of this NMOS element region.
10. strained channel mos device according to claim 8 is characterized in that wherein said NMOS element is formed on the end semiconductor layer.
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