CN100555255C - The method of the system of deal with data and selection interleaving policies - Google Patents
The method of the system of deal with data and selection interleaving policies Download PDFInfo
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
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Abstract
Product and associated method and system relate to and write interleaving policies with selection and irrespectively select to read interleaving policies.In various realizations, described to be chosen in operating period can be static or dynamic.Read interleaving policies and write in the realization of interleaving policies in Dynamic Selection, described selection can be based on various operating conditionss, such as temperature, power supply, cell voltage and operator scheme.The example of operator scheme can comprise: (1) is read or is write flash memory when being connected to external power source, (2) when (for example by compact power, read from flash memory when battery) powering, and (3) write to flash memory when being powered by compact power.
Description
Technical field
Various realizations generally speaking can relate to reference-to storage, and specific realization can relate to the method and system of the interleaving policies (interleaving policy) that is used for reference-to storage.
Background technology
Along with calculation element in the enhancing aspect performance and the characteristics, the needs of data memory storage are constantly increased.For example, data storage device can be used for storing the programmed instruction (that is code) that can be carried out by processor.Data storage device also is used to store the data of other type, comprises audio frequency, image and/or text message as example.Recently, the system with the data storage device that can store substantial data content (for example, song, music video etc.) can be extensive use of in portable terminal.
This mancarried device comprises data-carrier store, and described data-carrier store has less form factor and can operate under the compact power such as battery.Data storage device in some portable terminal can provide nonvolatile memory, and described nonvolatile memory can keep data when power supply disconnects.Mancarried device uses various nonvolatile data storage, such as hard disk drive, EEPROM (electrically erasable programmable ROM) and flash memory.
Flash memory has become the semiconductor memory that is extensive use of type.Flash memory can for example provide the nonvolatile memory in portable electron device and the consumer application apparatus.
There is this flash memory of two types of NOR flash memory and nand flash memory.Usually, the NOR flash can be different from nand flash memory in some aspects.For example, the NOR flash memory typically provides the performance of run time version on the spot, but and random access (that is, as RAM).For example, the NOR flash memory can provide code storage and directly carry out in portable electron device, cellular phone and PDA.
By comparison, the NAND flash can be typically obliterated data more apace, visit data with set of bursts (for example, the group section of 512 bytes), and can provide term of life than the longer erasing times of NOR flash memory of comparing.Nand flash memory provides the nonvolatile memory of every bit lower cost as the high density file storage medium that is used for consumer device usually, and described consumer device is such as digital camera and MP3 player as example.Nand flash memory also can be used in the application apparatus such as the data-carrier store in the camera cell telephones.
In some data-storage system, can between a plurality of memory locations, interlock and carry out memory access.In the system of RAID-0 type, for example, data can be divided into the N piece, they are write N memory location simultaneously or read them from N memory location simultaneously.Interleaving systems can be simultaneously writes in 4 different memory locations each with the piece of 2k, and needn't waiting system 8k be write a memory location.
Summary of the invention
In various realizations, product and associated method and system relate to and write interleaving policies with selection and irrespectively select to read interleaving policies.In various realizations, described to be chosen in operating period can be static or dynamic.Read interleaving policies and write in the realization of interleaving policies in Dynamic Selection, described selection can be based on various operating conditionss, such as temperature, power supply, cell voltage and operator scheme.The example of operator scheme can comprise: (1) is read or is write flash memory when being connected to external power source, (2) when (for example by compact power, read from flash memory when battery) powering, and (3) write to flash memory when being powered by compact power.
Some realization can provide one or more advantages.For example, for portable electrical power applications equipment, but extending battery life.Can be provided with or select to read and write interleaving policies independently realizing desired performance, thus under acceptable electric power consumption (for example, peak point current) characteristic the minimum memory access time.Can be according to various operating conditions adjustment to reading and write the selection of interleaving policies.Some realization can for example reduce the access time and minimize Dynamic Selection between the peak point current, described operating conditions such as temperature information, power availability, cell voltage and/or operator scheme based on operating conditions.
In order to realize the present invention, a kind of system that uses interlace memory to come deal with data is provided, described system comprises: power supply; In operation, be coupled to a plurality of storage unit of power supply; Memory Controller is used for optionally controlling the staggered ratio that is used to visit described a plurality of storage unit; And processor, be used to discern staggered ratio for Memory Controller, comprising: receive device for the request of storage unit access; And control the peak point current drawn from power supply by storer device by the staggered ratio of selecting to be used to carry out the request of access that is received with processes said request, wherein, staggered ratio is bigger, and then the peak point current of Xi Quing is bigger, and staggered ratio is less, and then the peak point current of Xi Quing is less.
In order to realize the present invention, provide a kind of selection to be used to visit the method for the interleaving policies of flash memory, described flash memory is configured to the memory interlace data, and described method comprises: receive the request of reading for from staggered flash memory; Identification is used for from what flash memory read reading staggered ratio based on first group of criterion; Reception is for the request that writes to flash memory; And based on second group of criterion identification is used for writing staggered ratio to what flash memory write, wherein, the staggered ratio of being discerned that reads is different with writing staggered ratio, and wherein, staggered ratio is bigger, then the peak point current of Xi Quing is bigger, and staggered ratio is less, and then the peak point current of Xi Quing is less; Wherein, first group of criterion comprises the one or more members in following group, and described group comprises: outer power voltage, can be used for to the flash memory power supply electric current, temperature, use be external power source or battery and cell voltage; Wherein, second group of criterion comprises the one or more members in following group, and described group comprises: outer power voltage, can be used for electric current, temperature, operator scheme, data transfer rate, power supply and cell voltage to the flash memory power supply; Wherein, when outer power voltage or can be used for when the electric current of flash memory power supply surpasses second threshold value, second group of criterion will write staggered ratio and be defined as greater than minimum is available and write staggered ratio; And wherein, first group of criterion be supply voltage or can be used for when the electric current of flash memory power supply surpasses first threshold externally, to read staggered ratio is defined as greater than minimum is available and reads staggered ratio, perhaps first group of criterion be not when using the power of drawing from the portable energy-storing source to operate flash memory, to read staggered ratio and be defined as the maximum available staggered ratio that reads, wherein, second threshold value is different from first threshold.
In order to realize the present invention, the method that provides a kind of selection to be used for the interleaving policies of reference-to storage, described method comprises: receive request and relational storage interrogation signal for reference-to storage; Receive first signal relevant with first group of criterion and with second group of secondary signal that criterion is relevant, described first group of criterion is included at least one different under at least one operating conditions criterions with second group of criterion; By carry out calculating selecting to read interleaving policies based on first signal or to select to write interleaving policies based on secondary signal, identification is used to carry out the interleaving policies of described request for reference-to storage; And the interleaving policies that uses identification sends output signal to carry out the memory access of being asked; Wherein, first group of criterion comprises the one or more members in following group, and described group comprises: outer power voltage, can be used for to the flash memory power supply electric current, temperature, use be external power source or battery and cell voltage; Wherein, second group of criterion comprises the one or more members in following group, and described group comprises: outer power voltage, can be used for electric current, temperature, operator scheme, data transfer rate, power supply and cell voltage to the flash memory power supply; Wherein, when supply voltage or can be used for when the electric current of flash memory power supply surpasses second threshold value, secondary signal will write interleaving policies and be defined as greater than the available interleaving policies that writes of minimum; And wherein, first signal is at supply voltage or can be used for when the electric current of flash memory power supply surpasses first threshold, to read interleaving policies is defined as greater than the available interleaving policies that reads of minimum, perhaps first signal is not when using the power of drawing from the portable energy-storing source to operate flash memory, to read interleaving policies and be defined as the maximum available interleaving policies that reads, wherein, second threshold value is different from first threshold.
In following drawing and description, set forth the details of one or more realizations of the present invention.By instructions and accompanying drawing and claim, other characteristics of the present invention, purpose and advantage will become clear.
Description of drawings
Fig. 1 is the block diagram that the example of the system that comprises flash memory is shown.
Fig. 2 is the process flow diagram that is illustrated in the method for selecting to read and write interleaving policies in the system of Fig. 1.
Fig. 3 is the process flow diagram that the method for the interleaving policies of application choice when the request memory access operation is shown.
Identical label is indicated identical parts in each accompanying drawing.
Embodiment
Fig. 1 illustrates and can use flash memory to store example with the system 100 of retrieve data.For example, system 100 can be a handheld portable devices, such as MP3 player, cellular phone, PDA (portable digital-assistant), GPS, portable processor, portable audio/video recording apparatus, portable video player etc.System 100 can use and select suitable interleaving policies that is used for read operation and the suitable interleaving policies that is used for write operation.In some implementations, the selected interleaving policies that reads can be different from the selected interleaving policies that writes.In some implementations, dynamically and/or independently of one another select to read and write interleaving policies.
Described system 100 comprises: microprocessor 102, Memory Controller 104 and one or more flash memory 106a, 106b, 106c and 106d.Microprocessor 102 can be carried out read or write operation after selection is read or write interleaving policies.For example, microprocessor 102 can send to Memory Controller 104 and initiate reading from flash memory 106a, 106b, 106c and 106d by read interleaving policies and the reading order that will select.Memory Controller 104 is carried out reading order according to the interleaving policies of selecting that reads subsequently.Microprocessor 102 can send to Memory Controller 104 and initiate writing to flash memory by write interleaving policies and the write command that will select.Memory Controller 104 is carried out write command according to the interleaving policies of selecting that writes subsequently.System 100 can be configured to select to be suitable for the interleaving policies of current operating conditions, described operating conditions is such as power supply, cell voltage, temperature and/or operator scheme as example.
Selectedly read and/or write interleaving policies and determine quantity that flash memory 106a, 106b, 106c and 106d are visited simultaneously.Staggered by using, Memory Controller 104 can read or be written in data staggered between a plurality of memory storages simultaneously.The definable interleaving policies is to select to be suitable for the staggered ratio of operating conditions.For example, 4: 1 staggered ratio can be corresponding to system 100 four word write stories with data in single operation,, each word are write diverse location among the flash memory 106a-106d simultaneously that is.2: 1 staggered ratio can use four the word write stories of two operations with data corresponding to system 100, that is, two words are write simultaneously.1: 1 staggered ratio can use four the word write stories of four operations with data corresponding to system 100, that is, and and word of write-once.
Higher staggered ratio can spend the less time flash memory is read or writes, but the peak electricity relevant with storage operation fails to be convened for lack of a quorum higher.Lower staggered ratio can spend the long time flash memory is read or writes, but the peak electricity relevant with storage operation fails to be convened for lack of a quorum lower.In some operating conditions, system 100 can be configured to limit or minimize peak point current or minimized memory access time.For example, if cell voltage drops to below the threshold value, then system 100 can be configured to select the lower staggered ratio that is used for read operation.
When Memory Controller 104 receives reading order or write command, it will carry out described order according to the interleaving policies of being selected by microprocessor that reads or write.In some implementations, microprocessor 102 and Memory Controller 104 can be the device that separates (for example, independently integrated circuit).In other is realized, microprocessor 102 and Memory Controller 104 can be integrated into single assembly (for example, ASIC microcontroller).In this example, Memory Controller 104 comprises Media Interface Connector 108.Media Interface Connector 108 comprises 4 register 110a, 110b, 110c and 110d.Among described 4 register 110a-110d each can store the word that will send to the data of flash memory 106a-106d respectively (or byte, long word, quad word etc.) temporarily or the word of the data that receive from flash memory 106a-106d respectively (or byte, long word, quad word etc.).
In a certain example, system 100 can following selection and use be used to read interleaving policies with write command.Microprocessor 102 can be initiated the write command succeeded by reading order.The said write order can relate to four words with data and write four positions among four flash memory 106a, 106b, 106c, the 106d, and reading order can relate to four words of four position reading of data from four flash memory 106a, 106b, 106c, 106d.Microprocessor 102 at first sends to Memory Controller 104 with the interleaving policies that writes of write command and selection.In described example, the selected interleaving policies that writes can be 4: 1.In order to finish the execution of write command, Memory Controller 104 can write flash memory 106a, 106b, 106c, 106d with the data that are stored among register 110a, 110b, 110c, the 110d subsequently simultaneously.
After write command was finished, microprocessor 102 can send to Memory Controller 104 with the interleaving policies that reads of reading order and selection.In described example, the selected interleaving policies that reads can be 1: 1.In order to finish the execution of reading order, Memory Controller 104 can use four storage operations, reads the data that are stored in register 110a, 110b, 110c, the 110d from flash memory 106a, 106b, 106c, 106d one at a time.For example, Memory Controller 104 can be sent to register 110a with the data that are stored among the flash memory 106a.Then, Memory Controller 104 can be sent to register 110b with the data that are stored among the flash memory 106b.Thereafter, Memory Controller 104 can be sent to register 110c with the data that are stored among the flash memory 106c.At last, Memory Controller 104 can be sent to register 110d with the data that are stored among the flash memory 106d.
In described example, each flash memory 106a, 106b, 106c, 106d comprise four flash memory tube cores, controller and register 112.Register 112 can be stored the minimum of each flash memory 106a-106d.The minimum of each flash memory 106a-106d can influence the selection to interleaving policies.For example, if cell voltage in the threshold value surplus that is lower than during the write operation on the minimum of each flash memory 106a-106d, then microprocessor can select to have the interleaving policies that writes of low staggered ratio.The threshold value balance information of write operation can be stored among the NVM124 relevant, the threshold value balance information of read operation can be stored among the NVM 124 relevant with fetch policy 130 with writing interleaving policies 130.
In the example shown, minimum can be 3.1 volts, for writing interleaving policies, voltage margin can be arranged on 0.5 volt (threshold value is placed 3.6 volts), and, voltage margin can be arranged on 0.2 volt (threshold value is placed 3.3 volts) for reading interleaving policies.When cell voltage dropped to below 3.6 volts, microprocessor 102 can reduce to 1: 1 from 2: 1 with writing staggered ratio.When cell voltage dropped to below 3.3 volts, microprocessor 102 can reduce to 2: 1 from 4: 1 with reading staggered ratio.These values only are exemplary, and are not subject to battery voltage range.In some implementations, drag zone can be applied to voltage threshold.
Can import 114 or the electric power of system 100 is provided by battery 116 by external power source.External power source input 114 and battery 116 are delivered to pressure regulator 118 with power supply.Pressure regulator 118 can comprise the DC of linear voltage regulator, switching mode to DC transducer and/or low leakage regulator (not shown), and pressure regulator 118 comprises power supervisor 120, the tabulation of the electricity condition 122 of its storage system 100.For example, the status information of supervision can comprise: whether external power source input 114 is connected to power supply; Whether battery exists; And battery voltage information.In some implementations, microprocessor 102 can be selected interleaving policies according to electricity condition 122.For example, microprocessor 102 can be configured to when system 100 is connected to external power source, the interleaving policies of selecting to have maximum staggered ratio allows higher relatively peak point current thus to reduce memory access time.
The operator scheme of data-interface 132 can influence the selection to interleaving policies.For example, if data-interface 132 receives data from external source, then microprocessor 102 can select to have the interleaving policies that reads of higher staggered ratio.If just as the mancarried device of the data that receive flash memory, then microprocessor 102 can select to have the interleaving policies that writes of low staggered ratio in system 100.
In some implementations, the input that this user selects can be overthrown.For example, when external power source was connected to external power source and imports 114, even be used to select the maximum battery life pattern as example, microprocessor 102 also can select maximum can realize staggered ratio.In another example, when the temperature of system 100 surpassed predetermined threshold value, even for example the user has selected minimum delay time pattern and external power source to be connected to external power source input 114, microprocessor 102 also can select minimum can realize staggered ratio.
In each was realized, audio output device 140 can be internal loudspeaker, hummer and/or other audible indicator.In some implementations, amplifier can be coupled to out connector, described out connector is suitable for providing the signal that comprises audio-frequency information to one or more earphones or external loudspeaker (it can be amplified by the outside) group.Some realization can provide wired or wireless (for example, bluetooth or other RF) between system 100 and the external audio converter apparatus interface.
In some implementations, display 142 can be that it provides text based interface and/or graphical interfaces to the user as the LCD of example or TFT display.The brightness of display 142 and/or light intensity can be adjustable.In some implementations, microprocessor 102 can operate in the lower interleaving policies of situation selection of following time of higher brightness and/or light intensity at display 142, to keep battery life.
For example, carrying out under the battery-powered operator scheme of the flow transmission of data and system at camera 150 and/or microprocessor 102, what microprocessor 102 can select to have enough staggered ratios writes interleaving policies to handle maximum data rate.In a certain example, for the Voice ﹠ Video information of combination, enough staggered ratio can be 4: 1, and for independent video information, enough staggered ratio can be 2: 1, and for rest image or audio-frequency information, enough staggered ratio can be 1: 1.
For another example, by battery 116 operations, simultaneously under the operator scheme that reads from flash memory 106a-106d, microprocessor 102 can be selected lower to read interleaving policies with maximized battery life in system 100.When for example, described operator scheme can occur in the mancarried device of video, audio frequency and/or other (for example, text) information that being used as is used for resetting is stored in flash memory 106a-106d.
As another example, by external power source, read or under the operator scheme that flash memory 106a-106d writes, microprocessor 102 can select to read and/or write interleaving policies to minimize the access time from flash memory 106a-106d simultaneously in system 100.In a certain application, can realize that data transfer rate transmits data (for example, song, video) to flash memory 106a-106d or from flash memory 106a-106d, finishes the required time of transfer operation to minimize by maximum.
Perhaps, can interleaving policies be determined to reading and writing independently, storage or alternate manner default, and needn't come dynamic adjustments according to cell voltage, temperature or operator scheme.
In Fig. 2, flow process Figure 200 illustrates the example of the operation that microprocessor 102 can carry out when the realization of carrying out test code 126.Although example shown in Figure 1 illustrates the single square frame of being carried out by microprocessor 102 that is stored in the test code 126 among the NVM 124, some or all shown in but other processor or logical circuit can be carried out in the operation, and can use the instruction that is different from the position among the NVM 124 that is stored in such as the RAM (not shown).
In described example, when interleaving policies 130 was upgraded in microprocessor 102 requests, described method began in step 205.Describe in further detail with reference to Fig. 3 and can impel microprocessor to initiate condition the renewal of interleaving policies 130.
If be not higher than the predetermined threshold value temperature in step 215 temperature, then microprocessor 102 is checked power supply in step 235.If using external power source in step 240 system 100, then microprocessor 102 selects to have the interleaving policies that is used to read and write both of maximum staggered ratio in step 245, and the staggered ratio of described maximum was such as 4: 1 as example.Then, the interleaving policies 130 that reads and write that microprocessor 102 will be selected in step 225 writes among the NVM 124, and described method finishes in step 230.
In step 240, if system 100 is used as power supply with battery 116, then microprocessor 102 is checked cell voltage by the status register 122 that reads the power supervisor 120 in the pressure regulator 118 in step 250.Then, microprocessor 102 is in the operator scheme of step 255 check system 100.For example, operator scheme can comprise the operation of system's 100 current execution and the operator scheme that the user selects, such as maximum battery life pattern or minimum delay pattern.As another example, microprocessor 102 can be checked the data stream in the data-interface 132, the operating conditions of display 142 and the output in the audio output device 140.If these devices are drawn a large amount of electric currents, then microprocessor 102 can select to have the interleaving policies of low staggered ratio.After checking cell voltage and operator scheme, microprocessor 102 is selected to write interleaving policies and is selected to read interleaving policies in step 265 in step 260 independently.Then, the interleaving policies 130 that reads and write that microprocessor 102 will be selected in step 225 is stored among the NVM 124, and described method finishes in step 230.
In Fig. 3, process flow diagram 300 illustrates the example of microprocessor 102 executable operation when carrying out the realization of control routine 128.Microprocessor 102 can be carried out control routine 128 to select suitable interleaving policies and the interleaving policies of selecting is sent to Memory Controller 104.In described example, when microprocessor 102 receives when being used to visit the order of flash memory 106a-106d, described method begins in step 305.In step 310, microprocessor 102 receives and writes or reading order.For example, when the user downloaded data to flash memory 106a-106d by data-interface 132, microprocessor 102 can receive write command.As another example, when the user used user interface 138 to come indication mechanism 100 to play the video that is stored among the flash memory 106a-106d, microprocessor 102 can receive reading order.
If microprocessor 102 determines not need to upgrade interleaving policies in step 315, then microprocessor 102 checks that in step 320 described order is reading order or write command.If the order that receives is write command, then microprocessor 102 will write interleaving policies in step 325 and send to Memory Controller 104.Then, in step 330, microprocessor 102 sends to Memory Controller 104 with write command, and described method finishes in step 335.
In step 320, if described order is a reading order, then microprocessor 102 will read interleaving policies in step 340 and send to Memory Controller 104.Then, in step 345, microprocessor 102 sends to Memory Controller 104 with reading order, and described method finishes in step 335.
Although described a kind of realization of described method, but other realization can be carried out described step according to different orders, perhaps can carry out the alter mode that is used to realize identical major function, described major function is used to select suitable interleaving policies that flash memory is read and writes.
Although described the example of the system that can be of portable form, in using, can adopt other realization such as other processing of desktop or networked environment with reference to Fig. 1.
Some system can be embodied as can be according to the computer system of realization use of the present invention.For example, various realizations can comprise: numeral and/or mimic channel, computer hardware, firmware, software or its combination.Can realize described equipment in the computer program that visibly is included in the information carrier, so that carried out by programmable processor, described information carrier is the signal of machine-readable storage device or propagation for example; And can carry out described method by the programmable processor of execution of programs of instructions, so that carry out function of the present invention by output is operated and produced to the input data.Can advantageously in one or more computer programs, realize described method, described computer program can be carried out in programmable system, described programmable system comprises at least one programmable processor, at least one input media and/or at least one output unit, wherein, described programmable processor is coupled and is used for receiving data and instruction from data-storage system, and data and instruction are sent to data storage device.Computer program is can directly or indirectly use in computing machine so that carry out the set of the instruction of specific activities or generation particular result.Can write computer program with any type of programming language, described programming language comprises compiling or interpretative code, can use described computer program by any form, comprise as being independent of the program of operating system, perhaps as module, parts, subroutine or other unit of being adapted at using in the computing environment.
As example, the suitable processor of the program that is used to execute instruction comprises general purpose microprocessor and special microprocessor, and they can comprise one of multiprocessor of uniprocessor or any kind of computing machine.Usually, processor will from ROM (read-only memory) or random access memory or above both receive instruction and data.The necessary parts of computing machine are the processors that is used to execute instruction and are used for storage instruction and one or more storeies of data.Usually, computing machine will also comprise one or more mass storages of being used for storing data files or be coupled as with described mass storage in operation and communicate; This device comprises such as the disk of internal hard drive and removable disk, magneto-optic disk and CD.The memory storage that is suitable for visibly comprising computer program instructions and data comprises the nonvolatile memory of form of ownership, as example, it comprises such as the semiconductor storage of EPROM, EPPROM and flash memory devices, disk, magneto-optic disk and CD-ROM such as internal hard drive and removable disk and DVD-ROM dish.Can replenish processor and storer by ASIC (special IC), perhaps described processor and storer be incorporated among the ASIC.
In some implementations, available same or analogous information comes each system 100 is programmed, and/or come each system 100 of initialization with the information that is equal to substantially that is stored in volatibility and/or the nonvolatile memory.For example, a data-interface can be configured to when the suitable host apparatus that is coupled to such as desktop PC or server, carry out configuration automatically, download and/or automatically updating function automatically.
In some implementations, can be configured to carry out specific function with one or more user interface characteristics are self-defined.Can in the computer system that comprises graphic user interface and/or Internet-browser, realize the present invention.In order to provide interaction to the user, can on such computing machine, carry out some realization, described computing machine has display device, keyboard and the pointing device to user's display message of being used for such as CRT (cathode-ray tube (CRT)) or LCD (LCD) monitor, described pointing device such as mouse or cursor movement ball, by them, the user can provide input to computing machine.
In various realizations, system 100 can use suitable communication means, equipment and technology to communicate.For example, system 100 (for example can use point-to-point communication and relevant apparatus, can to/transmit the device of data from system 100) communicate, in point-to-point communication, by special-purpose physical link (for example, optical fiber link, point-to-pointly write, daisy chain) message directly is transferred to receiver from the source.The parts of described system can be by comprising packet-based message on the communication network any form or the medium of analog or digital data communication come exchange message.For example, the example of communication network comprises: the computing machine and the network of LAN (LAN (Local Area Network)), WAN (wide area network), MAN (Metropolitan Area Network (MAN)), wireless and/or optical-fiber network and formation internet.Other realization can by to all devices that are coupled via communication network or basically all devices broadcast message transfer, for example, by using omni-directional radio frequency (RF) signal.Other realization can be transmitted the message that is characterized by short transverse, such as RF signal of directed (or narrow beam) antenna transmission of use or the infrared signal of using by focusing optics alternatively.Other realization can be used suitable interface and agreement, such as example and unrestricted USB 2.0, live wire, ATA/IDE, RS-232, RS-422, RS-485,802.11a/b/g, Wi-Fi, Ethernet, IrDA, FDDI (optical fiber distributed type interface), token-ring network or the multiplex technique that divides based on frequency division, time-division or sign indicating number.Some realize being combined with alternatively such as the characteristics of the data integrality being carried out error-detecting and correction (ECC) or such as encrypt (for example, WEP) with the security measures of cryptoguard.
Realizations more of the present invention have been described.Yet, be appreciated that under the situation that does not break away from the spirit and scope of the present invention, can carry out various modifications.For example, if carry out the step of disclosed technology,,, then may realize favourable result if perhaps replace or additional described parts by other parts if make up the parts of disclosed system by different way with different orders.Can carry out described function and processing (comprising algorithm) in hardware, software or both combinations, some realization can be carried out being different from disclosed module or the hardware.Therefore, other is realized also within the scope of the appended claims.
Claims (20)
1, a kind of system that uses interlace memory to come deal with data, described system comprises:
Power supply;
In operation, be coupled to a plurality of storage unit of power supply;
Memory Controller is used for optionally controlling the staggered ratio that is used to visit described a plurality of storage unit; And
Processor is used to discern the staggered ratio for Memory Controller, comprising:
Reception is for the device of the request of storage unit access; And
Control the peak point current drawn from power supply by storer device with processes said request by the staggered ratio of selecting to be used to carry out the request of access that is received,
Wherein, staggered ratio is bigger, and then the peak point current of Xi Quing is bigger, and staggered ratio is less, and then the peak point current of Xi Quing is less.
2, the system as claimed in claim 1, wherein, described a plurality of storage unit comprise flash memory.
3, the system as claimed in claim 1, wherein, described power supply comprises the portable energy-storing source.
4, the system as claimed in claim 1, wherein, the described peak point current drawn from power supply by storer controlled by the staggered ratio of selecting to be used to carry out the request of access that is received comprises with the device of processes said request:
Be used to select parts less than the staggered ratio of the available staggered ratio of maximum.
5, a kind of selection is used to visit the method for the interleaving policies of flash memory, and described flash memory is configured to the memory interlace data, and described method comprises:
Reception is for the request of reading from staggered flash memory;
Identification is used for from what flash memory read reading staggered ratio based on first group of criterion;
Reception is for the request that writes to flash memory; And
Identification is used for writing staggered ratio to what flash memory write based on second group of criterion, and wherein, reading staggered ratio and writing the ratio that interlocks of being discerned is different, and
Wherein, staggered ratio is bigger, and then the peak point current of Xi Quing is bigger, and staggered ratio is less, and then the peak point current of Xi Quing is less;
Wherein, first group of criterion comprises the one or more members in following group, and described group comprises: outer power voltage, can be used for to the flash memory power supply electric current, temperature, use be external power source or battery and cell voltage;
Wherein, second group of criterion comprises the one or more members in following group, and described group comprises: outer power voltage, can be used for to the flash memory power supply electric current, temperature, operator scheme, data transfer rate, use be external power source or battery and cell voltage;
Wherein, when outer power voltage or can be used for when the electric current of flash memory power supply surpasses second threshold value, second group of criterion will write staggered ratio and be defined as greater than minimum is available and write staggered ratio; And
Wherein, first group of criterion be supply voltage or can be used for when the electric current of flash memory power supply surpasses first threshold externally, to read staggered ratio is defined as greater than minimum is available and reads staggered ratio, perhaps first group of criterion be not when using the power of drawing from the portable energy-storing source to operate flash memory, to read staggered ratio and be defined as the maximum available staggered ratio that reads, wherein, second threshold value is different from first threshold.
6, method as claimed in claim 5, wherein, second group of criterion also will write staggered ratio and be defined as fixing.
7, method as claimed in claim 5, wherein, second group of criterion comprises the data transfer rate relevant with the data that will write flash memory.
8, method as claimed in claim 7 wherein, writes staggered ratio and comprises the ratio that is enough to by described data transfer rate data be write flash memory.
9, method as claimed in claim 8, wherein, for the data stream that comprises video and audio-frequency information, second group of criterion also it is write staggered ratio be defined as be higher than be used to comprise audio-frequency information and do not have video information data stream write staggered ratio.
10, method as claimed in claim 8, wherein, for the data stream that comprises video information, second group of criterion also writes it staggered ratio and is defined as the staggered ratio that writes that is higher than the data stream that is used to comprise information for still picture.
11, method as claimed in claim 5, wherein, at least one in first group of criterion and the second group of criterion when detecting temperature and surpass threshold value also respectively definition reduce read and write staggered ratio.
12, method as claimed in claim 5, wherein, at least one in first group of criterion and the second group of criterion in response to the signal that is used for minimizing power dissipation also respectively definition reduce read and write staggered ratio.
13, method as claimed in claim 5 wherein, under at least one operating conditions, reads staggered ratio and writes the ratio that interlocks and comprise different ratios.
14, method as claimed in claim 5, wherein, the step that staggered ratio is read in identification comprises that control is used to handle the maximum current level that the request of reading is drawn.
15, method as claimed in claim 5, wherein, the step that identification writes staggered ratio comprises that control is used to handle the maximum current level that the request of writing is drawn.
16, a kind of selection is used for the method for the interleaving policies of reference-to storage, and described method comprises:
Reception is for the request and the relational storage interrogation signal of reference-to storage;
Receive first signal relevant with first group of criterion and with second group of secondary signal that criterion is relevant, described first group of criterion is included at least one different under at least one operating conditions criterions with second group of criterion;
By carry out calculating selecting to read interleaving policies based on first signal or to select to write interleaving policies based on secondary signal, identification is used to carry out the interleaving policies of described request for reference-to storage; And
Use the interleaving policies of identification to send output signal to carry out the memory access of being asked;
Wherein, first group of criterion comprises the one or more members in following group, and described group comprises: outer power voltage, can be used for to the flash memory power supply electric current, temperature, use be external power source or battery and cell voltage;
Wherein, second group of criterion comprises the one or more members in following group, and described group comprises: outer power voltage, can be used for to the flash memory power supply electric current, temperature, operator scheme, data transfer rate, use be external power source or battery and cell voltage;
Wherein, when outer power voltage or can be used for when the electric current of flash memory power supply surpasses second threshold value, secondary signal will write interleaving policies and be defined as greater than the available interleaving policies that writes of minimum; And
Wherein, first signal is supply voltage or can be used for when the electric current of flash memory power supply surpasses first threshold externally, to read interleaving policies is defined as greater than the available interleaving policies that reads of minimum, perhaps first signal is not when using the power of drawing from the portable energy-storing source to operate flash memory, to read interleaving policies and be defined as the maximum available interleaving policies that reads, wherein, second threshold value is different from first threshold.
17, method as claimed in claim 16, described operation also comprises: use the interleaving policies of identification to visit a plurality of flash memory blocks.
18, method as claimed in claim 16, described operation also comprises: upgrade and to read interleaving policies and to write in the interleaving policies at least one.
19, method as claimed in claim 18, at least one the operation of upgrading in the described interleaving policies comprises: the change of at least one parameter that identification is selected from following group, described group comprises: temperature, use be external power source or battery, cell voltage and operator scheme.
20, method as claimed in claim 16 also comprises: when detecting temperature above predetermined threshold, reduce at least one that reads and write in the interleaving policies.
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Families Citing this family (133)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7552280B1 (en) * | 2006-06-28 | 2009-06-23 | Emc Corporation | Asymmetrically interleaving access to redundant storage devices |
| WO2008070814A2 (en) | 2006-12-06 | 2008-06-12 | Fusion Multisystems, Inc. (Dba Fusion-Io) | Apparatus, system, and method for a scalable, composite, reconfigurable backplane |
| US20080189558A1 (en) * | 2007-02-01 | 2008-08-07 | Sun Microsystems, Inc. | System and Method for Secure Data Storage |
| US8650352B2 (en) | 2007-09-20 | 2014-02-11 | Densbits Technologies Ltd. | Systems and methods for determining logical values of coupled flash memory cells |
| WO2009095902A2 (en) | 2008-01-31 | 2009-08-06 | Densbits Technologies Ltd. | Systems and methods for handling immediate data errors in flash memory |
| WO2009053962A2 (en) * | 2007-10-22 | 2009-04-30 | Densbits Technologies Ltd. | Systems and methods for averaging error rates in non-volatile devices and storage systems |
| US8694715B2 (en) | 2007-10-22 | 2014-04-08 | Densbits Technologies Ltd. | Methods for adaptively programming flash memory devices and flash memory systems incorporating same |
| WO2009053961A2 (en) * | 2007-10-25 | 2009-04-30 | Densbits Technologies Ltd. | Systems and methods for multiple coding rates in flash devices |
| US8335977B2 (en) * | 2007-12-05 | 2012-12-18 | Densbits Technologies Ltd. | Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells |
| WO2009072105A2 (en) | 2007-12-05 | 2009-06-11 | Densbits Technologies Ltd. | A low power chien-search based bch/rs decoding system for flash memory, mobile communications devices and other applications |
| US8453022B2 (en) | 2007-12-05 | 2013-05-28 | Densbits Technologies Ltd. | Apparatus and methods for generating row-specific reading thresholds in flash memory |
| US7836226B2 (en) | 2007-12-06 | 2010-11-16 | Fusion-Io, Inc. | Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment |
| US7979667B2 (en) * | 2007-12-10 | 2011-07-12 | Spansion Llc | Memory array search engine |
| WO2009074978A2 (en) | 2007-12-12 | 2009-06-18 | Densbits Technologies Ltd. | Systems and methods for error correction and decoding on multi-level physical media |
| US8276051B2 (en) | 2007-12-12 | 2012-09-25 | Densbits Technologies Ltd. | Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications |
| US8327246B2 (en) * | 2007-12-18 | 2012-12-04 | Densbits Technologies Ltd. | Apparatus for coding at a plurality of rates in multi-level flash memory systems, and methods useful in conjunction therewith |
| US9152496B2 (en) * | 2007-12-21 | 2015-10-06 | Cypress Semiconductor Corporation | High performance flash channel interface |
| US9495116B2 (en) * | 2007-12-26 | 2016-11-15 | Sandisk Il Ltd. | Storage device coordinator and a host device that includes the same |
| JP2009211192A (en) * | 2008-02-29 | 2009-09-17 | Toshiba Corp | Memory system |
| US8099539B2 (en) * | 2008-03-10 | 2012-01-17 | Lsi Corporation | Method and system of a shared bus architecture |
| WO2009118720A2 (en) | 2008-03-25 | 2009-10-01 | Densbits Technologies Ltd. | Apparatus and methods for hardware-efficient unbiased rounding |
| US7961544B2 (en) * | 2008-08-05 | 2011-06-14 | Sandisk Il Ltd. | Storage system and method for managing a plurality of storage devices |
| US8332725B2 (en) | 2008-08-20 | 2012-12-11 | Densbits Technologies Ltd. | Reprogramming non volatile memory portions |
| JP5489434B2 (en) * | 2008-08-25 | 2014-05-14 | 株式会社日立製作所 | Storage device with flash memory |
| US8370603B2 (en) | 2008-12-23 | 2013-02-05 | Apple Inc. | Architecture for address mapping of managed non-volatile memory |
| KR101581679B1 (en) * | 2009-03-18 | 2015-12-31 | 삼성전자주식회사 | Storage device and method for managing buffer memory of storage device |
| US8285917B2 (en) * | 2009-03-26 | 2012-10-09 | Scaleo Chip | Apparatus for enhancing flash memory access |
| US8819385B2 (en) | 2009-04-06 | 2014-08-26 | Densbits Technologies Ltd. | Device and method for managing a flash memory |
| US8458574B2 (en) | 2009-04-06 | 2013-06-04 | Densbits Technologies Ltd. | Compact chien-search based decoding apparatus and method |
| US8438453B2 (en) | 2009-05-06 | 2013-05-07 | Apple Inc. | Low latency read operation for managed non-volatile memory |
| US8321647B2 (en) * | 2009-05-06 | 2012-11-27 | Apple Inc. | Multipage preparation commands for non-volatile memory systems |
| JP5532671B2 (en) * | 2009-05-08 | 2014-06-25 | ソニー株式会社 | Data storage system and data storage method, execution device and control method, and control device and control method |
| US8566510B2 (en) | 2009-05-12 | 2013-10-22 | Densbits Technologies Ltd. | Systems and method for flash memory management |
| US8495332B2 (en) * | 2009-07-24 | 2013-07-23 | Apple Inc. | Controller for optimizing throughput of read operations |
| US8305812B2 (en) | 2009-08-26 | 2012-11-06 | Densbits Technologies Ltd. | Flash memory module and method for programming a page of flash memory cells |
| US8995197B1 (en) | 2009-08-26 | 2015-03-31 | Densbits Technologies Ltd. | System and methods for dynamic erase and program control for flash memory device memories |
| US8868821B2 (en) | 2009-08-26 | 2014-10-21 | Densbits Technologies Ltd. | Systems and methods for pre-equalization and code design for a flash memory |
| US9330767B1 (en) | 2009-08-26 | 2016-05-03 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Flash memory module and method for programming a page of flash memory cells |
| US8838877B2 (en) * | 2009-09-16 | 2014-09-16 | Apple Inc. | File system derived metadata for management of non-volatile memory |
| US8327092B2 (en) * | 2009-09-21 | 2012-12-04 | Freescale Semiconductor, Inc. | Memory device configurable as interleaved or non-interleaved memory |
| US8730729B2 (en) | 2009-10-15 | 2014-05-20 | Densbits Technologies Ltd. | Systems and methods for averaging error rates in non-volatile devices and storage systems |
| US8724387B2 (en) | 2009-10-22 | 2014-05-13 | Densbits Technologies Ltd. | Method, system, and computer readable medium for reading and programming flash memory cells using multiple bias voltages |
| US8626988B2 (en) | 2009-11-19 | 2014-01-07 | Densbits Technologies Ltd. | System and method for uncoded bit error rate equalization via interleaving |
| KR101623730B1 (en) * | 2009-11-23 | 2016-05-25 | 삼성전자주식회사 | Interleaver apparatus |
| US9037777B2 (en) | 2009-12-22 | 2015-05-19 | Densbits Technologies Ltd. | Device, system, and method for reducing program/read disturb in flash arrays |
| US8607124B2 (en) | 2009-12-24 | 2013-12-10 | Densbits Technologies Ltd. | System and method for setting a flash memory cell read threshold |
| US8904085B2 (en) * | 2010-01-14 | 2014-12-02 | Lenovo (Singapore) Pte. Ltd. | Solid-state memory management |
| US8700970B2 (en) | 2010-02-28 | 2014-04-15 | Densbits Technologies Ltd. | System and method for multi-dimensional decoding |
| US8516274B2 (en) | 2010-04-06 | 2013-08-20 | Densbits Technologies Ltd. | Method, system and medium for analog encryption in a flash memory |
| US8527840B2 (en) | 2010-04-06 | 2013-09-03 | Densbits Technologies Ltd. | System and method for restoring damaged data programmed on a flash device |
| US8745317B2 (en) | 2010-04-07 | 2014-06-03 | Densbits Technologies Ltd. | System and method for storing information in a multi-level cell memory |
| US9021177B2 (en) | 2010-04-29 | 2015-04-28 | Densbits Technologies Ltd. | System and method for allocating and using spare blocks in a flash memory |
| JP2011233114A (en) * | 2010-04-30 | 2011-11-17 | Toshiba Corp | Memory system |
| US8539311B2 (en) | 2010-07-01 | 2013-09-17 | Densbits Technologies Ltd. | System and method for data recovery in multi-level cell memories |
| US8468431B2 (en) | 2010-07-01 | 2013-06-18 | Densbits Technologies Ltd. | System and method for multi-dimensional encoding and decoding |
| US8467249B2 (en) | 2010-07-06 | 2013-06-18 | Densbits Technologies Ltd. | Systems and methods for storing, retrieving, and adjusting read thresholds in flash memory storage system |
| US8826051B2 (en) | 2010-07-26 | 2014-09-02 | Apple Inc. | Dynamic allocation of power budget to a system having non-volatile memory and a processor |
| US8555095B2 (en) | 2010-07-26 | 2013-10-08 | Apple Inc. | Methods and systems for dynamically controlling operations in a non-volatile memory to limit power consumption |
| US8522055B2 (en) | 2010-07-26 | 2013-08-27 | Apple Inc. | Peak power validation methods and systems for non-volatile memory |
| US8964464B2 (en) | 2010-08-24 | 2015-02-24 | Densbits Technologies Ltd. | System and method for accelerated sampling |
| US8508995B2 (en) | 2010-09-15 | 2013-08-13 | Densbits Technologies Ltd. | System and method for adjusting read voltage thresholds in memories |
| US9063878B2 (en) | 2010-11-03 | 2015-06-23 | Densbits Technologies Ltd. | Method, system and computer readable medium for copy back |
| US8850100B2 (en) | 2010-12-07 | 2014-09-30 | Densbits Technologies Ltd. | Interleaving codeword portions between multiple planes and/or dies of a flash memory device |
| US20120179883A1 (en) * | 2011-01-12 | 2012-07-12 | Broadcom Corpotation | System and method for dynamically adjusting memory performance |
| US10079068B2 (en) | 2011-02-23 | 2018-09-18 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Devices and method for wear estimation based memory management |
| US20120221767A1 (en) | 2011-02-28 | 2012-08-30 | Apple Inc. | Efficient buffering for a system having non-volatile memory |
| US8693258B2 (en) | 2011-03-17 | 2014-04-08 | Densbits Technologies Ltd. | Obtaining soft information using a hard interface |
| US8990665B1 (en) | 2011-04-06 | 2015-03-24 | Densbits Technologies Ltd. | System, method and computer program product for joint search of a read threshold and soft decoding |
| US8645723B2 (en) | 2011-05-11 | 2014-02-04 | Apple Inc. | Asynchronous management of access requests to control power consumption |
| US8996790B1 (en) | 2011-05-12 | 2015-03-31 | Densbits Technologies Ltd. | System and method for flash memory management |
| US9195592B1 (en) | 2011-05-12 | 2015-11-24 | Densbits Technologies Ltd. | Advanced management of a non-volatile memory |
| US9372792B1 (en) | 2011-05-12 | 2016-06-21 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Advanced management of a non-volatile memory |
| US9501392B1 (en) | 2011-05-12 | 2016-11-22 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Management of a non-volatile memory module |
| US9110785B1 (en) | 2011-05-12 | 2015-08-18 | Densbits Technologies Ltd. | Ordered merge of data sectors that belong to memory space portions |
| US9396106B2 (en) | 2011-05-12 | 2016-07-19 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Advanced management of a non-volatile memory |
| US8667211B2 (en) | 2011-06-01 | 2014-03-04 | Densbits Technologies Ltd. | System and method for managing a non-volatile memory |
| US8943336B2 (en) | 2011-07-01 | 2015-01-27 | Intel Corporation | Method and apparatus for configurable thermal management |
| US8588003B1 (en) | 2011-08-01 | 2013-11-19 | Densbits Technologies Ltd. | System, method and computer program product for programming and for recovering from a power failure |
| US8656251B2 (en) * | 2011-09-02 | 2014-02-18 | Apple Inc. | Simultaneous data transfer and error control to reduce latency and improve throughput to a host |
| US8553468B2 (en) | 2011-09-21 | 2013-10-08 | Densbits Technologies Ltd. | System and method for managing erase operations in a non-volatile memory |
| CN103064799B (en) * | 2011-10-21 | 2016-03-09 | 神讯电脑(昆山)有限公司 | Electronic system and data security method thereof and device |
| US20130117532A1 (en) * | 2011-11-07 | 2013-05-09 | Alexander Rabinovitch | Interleaving address modification |
| US9251086B2 (en) | 2012-01-24 | 2016-02-02 | SanDisk Technologies, Inc. | Apparatus, system, and method for managing a cache |
| US8947941B2 (en) | 2012-02-09 | 2015-02-03 | Densbits Technologies Ltd. | State responsive operations relating to flash memory cells |
| US8996788B2 (en) | 2012-02-09 | 2015-03-31 | Densbits Technologies Ltd. | Configurable flash interface |
| US8996793B1 (en) | 2012-04-24 | 2015-03-31 | Densbits Technologies Ltd. | System, method and computer readable medium for generating soft information |
| US8838937B1 (en) | 2012-05-23 | 2014-09-16 | Densbits Technologies Ltd. | Methods, systems and computer readable medium for writing and reading data |
| US8879325B1 (en) | 2012-05-30 | 2014-11-04 | Densbits Technologies Ltd. | System, method and computer program product for processing read threshold information and for reading a flash memory module |
| US9921954B1 (en) | 2012-08-27 | 2018-03-20 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method and system for split flash memory management between host and storage controller |
| TWI483111B (en) * | 2012-09-20 | 2015-05-01 | Phison Electronics Corp | Data processing method, memory controller and memory storage device |
| CN103699491B (en) * | 2012-09-28 | 2017-05-10 | 群联电子股份有限公司 | data storage method, memory controller and memory storage device |
| US9368225B1 (en) | 2012-11-21 | 2016-06-14 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Determining read thresholds based upon read error direction statistics |
| US9092327B2 (en) | 2012-12-10 | 2015-07-28 | Qualcomm Incorporated | System and method for allocating memory to dissimilar memory devices using quality of service |
| US9110795B2 (en) * | 2012-12-10 | 2015-08-18 | Qualcomm Incorporated | System and method for dynamically allocating memory in a memory subsystem having asymmetric memory components |
| US9069659B1 (en) | 2013-01-03 | 2015-06-30 | Densbits Technologies Ltd. | Read threshold determination using reference read threshold |
| US9136876B1 (en) | 2013-06-13 | 2015-09-15 | Densbits Technologies Ltd. | Size limited multi-dimensional decoding |
| US9612648B2 (en) * | 2013-08-08 | 2017-04-04 | Qualcomm Incorporated | System and method for memory channel interleaving with selective power or performance optimization |
| US9413491B1 (en) | 2013-10-08 | 2016-08-09 | Avago Technologies General Ip (Singapore) Pte. Ltd. | System and method for multiple dimension decoding and encoding a message |
| US9397706B1 (en) | 2013-10-09 | 2016-07-19 | Avago Technologies General Ip (Singapore) Pte. Ltd. | System and method for irregular multiple dimension decoding and encoding |
| US9348694B1 (en) | 2013-10-09 | 2016-05-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Detecting and managing bad columns |
| US9786388B1 (en) | 2013-10-09 | 2017-10-10 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Detecting and managing bad columns |
| EP2884369B1 (en) | 2013-12-16 | 2018-02-07 | Stichting IMEC Nederland | Memory control system for a non-volatile memory and control method |
| US9536612B1 (en) | 2014-01-23 | 2017-01-03 | Avago Technologies General Ip (Singapore) Pte. Ltd | Digital signaling processing for three dimensional flash memory arrays |
| US10120792B1 (en) | 2014-01-29 | 2018-11-06 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Programming an embedded flash storage device |
| US9977628B2 (en) * | 2014-04-16 | 2018-05-22 | Sandisk Technologies Llc | Storage module and method for configuring the storage module with memory operation parameters |
| KR102254099B1 (en) | 2014-05-19 | 2021-05-20 | 삼성전자주식회사 | Method for processing memory swapping operation, and host device, storage device and data processing system adopting the same |
| US9542262B1 (en) | 2014-05-29 | 2017-01-10 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Error correction |
| US9093160B1 (en) * | 2014-05-30 | 2015-07-28 | Sandisk Technologies Inc. | Methods and systems for staggered memory operations |
| US9892033B1 (en) | 2014-06-24 | 2018-02-13 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Management of memory units |
| US9972393B1 (en) | 2014-07-03 | 2018-05-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Accelerating programming of a flash memory module |
| US9584159B1 (en) | 2014-07-03 | 2017-02-28 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Interleaved encoding |
| US9449702B1 (en) | 2014-07-08 | 2016-09-20 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Power management |
| US9524211B1 (en) | 2014-11-18 | 2016-12-20 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Codeword management |
| US9632562B2 (en) * | 2014-11-20 | 2017-04-25 | Qualcomm Incorporated | Systems and methods for reducing volatile memory standby power in a portable computing device |
| US10305515B1 (en) | 2015-02-02 | 2019-05-28 | Avago Technologies International Sales Pte. Limited | System and method for encoding using multiple linear feedback shift registers |
| US9996276B2 (en) * | 2015-03-04 | 2018-06-12 | Toshiba Memory Corporation | Memory system, memory controller and control device |
| KR102222444B1 (en) | 2015-03-05 | 2021-03-04 | 삼성전자주식회사 | Storage device using power status information and operating method of the same |
| US10628255B1 (en) | 2015-06-11 | 2020-04-21 | Avago Technologies International Sales Pte. Limited | Multi-dimensional decoding |
| US9851921B1 (en) | 2015-07-05 | 2017-12-26 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Flash memory chip processing |
| US10241701B2 (en) | 2015-09-16 | 2019-03-26 | Samsung Electronics Co., Ltd. | Solid state memory system with power management mechanism and method of operation thereof |
| US11216323B2 (en) | 2015-09-16 | 2022-01-04 | Samsung Electronics Co., Ltd. | Solid state memory system with low power error correction mechanism and method of operation thereof |
| KR20170078307A (en) * | 2015-12-29 | 2017-07-07 | 에스케이하이닉스 주식회사 | Memory system and operation method for the same |
| US9954558B1 (en) | 2016-03-03 | 2018-04-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Fast decoding of data stored in a flash memory |
| US10459855B2 (en) | 2016-07-01 | 2019-10-29 | Intel Corporation | Load reduced nonvolatile memory interface |
| US10007311B2 (en) * | 2016-08-15 | 2018-06-26 | Sandisk Technologies Llc | Adaptive temperature and memory parameter throttling |
| CN110489051A (en) * | 2018-05-14 | 2019-11-22 | 慧荣科技股份有限公司 | The programmed method of data memory device and system information |
| TWI687811B (en) * | 2018-05-14 | 2020-03-11 | 慧榮科技股份有限公司 | Data storage apparatus and system information programming mehtod |
| TWI667606B (en) * | 2018-07-06 | 2019-08-01 | 深圳大心電子科技有限公司 | Memory management method and storage controller |
| KR102645786B1 (en) * | 2019-07-08 | 2024-03-12 | 에스케이하이닉스 주식회사 | Controller, memory system and operating method thereof |
| WO2021035436A1 (en) * | 2019-08-23 | 2021-03-04 | Micron Technology, Inc. | Temperature-based memory management |
| US11183248B1 (en) | 2020-07-29 | 2021-11-23 | Micron Technology, Inc. | Timing parameter adjustment mechanisms |
| WO2022041052A1 (en) * | 2020-08-27 | 2022-03-03 | Micron Technology, Inc. | External power functionality techniques for memory devices |
| WO2023009122A1 (en) * | 2021-07-29 | 2023-02-02 | Hewlett-Packard Development Company, L.P. | Minimize delay times for status checks to flash memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6405286B2 (en) * | 1998-07-31 | 2002-06-11 | Hewlett-Packard Company | Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes |
| CN1517880A (en) * | 2003-01-10 | 2004-08-04 | 英特尔公司 | Memory interleaving |
| CN1177282C (en) * | 2002-09-24 | 2004-11-24 | 威盛电子股份有限公司 | Method and system for executing hot key function |
Family Cites Families (65)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4503494A (en) * | 1980-06-26 | 1985-03-05 | Texas Instruments Incorporated | Non-volatile memory system |
| DE69034227T2 (en) | 1989-04-13 | 2007-05-03 | Sandisk Corp., Sunnyvale | EEprom system with block deletion |
| US5978569A (en) * | 1989-05-02 | 1999-11-02 | Norand Corporation | System having plurality of docking unit receptacles for transmitting data between plurality of portable data entry terminals in local area network with a central controller |
| US5663901A (en) | 1991-04-11 | 1997-09-02 | Sandisk Corporation | Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems |
| JPH05233551A (en) * | 1992-02-21 | 1993-09-10 | Toshiba Corp | Portable computer |
| TW231343B (en) | 1992-03-17 | 1994-10-01 | Hitachi Seisakusyo Kk | |
| US5341489A (en) | 1992-04-14 | 1994-08-23 | Eastman Kodak Company | Memory card with programmable interleaving |
| US5404543A (en) * | 1992-05-29 | 1995-04-04 | International Business Machines Corporation | Method and system for reducing an amount of power utilized by selecting a lowest power mode from a plurality of power modes |
| US5473753A (en) | 1992-10-30 | 1995-12-05 | Intel Corporation | Method of managing defects in flash disk memories |
| EP0629952B1 (en) | 1993-06-16 | 1999-09-01 | Bull HN Information Systems Italia S.p.A. | Variable interleaving level memory and related configuration unit |
| US5592641A (en) | 1993-06-30 | 1997-01-07 | Intel Corporation | Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status |
| US7137011B1 (en) | 1993-09-01 | 2006-11-14 | Sandisk Corporation | Removable mother/daughter peripheral card |
| US5508971A (en) | 1994-10-17 | 1996-04-16 | Sandisk Corporation | Programmable power generation circuit for flash EEPROM memory systems |
| FR2734061B1 (en) * | 1995-05-12 | 1997-06-20 | Thomson Csf | METHOD FOR DETERMINING THE AVAILABLE CHARGE OF AN ACCUMULATOR BATTERY AT THE END OF DISCHARGE |
| US5627784A (en) | 1995-07-28 | 1997-05-06 | Micron Quantum Devices, Inc. | Memory system having non-volatile data storage structure for memory control parameters and method |
| DE69521616T2 (en) * | 1995-11-28 | 2001-10-18 | Bull Sa | Memory access limiter for dynamic RAM |
| JPH1069420A (en) * | 1996-08-29 | 1998-03-10 | Sony Corp | Information recording and reproducing device and information recording and reproducing method |
| US5944829A (en) * | 1996-09-30 | 1999-08-31 | Intel Corporation | Adjusting software characteristics by user interface based upon battery level and the amount of time the user wants the battery to last |
| FI104528B (en) | 1996-10-03 | 2000-02-15 | Nokia Networks Oy | Procedure for locating a mobile station, and cellular radio network |
| KR100205006B1 (en) | 1996-10-08 | 1999-06-15 | 윤종용 | Semiconductor memory device having an automatic falut block mapping function |
| US6052306A (en) | 1996-11-04 | 2000-04-18 | Siemens Aktiengesellschaft | Method and device for automatic determination of the required high voltage for programming/erasing an EEPROM |
| JPH10187302A (en) | 1996-12-26 | 1998-07-14 | Toshiba Corp | Data storage system and method for saving power applied to the same system |
| JP3821536B2 (en) * | 1997-05-16 | 2006-09-13 | 沖電気工業株式会社 | Nonvolatile semiconductor disk device |
| US5994829A (en) * | 1997-05-23 | 1999-11-30 | Thomson Consumer Electronics, Inc. | Color cathode-ray tube having phosphor elements deposited on an imperforate matrix border |
| JP3508503B2 (en) * | 1997-10-02 | 2004-03-22 | 日本精工株式会社 | Linear guide device |
| US6148435A (en) | 1997-12-24 | 2000-11-14 | Cypress Semiconductor Corporation | Optimized programming/erase parameters for programmable devices |
| US6021076A (en) | 1998-07-16 | 2000-02-01 | Rambus Inc | Apparatus and method for thermal regulation in memory subsystems |
| JP2001067863A (en) * | 1999-08-31 | 2001-03-16 | Mitsubishi Electric Corp | Semiconductor storage |
| US6516381B1 (en) | 1999-09-28 | 2003-02-04 | Intel Corporation | Supplying voltage to a memory module |
| US6269025B1 (en) | 2000-02-09 | 2001-07-31 | Advanced Micro Devices, Inc. | Memory system having a program and erase voltage modifier |
| US6426893B1 (en) | 2000-02-17 | 2002-07-30 | Sandisk Corporation | Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks |
| US6304487B1 (en) | 2000-02-28 | 2001-10-16 | Advanced Micro Devices, Inc. | Register driven means to control programming voltages |
| JP2001297316A (en) * | 2000-04-14 | 2001-10-26 | Mitsubishi Electric Corp | Memory card and control method therefor |
| JP2001352373A (en) * | 2000-06-08 | 2001-12-21 | Nintendo Co Ltd | Display processing system using mobile terminal, mobile terminal used for it, and conversion adaptor used for it |
| US6748562B1 (en) | 2000-10-31 | 2004-06-08 | Agilent Technologies, Inc. | Memory tester omits programming of addresses in detected bad columns |
| US6763424B2 (en) | 2001-01-19 | 2004-07-13 | Sandisk Corporation | Partial block data programming and reading operations in a non-volatile memory |
| TW493119B (en) | 2001-03-28 | 2002-07-01 | Via Tech Inc | Method for automatically identifying the type of memory and motherboard using the same |
| JP4694040B2 (en) * | 2001-05-29 | 2011-06-01 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
| JP4841070B2 (en) | 2001-07-24 | 2011-12-21 | パナソニック株式会社 | Storage device |
| JP3822081B2 (en) | 2001-09-28 | 2006-09-13 | 東京エレクトロンデバイス株式会社 | Data writing apparatus, data writing control method, and program |
| US6871257B2 (en) | 2002-02-22 | 2005-03-22 | Sandisk Corporation | Pipelined parallel programming operation in a non-volatile memory system |
| KR100463199B1 (en) | 2002-03-04 | 2004-12-23 | 삼성전자주식회사 | Semiconductor memory device with flexible redundancy scheme |
| FI115562B (en) * | 2002-03-27 | 2005-05-31 | Nokia Corp | Method and system for determining power consumption in connection with electronic device and electronic device |
| JP2003308138A (en) | 2002-04-18 | 2003-10-31 | Toshiba Corp | Electronic equipment and method for controlling driving of the equipment |
| US6721820B2 (en) | 2002-05-15 | 2004-04-13 | M-Systems Flash Disk Pioneers Ltd. | Method for improving performance of a flash-based storage system using specialized flash controllers |
| US6879526B2 (en) * | 2002-10-31 | 2005-04-12 | Ring Technology Enterprises Llc | Methods and apparatus for improved memory access |
| US7127622B2 (en) | 2003-03-04 | 2006-10-24 | Micron Technology, Inc. | Memory subsystem voltage control and method |
| JP4554598B2 (en) | 2003-03-27 | 2010-09-29 | サンディスク アイエル リミテッド | A data storage device that is fully accessible by all users |
| US7240219B2 (en) | 2003-05-25 | 2007-07-03 | Sandisk Il Ltd. | Method and system for maintaining backup of portable storage devices |
| JP3902159B2 (en) * | 2003-06-13 | 2007-04-04 | 株式会社日立製作所 | Nonvolatile memory device |
| US7237074B2 (en) | 2003-06-13 | 2007-06-26 | Sandisk Corporation | Tracking cells for a memory system |
| JP4392590B2 (en) | 2003-10-31 | 2010-01-06 | ソニー株式会社 | Temperature control device and method, portable terminal device, and temperature control program |
| JP4264087B2 (en) | 2003-11-28 | 2009-05-13 | パナソニック株式会社 | Recording device |
| US7081897B2 (en) | 2003-12-24 | 2006-07-25 | Intel Corporation | Unified memory organization for power savings |
| US7631138B2 (en) * | 2003-12-30 | 2009-12-08 | Sandisk Corporation | Adaptive mode switching of flash memory address mapping based on host usage characteristics |
| US7577859B2 (en) | 2004-02-20 | 2009-08-18 | International Business Machines Corporation | System and method of controlling power consumption in an electronic system by applying a uniquely determined minimum operating voltage to an integrated circuit rather than a predetermined nominal voltage selected for a family of integrated circuits |
| JP2005234935A (en) * | 2004-02-20 | 2005-09-02 | Renesas Technology Corp | Information storage device |
| US7656635B2 (en) * | 2004-08-06 | 2010-02-02 | Intel Corporation | Overheat detection in thermally controlled devices |
| US7502256B2 (en) * | 2004-11-30 | 2009-03-10 | Siliconsystems, Inc. | Systems and methods for reducing unauthorized data recovery from solid-state storage devices |
| US7180813B2 (en) | 2004-12-15 | 2007-02-20 | Stmicroelectronics, Inc. | Programmable system device having a shared power supply voltage generator for FLASH and PLD modules |
| US7236894B2 (en) | 2004-12-23 | 2007-06-26 | Rambus Inc. | Circuits, systems and methods for dynamic reference voltage calibration |
| US7864615B2 (en) | 2005-02-25 | 2011-01-04 | Kingston Technology Corporation | Flash memory controller utilizing multiple voltages and a method of use |
| TWI319160B (en) | 2005-07-11 | 2010-01-01 | Via Tech Inc | Memory card capable of supporting various voltage supply and control chip and method of supporting voltage thereof |
| KR100725979B1 (en) | 2005-07-23 | 2007-06-08 | 삼성전자주식회사 | Apparatus and method for improving write/read endurance of non-volatile memory |
| US7712670B2 (en) * | 2005-09-28 | 2010-05-11 | Sauerwein Jr James T | Data collection device and network having radio signal responsive mode switching |
-
2006
- 2006-01-18 US US11/334,293 patent/US7793059B2/en not_active Expired - Fee Related
-
2007
- 2007-01-12 TW TW096101302A patent/TWI340903B/en not_active IP Right Cessation
- 2007-01-15 EP EP10177482.6A patent/EP2267602B1/en not_active Not-in-force
- 2007-01-15 EP EP07000695.2A patent/EP1818830B1/en not_active Not-in-force
- 2007-01-17 CN CNB2007100022797A patent/CN100555255C/en not_active Expired - Fee Related
- 2007-01-17 CN CN200910169185.8A patent/CN101661434B/en not_active Expired - Fee Related
- 2007-01-18 JP JP2007009575A patent/JP4870582B2/en not_active Expired - Fee Related
-
2010
- 2010-09-03 US US12/875,738 patent/US20100332741A1/en not_active Abandoned
-
2011
- 2011-09-30 JP JP2011218262A patent/JP5551136B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6405286B2 (en) * | 1998-07-31 | 2002-06-11 | Hewlett-Packard Company | Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes |
| CN1177282C (en) * | 2002-09-24 | 2004-11-24 | 威盛电子股份有限公司 | Method and system for executing hot key function |
| CN1517880A (en) * | 2003-01-10 | 2004-08-04 | 英特尔公司 | Memory interleaving |
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| JP2012043451A (en) | 2012-03-01 |
| JP4870582B2 (en) | 2012-02-08 |
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| US7793059B2 (en) | 2010-09-07 |
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| JP2007193810A (en) | 2007-08-02 |
| CN101661434A (en) | 2010-03-03 |
| EP2267602A2 (en) | 2010-12-29 |
| TW200741464A (en) | 2007-11-01 |
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