CN100570847C - The three dimensional integrated circuits implementation method of transfer-free disc - Google Patents
The three dimensional integrated circuits implementation method of transfer-free disc Download PDFInfo
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- CN100570847C CN100570847C CN200710179533.0A CN200710179533A CN100570847C CN 100570847 C CN100570847 C CN 100570847C CN 200710179533 A CN200710179533 A CN 200710179533A CN 100570847 C CN100570847 C CN 100570847C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Abstract
The invention discloses a kind of three dimensional integrated circuits implementation method that belongs to semiconductor and microsensor manufacturing technology field.This method utilizes lithographic technique that attenuate is carried out in substrate disk part, and in local reduction district etching high aspect ratio vias, owing to be local reduction, substrate disk intensity is guaranteed, thereby do not need to shift disk; Adopt bottom-up electro-plating method to fill the high-aspect-ratio blind hole in addition, the attenuate disk is realized the three-dimensional interconnection that penetrates substrate of high-aspect-ratio behind the last bonding, obtains three dimensional integrated circuits.This method obtains highdensity through-hole interconnection easily at local reduction's district's etching through hole; Do not use the transfer disk, simplified manufacture process.This method can be applied to three dimensional integrated circuits field and microsensor integration field, not only can realize the three-dimensional integrated of silicon substrate, can also expand to the three-dimensional integrated of other Semiconductor substrate.
Description
Technical field
The invention belongs to semiconductor and microsensor manufacturing technology field, particularly a kind of three dimensional integrated circuits implementation method of integrated micro transducer and treatment circuit.
Background technology
Constantly dwindling of integrated circuit (IC)-components improves constantly integrated level, can integratedly surpass 1,000,000,000 transistors on present every square centimeter the chip area, and the total length of metal interconnecting wires reaches tens kilometers especially.This makes that not only wiring becomes complicated unusually, the more important thing is that metal interconnected delay, power consumption, noise etc. all constantly increase along with the reduction of characteristic size, and particularly globally interconnected RC postpones, and has had a strong impact on the performance of integrated circuit.In addition, dynamic power consumption is directly proportional with the load capacitance value of circuit, in the dynamic power consumption of mainstream high performance microprocessor, has above half all to be caused by interconnection line at present.The method that solves interconnect delay at present is to increase a series of buffers on globally interconnected line, but the effect of this method is limited, and because the adding of a large amount of buffers, the power consumption of circuit increases considerably, and promptly utilizes power consumption to exchange speed for.The use of copper-connection and low-K dielectric decreases serial resistance and parasitic capacitance, makes technology develop into 90nm by 130nm and overall performance increases, and also can only keep technological development to the 65nm node and introduce ultralow K medium.Therefore, the metal interconnected transistor that replaced becomes the principal element that determines performance of integrated circuits, and the development of integrated circuits limit is not the inefficacy of Moore's Law, and interconnection, cost and complexity are becoming the real bottleneck of the following integrated circuit development of restriction.
Chip system (SOC, System on a Chip) technology is wished the repertoire of the system that realizes on single-chip, as numeral, simulation, radio frequency, and photoelectricity and MEMS etc.Difficulty maximum in the SOC development is the compatibling problem of different process, for example realizes that SOC may need standard CMOS, SiGe RF, BiCMOS, Bipolar, high frequency GaAs, and technology such as MEMS.These manufacturing process are all different with backing material, hardly may be with its integrated being manufactured on the chip.Even the module that backing material is identical also will be considered the manufacturing feasibility of each circuit module in the mill.This can not optimize fully to each circuit module on the one hand, on the other hand in order in one plane to realize a plurality of modules, need to increase mask quantity, limit mutually when arranging process sequence, certainly will increase the cost of circuit manufacturing, the raising of limiting performance.Therefore, the chip of multifunction module still is discrete at present, and the various advantages of SOC are because the restriction of making still rests on the stage of imagination.
Three-dimensional interconnection is on the planar circuit basis, utilize the third dimension to realize the integrated of the interior multilayer device of single chip, promptly a big planar circuit is divided into some functional modules that are associated in logic and is distributed on a plurality of adjacent chip layer, by the three-dimensional perpendicular interconnection that penetrates substrate that multilayer chiop is integrated then.Three-dimensional interconnection can be realized multicore sheet vertically integrated of difference in functionality, different process, reduces globally interconnected length significantly, thereby reduces interconnect delay significantly, improves integrated circuit speed, reduces the power consumption of chip.Three-dimensional interconnection can the integrated multi-layer different process or the integrated circuit of different backing materials, for the SOC of heterogeneous chip provides good solution.Three-dimensional interconnection all is a physical interconnections, can solve problems such as delay that heterogeneous integrated, high-bandwidth communication of multicore sheet and interconnection cause and noise, and these characteristics make it become the most feasible means that solve the bottleneck problem that planar integrated circuit faced.
Realize that three dimensional integrated circuits at first needs to realize penetrating the three-dimensional interconnection line of circuit wafer substrate, this is the core of three-dimensional integrated technology.The technology of present realization three-dimensional interconnection mainly comprises can be based on the implementation of blind hole based on the implementation of through hole.
Fill the hole of single face opening based on the implementation method of blind hole, then obtain to penetrate the interconnection line of semiconductor layer, utilize single face etching and Damascus to electroplate and realize interconnecting by operations such as attenuates.Circuit wafer keeps original thickness, operability is good, can be after interconnection line is populated by closing and attenuate is manufactured with the circuit wafer of vertical interconnects with auxiliary disk is strong, to obtain to penetrate the three-dimensional interconnection of substrate, therefore can obtain very thin substrate layer, generally at tens microns to tens microns.But owing to can only adopt Damascus to electroplate, be easy to make the hole at first to be shut, form the interconnection line inside holes at opening part.
Before filling vertical interconnects, at first obtain to penetrate the through hole of substrate based on the implementation method of through hole, can carry out double-side operation, promptly electroplate and utilize the mode of bottom-up plating to fill copper after shutting via openings at single face.This method filling vias is easy, but in order to guarantee the operability of circuit wafer, the thickness of individual layer circuit wafer often surpasses 200 microns, and the lateral dimension of interconnection line has limited the raising of interconnection line density also more than 10 microns.The method that solves is to use disk (auxiliary disk) technology that shifts, promptly circuit wafer and the interim bonding of transfer disk, attenuate circuit wafer is utilized and is shifted disk supporting circuit wafer, made behind the through hole again with circuit wafer and other circuit wafer bondings, removed at last and shift disk.Its shortcoming is interim bonding complex process, and cost is very high.
Summary of the invention
The objective of the invention is to disclose a kind of implementation method of three dimensional integrated circuits, it is characterized in that, the substrate disk is carried out local reduction, and in local reduction district etching high aspect ratio vias, adopt bottom-up electro-plating method to fill the high-aspect-ratio blind hole, the attenuate disk is realized the three-dimensional interconnection that penetrates substrate of high-aspect-ratio behind the last bonding, obtains three dimensional integrated circuits.The step that realizes this method comprises:
Steps A: utilize the potassium hydroxide lithographic technique to carry out local reduction from the back side to ground floor substrate disk; Utilize the DRIE lithographic technique to penetrate the through hole of ground floor substrate disk in described local reduction zone etching from the front;
Step B: at ground floor substrate disk back side deposition insulating layer, copper diffusion barrier layer and copper seed layer; Through hole opening is overleaf shut in the single face electro-coppering; As Seed Layer, utilize the positive electro-coppering filling vias of bottom-up electro-plating method with the copper of shutting opening, and on the through hole of filling, make the bonding salient point from described disk;
Step C: the described ground floor substrate disk that overturns, the mode that adopts the copper bump bonding is with described ground floor substrate disk and second layer wafer bonding; From thinning back side ground floor disk, realize that the circuit of ground floor substrate disk and second layer disk is connected, constitute three-dimensional integrated.
Described each disk uses silicon, germanium silicon, GaAs or silicon-on-insulator as the backing material of making circuit.
Described steps A realizes that the method for local reduction also comprises: the wet etching technique or the reaction ion deep etching dry etching technologies such as (DRIE) that adopt Tetramethylammonium hydroxide alkaline solutions such as (TAMH).
Also comprise among the described step C: the material of described salient point is one or more materials in copper, tin, gold or the lead, or any alloy material of two or more formations in them.
The bonding method of described step C also comprises: the adhesive bonding (adhesivebonding) that adopts organic substance to realize, or adopt low temperature oxide layer bonding (oxide-oxide bonding).
Also comprise among the described step C: the use organic substance is filled the slit between described ground floor substrate disk and the described second layer disk, and is cured.
Described method also comprises: the three dimensional integrated circuits that described ground floor substrate disk and described second layer disk are constituted repeats described steps A to described step C as new circuit wafer, realizes the three dimensional integrated circuits that the multilayer disk constitutes.
The invention has the beneficial effects as follows: keep the mechanical strength of each disk can satisfy the requirement of manufacturing process by local reduction, therefore can avoid using auxiliary disk, simplify manufacture process greatly and reduce cost; And the local reduction district can realize bigger depth-to-width ratio through hole, and the interconnection area occupied is little, density is high.Utilize bottom-up copper electro-plating method, can be in the through hole of high-aspect-ratio seamless filled copper forms three-dimensional interconnection, avoids the influence to interlinking reliability and electrical property such as slit.
Description of drawings
Fig. 1 is the implementation method flow chart of the three dimensional integrated circuits that provides of the embodiment of the invention.
Fig. 2 is the substrate disk schematic diagram that has integrated circuit that the embodiment of the invention provides.
Fig. 3 be the embodiment of the invention provide the integrated circuit wafer among Fig. 2 is carried out schematic diagram behind the local KOH etching attenuate.
Fig. 4 is the schematic diagram after the integrated circuit wafer local reduction district among Fig. 3 that the embodiment of the invention provides utilizes DRIE etching high aspect ratio vias.
Fig. 5 be the embodiment of the invention provide to the schematic diagram after integrated circuit wafer back side deposit dielectric insulation layer, copper diffusion barrier layer and the cement copper Seed Layer among Fig. 4.
Fig. 6 be the embodiment of the invention provide schematic diagram behind the opening shut through hole 6 is electroplated at the integrated circuit net sheet back side among Fig. 5.
Fig. 7 be the embodiment of the invention provide utilize bottom-up electroplating technology to fill up the schematic diagram of conducting metal copper to the through hole among Fig. 66.
Fig. 8 be the embodiment of the invention provide to the device among Fig. 7 be connected with three-dimensional interconnection and again the wiring after schematic diagram.
Fig. 9 be the embodiment of the invention provide will carry out schematic diagram behind the copper bump bonding to integrated circuit wafer shown in Figure 8 upset back and another disk.
Figure 10 is the schematic diagram after the ground floor disk to behind Fig. 9 bonding that the embodiment of the invention provides carries out thinning back side and makes the bonding salient point.
Figure 11 is the three stacked three dimensional integrated circuits schematic diagrames that add that the embodiment of the invention provides.
Embodiment
The present invention is a kind of three dimensional integrated circuits implementation method, and this method utilizes lithographic technique to substrate disk local reduction, and in local reduction district etching high aspect ratio vias, owing to be local reduction, disk intensity is guaranteed, thereby do not need to shift disk; Adopt bottom-up electro-plating method to fill the high-aspect-ratio blind hole in addition, and the bonding and wafer thinning disk is realized the three-dimensional interconnection that penetrates substrate of high-aspect-ratio, the acquisition three dimensional integrated circuits.Embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
Figure 1 shows that the present invention realizes the method flow diagram of three dimensional integrated circuits; Fig. 2 is the substrate disk that has integrated circuit, comprises the metal interconnected 2 of the surface passivation layer 1 of Semiconductor substrate W1, Semiconductor substrate W1 and W1, and wherein, semiconductor substrate materials can be silicon, germanium silicon, GaAs (GaAs) or silicon-on-insulator (SOI).The circuit wafer that provides with Fig. 2 serves as that the basis realizes that double layer circuit vertically is integrated into example, and the implementation method of three dimensional integrated circuits may further comprise the steps:
Step 1-01: deposit etching protective layer 3 on the surface passivation layer 1 of the Semiconductor substrate W1 that has integrated circuit or microsensor or MEMS device.
Wherein, protective layer 3 can be but be not limited to silicon nitride (Si
xN
y) material.The deposition process of protective layer can adopt methods such as low-pressure chemical vapor deposition of the prior art (LPCVD), plasma activated chemical vapour deposition (PECVD) or sputter.
Step 1-02: the protective layer at the etching W1 back side, utilize then potassium hydroxide (KOH) etching from the back side with W1 local etching attenuate, the residual thickness in final Semiconductor substrate W1 local reduction district can be below 50 microns.As shown in Figure 3.
The etching here can utilize the KOH etching to realize, also can utilize Tetramethylammonium hydroxide (TMAH) or reaction ion deep etching DRIE etching to realize.
Step 10-3:, utilize the through hole 6 of DRIE deep etching method then in local reduction's zone etching high-aspect-ratio with the protective layer and the passivation layer difference etching in Semiconductor substrate W1 front.As shown in Figure 4.
Step 10-4: at two-sided deposit dielectric insulation layer of Semiconductor substrate W1 and copper diffusion barrier layer 7, make through hole 6 inside and insulated substrate, in the Seed Layer 8 of W1 back spatter deposit plated metal copper.As shown in Figure 5.
Wherein, dielectric insulation layer can be but be not limited to silicon dioxide or silicon nitride.
Step 10-5: electroplate at the back side to Semiconductor substrate W1, utilizes through hole 6 opening parts laterally to electroplate fast characteristics, forms copper plug 9 through hole 6 is shut at the opening at the W1 back side.As shown in Figure 6.
Step 10-6: with the copper plug 9 at the Semiconductor substrate W1 back side as Seed Layer, utilize bottom-up electroplating technology to electroplate to W1 is positive, owing to have only the bottom of through hole 6 that Seed Layer is arranged, electroplating process makes through hole 6 be filled up by copper post 10, and makes the metal bonding salient point on copper post surface.As shown in Figure 7.
Here the metal material of filling and salient point can be one or more materials in tungsten, copper, tin, gold or the lead, or the alloy material of any two kinds and multiple formation in tungsten, copper, tin, gold or the lead, but be not limited to that these are several, for example: use copper to finish a part earlier and fill, and then use tin.Present embodiment is that example describes with the copper product.
Step 10-7: connect the metal interconnected 2 of the salient point of three-dimensional interconnection and Semiconductor substrate W1 with conventional method, form and connect up 11 again.As shown in Figure 8.
Step 10-8:, carry out bump bonding by salient point 12 with another Semiconductor substrate W2, at the slit of bonding filled high polymer polymeric material with Semiconductor substrate W1 upset.As shown in Figure 9.
The interlayer bonding techniques can also adopt high-molecular organic material bonding or oxide layer bonding.Present embodiment is with the metal salient point bonding
Step 10-9: utilize the thinning back side of thinning technique, till the interconnection of high-aspect-ratio is exposed to the W1 surface, in interconnection, make bonding salient point 14, formed the three dimensional integrated circuits that constitutes by 2 layers of Semiconductor substrate with Semiconductor substrate W1.As shown in figure 10.
Wherein, the method for attenuate can be that mechanical lapping, etching or chemical machinery cut open light, and perhaps multiple mode combines.
After finishing, above step realized the vertically integrated of two-tier circuit.Use the method that the embodiment of the invention provides, repeat above step and just can realize the three-dimensional integrated of the vertical stack of multilayer circuit.And kind and crystal lattice orientation to backing material do not require, and have good versatility.Figure 11 is a three dimensional integrated circuits schematic diagram of reusing three layers of disks stack of said method realization, wherein, W1 represents to have integrated circuit (or microsensor, MEMS structure etc.) Semiconductor substrate, what W2 represented common thickness has an integrated circuit (or microsensor, the MEMS structure) Semiconductor substrate, W3 represents that the upper strata has integrated circuit (or microsensor, the MEMS structure) Semiconductor substrate, copper tin bump bonding interface between 14 presentation layers, the vertical copper interconnecting line of realizing is electroplated in 10 expressions, the 7th, the side wall insulating layer of vertical copper-connection and substrate, 13 expression bump bondings are intact afterwards at the bonding face organic substance that fill in the zone except that the salient point position.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. three dimensional integrated circuits implementation method, it is characterized in that, the substrate disk is carried out local reduction, and in local reduction district etching high aspect ratio vias, adopt bottom-up electro-plating method to fill high aspect ratio vias, last bonding and wafer thinning disk, the three-dimensional interconnection that penetrates substrate of realization high-aspect-ratio, obtain three dimensional integrated circuits, realize that the step of this method comprises:
Steps A: utilize potassium hydroxide KOH lithographic technique to carry out local reduction from the back side to ground floor substrate disk; Utilize the DRIE lithographic technique to penetrate the through hole of ground floor substrate disk in described local reduction district's etching from the front;
Step B: at ground floor substrate disk back side deposition insulating layer, copper diffusion barrier layer and copper seed layer; Through hole opening is overleaf shut in the single face electro-coppering; As Seed Layer, utilize the positive electro-coppering filling vias of bottom-up electro-plating method with the copper of shutting opening, and on the through hole of filling, make the bonding salient point from described ground floor substrate disk;
Step C: the described ground floor substrate disk that overturns, the mode that adopts the copper bump bonding is with described ground floor substrate disk and second layer wafer bonding; Thereby the circuit of realizing ground floor substrate disk and second layer disk is connected, and constitutes three dimensional integrated circuits.
2. according to the described three dimensional integrated circuits implementation method of claim 1, it is characterized in that described each disk uses silicon, germanium silicon, GaAs or silicon-on-insulator as the backing material of making circuit.
3. according to the described three dimensional integrated circuits implementation method of claim 1, it is characterized in that described steps A realizes that the method for local reduction also comprises: adopt the wet etching technique of Tetramethylammonium hydroxide TAMH alkaline solution or the dry etching technology of reaction ion deep etching DRIE.
4. according to the described three dimensional integrated circuits implementation method of claim 1, it is characterized in that, also comprise in step C: the material of described salient point is one or more materials in copper, tin, gold or the lead, or any alloy material of two or more formations in them.
5. according to the described three dimensional integrated circuits implementation method of claim 1, it is characterized in that the bonding method of described step C also comprises: adopt the high-molecular organic material bonding, or adopt the low temperature oxide layer bonding.
6. according to the described three dimensional integrated circuits implementation method of claim 1, it is characterized in that, also comprise in step C: the slit between described ground floor substrate disk and the described second layer disk uses macromolecule polymer material to fill, and is cured.
7. according to the described three dimensional integrated circuits implementation method of claim 1, it is characterized in that, described method also comprises: the three dimensional integrated circuits that described ground floor substrate disk and described second layer disk are constituted is as new circuit wafer, repeat described steps A to described step C, realize the three dimensional integrated circuits that the multilayer disk constitutes.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200710179533.0A CN100570847C (en) | 2007-12-14 | 2007-12-14 | The three dimensional integrated circuits implementation method of transfer-free disc |
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| CN200710179533.0A CN100570847C (en) | 2007-12-14 | 2007-12-14 | The three dimensional integrated circuits implementation method of transfer-free disc |
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| CN100570847C true CN100570847C (en) | 2009-12-16 |
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| CN105513943B (en) * | 2014-09-22 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
| CN104347364A (en) * | 2014-09-23 | 2015-02-11 | 武汉新芯集成电路制造有限公司 | Preparation method of three-dimensional stacked device |
| CN111564429A (en) * | 2020-04-29 | 2020-08-21 | 北京大学深圳研究生院 | Three-dimensional heterogeneous integrated chip of integrated circuit and packaging method |
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