CN100573887C - Array base palte and manufacture method thereof and the liquid crystal display device that comprises it - Google Patents
Array base palte and manufacture method thereof and the liquid crystal display device that comprises it Download PDFInfo
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- CN100573887C CN100573887C CNB2007101230301A CN200710123030A CN100573887C CN 100573887 C CN100573887 C CN 100573887C CN B2007101230301 A CNB2007101230301 A CN B2007101230301A CN 200710123030 A CN200710123030 A CN 200710123030A CN 100573887 C CN100573887 C CN 100573887C
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Abstract
The invention discloses a kind of array base palte, have its LCD device and the method that adopts IPP manufacturing array substrate.Described method comprises: adopt first model to form grid line and grid on substrate, above substrate and grid line, form gate insulation layer, in the first of gate insulation layer, form first plane layer, adopt second model on the second portion of gate insulation layer, to form semiconductor layer, above first plane layer, form second plane layer, adopt the 3rd model on second plane layer, to form data wire and formation source electrode and drain electrode on semiconductor layer, adopt four-model to form passivation layer with contact hole, and adopting the 5th model on passivation layer, to form pixel electrode, described pixel electrode is electrically connected to described drain electrode via contact hole.
Description
It is the priority of the korean patent application of No.10-2006-0057373 that the application requires to enjoy the application number that proposed on June 26th, 2006, at this in conjunction with its full content as a reference.
Technical field
The present invention relates to a kind of liquid crystal display (LCD) device, especially, relate to a kind of array base palte and manufacture method thereof with high resolution design, and the LCD with this array base palte.
Background technology
At present, about being used for producing the semiconductor devices and the interest of the composition technology of display device increases.The composition technology has significant impact to the output of miniaturization, high integration and semiconductor device and display device.That is, along with the composition technology becomes complicated, output reduces and error rate may increase.The photoetching technique of the photoresist resin of employing and light reaction has been widely used in the composition technology of correlation technique.
Figure 1A to 1E is that explanation adopts the photolithography of correlation technique to be used to form the schematic cross section of the method for metal composition.Shown in Figure 1A, form metallic film 20a by plated metal on substrate 10.Then, the photoresist resin forms on metallic film 20a to form photoresist film 90.
Shown in Figure 1B, mask M is arranged on after photoresist film 90 tops, and the UV irradiate light is on it.
Shown in Fig. 1 C, the photoresist film 90 that is mapped to from the illumination by mask M forms hardening region 90a.Development substrate 10, and remove photoresist film 90 except hardening region 90a.Therefore, form photoresist pattern with hardening region 90a.
Shown in Fig. 1 D, adopt the photoresist pattern to carry out etching as mask.
Shown in Fig. 1 E, on substrate 10, form metal composition 20 by the stripping photoresist pattern.
Because the photolithography of correlation technique needs depositing operation, exposure technology, developing process, etch process and five technologies of stripping technology in order to form a metal pattern, whole technology is very complicated.Simultaneously, the photolithography of correlation technique need have the exposure sources of the light source that is used for irradiates light.Yet this exposure sources is quite expensive.Adopt the exposure sources of this costliness to form under the situation of pattern, the technology cost increases.In addition, the photolithography of correlation technique adopts light to form the photoresist pattern.Yet light may be because the restriction of exposure sources and diffraction, may make photoresist pattern inaccuracy like this.Therefore, thus the metal pattern that adopts this photoresist pattern to form also may inaccuracy can not obtain high-resolution pattern.Because this inaccuracy of pattern descends productive rate greatly.
Summary of the invention
Therefore, embodiments of the present invention relate to a kind of array base palte and manufacture method thereof, and the LCD device with this array base palte, and it is eliminated basically because the limitation of correlation technique and one or more problems that defective causes.
One object of the present invention is to provide a kind of can form the array base palte with high resolution design and the manufacture method thereof of accurate pattern with low cost simply by adopting non-exposure technology to carry out composition, and the LCD device with this array base palte.
Other features and advantages of the present invention will be illustrated in specification, be familiar with those of ordinary skill in the art and can partly understand from specification, maybe can understand by embodiments of the present invention.The purpose of embodiments of the present invention and other advantage will realize and obtain by specification and claims and the pointed structure of accompanying drawing.
For the advantage that obtains these purposes and other and according to purpose of the present invention, as concrete and broadly described at this, a kind of array base palte comprises: the grid line that first direction is provided with on the substrate; From the extended grid of described grid line; At the gate insulation layer that comprises above the substrate of described grid line; Described gate insulation layer than first plane layer on the lower part, described first plane layer has the top surface with the upper surface equal height of the higher part of described gate insulation layer; Semiconductor layer on the part of the corresponding described grid of described gate insulation layer; Surround second plane layer of described semiconductor layer on described first plane layer, described second plane layer has the top surface with the upper surface equal height of described semiconductor layer; Data wire; Source electrode and drain electrode on the described semiconductor layer and second plane layer, described source electrode extends from described data wire; Passivation layer on described second plane layer, source electrode, drain electrode and the semiconductor layer; And the pixel electrode on the described passivation layer, described pixel electrode is electrically connected to described drain electrode via first contact hole.
On the other hand, a kind of liquid crystal display device comprises colour filtering chip basic board; Array base palte comprises: the grid line that first direction is provided with on the substrate; From the extended grid of described grid line; At the gate insulation layer that comprises above the substrate of described grid line; Described gate insulation layer than first plane layer on the lower part, described first plane layer has the top surface with the upper surface equal height of the higher part of described gate insulation layer; Semiconductor layer on the part of the corresponding described grid of described gate insulation layer; Surround second plane layer of described semiconductor layer on described first plane layer, described second plane layer has the top surface with the upper surface equal height of described semiconductor layer; Data wire; Source electrode and drain electrode on the described semiconductor layer and second plane layer, described source electrode extends from described data wire; Passivation layer on described second plane layer, source electrode, drain electrode and semiconductor layer; And the pixel electrode on the described passivation layer, described pixel electrode is electrically connected to described drain electrode via first contact hole; And the liquid crystal layer between described colour filtering chip basic board and the array base palte.
On the other hand, a kind of method that is used for the manufacturing array substrate, described method comprises: adopt first model to form grid line, grid and common wire on substrate; Above the substrate that comprises described grid line, grid and common wire, form gate insulation layer; Described gate insulation layer than lower part on form first plane layer, described first plane layer has the top surface with the upper surface equal height of the higher part of described gate insulation layer; Adopt second model on the part of the corresponding described grid of described gate insulation layer, to form semiconductor layer; Surround described semiconductor layer and form second plane layer on described first plane layer, described second plane layer has the top surface with the upper surface equal height of described semiconductor layer; Adopt the 3rd model on described second plane layer, to form data wire and formation source electrode and drain electrode on described semiconductor layer; Adopt four-model to form passivation layer with first contact hole and second contact hole; And adopting the 5th model on described passivation layer, to form pixel electrode, described pixel electrode is electrically connected to described drain electrode via described first contact hole; Wherein said grid, common wire, semiconductor layer, data wire, source electrode and drain electrode adopt the copline printing process to form.
Should be appreciated that the generality above the present invention is described and following detailed description all is exemplary and indicative, its purpose is claim of the present invention is further explained.
Description of drawings
The accompanying drawing that the application comprised is used for further understanding the present invention, and it combines with specification and constitutes the part of specification, and described accompanying drawing is represented embodiments of the invention and explained principle of the present invention with specification.In the drawings:
Figure 1A to 1E is that explanation adopts the photolithography of correlation technique to be used to form the schematic cross section of the method for metal pattern;
Fig. 2 A shows the plane graph that is used to make array base palte according to an embodiment of the present invention;
Fig. 2 B is line A-A ', the B-B ' in Fig. 2 A, and the cross-sectional view of C-C ' intercepting;
Fig. 3 A to 19A shows the cross-sectional view of the operation of manufacturing array substrate according to an embodiment of the present invention;
Fig. 3 B to 19B is respectively the plane graph of Fig. 3 A to 19A; And
Figure 20 is the cross-sectional view of liquid crystal display device according to an embodiment of the present invention.
Embodiment
In detail with reference to example shown in the drawings, preferred implementation of the present invention is described now.
Can adopt copline printing (in-plane printing, IPP) the manufacturing array base palte that is used for liquid crystal display device according to an embodiment of the present invention.Different with the photolithography of correlation technique, IPP adopts the non-exposure technology of not using up to form pattern.For example, on substrate, form metallic film, on metallic film, form film against corrosion (etching resist film) then.Afterwards, be patterned into part with projection and (unevenness) model of depression and contact film against corrosion.By this structure, by because the repulsive force (repulsive force) of surface energy difference and film absorption against corrosion arrived film against corrosion to the uneven design transfer of model to the capillary force of the recess patterns of model between film against corrosion and the model.That is, can form the corrosion-resisting pattern of the recess patterns of corresponding model.
When adopting IPP, can simplify technology and reduce cost.Because the uneven pattern of model is directly transferred to substrate, can form high-resolution pattern and can improve productive rate.The array base palte of being made by IPP will be described below.Though the example as the array base palte that adopts IPP has illustrated in-plain switching (IPS) pattern array substrate below, embodiments of the present invention are not limited to this but can easily be applied to comprise the array base palte of the various patterns of twisted-nematic (TN) pattern.Simultaneously, embodiments of the present invention are not limited to array base palte.Colour filtering chip basic board also can adopt IPP to make.
Fig. 2 A shows the plane graph of array base palte according to the embodiment of the present invention, and Fig. 2 B is line A-A ', B-B ' in Fig. 2 A, and the cross-sectional view of C-C ' intercepting.With reference to Fig. 2 A and 2B, along the first direction setting, and the grid 114 that extends from grid line 112 also is arranged on the substrate 110 grid line 112 on substrate 110.Common wire 115 parallel grid lines 112 are provided with.Common wire 115 and grid line 112 can be arranged in the same plane.
Pattern forms on the substrate 110 that material should be arranged on the plane to adopt an IPP operation to form uniform pattern.This is because the model that is used for IPP is that plane surface is to produce required pattern equably and as one man.Gate insulation layer 116 has the difference in height that is caused by grid line 112, grid 114 and common wire 115.This difference in height can cause heterogeneous or nonplanar surface.
In order to produce the surface on plane, the gate insulation layer 116 the higher part that first plane layer 120 is arranged on corresponding grid line 112, grid 114 and common wire 115 in gate insulation layer 116 is divided than lower part.First plane layer 120 can be by forming or formed by the material that is different from gate insulation layer 116 with gate insulation layer 116 identical materials.The upper surface of first plane layer 120 is set to consistent with the upper surface of the higher part of the gate insulation layer 116 of corresponding grid line 112, grid 114 and common wire 115.Therefore, the upper surface of the higher part of corresponding grid line 112, grid 114 and common wire 115 obtains the surface on plane in the upper surface of first plane layer 120 and gate insulation layer 116.
Then, on the substrate 110 that comprises first plane layer 120, the semiconductor layer 118 that comprises active layer and ohmic contact layer is set on the part of gate insulation layer 116 corresponding grids 114.Because semiconductor layer 118 forms and be overlapping with the upper surface of first plane layer 120, between other zone that does not form semiconductor layer 118 on the zone that is formed with semiconductor layer 118 on first plane layer 120 and first plane layer 120, produce difference in height on the higher part of gate insulation layer 116.Therefore, second plane layer 122 is arranged on first plane layer 120, surrounds semiconductor layer 118.The upper surface of second plane layer 122 is set to consistent with the upper surface of semiconductor layer 118.Therefore, obtain the surface on plane by the semiconductor layer 118 and second plane layer 122.
Exposing the first contact hole 132a of drain electrode 126b and the second contact hole 132b of exposure common wire 115 can adopt an IPP operation to form in passivation layer 130.Pixel electrode 134 is set to be electrically connected to drain electrode 126a via the first contact hole 132a.A plurality of pixel electrode rod 134a, 134b and 134c extend from pixel electrode 134.Simultaneously, public electrode 136 is set to be electrically connected to common wire 115 via the second contact hole 132b.A plurality of public electrode rod 136a, 136b, 136c and 136d extend from public electrode 136. Pixel electrode rod 134a, 134b and 134c and public electrode rod 136a, 136b, 136c and 136d can alternately arrange.Pixel electrode 134, pixel electrode rod 134a, 134b and 134c, public electrode 136 and public electrode rod 136a, 136b, 136c and 136d can adopt an IPP operation to form simultaneously.
In the above description, public electrode 136 and public electrode rod 136a, 136b, 136c and 136d can be with pixel electrode 134 and pixel electrode rod 134a, 134b and 134c formation simultaneously at grade.Yet for the array base palte of the IPS pattern of embodiment of the present invention, public electrode 136, public electrode rod 136a, 136b, 136c and 136d can form in different layers with pixel electrode 134 and pixel electrode rod 134a, 134b and 134c.For example, public electrode can be integrally formed with common wire 115, and can form simultaneously when common wire 115 forms from the public electrode rod that public electrode extends.Like this, have only pixel electrode 134 and pixel electrode rod 134a, 134b and 134c to be arranged on the passivation layer 130.
When adopting IPP rather than photoetching technique manufacturing array substrate, can simplify working process and do not use exposure sources.Like this, significantly reduce process cost.Simultaneously and since adopt model directly design transfer to substrate, can obtain high resolution design, and can increase productive rate.
Fig. 3 A to 19B shows the operation of manufacturing array substrate according to an embodiment of the present invention.According to the embodiment of the present invention, employing can form the IPP manufacturing array substrate of composition with non-exposure technology.In IPP, because moving pattern material, repulsive force that contact model produces and capillary force form desirable pattern to the recess patterns of model by adopting.
With reference to Fig. 3 A and 3B, first metallic film 111 is deposited on the whole surface of substrate 110.First metallic film 111 can be formed by the metal with conductivity.Can adopt sputter or chemical vapor deposition (CVD) deposition first metallic film 111.
(ER) against corrosion coated materials forms an ER layer 190a on first metallic film 111.The one ER layer 190a conduct is used to form the mask of pattern, and can be by polyethylene glycol, hexanediyl ester, 1, one of them formation of 4-butanediol diglycidyl ether.The surface energy of the one ER layer 190a approximately is 33mJ/cm
2To 40mJ/cm
2
With reference to Fig. 4 A and 4B, the first model 300a with projection/recess patterns (unevenness) is arranged on the ER layer 190a.The first model 300a can be by having about 20mJ/cm
2The dimethyl silicone polymer (PDMS) of surface energy form.Therefore, the difference of the surface energy between the first model 300a and the ER layer 190a is about 13-20mJ/cm
2Therefore, when the first model 300a contacts an ER layer 190a, an ER layer 190a has the repulsive force to the first model 300a.Simultaneously, when the first model 300a contacts an ER layer 190a, produce capillary force, move on to the recess patterns of the first model 300a by the part of the projection pattern of the corresponding first model 300a among capillary force the one ER layer 190a.Because this capillary force is subjected to the width and the thickness of the recess patterns of the first model 300a, perhaps the influence of the thickness of an ER layer 190a is very big, so need be by carrying out width and the thickness of the test optimization first model 300a in advance, the perhaps thickness of an ER layer 190a.
Thereby can being elastomeric material with low surface free energy and strong durability, the material of the first model 300a can form and when molded other polymer, not produce adhesion easily.For example, the material that is used for the first model 300a can be PDMS.
The first model 300a can be made by main mould (master mold).For example, on main mould, form resist pattern (resist pattern) with predetermined pattern.On resist pattern, form for example cast material of PDMS.Can be by after the PDMS sclerosis, the PDMS that hardens being separated the manufacturing first model 300a from main mould.
When the first model 300a contacted an ER layer 190a, the part of the projection pattern of the corresponding first model 300a moved on to the recess patterns of the first model 300a among the ER layer 190a by the repulsive force between capillary force and the first model 300a and the ER layer 190a.Therefore, that part of recess patterns that moves on to the first model 300a fully of the projection pattern of the corresponding first model 300a among the ER layer 190a, thus the lower surface of the projection pattern of the first model 300a contacts first metallic film 111.Simultaneously, the recess patterns of the corresponding first model 300a of the one ER layer 190a that part of, and the one ER layer 190a that part ofly be added to the recess patterns of the first model 300a to form an ER pattern 190b, shown in Fig. 5 A and 5B from what the projection pattern of the first model 300a was removed.
The thickness that the composition of the first model 300a can have is at least greater than the thickness of an ER layer 190a.Therefore, the recess patterns of the corresponding first model 300a of the one ER layer 190a that part of, and that part of recess patterns that is added to the first model 300a removed of ER layer 190a, thereby form an ER pattern 190b from the projection pattern of the first model 300a.Then, an ER pattern 190b is a solid from liquid hardening.Hardening process can be thermmohardening operation or photo-hardening operation.
After hardening process was finished, the first model 300a separated from substrate 110.
By above-mentioned operation, an ER pattern 190b forms on substrate 110.
With reference to Fig. 6 A and 6B, adopt an ER pattern 190b as mask composition first metallic film 111 forming grid line 112, the grid 114 that extends from grid line 112, and the common wire 115 that is parallel to grid line 112.After the composition, peel off an ER pattern 190b.
Under the situation that produces first difference in height 138, be difficult to carry out IPP and obtain required pattern.That is, IPP can be used in the surface on plane.Therefore, thus should compensate first difference in height 138 is prepared the plane for the IPP of back surface.
With reference to Fig. 7 A and 7B, on gate insulation layer 116, form first levelling blanket 210 to compensate first difference in height 138.First levelling blanket 210 can be by forming with gate insulation layer 116 identical materials or different material.First levelling blanket 210 is preferably formed by the low-dielectric insulating material.Can reduce parasitic capacitance by adopting low-dielectric material to form first levelling blanket 210.Because first levelling blanket 210 forms on the whole surface of gate insulation layer 116, thus first levelling blanket 210 also on the part of gate insulation layer 116 corresponding lines 112,114 and 115, form, thereby do not expose gate insulation layer 116.Then, thus carrying out that part of 212 that part of of gate insulation layer 116 that cineration technics removes first levelling blanket 210 of the higher part that is positioned at gate insulation layer 116 corresponding lines 112,114 and 115 is exposed.By this technology, formation and gate insulation layer 116 have first plane layer 120 of equal height.Because gate insulation layer 116 has identical height with first plane layer 120, has eliminated first difference in height 138.Therefore, the part and first plane layer 120 by the corresponding line 112,114 of gate insulation layer and 115 keeps having unified plane highly.
With reference to Fig. 8 A and 8B, semi-conducting material 124a forms on the substrate 110 that comprises first plane layer 120, and applies erosion resistant (etching resist material) formation the 2nd ER layer 190c thereon.The 2nd ER layer 190c can be by forming with an ER layer 190a identical materials.Semi-conducting material 124a can comprise to be the active material of amorphous silicon or polysilicon and to contain doped amorphous silicon or the ohmic contact material of doped polycrystalline silicon.
The 2nd ER layer 190c is as mask and can be by polyethylene glycol, hexanediyl ester, 1, one of them formation of 4-butanediol diglycidyl ether.
With reference to Fig. 9 A and 9B, the second model 300ch with projection/recess patterns is arranged on the 2nd ER layer 190c.The second model 300ch is by main molded making, and can understand easily from the above-mentioned method that is used to make the first model 300a.When the second model 300ch contacts the 2nd ER layer 190c, the part of the projection pattern of the corresponding second model 300ch of the 2nd ER layer 190c is moved to the recess patterns of the second model 300ch by above-mentioned repulsive force and capillary force, thereby forms the 2nd ER pattern 190ch.
Afterwards, with reference to Figure 10 A and 10B, adopt thermmohardening technology or photo-hardening technology the 2nd ER pattern 190ch that hardens, then, the second model 300ch separates from substrate 110.
The thickness of the pattern of the second model 300ch can be at least greater than the thickness of the 2nd ER layer 190c.Therefore, the recess patterns of the corresponding second model 300ch is that part of among the 2nd ER layer 190c, and the 2nd that part of recess patterns of having removed among the ER layer 190c that is added to the second model 300ch, thereby form the 2nd ER pattern 190ch from the jut of the second model 300ch.
With reference to Figure 11 A and 11B, come composition semi-conducting material 142a to form semiconductor layer 118 by adopting the 2nd ER pattern 190ch to carry out etch process as etching mask.Semiconductor layer 118 can form on the part of gate insulation layer 116 corresponding grids 114.After composition, the 2nd ER pattern 190ch is stripped from.Produce second difference in height 148 by semiconductor layer 118.Therefore, second levelling blanket 220 is comprising that formation compensates second difference in height 148 on first plane layer 120 of semiconductor layer 118.
Then, thus carrying out cineration technics removes that part of 222 semiconductor layers 118 of second levelling blanket 220 are exposed second plane layer 122 that has equal height with semiconductor layer 118 to form on the semiconductor layer 118.Because the semiconductor layer 118 and second plane layer 122 have equal height, so can eliminate second difference in height 148 that is caused by semiconductor layer 118.Therefore, keep having the plane of unified height by the semiconductor layer 118 and second plane layer 122.Second plane layer 122 can be by forming with first plane layer, 120 identical materials or different material.
With reference to Figure 12 A and 12B, on the substrate 110 that comprises second plane layer 122, form, and apply erosion resistant thereon to form the 3rd ER layer 190d.The second metallic film 150M can be formed by the metal with conductivity.The second metallic film 150M can adopt sputter or CVD method to deposit.
The 3rd ER layer 190d is as mask and can be by comprising polyethylene glycol, hexanediyl ester, 1, one of them formation of 4-butanediol diglycidyl ether.
Therefore, the 3rd model 300b with projection/recess patterns is arranged on the 3rd ER layer 190d.The 3rd model 300b is from main molded making, and can understand easily from the above-mentioned method that is used to make the first model 300a.When the 3rd model 300b contacted the 3rd ER layer 190d, the part of the projection pattern of corresponding the 3rd model 300b of the 3rd ER layer 190d was moved to the recess patterns of the 3rd model 300b by above-mentioned repulsive force and capillary force, thereby forms the 3rd ER pattern 190e.
Then, with reference to Figure 13 A and 13B, adopt thermmohardening technology or photo-hardening technology to harden after the 3rd ER pattern 190e, the 3rd model 300b separates from substrate 110.The thickness of the pattern of the 3rd model 300b can be at least greater than the thickness of the 3rd ER layer 190d.Therefore, the recess patterns of corresponding the 3rd model 300b of the 3rd ER layer 190d that part of, and the 3rd that part of recess patterns of having removed among the ER layer 190d that is added to the 3rd model 300b, thereby form the 3rd ER pattern 190e from the jut of the 3rd model 300b.
Shown in Figure 14 A and 14B, adopt the 3rd ER pattern 190e as the mask composition second metallic film 150M to form and grid line 112 data line crossing 124, from the source electrode 126a of data wire 124 extensions, and the drain electrode 126b that separates with source electrode 126a.Then, peel off the 3rd ER pattern 190e.
By above-mentioned operation, formation comprises grid 114, semiconductor layer 118, source electrode 126a and drain electrode 126b.
With reference to Figure 15 A and 15B, passivation layer 130 forms on the substrate 110 that comprises data wire 124.Passivation layer 130 can by the inorganic insulating material of for example SiN or for example the organic insulating material of BCB form.Because passivation layer 130 generally forms very thickly, the upper surface of passivation layer 130 obtains uniform in-plane.In other words, passivation layer 130 is less than the difference in height that is caused by data wire 124, source electrode 126a and drain electrode 126b.Therefore, the independent plane layer that does not need the compensate for height difference.
When having the four-model 300c contact passivation layer 130 of projection/recess patterns, the part of the projection pattern of passivation layer 130 corresponding four-model 300c moves on to the recess patterns of four-model 300c, thus the upper surface of the projection pattern of four-model 300c contact drain electrode 126b or common wire 115.In other words, the part of the projection pattern of passivation layer 130 corresponding four-model 300c is removed fully, thereby shown in Figure 16 A and 16B, forms first contact hole 132a that exposes drain electrode 126b and the second contact hole 132b that exposes common wire 115.
Because passivation layer 130 is formed by the organic or inorganic material, the first contact hole 132a can adopt four-model 300c to form in passivation layer 130 and not form independent ER pattern.At this moment, adopt four-model 300c in the part of passivation layer 130 corresponding common wires 115, to form bore portion.
Below, do to carve operation by carrying out, first and second plane layers 120 and 122 patterned to expose common wire 115 by this bore portion.Like this, can form the second contact hole 132b.
Then, adopt thermmohardening technology or photo-hardening technology sclerosis passivation layer 130, four-model 300c separates from passivation layer 130 then.
With reference to Figure 17 A and 17B, on passivation layer 130, form transparent conductive film 170M.Transparent conductive film 170M can be tin indium oxide (ITO) or indium zinc oxide (IZO).
On transparent conductive film 170M, apply erosion resistant to form the 4th ER layer 190f with as mask.The 4th ER layer 190f can be by polyethylene glycol, hexanediyl ester, 1, one of them formation of 4-butanediol diglycidyl ether.
When the 5th model 300d with projection/recess patterns is arranged on the 4th ER layer 190f, the part of the projection pattern of corresponding the 5th model 300d is moved to the recess patterns of the 5th model 300d by above-mentioned repulsive force and capillary force among the 4th ER layer 190f, thereby forms the 4th ER pattern 190g.Then, with reference to Figure 18 A and 18B, adopt thermmohardening technology or photo-hardening technology the 4th ER pattern 190g that hardens, the 5th model 300d separates from substrate 110 then.
The thickness of the pattern of the 5th model 300d can be at least greater than the thickness of the 4th ER layer 190f.Therefore, the recess patterns of corresponding the 5th model 300d is that part of among the 4th ER layer 190f, and the 4th that part of recess patterns that is added to the 5th model 300d of having removed of ER layer 190f, thereby form the 4th ER pattern 190g from the jut of the 5th model 300d.
Therefore, shown in Figure 19 A and 19B, adopt the 4th ER pattern 190g to be electrically connected to the pixel electrode 134 of drain electrode 126b via the first contact hole 132a with formation as etching mask composition transparent conductive film 170M, a plurality of pixel electrodes rod 134a, 134b and 134c from pixel electrode 134 extensions, be electrically connected to the public electrode 136 of common wire 115 via the second contact hole 132b, a plurality of public electrodes rod 136a, the 136b, 136c and the 136d that extend from public electrode 136.After composition, peel off the 4th ER pattern 190g. Pixel electrode rod 134a, 134b and 134c and public electrode rod 136a, 136b, 136c and 136d can alternately form.
According to the embodiment of the present invention, adopt model accurately to form the ER pattern, and adopt this ER pattern accurately to form required pattern.On the other hand, adopt the photolithography of correlation technique to form under the situation of pattern, because diffraction of light is in photoresist pattern generating error, it causes coarse pattern.According to the embodiment of the present invention, form the ER pattern, can form more accurate ER pattern and form high resolution design owing to adopt model that pattern is directly transferred to substrate.
Simultaneously, according to the embodiment of the present invention, make model easily with projection/recess patterns by main mould, different with the photolithography of the correlation technique of the exposure sources of needs costliness, and adopt this model to form the ER pattern, thereby can significantly reduce the technology cost.In addition, according to the embodiment of the present invention, adopt the single operation of model to be used to form the ER pattern, and in correlation technique, comprise that the photolithography of exposure process and developing procedure is used to form the photoresist pattern at least.Therefore, the number that reduces and simplify working process.
Figure 20 is the cross-sectional view of LCD device according to the embodiment of the present invention.As shown in figure 20, the LCD device comprises array base palte 100, the colour filtering chip basic board 400 relative with array base palte 100, is clipped in liquid crystal (LC) layer 450 between array base palte 100 and the colour filtering chip basic board 400.Because can be by the technology manufacturing array substrate 100 shown in Fig. 3 A and the 19B, with detailed.
Colour filtering chip basic board 400 comprises color filter layer 420 and black matrix (BM) layer 430.Color filter layer 420 comprises the colour filter that forms respectively on each pixel region.BM layer 430 absorbs and stops light to pass through between colour filter.
Array base palte 100 and color filter substrate 400 adopts seal patterns bonding mutually, and liquid crystal (LC) layer 450 is clipped between array base palte 100 and the color filter substrate 400, thereby finally can make the LCD device.This process technology limit is in the LC injection method.Under the situation of LC drip, the LC layer instil array base palte 100 and color filter substrate 400 one of them, and array base palte 100 adopts seal patterns to be bonded in color filter substrate 400 then.
According to the embodiment of the present invention, can adopt IPP to make and have the array base palte of more accurate pattern, and the LCD device that comprises it.Owing to do not adopt photolithography, so the number that can significantly reduce technology cost and minimizing and simplify working process.Like this, can obtain high resolution design and improve productive rate by the pattern of model directly being transferred to substrate.
Obviously, can carry out various modifications and distortion to the present invention to those skilled in the art.Thereby, the invention is intended to cover the modification of the present invention and the distortion that fall in appended claims and the equivalent scope thereof.
Claims (45)
1, a kind of array base palte comprises:
The grid line that first direction is provided with on the substrate;
From the extended grid of described grid line;
At the gate insulation layer that comprises above the substrate of described grid line;
Described gate insulation layer than first plane layer on the lower part, described first plane layer has the top surface with the upper surface equal height of the higher part of described gate insulation layer;
Semiconductor layer on the part of the corresponding described grid of described gate insulation layer;
Surround second plane layer of described semiconductor layer on described first plane layer, described second plane layer has the top surface with the upper surface equal height of described semiconductor layer;
Data wire;
Source electrode and drain electrode on the described semiconductor layer and second plane layer, described source electrode extends out from described data wire;
Passivation layer on described second plane layer, source electrode, drain electrode and the semiconductor layer; And
Pixel electrode on the described passivation layer, described pixel electrode is electrically connected to described drain electrode via first contact hole.
2, array base palte according to claim 1 is characterized in that, described data wire on second plane layer along the second direction setting that intersects with first direction.
3, array base palte according to claim 1 is characterized in that, described semiconductor layer overlaps on the upper surface of first plane layer.
4, array base palte according to claim 1 is characterized in that, described first plane layer comprises the material different with gate insulation layer.
5, array base palte according to claim 1 is characterized in that, described first plane layer comprises and the gate insulation layer identical materials.
6, array base palte according to claim 1 is characterized in that, described second plane layer comprises the material different with gate insulation layer.
7, array base palte according to claim 1 is characterized in that, described second plane layer comprises and the gate insulation layer identical materials.
8, array base palte according to claim 1 is characterized in that, described pixel electrode comprises a plurality of pixel electrode rods, and described pixel electrode rod extends from pixel electrode.
9, array base palte according to claim 1 is characterized in that, also comprises being parallel to the common wire that described grid line is provided with; And
Public electrode on the described passivation layer, described public electrode is electrically connected to common wire via second contact hole.
10, array base palte according to claim 9 is characterized in that, described public electrode comprises a plurality of public electrode rods, and the public electrode rod extends from public electrode.
11, array base palte according to claim 1 is characterized in that, described first plane layer is formed by one of organic insulating material and inorganic insulating material.
12, array base palte according to claim 1 is characterized in that, described second plane layer is formed by one of organic insulating material and inorganic insulating material.
13, a kind of liquid crystal display device comprises:
Colour filtering chip basic board;
Array base palte comprises:
The grid line that first direction is provided with on the substrate;
From the extended grid of described grid line;
At the gate insulation layer that comprises above the substrate of described grid line;
Described gate insulation layer than first plane layer on the lower part, described first plane layer has the top surface with the upper surface equal height of the higher part of described gate insulation layer;
Semiconductor layer on the part of the corresponding described grid of described gate insulation layer;
Surround described semiconductor layer second plane layer on described first plane layer, described second plane layer has the top surface with the upper surface equal height of described semiconductor layer;
Data wire;
Source electrode and drain electrode on the described semiconductor layer and second plane layer, described source electrode extends from described data wire;
Passivation layer on described second plane layer, source electrode, drain electrode and the semiconductor layer; And
Pixel electrode on the described passivation layer, described pixel electrode is electrically connected to described drain electrode via first contact hole; And
Liquid crystal layer between described colour filtering chip basic board and the array base palte.
14, a kind of method that is used for the manufacturing array substrate, described method comprises:
Adopt first model on substrate, to form grid line, grid and common wire;
Above the substrate that comprises described grid line, grid and common wire, form gate insulation layer;
Described gate insulation layer than lower part on form first plane layer, described first plane layer has the top surface with the upper surface equal height of the higher part of described gate insulation layer;
Adopt second model on the part of the corresponding described grid of described gate insulation layer, to form semiconductor layer;
Surround described semiconductor layer and form second plane layer on described first plane layer, described second plane layer has the top surface with the upper surface equal height of described semiconductor layer;
Adopt the 3rd model on described second plane layer, to form data wire and formation source electrode and drain electrode on described semiconductor layer;
Adopt four-model to form passivation layer with first contact hole and second contact hole; And
Adopt the 5th model to form pixel electrode on described passivation layer, described pixel electrode is electrically connected to described drain electrode via described first contact hole;
Wherein said grid, common wire, semiconductor layer, data wire, source electrode and drain electrode adopt the copline printing process to form.
15, method according to claim 14 is characterized in that, the step of described formation first plane layer comprises:
Deposition first material above described gate insulation layer; And
First material of smooth described deposition is to expose the higher part of described gate insulation layer.
16, method according to claim 14 is characterized in that, the step of described formation second plane layer comprises:
Depositing second material above described first plane layer and semiconductor layer; And
Second material of smooth described deposition is to expose described semiconductor layer.
17, method according to claim 14 is characterized in that, also comprises adopting the 5th model to form public electrode on passivation layer, and described public electrode is electrically connected to common wire via second contact hole.
18, method according to claim 17 is characterized in that, described public electrode comprises a plurality of public electrode rods, and described public electrode rod extends from public electrode.
19, method according to claim 17 is characterized in that, the described step that forms pixel electrode and public electrode on passivation layer comprises employing copline printing process.
20, method according to claim 17 is characterized in that, the step of described formation public electrode comprises:
On described passivation layer, form transparent conductive material;
Adopt described the 5th model on transparent conductive material, to form the 4th corrosion-resisting pattern; And
Adopt the described transparent conductive material of described the 4th corrosion-resisting pattern composition.
21, method according to claim 14 is characterized in that, described pixel electrode comprises a plurality of pixel electrode rods, and described pixel electrode rod extends from pixel electrode.
22, method according to claim 14 is characterized in that, the step that described formation has the passivation layer of first and second contact holes comprises employing copline printing process.
23, method according to claim 14 is characterized in that, described first plane layer is formed by one of organic insulating material and inorganic insulating material.
24, method according to claim 14 is characterized in that, described first plane layer is by forming with the gate insulation layer identical materials.
25, method according to claim 14 is characterized in that, described first plane layer comprises different materials with gate insulation layer.
26, method according to claim 14 is characterized in that, described second plane layer is by forming with the first plane layer identical materials.
27, method according to claim 14 is characterized in that, described first plane layer comprises different materials with second plane layer.
28, method according to claim 14 is characterized in that, the step of described formation grid line, grid and common wire comprises:
On substrate, form first metallic film;
Adopt first model on first metallic film, to form first corrosion-resisting pattern; And
Adopt the first corrosion-resisting pattern composition, first metallic film.
29, method according to claim 28 is characterized in that, the thickness of the pattern of described first model is greater than the thickness of first corrosion-resisting pattern.
30, method according to claim 28 is characterized in that, described first corrosion-resisting pattern forms by having the erosion resistant of surface energy difference greater than first model.
31, method according to claim 30 is characterized in that, described erosion resistant comprises polyethylene glycol, hexanediyl ester, 1, one of 4-butanediol diglycidyl ether.
32, method according to claim 14 is characterized in that, the step of described formation semiconductor layer comprises:
On the gate insulation layer and first plane layer, form semi-conducting material;
Adopt second model on semi-conducting material, to form second corrosion-resisting pattern; And
Adopt the second corrosion-resisting pattern composition semi-conducting material.
33, method according to claim 32 is characterized in that, the thickness of the pattern of described second model is greater than the thickness of second corrosion-resisting pattern.
34, method according to claim 32 is characterized in that, described second corrosion-resisting pattern forms by having the erosion resistant of surface energy difference greater than second model.
35, method according to claim 34 is characterized in that, described erosion resistant comprises polyethylene glycol, hexanediyl ester, 1, one of 4-butanediol diglycidyl ether.
36, method according to claim 14 is characterized in that, the step of described formation data wire, source electrode and drain electrode comprises:
On the semiconductor layer and second plane layer, form second metallic film;
Adopt the 3rd model on second metallic film, to form the 3rd corrosion-resisting pattern; And
Adopt the 3rd corrosion-resisting pattern composition second metallic film.
37, method according to claim 36 is characterized in that, the thickness of the pattern of described the 3rd model is greater than the thickness of the 3rd corrosion-resisting pattern.
38, method according to claim 36 is characterized in that, described the 3rd corrosion-resisting pattern forms by having the erosion resistant of surface energy difference greater than the 3rd model.
According to the described method of claim 38, it is characterized in that 39, described erosion resistant comprises polyethylene glycol, hexanediyl ester, 1, one of 4-butanediol diglycidyl ether.
40, method according to claim 14 is characterized in that, the step that described formation has the passivation layer of first and second contact holes comprises:
On second plane layer, form insulating material;
Adopt four-model to form first contact hole and bore portion, described first contact holes exposing drain electrode; And
Expose second contact hole of common wire with formation by described bore portion composition first and second plane layers.
41, method according to claim 14 is characterized in that, the step of described formation pixel electrode comprises:
On passivation layer, form transparent conductive material;
Adopt the 5th model on transparent conductive material, to form the 4th corrosion-resisting pattern; And
Adopt the 4th corrosion-resisting pattern composition transparent conductive material.
According to the described method of claim 41, it is characterized in that 42, the thickness of the pattern of described the 5th model is greater than the thickness of the 4th corrosion-resisting pattern.
According to the described method of claim 41, it is characterized in that 43, described the 4th corrosion-resisting pattern forms by having the erosion resistant of surface energy difference greater than the 5th model.
According to the described method of claim 43, it is characterized in that 44, described erosion resistant comprises polyethylene glycol, hexanediyl ester, 1, one of 4-butanediol diglycidyl ether.
45, method according to claim 14 is characterized in that, described first plane layer not corresponding described grid line, grid and common wire on the gate insulation layer than lower part on form.
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| KR1020060057373 | 2006-06-26 | ||
| KR20060057373 | 2006-06-26 | ||
| KR1020070041023 | 2007-04-26 |
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| CN103500746A (en) | 2013-09-29 | 2014-01-08 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN105390505B (en) * | 2015-11-05 | 2018-09-18 | 昆山龙腾光电有限公司 | Thin-film transistor array base-plate and preparation method thereof |
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| JPH01297624A (en) * | 1988-05-26 | 1989-11-30 | Casio Comput Co Ltd | Thin film transistor and its production |
| JP3676906B2 (en) * | 1997-04-25 | 2005-07-27 | 松下電器産業株式会社 | Liquid crystal image display device |
| KR100550089B1 (en) * | 2001-12-29 | 2006-02-08 | 삼성전자주식회사 | Metallic Nanoparticle Cluster Ink and Method for Forming Metal Pattern Using the Same |
| KR101012495B1 (en) * | 2004-06-11 | 2011-02-08 | 엘지디스플레이 주식회사 | Method of fabricating array panel for Liquid Crystal Display Device |
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| CN101101914A (en) | 2008-01-09 |
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